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GET /api/patches/100250/?format=api
{ "id": 100250, "url": "https://patches.dpdk.org/api/patches/100250/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211001134022.22700-5-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211001134022.22700-5-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211001134022.22700-5-ndabilpuram@marvell.com", "date": "2021-10-01T13:39:58", "name": "[v3,04/28] common/cnxk: change NIX debug API and queue API interface", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b4d6f0c4ee1a64ab12f8df4948764c898f6ff8ba", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211001134022.22700-5-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 19325, "url": "https://patches.dpdk.org/api/series/19325/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19325", "date": "2021-10-01T13:39:54", "name": "net/cnxk: support for inline ipsec", "version": 3, "mbox": "https://patches.dpdk.org/series/19325/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/100250/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/100250/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 19532A0032;\n\tFri, 1 Oct 2021 15:40:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3767D41193;\n\tFri, 1 Oct 2021 15:40:42 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 927AB411A0\n for <dev@dpdk.org>; Fri, 1 Oct 2021 15:40:40 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 191ACEFC001661\n for <dev@dpdk.org>; Fri, 1 Oct 2021 06:40:40 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3bdrxmhx8t-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 01 Oct 2021 06:40:39 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Fri, 1 Oct 2021 06:40:37 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Fri, 1 Oct 2021 06:40:37 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id B9CF93F7063;\n Fri, 1 Oct 2021 06:40:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=VLfm7pR7lvGbbp3ls/EB3yD4iRCq4RnbfRbNASOBz/o=;\n b=Lr3/bFtAGmkaz7kkd5Yzs4NSDpzwBElJGBIqNCz4o0p49Vj+0Bgk/eP1toWPzjX61fNi\n 3Yzxf57C7uH74CJ5XAwpriYyOelevkb4CFrwd3mWtHWB5UOGa6eqQ65Lnch7a1BXuoWG\n InMjEEqsZJPpj8whgj+iFhQgY4/xjcaEjB6647pGKEDQoe8qEidijUPGKtxVSAwoOPNQ\n 97C0IS8ZLqLcBzOPf93c4/2A2bZghoUkaWDZINoW5l6Aq3upftDNMQAQTn+9WL71d0qn\n eZX9fjZAPi9M9UmjopIutAmxEKcT+pfy/YMLUiTyKcErrr8XZDAA2y+bLcQsVZutEehE sw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 1 Oct 2021 19:09:58 +0530", "Message-ID": "<20211001134022.22700-5-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20211001134022.22700-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>\n <20211001134022.22700-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "1vLY48yAlDiSBEEOpbG5yPN9ojIshFHv", "X-Proofpoint-ORIG-GUID": "1vLY48yAlDiSBEEOpbG5yPN9ojIshFHv", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-10-01_02,2021-10-01_02,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v3 04/28] common/cnxk: change NIX debug API and\n queue API interface", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Change NIX debug API and queue API interface for use by\ninternal NIX inline device initialization.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.c | 2 +-\n drivers/common/cnxk/roc_nix_debug.c | 118 +++++++++++++++++++++++++++---------\n drivers/common/cnxk/roc_nix_priv.h | 16 +++++\n drivers/common/cnxk/roc_nix_queue.c | 89 +++++++++++++++------------\n 4 files changed, 159 insertions(+), 66 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex ee9e81d..b7ef843 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -306,7 +306,7 @@ sdp_lbk_id_update(struct plt_pci_device *pci_dev, struct nix *nix)\n \t}\n }\n \n-static inline uint64_t\n+uint64_t\n nix_get_blkaddr(struct dev *dev)\n {\n \tuint64_t reg;\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 6e56513..9539bb9 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -110,17 +110,12 @@ roc_nix_lf_get_reg_count(struct roc_nix *roc_nix)\n }\n \n int\n-roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n+nix_lf_gen_reg_dump(uintptr_t nix_lf_base, uint64_t *data)\n {\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tuintptr_t nix_lf_base = nix->base;\n \tbool dump_stdout;\n \tuint64_t reg;\n \tuint32_t i;\n \n-\tif (roc_nix == NULL)\n-\t\treturn NIX_ERR_PARAM;\n-\n \tdump_stdout = data ? 0 : 1;\n \n \tfor (i = 0; i < PLT_DIM(nix_lf_reg); i++) {\n@@ -131,8 +126,21 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\t\t*data++ = reg;\n \t}\n \n+\treturn i;\n+}\n+\n+int\n+nix_lf_stat_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint8_t lf_tx_stats,\n+\t\t uint8_t lf_rx_stats)\n+{\n+\tuint32_t i, count = 0;\n+\tbool dump_stdout;\n+\tuint64_t reg;\n+\n+\tdump_stdout = data ? 0 : 1;\n+\n \t/* NIX_LF_TX_STATX */\n-\tfor (i = 0; i < nix->lf_tx_stats; i++) {\n+\tfor (i = 0; i < lf_tx_stats; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_TX_STATX(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_TX_STATX\", i,\n@@ -140,9 +148,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_RX_STATX */\n-\tfor (i = 0; i < nix->lf_rx_stats; i++) {\n+\tfor (i = 0; i < lf_rx_stats; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_RX_STATX(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_RX_STATX\", i,\n@@ -151,8 +160,21 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\t\t*data++ = reg;\n \t}\n \n+\treturn count + i;\n+}\n+\n+int\n+nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints,\n+\t\t uint16_t cints)\n+{\n+\tuint32_t i, count = 0;\n+\tbool dump_stdout;\n+\tuint64_t reg;\n+\n+\tdump_stdout = data ? 0 : 1;\n+\n \t/* NIX_LF_QINTX_CNT*/\n-\tfor (i = 0; i < nix->qints; i++) {\n+\tfor (i = 0; i < qints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_CNT\", i,\n@@ -160,9 +182,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_QINTX_INT */\n-\tfor (i = 0; i < nix->qints; i++) {\n+\tfor (i = 0; i < qints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_INT(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_INT\", i,\n@@ -170,9 +193,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_QINTX_ENA_W1S */\n-\tfor (i = 0; i < nix->qints; i++) {\n+\tfor (i = 0; i < qints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_ENA_W1S\",\n@@ -180,9 +204,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_QINTX_ENA_W1C */\n-\tfor (i = 0; i < nix->qints; i++) {\n+\tfor (i = 0; i < qints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_ENA_W1C\",\n@@ -190,9 +215,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_CINTX_CNT */\n-\tfor (i = 0; i < nix->cints; i++) {\n+\tfor (i = 0; i < cints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_CNT\", i,\n@@ -200,9 +226,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_CINTX_WAIT */\n-\tfor (i = 0; i < nix->cints; i++) {\n+\tfor (i = 0; i < cints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_WAIT\", i,\n@@ -210,9 +237,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_CINTX_INT */\n-\tfor (i = 0; i < nix->cints; i++) {\n+\tfor (i = 0; i < cints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_INT\", i,\n@@ -220,9 +248,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_CINTX_INT_W1S */\n-\tfor (i = 0; i < nix->cints; i++) {\n+\tfor (i = 0; i < cints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_INT_W1S\",\n@@ -230,9 +259,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_CINTX_ENA_W1S */\n-\tfor (i = 0; i < nix->cints; i++) {\n+\tfor (i = 0; i < cints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_ENA_W1S\",\n@@ -240,9 +270,10 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\tcount += i;\n \n \t/* NIX_LF_CINTX_ENA_W1C */\n-\tfor (i = 0; i < nix->cints; i++) {\n+\tfor (i = 0; i < cints; i++) {\n \t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));\n \t\tif (dump_stdout && reg)\n \t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_ENA_W1C\",\n@@ -250,12 +281,40 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n \t\tif (data)\n \t\t\t*data++ = reg;\n \t}\n+\n+\treturn count + i;\n+}\n+\n+int\n+roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tbool dump_stdout = data ? 0 : 1;\n+\tuintptr_t nix_base;\n+\tuint32_t i;\n+\n+\tif (roc_nix == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tnix_base = nix->base;\n+\t/* General registers */\n+\ti = nix_lf_gen_reg_dump(nix_base, data);\n+\n+\t/* Rx, Tx stat registers */\n+\ti += nix_lf_stat_reg_dump(nix_base, dump_stdout ? NULL : &data[i],\n+\t\t\t\t nix->lf_tx_stats, nix->lf_rx_stats);\n+\n+\t/* Intr registers */\n+\ti += nix_lf_int_reg_dump(nix_base, dump_stdout ? NULL : &data[i],\n+\t\t\t\t nix->qints, nix->cints);\n+\n \treturn 0;\n }\n \n-static int\n-nix_q_ctx_get(struct mbox *mbox, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n+int\n+nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n {\n+\tstruct mbox *mbox = dev->mbox;\n \tint rc;\n \n \tif (roc_model_is_cn9k()) {\n@@ -485,7 +544,7 @@ nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s *ctx)\n \tnix_dump(\"W10: re_pkts \\t\\t\\t0x%\" PRIx64 \"\\n\", (uint64_t)ctx->re_pkts);\n }\n \n-static inline void\n+void\n nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx)\n {\n \tnix_dump(\"W0: wqe_aura \\t\\t\\t%d\\nW0: len_ol3_dis \\t\\t\\t%d\",\n@@ -595,12 +654,12 @@ roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tint rc = -1, q, rq = nix->nb_rx_queues;\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n \tstruct npa_aq_enq_rsp *npa_rsp;\n \tstruct npa_aq_enq_req *npa_aq;\n-\tvolatile void *ctx;\n+\tstruct dev *dev = &nix->dev;\n \tint sq = nix->nb_tx_queues;\n \tstruct npa_lf *npa_lf;\n+\tvolatile void *ctx;\n \tuint32_t sqb_aura;\n \n \tnpa_lf = idev_npa_obj_get();\n@@ -608,7 +667,7 @@ roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)\n \t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n \n \tfor (q = 0; q < rq; q++) {\n-\t\trc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_CQ, q, &ctx);\n+\t\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_CQ, q, &ctx);\n \t\tif (rc) {\n \t\t\tplt_err(\"Failed to get cq context\");\n \t\t\tgoto fail;\n@@ -619,7 +678,7 @@ roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)\n \t}\n \n \tfor (q = 0; q < rq; q++) {\n-\t\trc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_RQ, q, &ctx);\n+\t\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, q, &ctx);\n \t\tif (rc) {\n \t\t\tplt_err(\"Failed to get rq context\");\n \t\t\tgoto fail;\n@@ -633,7 +692,7 @@ roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)\n \t}\n \n \tfor (q = 0; q < sq; q++) {\n-\t\trc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_SQ, q, &ctx);\n+\t\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx);\n \t\tif (rc) {\n \t\t\tplt_err(\"Failed to get sq context\");\n \t\t\tgoto fail;\n@@ -686,11 +745,13 @@ roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)\n {\n \tconst union nix_rx_parse_u *rx =\n \t\t(const union nix_rx_parse_u *)((const uint64_t *)cq + 1);\n+\tconst uint64_t *sgs = (const uint64_t *)(rx + 1);\n+\tint i;\n \n \tnix_dump(\"tag \\t\\t0x%x\\tq \\t\\t%d\\t\\tnode \\t\\t%d\\tcqe_type \\t%d\",\n \t\t cq->tag, cq->q, cq->node, cq->cqe_type);\n \n-\tnix_dump(\"W0: chan \\t%d\\t\\tdesc_sizem1 \\t%d\", rx->chan,\n+\tnix_dump(\"W0: chan \\t0x%x\\t\\tdesc_sizem1 \\t%d\", rx->chan,\n \t\t rx->desc_sizem1);\n \tnix_dump(\"W0: imm_copy \\t%d\\t\\texpress \\t%d\", rx->imm_copy,\n \t\t rx->express);\n@@ -731,6 +792,9 @@ roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)\n \n \tnix_dump(\"W5: vtag0_ptr \\t%d\\t\\tvtag1_ptr \\t%d\\t\\tflow_key_alg \\t%d\",\n \t\t rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);\n+\n+\tfor (i = 0; i < (rx->desc_sizem1 + 1) << 1; i++)\n+\t\tnix_dump(\"sg[%u] = %p\", i, (void *)sgs[i]);\n }\n \n void\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex b573879..b140dad 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -352,6 +352,12 @@ int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);\n int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \t\t\t bool rr_quantum_only);\n \n+int nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n+\t\t bool cfg, bool ena);\n+int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n+\t bool ena);\n+int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable);\n+\n /*\n * TM priv utils.\n */\n@@ -397,4 +403,14 @@ void nix_tm_node_free(struct nix_tm_node *node);\n struct nix_tm_shaper_profile *nix_tm_shaper_profile_alloc(void);\n void nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile);\n \n+uint64_t nix_get_blkaddr(struct dev *dev);\n+void nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx);\n+int nix_lf_gen_reg_dump(uintptr_t nix_lf_base, uint64_t *data);\n+int nix_lf_stat_reg_dump(uintptr_t nix_lf_base, uint64_t *data,\n+\t\t\t uint8_t lf_tx_stats, uint8_t lf_rx_stats);\n+int nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints,\n+\t\t\tuint16_t cints);\n+int nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid,\n+\t\t __io void **ctx_p);\n+\n #endif /* _ROC_NIX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex d7c4844..cff0ec3 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -29,46 +29,54 @@ nix_qsize_clampup(uint32_t val)\n }\n \n int\n+nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)\n+{\n+\tstruct mbox *mbox = dev->mbox;\n+\n+\t/* Pkts will be dropped silently if RQ is disabled */\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = rq->qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\t\taq->rq.ena = enable;\n+\t\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\taq->qidx = rq->qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\t\taq->rq.ena = enable;\n+\t\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n+\t}\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+int\n roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(rq->roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n \tint rc;\n \n-\t/* Pkts will be dropped silently if RQ is disabled */\n-\tif (roc_model_is_cn9k()) {\n-\t\tstruct nix_aq_enq_req *aq;\n-\n-\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = rq->qid;\n-\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\t\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\t\taq->rq.ena = enable;\n-\t\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n-\t} else {\n-\t\tstruct nix_cn10k_aq_enq_req *aq;\n-\n-\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\taq->qidx = rq->qid;\n-\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\t\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\t\taq->rq.ena = enable;\n-\t\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n-\t}\n-\n-\trc = mbox_process(mbox);\n+\trc = nix_rq_ena_dis(&nix->dev, rq, enable);\n \n \tif (roc_model_is_cn10k())\n \t\tplt_write64(rq->qid, nix->base + NIX_LF_OP_VWQE_FLUSH);\n \treturn rc;\n }\n \n-static int\n-rq_cn9k_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n+int\n+nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n+\t\tbool cfg, bool ena)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = dev->mbox;\n \tstruct nix_aq_enq_req *aq;\n \n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n@@ -118,7 +126,7 @@ rq_cn9k_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n \taq->rq.rq_int_ena = 0;\n \t/* Many to one reduction */\n-\taq->rq.qint_idx = rq->qid % nix->qints;\n+\taq->rq.qint_idx = rq->qid % qints;\n \taq->rq.xqe_drop_ena = 1;\n \n \t/* If RED enabled, then fill enable for all cases */\n@@ -179,11 +187,12 @@ rq_cn9k_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \treturn 0;\n }\n \n-static int\n-rq_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n+int\n+nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n+\t bool ena)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n \tstruct nix_cn10k_aq_enq_req *aq;\n+\tstruct mbox *mbox = dev->mbox;\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n \taq->qidx = rq->qid;\n@@ -220,8 +229,10 @@ rq_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \t\taq->rq.cq = rq->qid;\n \t}\n \n-\tif (rq->ipsech_ena)\n+\tif (rq->ipsech_ena) {\n \t\taq->rq.ipsech_ena = 1;\n+\t\taq->rq.ipsecd_drop_en = 1;\n+\t}\n \n \taq->rq.lpb_aura = roc_npa_aura_handle_to_aura(rq->aura_handle);\n \n@@ -260,7 +271,7 @@ rq_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n \taq->rq.rq_int_ena = 0;\n \t/* Many to one reduction */\n-\taq->rq.qint_idx = rq->qid % nix->qints;\n+\taq->rq.qint_idx = rq->qid % qints;\n \taq->rq.xqe_drop_ena = 1;\n \n \t/* If RED enabled, then fill enable for all cases */\n@@ -359,6 +370,7 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct mbox *mbox = (&nix->dev)->mbox;\n \tbool is_cn9k = roc_model_is_cn9k();\n+\tstruct dev *dev = &nix->dev;\n \tint rc;\n \n \tif (roc_nix == NULL || rq == NULL)\n@@ -370,9 +382,9 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \trq->roc_nix = roc_nix;\n \n \tif (is_cn9k)\n-\t\trc = rq_cn9k_cfg(nix, rq, false, ena);\n+\t\trc = nix_rq_cn9k_cfg(dev, rq, nix->qints, false, ena);\n \telse\n-\t\trc = rq_cfg(nix, rq, false, ena);\n+\t\trc = nix_rq_cfg(dev, rq, nix->qints, false, ena);\n \n \tif (rc)\n \t\treturn rc;\n@@ -386,6 +398,7 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct mbox *mbox = (&nix->dev)->mbox;\n \tbool is_cn9k = roc_model_is_cn9k();\n+\tstruct dev *dev = &nix->dev;\n \tint rc;\n \n \tif (roc_nix == NULL || rq == NULL)\n@@ -397,9 +410,9 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \trq->roc_nix = roc_nix;\n \n \tif (is_cn9k)\n-\t\trc = rq_cn9k_cfg(nix, rq, true, ena);\n+\t\trc = nix_rq_cn9k_cfg(dev, rq, nix->qints, true, ena);\n \telse\n-\t\trc = rq_cfg(nix, rq, true, ena);\n+\t\trc = nix_rq_cfg(dev, rq, nix->qints, true, ena);\n \n \tif (rc)\n \t\treturn rc;\n", "prefixes": [ "v3", "04/28" ] }