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GET /api/patches/100141/?format=api
{ "id": 100141, "url": "https://patches.dpdk.org/api/patches/100141/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210930170113.29030-8-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210930170113.29030-8-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210930170113.29030-8-ndabilpuram@marvell.com", "date": "2021-09-30T17:00:52", "name": "[v2,07/28] common/cnxk: support NIX inline inbound and outbound setup", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "073fea6b50bd08c48b211693f3450e466c7b8d71", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210930170113.29030-8-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 19307, "url": "https://patches.dpdk.org/api/series/19307/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19307", "date": "2021-09-30T17:00:48", "name": "net/cnxk: support for inline ipsec", "version": 2, "mbox": "https://patches.dpdk.org/series/19307/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/100141/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/100141/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AF8C4A0C43;\n\tThu, 30 Sep 2021 19:02:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EEECE4113B;\n\tThu, 30 Sep 2021 19:02:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id F3448410FE\n for <dev@dpdk.org>; Thu, 30 Sep 2021 19:01:58 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 18UCUQBt001428;\n Thu, 30 Sep 2021 10:01:55 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g3b9da-8\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 30 Sep 2021 10:01:54 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 30 Sep 2021 10:01:40 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 30 Sep 2021 10:01:40 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 3FC0F3F7068;\n Thu, 30 Sep 2021 10:01:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=rWI9Ic8Ex7HmeEkJ2poX+62IZ7wuZ6S9Wl+eEVJbXfg=;\n b=dbMzQ9Y6qcx+zfOzN/eWYw4XCcYASRoBp3OqR/77DkPfIWoxwu8pfjs+twMOSWVEQ6PM\n HzACuhnmzRAoeDrmEh4Ve/O9UF8sQAHSLbCeHDOGAUBuhOV4mJPaF9WCE5ySLDjrjO2q\n H+qesHnWJ2NKkYHibrI1xGFa2HacTypxUm1ZjUfjjE93YxMou0QwPV6J4zi+bfncISH6\n hKYkPIFjk6oXIgCwRNXOpd3muACXyaZRAPmH4HsofvA1rU8ss8hB2sBn+bWF89eeKnGj\n w0mbkbt1Skxb3IG7b1gxfP124zGXLzjRei2ZqfL43kS0w7qYR0DTkvKPLVy67YGGeZLE Yg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Date": "Thu, 30 Sep 2021 22:30:52 +0530", "Message-ID": "<20210930170113.29030-8-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210930170113.29030-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>\n <20210930170113.29030-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "OvS3JOB1XgPoHpktIuxNkF443H1gKh3a", "X-Proofpoint-ORIG-GUID": "OvS3JOB1XgPoHpktIuxNkF443H1gKh3a", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-30_06,2021-09-30_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v2 07/28] common/cnxk: support NIX inline inbound\n and outbound setup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add API to support setting up NIX inline inbound and\nNIX inline outbound. In case of inbound, SA base is setup\non NIX PFFUNC and in case of outbound, required number of\nCPT LF's are attached to NIX PFFUNC.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/hw/cpt.h | 8 +\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 48 +--\n drivers/common/cnxk/roc_constants.h | 58 +++\n drivers/common/cnxk/roc_io.h | 9 +\n drivers/common/cnxk/roc_io_generic.h | 3 +-\n drivers/common/cnxk/roc_nix.h | 5 +\n drivers/common/cnxk/roc_nix_debug.c | 15 +\n drivers/common/cnxk/roc_nix_inl.c | 778 +++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_inl.h | 101 +++++\n drivers/common/cnxk/roc_nix_priv.h | 15 +\n drivers/common/cnxk/roc_nix_queue.c | 28 +-\n drivers/common/cnxk/roc_npc.c | 27 +-\n drivers/common/cnxk/version.map | 26 ++\n 14 files changed, 1047 insertions(+), 75 deletions(-)\n create mode 100644 drivers/common/cnxk/roc_constants.h\n create mode 100644 drivers/common/cnxk/roc_nix_inl.c", "diff": "diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h\nindex 84ebf2d..975139f 100644\n--- a/drivers/common/cnxk/hw/cpt.h\n+++ b/drivers/common/cnxk/hw/cpt.h\n@@ -40,6 +40,7 @@\n #define CPT_LF_CTX_ENC_PKT_CNT\t(0x540ull)\n #define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)\n #define CPT_LF_CTX_DEC_PKT_CNT\t(0x560ull)\n+#define CPT_LF_CTX_RELOAD\t(0x570ull)\n \n #define CPT_AF_LFX_CTL(a) (0x27000ull | (uint64_t)(a) << 3)\n #define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)\n@@ -68,6 +69,13 @@ union cpt_lf_ctx_flush {\n \t} s;\n };\n \n+union cpt_lf_ctx_reload {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t cptr : 46;\n+\t} s;\n+};\n+\n union cpt_lf_inprog {\n \tuint64_t u;\n \tstruct cpt_lf_inprog_s {\ndiff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex e8940d7..cd19ad2 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -28,6 +28,7 @@ sources = files(\n 'roc_nix_debug.c',\n 'roc_nix_fc.c',\n 'roc_nix_irq.c',\n+ 'roc_nix_inl.c',\n 'roc_nix_inl_dev.c',\n 'roc_nix_inl_dev_irq.c',\n 'roc_nix_mac.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 53f4e4b..b8f3667 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -9,28 +9,21 @@\n #include <stdint.h>\n #include <string.h>\n \n-/* Alignment */\n-#define ROC_ALIGN 128\n-\n /* Bits manipulation */\n #include \"roc_bits.h\"\n \n /* Bitfields manipulation */\n #include \"roc_bitfield.h\"\n \n+/* ROC Constants */\n+#include \"roc_constants.h\"\n+\n /* Constants */\n #define PLT_ETHER_ADDR_LEN 6\n \n /* Platform definition */\n #include \"roc_platform.h\"\n \n-#define ROC_LMT_LINE_SZ\t\t 128\n-#define ROC_NUM_LMT_LINES\t 2048\n-#define ROC_LMT_LINES_PER_CORE_LOG2 5\n-#define ROC_LMT_LINE_SIZE_LOG2\t 7\n-#define ROC_LMT_BASE_PER_CORE_LOG2 \\\n-\t(ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2)\n-\n /* IO */\n #if defined(__aarch64__)\n #include \"roc_io.h\"\n@@ -38,41 +31,6 @@\n #include \"roc_io_generic.h\"\n #endif\n \n-/* PCI IDs */\n-#define PCI_VENDOR_ID_CAVIUM\t 0x177D\n-#define PCI_DEVID_CNXK_RVU_PF\t 0xA063\n-#define PCI_DEVID_CNXK_RVU_VF\t 0xA064\n-#define PCI_DEVID_CNXK_RVU_AF\t 0xA065\n-#define PCI_DEVID_CNXK_RVU_SSO_TIM_PF 0xA0F9\n-#define PCI_DEVID_CNXK_RVU_SSO_TIM_VF 0xA0FA\n-#define PCI_DEVID_CNXK_RVU_NPA_PF 0xA0FB\n-#define PCI_DEVID_CNXK_RVU_NPA_VF 0xA0FC\n-#define PCI_DEVID_CNXK_RVU_AF_VF 0xA0f8\n-#define PCI_DEVID_CNXK_DPI_VF\t 0xA081\n-#define PCI_DEVID_CNXK_EP_VF\t 0xB203\n-#define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6\n-#define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7\n-#define PCI_DEVID_CNXK_BPHY\t 0xA089\n-#define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0\n-#define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1\n-\n-#define PCI_DEVID_CN9K_CGX 0xA059\n-#define PCI_DEVID_CN10K_RPM 0xA060\n-\n-#define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD\n-#define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE\n-#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2\n-#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3\n-\n-#define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900\n-#define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900\n-\n-#define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000\n-#define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400\n-#define PCI_SUBSYSTEM_DEVID_CN9KC 0x0200\n-#define PCI_SUBSYSTEM_DEVID_CN9KD 0xB200\n-#define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100\n-\n /* HW structure definition */\n #include \"hw/cpt.h\"\n #include \"hw/nix.h\"\ndiff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h\nnew file mode 100644\nindex 0000000..1e6427c\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_constants.h\n@@ -0,0 +1,58 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef _ROC_CONSTANTS_H_\n+#define _ROC_CONSTANTS_H_\n+\n+/* Alignment */\n+#define ROC_ALIGN 128\n+\n+/* LMTST constants */\n+/* [CN10K, .) */\n+#define ROC_LMT_LINE_SZ\t\t 128\n+#define ROC_NUM_LMT_LINES\t 2048\n+#define ROC_LMT_LINES_PER_CORE_LOG2 5\n+#define ROC_LMT_LINE_SIZE_LOG2\t 7\n+#define ROC_LMT_BASE_PER_CORE_LOG2 \\\n+\t(ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2)\n+#define ROC_LMT_MAX_THREADS\t\t42UL\n+#define ROC_LMT_CPT_LINES_PER_CORE_LOG2 4\n+#define ROC_LMT_CPT_BASE_ID_OFF \\\n+\t(ROC_LMT_MAX_THREADS << ROC_LMT_LINES_PER_CORE_LOG2)\n+\n+/* PCI IDs */\n+#define PCI_VENDOR_ID_CAVIUM\t 0x177D\n+#define PCI_DEVID_CNXK_RVU_PF\t 0xA063\n+#define PCI_DEVID_CNXK_RVU_VF\t 0xA064\n+#define PCI_DEVID_CNXK_RVU_AF\t 0xA065\n+#define PCI_DEVID_CNXK_RVU_SSO_TIM_PF 0xA0F9\n+#define PCI_DEVID_CNXK_RVU_SSO_TIM_VF 0xA0FA\n+#define PCI_DEVID_CNXK_RVU_NPA_PF 0xA0FB\n+#define PCI_DEVID_CNXK_RVU_NPA_VF 0xA0FC\n+#define PCI_DEVID_CNXK_RVU_AF_VF 0xA0f8\n+#define PCI_DEVID_CNXK_DPI_VF\t 0xA081\n+#define PCI_DEVID_CNXK_EP_VF\t 0xB203\n+#define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6\n+#define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7\n+#define PCI_DEVID_CNXK_BPHY\t 0xA089\n+#define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0\n+#define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1\n+\n+#define PCI_DEVID_CN9K_CGX 0xA059\n+#define PCI_DEVID_CN10K_RPM 0xA060\n+\n+#define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD\n+#define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE\n+#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2\n+#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3\n+\n+#define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900\n+#define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900\n+\n+#define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000\n+#define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400\n+#define PCI_SUBSYSTEM_DEVID_CN9KC 0x0200\n+#define PCI_SUBSYSTEM_DEVID_CN9KD 0xB200\n+#define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100\n+\n+#endif /* _ROC_CONSTANTS_H_ */\ndiff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h\nindex aee8c7f..fe5f7f4 100644\n--- a/drivers/common/cnxk/roc_io.h\n+++ b/drivers/common/cnxk/roc_io.h\n@@ -13,6 +13,15 @@\n \t\t(lmt_addr) += ((uint64_t)lmt_id << ROC_LMT_LINE_SIZE_LOG2); \\\n \t} while (0)\n \n+#define ROC_LMT_CPT_BASE_ID_GET(lmt_addr, lmt_id) \\\n+\tdo { \\\n+\t\t/* 16 Lines per core */ \\\n+\t\tlmt_id = ROC_LMT_CPT_BASE_ID_OFF; \\\n+\t\tlmt_id += (plt_lcore_id() << ROC_LMT_CPT_LINES_PER_CORE_LOG2); \\\n+\t\t/* Each line is of 128B */ \\\n+\t\t(lmt_addr) += ((uint64_t)lmt_id << ROC_LMT_LINE_SIZE_LOG2); \\\n+\t} while (0)\n+\n #define roc_load_pair(val0, val1, addr) \\\n \t({ \\\n \t\tasm volatile(\"ldp %x[x0], %x[x1], [%x[p1]]\" \\\ndiff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h\nindex 28cb096..ceaa3a3 100644\n--- a/drivers/common/cnxk/roc_io_generic.h\n+++ b/drivers/common/cnxk/roc_io_generic.h\n@@ -5,7 +5,8 @@\n #ifndef _ROC_IO_GENERIC_H_\n #define _ROC_IO_GENERIC_H_\n \n-#define ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id) (lmt_id = 0)\n+#define ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id)\t (lmt_id = 0)\n+#define ROC_LMT_CPT_BASE_ID_GET(lmt_addr, lmt_id) (lmt_id = 0)\n \n #define roc_load_pair(val0, val1, addr) \\\n \tdo { \\\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex b0e6fab..ff8c93a 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -171,6 +171,7 @@ struct roc_nix_rq {\n \tuint8_t spb_red_pass;\n \t/* End of Input parameters */\n \tstruct roc_nix *roc_nix;\n+\tbool inl_dev_ref;\n };\n \n struct roc_nix_cq {\n@@ -258,6 +259,10 @@ struct roc_nix {\n \tbool enable_loop;\n \tbool hw_vlan_ins;\n \tuint8_t lock_rx_ctx;\n+\tuint32_t outb_nb_desc;\n+\tuint16_t outb_nb_crypto_qs;\n+\tuint16_t ipsec_in_max_spi;\n+\tuint16_t ipsec_out_max_sa;\n \t/* End of input parameters */\n \t/* LMT line base for \"Per Core Tx LMT line\" mode*/\n \tuintptr_t lmt_base;\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 582f5a3..266935a 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -818,6 +818,7 @@ roc_nix_rq_dump(struct roc_nix_rq *rq)\n \tnix_dump(\" vwqe_wait_tmo = %ld\", rq->vwqe_wait_tmo);\n \tnix_dump(\" vwqe_aura_handle = %ld\", rq->vwqe_aura_handle);\n \tnix_dump(\" roc_nix = %p\", rq->roc_nix);\n+\tnix_dump(\" inl_dev_ref = %d\", rq->inl_dev_ref);\n }\n \n void\n@@ -1160,6 +1161,7 @@ roc_nix_dump(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct dev *dev = &nix->dev;\n+\tint i;\n \n \tnix_dump(\"nix@%p\", nix);\n \tnix_dump(\" pf = %d\", dev_get_pf(dev->pf_func));\n@@ -1169,6 +1171,7 @@ roc_nix_dump(struct roc_nix *roc_nix)\n \tnix_dump(\" port_id = %d\", roc_nix->port_id);\n \tnix_dump(\" rss_tag_as_xor = %d\", roc_nix->rss_tag_as_xor);\n \tnix_dump(\" rss_tag_as_xor = %d\", roc_nix->max_sqb_count);\n+\tnix_dump(\" outb_nb_desc = %u\", roc_nix->outb_nb_desc);\n \n \tnix_dump(\" \\tpci_dev = %p\", nix->pci_dev);\n \tnix_dump(\" \\tbase = 0x%\" PRIxPTR \"\", nix->base);\n@@ -1206,12 +1209,24 @@ roc_nix_dump(struct roc_nix *roc_nix)\n \tnix_dump(\" \\ttx_link = %d\", nix->tx_link);\n \tnix_dump(\" \\tsqb_size = %d\", nix->sqb_size);\n \tnix_dump(\" \\tmsixoff = %d\", nix->msixoff);\n+\tfor (i = 0; i < nix->nb_cpt_lf; i++)\n+\t\tnix_dump(\" \\tcpt_msixoff[%d] = %d\", i, nix->cpt_msixoff[i]);\n \tnix_dump(\" \\tcints = %d\", nix->cints);\n \tnix_dump(\" \\tqints = %d\", nix->qints);\n \tnix_dump(\" \\tsdp_link = %d\", nix->sdp_link);\n \tnix_dump(\" \\tptp_en = %d\", nix->ptp_en);\n \tnix_dump(\" \\trss_alg_idx = %d\", nix->rss_alg_idx);\n \tnix_dump(\" \\ttx_pause = %d\", nix->tx_pause);\n+\tnix_dump(\" \\tinl_inb_ena = %d\", nix->inl_inb_ena);\n+\tnix_dump(\" \\tinl_outb_ena = %d\", nix->inl_outb_ena);\n+\tnix_dump(\" \\tinb_sa_base = 0x%p\", nix->inb_sa_base);\n+\tnix_dump(\" \\tinb_sa_sz = %\" PRIu64, nix->inb_sa_sz);\n+\tnix_dump(\" \\toutb_sa_base = 0x%p\", nix->outb_sa_base);\n+\tnix_dump(\" \\toutb_sa_sz = %\" PRIu64, nix->outb_sa_sz);\n+\tnix_dump(\" \\toutb_err_sso_pffunc = 0x%x\", nix->outb_err_sso_pffunc);\n+\tnix_dump(\" \\tcpt_lf_base = 0x%p\", nix->cpt_lf_base);\n+\tnix_dump(\" \\tnb_cpt_lf = %d\", nix->nb_cpt_lf);\n+\tnix_dump(\" \\tinb_inl_dev = %d\", nix->inb_inl_dev);\n }\n \n void\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nnew file mode 100644\nindex 0000000..1d962e3\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -0,0 +1,778 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ ==\n+\t\t 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2);\n+PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == 512);\n+PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ ==\n+\t\t 1UL << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2);\n+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==\n+\t\t 1UL << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2);\n+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);\n+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==\n+\t\t 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);\n+\n+static int\n+nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)\n+{\n+\tuint16_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct roc_nix_ipsec_cfg cfg;\n+\tsize_t inb_sa_sz;\n+\tint rc;\n+\n+\t/* CN9K SA size is different */\n+\tif (roc_model_is_cn9k())\n+\t\tinb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ;\n+\telse\n+\t\tinb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;\n+\n+\t/* Alloc contiguous memory for Inbound SA's */\n+\tnix->inb_sa_sz = inb_sa_sz;\n+\tnix->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,\n+\t\t\t\t ROC_NIX_INL_SA_BASE_ALIGN);\n+\tif (!nix->inb_sa_base) {\n+\t\tplt_err(\"Failed to allocate memory for Inbound SA\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tmemset(&cfg, 0, sizeof(cfg));\n+\tcfg.sa_size = inb_sa_sz;\n+\tcfg.iova = (uintptr_t)nix->inb_sa_base;\n+\tcfg.max_sa = ipsec_in_max_spi + 1;\n+\tcfg.tt = SSO_TT_ORDERED;\n+\n+\t/* Setup device specific inb SA table */\n+\trc = roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to setup NIX Inbound SA conf, rc=%d\", rc);\n+\t\tgoto free_mem;\n+\t}\n+\n+\treturn 0;\n+free_mem:\n+\tplt_free(nix->inb_sa_base);\n+\tnix->inb_sa_base = NULL;\n+\treturn rc;\n+}\n+\n+static int\n+nix_inl_sa_tbl_release(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint rc;\n+\n+\trc = roc_nix_lf_inl_ipsec_cfg(roc_nix, NULL, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to disable Inbound inline ipsec, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tplt_free(nix->inb_sa_base);\n+\tnix->inb_sa_base = NULL;\n+\treturn 0;\n+}\n+\n+struct roc_cpt_lf *\n+roc_nix_inl_outb_lf_base_get(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\t/* NIX Inline config needs to be done */\n+\tif (!nix->inl_outb_ena || !nix->cpt_lf_base)\n+\t\treturn NULL;\n+\n+\treturn (struct roc_cpt_lf *)nix->cpt_lf_base;\n+}\n+\n+uintptr_t\n+roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn (uintptr_t)nix->outb_sa_base;\n+}\n+\n+uintptr_t\n+roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\tif (!nix->inl_inb_ena)\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (inb_inl_dev) {\n+\t\t/* Return inline dev sa base */\n+\t\tif (inl_dev)\n+\t\t\treturn (uintptr_t)inl_dev->inb_sa_base;\n+\t\treturn 0;\n+\t}\n+\n+\treturn (uintptr_t)nix->inb_sa_base;\n+}\n+\n+uint32_t\n+roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\tif (!nix->inl_inb_ena)\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (inb_inl_dev) {\n+\t\tif (inl_dev)\n+\t\t\treturn inl_dev->ipsec_in_max_spi;\n+\t\treturn 0;\n+\t}\n+\n+\treturn roc_nix->ipsec_in_max_spi;\n+}\n+\n+uint32_t\n+roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\tif (!inl_dev_sa)\n+\t\treturn nix->inb_sa_sz;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (inl_dev_sa && inl_dev)\n+\t\treturn inl_dev->inb_sa_sz;\n+\n+\t/* On error */\n+\treturn 0;\n+}\n+\n+uintptr_t\n+roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)\n+{\n+\tuintptr_t sa_base;\n+\tuint32_t max_spi;\n+\tuint64_t sz;\n+\n+\tsa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev);\n+\t/* Check if SA base exists */\n+\tif (!sa_base)\n+\t\treturn 0;\n+\n+\t/* Check if SPI is in range */\n+\tmax_spi = roc_nix_inl_inb_sa_max_spi(roc_nix, inb_inl_dev);\n+\tif (spi > max_spi) {\n+\t\tplt_err(\"Inbound SA SPI %u exceeds max %u\", spi, max_spi);\n+\t\treturn 0;\n+\t}\n+\n+\t/* Get SA size */\n+\tsz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev);\n+\tif (!sz)\n+\t\treturn 0;\n+\n+\t/* Basic logic of SPI->SA for now */\n+\treturn (sa_base + (spi * sz));\n+}\n+\n+int\n+roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct roc_cpt *roc_cpt;\n+\tuint16_t param1;\n+\tint rc;\n+\n+\tif (idev == NULL)\n+\t\treturn -ENOTSUP;\n+\n+\t/* Unless we have another mechanism to trigger\n+\t * onetime Inline config in CPTPF, we cannot\n+\t * support without CPT being probed.\n+\t */\n+\troc_cpt = idev->cpt;\n+\tif (!roc_cpt) {\n+\t\tplt_err(\"Cannot support inline inbound, cryptodev not probed\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tparam1 = ROC_ONF_IPSEC_INB_MAX_L2_SZ;\n+\t} else {\n+\t\tunion roc_ot_ipsec_inb_param1 u;\n+\n+\t\tu.u16 = 0;\n+\t\tu.s.esp_trailer_disable = 1;\n+\t\tparam1 = u.u16;\n+\t}\n+\n+\t/* Do onetime Inbound Inline config in CPTPF */\n+\trc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, 0);\n+\tif (rc && rc != -EEXIST) {\n+\t\tplt_err(\"Failed to setup inbound lf, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Setup Inbound SA table */\n+\trc = nix_inl_inb_sa_tbl_setup(roc_nix);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->inl_inb_ena = true;\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_inl_inb_fini(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (!nix->inl_inb_ena)\n+\t\treturn 0;\n+\n+\tnix->inl_inb_ena = false;\n+\n+\t/* Disable Inbound SA */\n+\treturn nix_inl_sa_tbl_release(roc_nix);\n+}\n+\n+int\n+roc_nix_inl_outb_init(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct roc_cpt_lf *lf_base, *lf;\n+\tstruct dev *dev = &nix->dev;\n+\tstruct msix_offset_rsp *rsp;\n+\tstruct nix_inl_dev *inl_dev;\n+\tuint16_t sso_pffunc;\n+\tuint8_t eng_grpmask;\n+\tuint64_t blkaddr;\n+\tuint16_t nb_lf;\n+\tvoid *sa_base;\n+\tsize_t sa_sz;\n+\tint i, j, rc;\n+\n+\tif (idev == NULL)\n+\t\treturn -ENOTSUP;\n+\n+\tnb_lf = roc_nix->outb_nb_crypto_qs;\n+\tblkaddr = nix->is_nix1 ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;\n+\n+\t/* Retrieve inline device if present */\n+\tinl_dev = idev->nix_inl_dev;\n+\tsso_pffunc = inl_dev ? inl_dev->dev.pf_func : idev_sso_pffunc_get();\n+\tif (!sso_pffunc) {\n+\t\tplt_err(\"Failed to setup inline outb, need either \"\n+\t\t\t\"inline device or sso device\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/* Attach CPT LF for outbound */\n+\trc = cpt_lfs_attach(dev, blkaddr, true, nb_lf);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to attach CPT LF for inline outb, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Alloc CPT LF */\n+\teng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |\n+\t\t 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |\n+\t\t 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);\n+\trc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to alloc CPT LF resources, rc=%d\", rc);\n+\t\tgoto lf_detach;\n+\t}\n+\n+\t/* Get msix offsets */\n+\trc = cpt_get_msix_offset(dev, &rsp);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to get CPT LF msix offset, rc=%d\", rc);\n+\t\tgoto lf_free;\n+\t}\n+\n+\tmbox_memcpy(nix->cpt_msixoff,\n+\t\t nix->is_nix1 ? rsp->cpt1_lf_msixoff : rsp->cptlf_msixoff,\n+\t\t sizeof(nix->cpt_msixoff));\n+\n+\t/* Alloc required num of cpt lfs */\n+\tlf_base = plt_zmalloc(nb_lf * sizeof(struct roc_cpt_lf), 0);\n+\tif (!lf_base) {\n+\t\tplt_err(\"Failed to alloc cpt lf memory\");\n+\t\trc = -ENOMEM;\n+\t\tgoto lf_free;\n+\t}\n+\n+\t/* Initialize CPT LF's */\n+\tfor (i = 0; i < nb_lf; i++) {\n+\t\tlf = &lf_base[i];\n+\n+\t\tlf->lf_id = i;\n+\t\tlf->nb_desc = roc_nix->outb_nb_desc;\n+\t\tlf->dev = &nix->dev;\n+\t\tlf->msixoff = nix->cpt_msixoff[i];\n+\t\tlf->pci_dev = nix->pci_dev;\n+\n+\t\t/* Setup CPT LF instruction queue */\n+\t\trc = cpt_lf_init(lf);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to initialize CPT LF, rc=%d\", rc);\n+\t\t\tgoto lf_fini;\n+\t\t}\n+\n+\t\t/* Associate this CPT LF with NIX PFFUNC */\n+\t\trc = cpt_lf_outb_cfg(dev, sso_pffunc, nix->dev.pf_func, i,\n+\t\t\t\t true);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to setup CPT LF->(NIX,SSO) link, rc=%d\",\n+\t\t\t\trc);\n+\t\t\tgoto lf_fini;\n+\t\t}\n+\n+\t\t/* Enable IQ */\n+\t\troc_cpt_iq_enable(lf);\n+\t}\n+\n+\tif (!roc_nix->ipsec_out_max_sa)\n+\t\tgoto skip_sa_alloc;\n+\n+\t/* CN9K SA size is different */\n+\tif (roc_model_is_cn9k())\n+\t\tsa_sz = ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ;\n+\telse\n+\t\tsa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;\n+\t/* Alloc contiguous memory of outbound SA */\n+\tsa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,\n+\t\t\t ROC_NIX_INL_SA_BASE_ALIGN);\n+\tif (!sa_base) {\n+\t\tplt_err(\"Outbound SA base alloc failed\");\n+\t\tgoto lf_fini;\n+\t}\n+\tnix->outb_sa_base = sa_base;\n+\tnix->outb_sa_sz = sa_sz;\n+\n+skip_sa_alloc:\n+\n+\tnix->cpt_lf_base = lf_base;\n+\tnix->nb_cpt_lf = nb_lf;\n+\tnix->outb_err_sso_pffunc = sso_pffunc;\n+\tnix->inl_outb_ena = true;\n+\treturn 0;\n+\n+lf_fini:\n+\tfor (j = i - 1; j >= 0; j--)\n+\t\tcpt_lf_fini(&lf_base[j]);\n+\tplt_free(lf_base);\n+lf_free:\n+\trc |= cpt_lfs_free(dev);\n+lf_detach:\n+\trc |= cpt_lfs_detach(dev);\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_inl_outb_fini(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct roc_cpt_lf *lf_base = nix->cpt_lf_base;\n+\tstruct dev *dev = &nix->dev;\n+\tint i, rc, ret = 0;\n+\n+\tif (!nix->inl_outb_ena)\n+\t\treturn 0;\n+\n+\tnix->inl_outb_ena = false;\n+\n+\t/* Cleanup CPT LF instruction queue */\n+\tfor (i = 0; i < nix->nb_cpt_lf; i++)\n+\t\tcpt_lf_fini(&lf_base[i]);\n+\n+\t/* Free LF resources */\n+\trc = cpt_lfs_free(dev);\n+\tif (rc)\n+\t\tplt_err(\"Failed to free CPT LF resources, rc=%d\", rc);\n+\tret |= rc;\n+\n+\t/* Detach LF */\n+\trc = cpt_lfs_detach(dev);\n+\tif (rc)\n+\t\tplt_err(\"Failed to detach CPT LF, rc=%d\", rc);\n+\n+\t/* Free LF memory */\n+\tplt_free(lf_base);\n+\tnix->cpt_lf_base = NULL;\n+\tnix->nb_cpt_lf = 0;\n+\n+\t/* Free outbound SA base */\n+\tplt_free(nix->outb_sa_base);\n+\tnix->outb_sa_base = NULL;\n+\n+\tret |= rc;\n+\treturn ret;\n+}\n+\n+bool\n+roc_nix_inl_dev_is_probed(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\treturn !!idev->nix_inl_dev;\n+}\n+\n+bool\n+roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->inl_inb_ena;\n+}\n+\n+bool\n+roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->inl_outb_ena;\n+}\n+\n+int\n+roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\tstruct roc_nix_rq *inl_rq;\n+\tstruct dev *dev;\n+\tint rc;\n+\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\t/* Nothing to do if no inline device */\n+\tif (!inl_dev)\n+\t\treturn 0;\n+\n+\t/* Just take reference if already inited */\n+\tif (inl_dev->rq_refs) {\n+\t\tinl_dev->rq_refs++;\n+\t\trq->inl_dev_ref = true;\n+\t\treturn 0;\n+\t}\n+\n+\tdev = &inl_dev->dev;\n+\tinl_rq = &inl_dev->rq;\n+\tmemset(inl_rq, 0, sizeof(struct roc_nix_rq));\n+\n+\t/* Take RQ pool attributes from the first ethdev RQ */\n+\tinl_rq->qid = 0;\n+\tinl_rq->aura_handle = rq->aura_handle;\n+\tinl_rq->first_skip = rq->first_skip;\n+\tinl_rq->later_skip = rq->later_skip;\n+\tinl_rq->lpb_size = rq->lpb_size;\n+\n+\tif (!roc_model_is_cn9k()) {\n+\t\tuint64_t aura_limit =\n+\t\t\troc_npa_aura_op_limit_get(inl_rq->aura_handle);\n+\t\tuint64_t aura_shift = plt_log2_u32(aura_limit);\n+\n+\t\tif (aura_shift < 8)\n+\t\t\taura_shift = 0;\n+\t\telse\n+\t\t\taura_shift = aura_shift - 8;\n+\n+\t\t/* Set first pass RQ to drop when half of the buffers are in\n+\t\t * use to avoid metabuf alloc failure. This is needed as long\n+\t\t * as we cannot use different\n+\t\t */\n+\t\tinl_rq->red_pass = (aura_limit / 2) >> aura_shift;\n+\t\tinl_rq->red_drop = ((aura_limit / 2) - 1) >> aura_shift;\n+\t}\n+\n+\t/* Enable IPSec */\n+\tinl_rq->ipsech_ena = true;\n+\n+\tinl_rq->flow_tag_width = 20;\n+\t/* Special tag mask */\n+\tinl_rq->tag_mask = 0xFFF00000;\n+\tinl_rq->tt = SSO_TT_ORDERED;\n+\tinl_rq->hwgrp = 0;\n+\tinl_rq->wqe_skip = 1;\n+\tinl_rq->sso_ena = true;\n+\n+\t/* Prepare and send RQ init mbox */\n+\tif (roc_model_is_cn9k())\n+\t\trc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, true);\n+\telse\n+\t\trc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to prepare aq_enq msg, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to send aq_enq msg, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tinl_dev->rq_refs++;\n+\trq->inl_dev_ref = true;\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\tstruct roc_nix_rq *inl_rq;\n+\tstruct dev *dev;\n+\tint rc;\n+\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\tif (!rq->inl_dev_ref)\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\t/* Inline device should be there if we have ref */\n+\tif (!inl_dev) {\n+\t\tplt_err(\"Failed to find inline device with refs\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\trq->inl_dev_ref = false;\n+\tinl_dev->rq_refs--;\n+\tif (inl_dev->rq_refs)\n+\t\treturn 0;\n+\n+\tdev = &inl_dev->dev;\n+\tinl_rq = &inl_dev->rq;\n+\t/* There are no more references, disable RQ */\n+\trc = nix_rq_ena_dis(dev, inl_rq, false);\n+\tif (rc)\n+\t\tplt_err(\"Failed to disable inline device rq, rc=%d\", rc);\n+\n+\t/* Flush NIX LF for CN10K */\n+\tif (roc_model_is_cn10k())\n+\t\tplt_write64(0, inl_dev->nix_base + NIX_LF_OP_VWQE_FLUSH);\n+\n+\treturn rc;\n+}\n+\n+uint64_t\n+roc_nix_inl_dev_rq_limit_get(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\tstruct roc_nix_rq *inl_rq;\n+\n+\tif (!idev || !idev->nix_inl_dev)\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (!inl_dev->rq_refs)\n+\t\treturn 0;\n+\n+\tinl_rq = &inl_dev->rq;\n+\n+\treturn roc_npa_aura_op_limit_get(inl_rq->aura_handle);\n+}\n+\n+void\n+roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\t/* Info used by NPC flow rule add */\n+\tnix->inb_inl_dev = use_inl_dev;\n+}\n+\n+bool\n+roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->inb_inl_dev;\n+}\n+\n+struct roc_nix_rq *\n+roc_nix_inl_dev_rq(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev != NULL) {\n+\t\tinl_dev = idev->nix_inl_dev;\n+\t\tif (inl_dev != NULL && inl_dev->rq_refs)\n+\t\t\treturn &inl_dev->rq;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+uint16_t __roc_api\n+roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->outb_err_sso_pffunc;\n+}\n+\n+int\n+roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev == NULL)\n+\t\treturn -EIO;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (!inl_dev)\n+\t\treturn -EIO;\n+\n+\t/* Be silent if registration called with same cb and args */\n+\tif (inl_dev->work_cb == cb && inl_dev->cb_args == args)\n+\t\treturn 0;\n+\n+\t/* Don't allow registration again if registered with different cb */\n+\tif (inl_dev->work_cb)\n+\t\treturn -EBUSY;\n+\n+\tinl_dev->work_cb = cb;\n+\tinl_dev->cb_args = args;\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb, void *args)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev == NULL)\n+\t\treturn -ENOENT;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (!inl_dev)\n+\t\treturn -ENOENT;\n+\n+\tif (inl_dev->work_cb != cb || inl_dev->cb_args != args)\n+\t\treturn -EINVAL;\n+\n+\tinl_dev->work_cb = NULL;\n+\tinl_dev->cb_args = NULL;\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const,\n+\t\t\t uint8_t tt)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct roc_nix_ipsec_cfg cfg;\n+\n+\t/* Be silent if inline inbound not enabled */\n+\tif (!nix->inl_inb_ena)\n+\t\treturn 0;\n+\n+\tmemset(&cfg, 0, sizeof(cfg));\n+\tcfg.sa_size = nix->inb_sa_sz;\n+\tcfg.iova = (uintptr_t)nix->inb_sa_base;\n+\tcfg.max_sa = roc_nix->ipsec_in_max_spi + 1;\n+\tcfg.tt = tt;\n+\tcfg.tag_const = tag_const;\n+\n+\treturn roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);\n+}\n+\n+int\n+roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,\n+\t\t enum roc_nix_inl_sa_sync_op op)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct roc_cpt_lf *outb_lf = nix->cpt_lf_base;\n+\tunion cpt_lf_ctx_reload reload;\n+\tunion cpt_lf_ctx_flush flush;\n+\tuintptr_t rbase;\n+\n+\t/* Nothing much to do on cn9k */\n+\tif (roc_model_is_cn9k()) {\n+\t\tplt_atomic_thread_fence(__ATOMIC_ACQ_REL);\n+\t\treturn 0;\n+\t}\n+\n+\tif (!inb && !outb_lf)\n+\t\treturn -EINVAL;\n+\n+\t/* Performing op via outbound lf is enough\n+\t * when inline dev is not in use.\n+\t */\n+\tif (outb_lf && !nix->inb_inl_dev) {\n+\t\trbase = outb_lf->rbase;\n+\n+\t\tflush.u = 0;\n+\t\treload.u = 0;\n+\t\tswitch (op) {\n+\t\tcase ROC_NIX_INL_SA_OP_FLUSH_INVAL:\n+\t\t\tflush.s.inval = 1;\n+\t\t\t/* fall through */\n+\t\tcase ROC_NIX_INL_SA_OP_FLUSH:\n+\t\t\tflush.s.cptr = ((uintptr_t)sa) >> 7;\n+\t\t\tplt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH);\n+\t\t\tbreak;\n+\t\tcase ROC_NIX_INL_SA_OP_RELOAD:\n+\t\t\treload.s.cptr = ((uintptr_t)sa) >> 7;\n+\t\t\tplt_write64(reload.u, rbase + CPT_LF_CTX_RELOAD);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTSUP;\n+}\n+\n+void\n+roc_nix_inl_dev_lock(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\n+\tif (idev != NULL)\n+\t\tplt_spinlock_lock(&idev->nix_inl_dev_lock);\n+}\n+\n+void\n+roc_nix_inl_dev_unlock(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\n+\tif (idev != NULL)\n+\t\tplt_spinlock_unlock(&idev->nix_inl_dev_lock);\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 1b3aab0..6b8c268 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -43,6 +43,62 @@\n /* Alignment of SA Base */\n #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)\n \n+static inline struct roc_onf_ipsec_inb_sa *\n+roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx)\n+{\n+\tuint64_t off = idx << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2;\n+\n+\treturn PLT_PTR_ADD(base, off);\n+}\n+\n+static inline struct roc_onf_ipsec_outb_sa *\n+roc_nix_inl_onf_ipsec_outb_sa(uintptr_t base, uint64_t idx)\n+{\n+\tuint64_t off = idx << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2;\n+\n+\treturn PLT_PTR_ADD(base, off);\n+}\n+\n+static inline void *\n+roc_nix_inl_onf_ipsec_inb_sa_sw_rsvd(void *sa)\n+{\n+\treturn PLT_PTR_ADD(sa, ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ);\n+}\n+\n+static inline void *\n+roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd(void *sa)\n+{\n+\treturn PLT_PTR_ADD(sa, ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ);\n+}\n+\n+static inline struct roc_ot_ipsec_inb_sa *\n+roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx)\n+{\n+\tuint64_t off = idx << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2;\n+\n+\treturn PLT_PTR_ADD(base, off);\n+}\n+\n+static inline struct roc_ot_ipsec_outb_sa *\n+roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx)\n+{\n+\tuint64_t off = idx << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2;\n+\n+\treturn PLT_PTR_ADD(base, off);\n+}\n+\n+static inline void *\n+roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void *sa)\n+{\n+\treturn PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_INB_HW_SZ);\n+}\n+\n+static inline void *\n+roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa)\n+{\n+\treturn PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ);\n+}\n+\n /* Inline device SSO Work callback */\n typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);\n \n@@ -62,5 +118,50 @@ struct roc_nix_inl_dev {\n int __roc_api roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev);\n int __roc_api roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev);\n void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);\n+bool __roc_api roc_nix_inl_dev_is_probed(void);\n+void __roc_api roc_nix_inl_dev_lock(void);\n+void __roc_api roc_nix_inl_dev_unlock(void);\n+\n+/* NIX Inline Inbound API */\n+int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);\n+bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);\n+uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,\n+\t\t\t\t\t\tbool inl_dev_sa);\n+uint32_t __roc_api roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix,\n+\t\t\t\t\t bool inl_dev_sa);\n+uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix,\n+\t\t\t\t\t bool inl_dev_sa);\n+uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix,\n+\t\t\t\t\t bool inl_dev_sa, uint32_t spi);\n+void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev);\n+int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq);\n+int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq);\n+bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix);\n+struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(void);\n+int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix,\n+\t\t\t\t\t uint32_t tag_const, uint8_t tt);\n+uint64_t __roc_api roc_nix_inl_dev_rq_limit_get(void);\n+\n+/* NIX Inline Outbound API */\n+int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_inl_outb_fini(struct roc_nix *roc_nix);\n+bool __roc_api roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix);\n+uintptr_t __roc_api roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix);\n+struct roc_cpt_lf *__roc_api\n+roc_nix_inl_outb_lf_base_get(struct roc_nix *roc_nix);\n+uint16_t __roc_api roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args);\n+int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb,\n+\t\t\t\t\tvoid *args);\n+/* NIX Inline/Outbound API */\n+enum roc_nix_inl_sa_sync_op {\n+\tROC_NIX_INL_SA_OP_FLUSH,\n+\tROC_NIX_INL_SA_OP_FLUSH_INVAL,\n+\tROC_NIX_INL_SA_OP_RELOAD,\n+};\n+\n+int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,\n+\t\t\t\t enum roc_nix_inl_sa_sync_op op);\n \n #endif /* _ROC_NIX_INL_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 0cabcd2..13867b9 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -163,6 +163,21 @@ struct nix {\n \tuint16_t tm_link_cfg_lvl;\n \tuint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];\n \tuint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];\n+\n+\t/* Ipsec info */\n+\tuint16_t cpt_msixoff[MAX_RVU_BLKLF_CNT];\n+\tbool inl_inb_ena;\n+\tbool inl_outb_ena;\n+\tvoid *inb_sa_base;\n+\tsize_t inb_sa_sz;\n+\tvoid *outb_sa_base;\n+\tsize_t outb_sa_sz;\n+\tuint16_t outb_err_sso_pffunc;\n+\tstruct roc_cpt_lf *cpt_lf_base;\n+\tuint16_t nb_cpt_lf;\n+\t/* Mode provided by driver */\n+\tbool inb_inl_dev;\n+\n } __plt_cache_aligned;\n \n enum nix_err_status {\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex cff0ec3..41e8f2c 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -131,11 +131,11 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n \n \t/* If RED enabled, then fill enable for all cases */\n \tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n-\t\taq->rq.spb_aura_pass = rq->spb_red_pass;\n-\t\taq->rq.lpb_aura_pass = rq->red_pass;\n+\t\taq->rq.spb_pool_pass = rq->spb_red_pass;\n+\t\taq->rq.lpb_pool_pass = rq->red_pass;\n \n-\t\taq->rq.spb_aura_drop = rq->spb_red_drop;\n-\t\taq->rq.lpb_aura_drop = rq->red_drop;\n+\t\taq->rq.spb_pool_drop = rq->spb_red_drop;\n+\t\taq->rq.lpb_pool_drop = rq->red_drop;\n \t}\n \n \tif (cfg) {\n@@ -176,11 +176,11 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n \t\taq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;\n \n \t\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n-\t\t\taq->rq_mask.spb_aura_pass = ~aq->rq_mask.spb_aura_pass;\n-\t\t\taq->rq_mask.lpb_aura_pass = ~aq->rq_mask.lpb_aura_pass;\n+\t\t\taq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;\n+\t\t\taq->rq_mask.lpb_pool_pass = ~aq->rq_mask.lpb_pool_pass;\n \n-\t\t\taq->rq_mask.spb_aura_drop = ~aq->rq_mask.spb_aura_drop;\n-\t\t\taq->rq_mask.lpb_aura_drop = ~aq->rq_mask.lpb_aura_drop;\n+\t\t\taq->rq_mask.spb_pool_drop = ~aq->rq_mask.spb_pool_drop;\n+\t\t\taq->rq_mask.lpb_pool_drop = ~aq->rq_mask.lpb_pool_drop;\n \t\t}\n \t}\n \n@@ -276,17 +276,13 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \n \t/* If RED enabled, then fill enable for all cases */\n \tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n-\t\taq->rq.spb_pool_pass = rq->red_pass;\n-\t\taq->rq.spb_aura_pass = rq->red_pass;\n+\t\taq->rq.spb_pool_pass = rq->spb_red_pass;\n \t\taq->rq.lpb_pool_pass = rq->red_pass;\n-\t\taq->rq.lpb_aura_pass = rq->red_pass;\n \t\taq->rq.wqe_pool_pass = rq->red_pass;\n \t\taq->rq.xqe_pass = rq->red_pass;\n \n-\t\taq->rq.spb_pool_drop = rq->red_drop;\n-\t\taq->rq.spb_aura_drop = rq->red_drop;\n+\t\taq->rq.spb_pool_drop = rq->spb_red_drop;\n \t\taq->rq.lpb_pool_drop = rq->red_drop;\n-\t\taq->rq.lpb_aura_drop = rq->red_drop;\n \t\taq->rq.wqe_pool_drop = rq->red_drop;\n \t\taq->rq.xqe_drop = rq->red_drop;\n \t}\n@@ -346,16 +342,12 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \n \t\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n \t\t\taq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;\n-\t\t\taq->rq_mask.spb_aura_pass = ~aq->rq_mask.spb_aura_pass;\n \t\t\taq->rq_mask.lpb_pool_pass = ~aq->rq_mask.lpb_pool_pass;\n-\t\t\taq->rq_mask.lpb_aura_pass = ~aq->rq_mask.lpb_aura_pass;\n \t\t\taq->rq_mask.wqe_pool_pass = ~aq->rq_mask.wqe_pool_pass;\n \t\t\taq->rq_mask.xqe_pass = ~aq->rq_mask.xqe_pass;\n \n \t\t\taq->rq_mask.spb_pool_drop = ~aq->rq_mask.spb_pool_drop;\n-\t\t\taq->rq_mask.spb_aura_drop = ~aq->rq_mask.spb_aura_drop;\n \t\t\taq->rq_mask.lpb_pool_drop = ~aq->rq_mask.lpb_pool_drop;\n-\t\t\taq->rq_mask.lpb_aura_drop = ~aq->rq_mask.lpb_aura_drop;\n \t\t\taq->rq_mask.wqe_pool_drop = ~aq->rq_mask.wqe_pool_drop;\n \t\t\taq->rq_mask.xqe_drop = ~aq->rq_mask.xqe_drop;\n \t\t}\ndiff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c\nindex 52a54b3..047b969 100644\n--- a/drivers/common/cnxk/roc_npc.c\n+++ b/drivers/common/cnxk/roc_npc.c\n@@ -340,10 +340,11 @@ roc_npc_fini(struct roc_npc *roc_npc)\n }\n \n static int\n-npc_parse_actions(struct npc *npc, const struct roc_npc_attr *attr,\n+npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,\n \t\t const struct roc_npc_action actions[],\n \t\t struct roc_npc_flow *flow)\n {\n+\tstruct npc *npc = roc_npc_to_npc_priv(roc_npc);\n \tconst struct roc_npc_action_mark *act_mark;\n \tconst struct roc_npc_action_queue *act_q;\n \tconst struct roc_npc_action_vf *vf_act;\n@@ -425,15 +426,16 @@ npc_parse_actions(struct npc *npc, const struct roc_npc_attr *attr,\n \t\t\t * NPC_SECURITY_ACTION_TYPE_INLINE_PROTOCOL &&\n \t\t\t * session_protocol ==\n \t\t\t * NPC_SECURITY_PROTOCOL_IPSEC\n-\t\t\t *\n-\t\t\t * RSS is not supported with inline ipsec. Get the\n-\t\t\t * rq from associated conf, or make\n-\t\t\t * ROC_NPC_ACTION_TYPE_QUEUE compulsory with this\n-\t\t\t * action.\n-\t\t\t * Currently, rq = 0 is assumed.\n \t\t\t */\n \t\t\treq_act |= ROC_NPC_ACTION_TYPE_SEC;\n \t\t\trq = 0;\n+\n+\t\t\t/* Special processing when with inline device */\n+\t\t\tif (roc_nix_inb_is_with_inl_dev(roc_npc->roc_nix) &&\n+\t\t\t roc_nix_inl_dev_is_probed()) {\n+\t\t\t\trq = 0;\n+\t\t\t\tpf_func = nix_inl_dev_pffunc_get();\n+\t\t\t}\n \t\t\tbreak;\n \t\tcase ROC_NPC_ACTION_TYPE_VLAN_STRIP:\n \t\t\treq_act |= ROC_NPC_ACTION_TYPE_VLAN_STRIP;\n@@ -677,11 +679,12 @@ npc_parse_attr(struct npc *npc, const struct roc_npc_attr *attr,\n }\n \n static int\n-npc_parse_rule(struct npc *npc, const struct roc_npc_attr *attr,\n+npc_parse_rule(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,\n \t const struct roc_npc_item_info pattern[],\n \t const struct roc_npc_action actions[], struct roc_npc_flow *flow,\n \t struct npc_parse_state *pst)\n {\n+\tstruct npc *npc = roc_npc_to_npc_priv(roc_npc);\n \tint err;\n \n \t/* Check attr */\n@@ -695,7 +698,7 @@ npc_parse_rule(struct npc *npc, const struct roc_npc_attr *attr,\n \t\treturn err;\n \n \t/* Check action */\n-\terr = npc_parse_actions(npc, attr, actions, flow);\n+\terr = npc_parse_actions(roc_npc, attr, actions, flow);\n \tif (err)\n \t\treturn err;\n \treturn 0;\n@@ -711,7 +714,8 @@ roc_npc_flow_parse(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,\n \tstruct npc_parse_state parse_state = {0};\n \tint rc;\n \n-\trc = npc_parse_rule(npc, attr, pattern, actions, flow, &parse_state);\n+\trc = npc_parse_rule(roc_npc, attr, pattern, actions, flow,\n+\t\t\t &parse_state);\n \tif (rc)\n \t\treturn rc;\n \n@@ -1191,7 +1195,8 @@ roc_npc_flow_create(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,\n \t}\n \tmemset(flow, 0, sizeof(*flow));\n \n-\trc = npc_parse_rule(npc, attr, pattern, actions, flow, &parse_state);\n+\trc = npc_parse_rule(roc_npc, attr, pattern, actions, flow,\n+\t\t\t &parse_state);\n \tif (rc != 0) {\n \t\t*errcode = rc;\n \t\tgoto err_exit;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 3256aeb..0ea3cbd 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -100,9 +100,35 @@ INTERNAL {\n \troc_nix_get_pf_func;\n \troc_nix_get_vf;\n \troc_nix_get_vwqe_interval;\n+\troc_nix_inl_cb_register;\n+\troc_nix_inl_cb_unregister;\n \troc_nix_inl_dev_dump;\n \troc_nix_inl_dev_fini;\n \troc_nix_inl_dev_init;\n+\troc_nix_inl_dev_is_probed;\n+\troc_nix_inl_dev_lock;\n+\troc_nix_inl_dev_unlock;\n+\troc_nix_inl_dev_rq;\n+\troc_nix_inl_dev_rq_get;\n+\troc_nix_inl_dev_rq_put;\n+\troc_nix_inl_dev_rq_limit_get;\n+\troc_nix_inl_inb_is_enabled;\n+\troc_nix_inl_inb_init;\n+\troc_nix_inl_inb_sa_base_get;\n+\troc_nix_inl_inb_sa_get;\n+\troc_nix_inl_inb_sa_max_spi;\n+\troc_nix_inl_inb_sa_sz;\n+\troc_nix_inl_inb_tag_update;\n+\troc_nix_inl_inb_fini;\n+\troc_nix_inb_is_with_inl_dev;\n+\troc_nix_inb_mode_set;\n+\troc_nix_inl_outb_fini;\n+\troc_nix_inl_outb_init;\n+\troc_nix_inl_outb_lf_base_get;\n+\troc_nix_inl_outb_sa_base_get;\n+\troc_nix_inl_outb_sso_pffunc_get;\n+\troc_nix_inl_outb_is_enabled;\n+\troc_nix_inl_sa_sync;\n \troc_nix_is_lbk;\n \troc_nix_is_pf;\n \troc_nix_is_sdp;\n", "prefixes": [ "v2", "07/28" ] }