[V2] pipeline: remove limitation on number of input ports

Message ID 20240214205836.1561803-1-cristian.dumitrescu@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series [V2] pipeline: remove limitation on number of input ports |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/github-robot: build success github build: passed
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/intel-Functional success Functional PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-abi-testing success Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-unit-arm64-testing success Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
ci/iol-compile-arm64-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-sample-apps-testing success Testing PASS

Commit Message

Cristian Dumitrescu Feb. 14, 2024, 8:58 p.m. UTC
  Removed the requirement that the number of pipeline input ports be a
power of 2, which is problematic for many real life use-cases. Also
adding checks for the output port validity used for sending the
current packet.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---
 lib/pipeline/rte_swx_pipeline.c          |  1 -
 lib/pipeline/rte_swx_pipeline_internal.h | 38 ++++++++++++++++++++----
 2 files changed, 33 insertions(+), 6 deletions(-)
  

Comments

Thomas Monjalon Feb. 18, 2024, 11:48 p.m. UTC | #1
14/02/2024 21:58, Cristian Dumitrescu:
> Removed the requirement that the number of pipeline input ports be a
> power of 2, which is problematic for many real life use-cases. Also
> adding checks for the output port validity used for sending the
> current packet.
> 
> Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>

Applied, thanks.
  

Patch

diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c
index 147c1c2ad4..6ba86bee1f 100644
--- a/lib/pipeline/rte_swx_pipeline.c
+++ b/lib/pipeline/rte_swx_pipeline.c
@@ -340,7 +340,6 @@  port_in_build(struct rte_swx_pipeline *p)
 	uint32_t i;
 
 	CHECK(p->n_ports_in, EINVAL);
-	CHECK(rte_is_power_of_2(p->n_ports_in), EINVAL);
 
 	for (i = 0; i < p->n_ports_in; i++)
 		CHECK(port_in_find(p, i), EINVAL);
diff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h
index f5a64e0fe1..8b3e79e8fe 100644
--- a/lib/pipeline/rte_swx_pipeline_internal.h
+++ b/lib/pipeline/rte_swx_pipeline_internal.h
@@ -1612,7 +1612,13 @@  struct rte_swx_pipeline {
 static inline void
 pipeline_port_inc(struct rte_swx_pipeline *p)
 {
-	p->port_id = (p->port_id + 1) & (p->n_ports_in - 1);
+	uint32_t port_id = p->port_id;
+
+	port_id++;
+	if (port_id == p->n_ports_in)
+		port_id = 0;
+
+	p->port_id = port_id;
 }
 
 static inline void
@@ -1825,9 +1831,9 @@  mirroring_handler(struct rte_swx_pipeline *p, struct thread *t, struct rte_swx_p
 static inline void
 __instr_tx_exec(struct rte_swx_pipeline *p, struct thread *t, const struct instruction *ip)
 {
-	uint64_t port_id = METADATA_READ(t, ip->io.io.offset, ip->io.io.n_bits);
-	struct port_out_runtime *port = &p->out[port_id];
 	struct rte_swx_pkt *pkt = &t->pkt;
+	struct port_out_runtime *port;
+	uint64_t port_id;
 
 	/* Recirculation: keep the current packet. */
 	if (t->recirculate) {
@@ -1843,6 +1849,15 @@  __instr_tx_exec(struct rte_swx_pipeline *p, struct thread *t, const struct instr
 		return;
 	}
 
+	/* If the output port ID is invalid, then set it to the drop output port that has been set
+	 * up internally by the pipeline for this purpose.
+	 */
+	port_id = METADATA_READ(t, ip->io.io.offset, ip->io.io.n_bits);
+	if (port_id >= p->n_ports_out)
+		port_id = p->n_ports_out - 1;
+
+	port = &p->out[port_id];
+
 	TRACE("[Thread %2u]: tx 1 pkt to port %u\n",
 	      p->thread_id,
 	      (uint32_t)port_id);
@@ -1858,9 +1873,9 @@  __instr_tx_exec(struct rte_swx_pipeline *p, struct thread *t, const struct instr
 static inline void
 __instr_tx_i_exec(struct rte_swx_pipeline *p, struct thread *t, const struct instruction *ip)
 {
-	uint64_t port_id = ip->io.io.val;
-	struct port_out_runtime *port = &p->out[port_id];
 	struct rte_swx_pkt *pkt = &t->pkt;
+	struct port_out_runtime *port;
+	uint64_t port_id;
 
 	/* Recirculation: keep the current packet. */
 	if (t->recirculate) {
@@ -1876,6 +1891,19 @@  __instr_tx_i_exec(struct rte_swx_pipeline *p, struct thread *t, const struct ins
 		return;
 	}
 
+	/* If the output port ID is invalid, then set it to the drop output port that has been set
+	 * up internally by the pipeline for this purpose.
+	 *
+	 * This test cannot be done earlier at instruction translation time, even though the output
+	 * port ID is an immediate value, as the number of output ports is only known later at the
+	 * pipeline build time.
+	 */
+	port_id = ip->io.io.val;
+	if (port_id >= p->n_ports_out)
+		port_id = p->n_ports_out - 1;
+
+	port = &p->out[port_id];
+
 	TRACE("[Thread %2u]: tx (i) 1 pkt to port %u\n",
 	      p->thread_id,
 	      (uint32_t)port_id);