diff mbox series

[01/12] eal: introduce more macro for bit definition

Message ID	20240122035802.31491-2-fengchengwen@huawei.com (mailing list archive)
State	Superseded, archived
Delegated to:	Thomas Monjalon
Headers	From: Chengwen Feng <fengchengwen@huawei.com> To: <dev@dpdk.org>, <thomas@monjalon.net>, <ferruh.yigit@amd.com>, <stephen@networkplumber.org> CC: <tangkunshan@huawei.com> Subject: [PATCH 01/12] eal: introduce more macro for bit definition Date: Mon, 22 Jan 2024 03:57:51 +0000 Message-ID: <20240122035802.31491-2-fengchengwen@huawei.com> In-Reply-To: <20240122035802.31491-1-fengchengwen@huawei.com> References: <20231121122651.7078-1-fengchengwen@huawei.com> <20240122035802.31491-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	add argparse library \| [00/12] add argparse library [01/12] eal: introduce more macro for bit definition [02/12] argparse: add argparse library [03/12] argparse: support verify argument config [04/12] test/argparse: add verify argument config test [05/12] argparse: support parse parameters [06/12] test/argparse: add parse parameters test [07/12] argparse: provide parsing known type API [08/12] test/argparse: add parse type test [09/12] argparse: support parse unsigned base type [10/12] test/argparse: add parse unsigned base type test [11/12] argparse: pretty help info [12/12] examples/dma: replace getopt with argparse

Checks

Context	Check	Description
ci/checkpatch	warning	coding style issues

Commit Message

fengchengwen Jan. 22, 2024, 3:57 a.m. UTC

  Introduce macros: RTE_MBIT64/RTE_MBIT32, RTE_GENMASK64/RTE_GENMASK32,
and RTE_FIELD_GET64/RTE_FIELD_GET32.

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
 lib/eal/include/rte_bitops.h | 64 ++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

Comments

Thomas Monjalon Jan. 24, 2024, 1 p.m. UTC | #1

22/01/2024 04:57, Chengwen Feng:
> Introduce macros: RTE_MBIT64/RTE_MBIT32, RTE_GENMASK64/RTE_GENMASK32,
> and RTE_FIELD_GET64/RTE_FIELD_GET32.

A bit of context and description would help.

> +/**
> + * Get the uint64_t value for a multiple bits set.
> + *
> + * @param val
> + *   The value may not all 1s.
> + * @param nr
> + *   The bit number in range of 0 to (64 - width of val).
> + */
> +#define RTE_MBIT64(val, nr) (UINT64_C(val) << (nr))

I don't understand this macro.
I think you mean that val is shifted by nr.
Please revise the description.

diff mbox series

Patch

diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h
index 6bd8bae21a..e1f3c4b195 100644
--- a/lib/eal/include/rte_bitops.h
+++ b/lib/eal/include/rte_bitops.h
@@ -39,6 +39,70 @@  extern "C" {
  */
 #define RTE_BIT32(nr) (UINT32_C(1) << (nr))
 
+/**
+ * Get the uint64_t value for a multiple bits set.
+ *
+ * @param val
+ *   The value may not all 1s.
+ * @param nr
+ *   The bit number in range of 0 to (64 - width of val).
+ */
+#define RTE_MBIT64(val, nr) (UINT64_C(val) << (nr))
+
+/**
+ * Get the uint32_t value for a multiple bits set.
+ *
+ * @param val
+ *   The value may not all 1s.
+ * @param nr
+ *   The bit number in range of 0 to (32 - width of val).
+ */
+#define RTE_MBIT32(val, nr) (UINT32_C(val) << (nr))
+
+/**
+ * Generate a contiguous 64bit bitmask starting at bit position low
+ * and ending at position high.
+ *
+ * @param high
+ *   High bit position.
+ * @param low
+ *   Low bit position.
+ */
+#define RTE_GENMASK64(high, low) (((~UINT64_C(0)) << (low)) & (~UINT64_C(0) >> (63u - (high))))
+
+/**
+ * Generate a contiguous 32bit bitmask starting at bit position low
+ * and ending at position high.
+ *
+ * @param high
+ *   High bit position.
+ * @param low
+ *   Low bit position.
+ */
+#define RTE_GENMASK32(high, low) (((~UINT32_C(0)) << (low)) & (~UINT32_C(0) >> (31u - (high))))
+
+/**
+ * Extract a 64bit field element.
+ *
+ * @param mask
+ *   shifted mask.
+ * @param reg
+ *   value of entire bitfield.
+ */
+#define RTE_FIELD_GET64(mask, reg) \
+		(typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask))
+
+/**
+ * Extract a 32bit field element.
+ *
+ * @param mask
+ *   shifted mask.
+ * @param reg
+ *   value of entire bitfield.
+ */
+#define RTE_FIELD_GET32(mask, reg) \
+		(typeof(mask))(((reg) & (mask)) >> rte_ctz32(mask))
+
 /*------------------------ 32-bit relaxed operations ------------------------*/
 
 /**