diff mbox series

[1/5] net/mlx5/hws: add support for matching on bth_a bit

Message ID 20230918120705.265025-1-igozlan@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series [1/5] net/mlx5/hws: add support for matching on bth_a bit |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Itamar Gozlan Sept. 18, 2023, 12:07 p.m. UTC 
  RTE_FLOW_ITEM_TYPE_IB_BTH matches an InfiniBand base transport
header. We extend the match on the acknowledgment bit (BTH_A).

Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 12 ++++++++++--
 drivers/net/mlx5/hws/mlx5dr_definer.h |  1 +
 2 files changed, 11 insertions(+), 2 deletions(-)

Comments

Matan Azrad Oct. 9, 2023, 7:57 a.m. UTC | #1 
> RTE_FLOW_ITEM_TYPE_IB_BTH matches an InfiniBand base transport header.
> We extend the match on the acknowledgment bit (BTH_A).
> 
> Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>

Series-acked-by: Matan Azrad <matan@nvidia.com>

> ---
>  drivers/net/mlx5/hws/mlx5dr_definer.c | 12 ++++++++++--
> drivers/net/mlx5/hws/mlx5dr_definer.h |  1 +
>  2 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c
> b/drivers/net/mlx5/hws/mlx5dr_definer.c
> index 33d0f2d18e..b82af9d102 100644
> --- a/drivers/net/mlx5/hws/mlx5dr_definer.c
> +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
> @@ -177,7 +177,8 @@ struct mlx5dr_definer_conv_data {
>  	X(SET_BE32,     ipsec_spi,              v->hdr.spi,             rte_flow_item_esp) \
>  	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,
> rte_flow_item_esp) \
>  	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,
> 	rte_flow_item_ib_bth) \
> -	X(SET,		ib_l4_opcode,		v->hdr.opcode,
> 	rte_flow_item_ib_bth)
> +	X(SET,		ib_l4_opcode,		v->hdr.opcode,
> 	rte_flow_item_ib_bth) \
> +	X(SET,		ib_l4_bth_a,		v->hdr.a,
> 	rte_flow_item_ib_bth) \
> 
>  /* Item set function format */
>  #define X(set_type, func_name, value, item_type) \ @@ -2148,7 +2149,7 @@
> mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,
> 
>  	if (m->hdr.se || m->hdr.m || m->hdr.padcnt || m->hdr.tver ||
>  		m->hdr.pkey || m->hdr.f || m->hdr.b || m->hdr.rsvd0 ||
> -		m->hdr.a || m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {
> +		m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {
>  		rte_errno = ENOTSUP;
>  		return rte_errno;
>  	}
> @@ -2167,6 +2168,13 @@ mlx5dr_definer_conv_item_ib_l4(struct
> mlx5dr_definer_conv_data *cd,
>  		DR_CALC_SET_HDR(fc, ib_l4, qp);
>  	}
> 
> +	if (m->hdr.a) {
> +		fc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_A];
> +		fc->item_idx = item_idx;
> +		fc->tag_set = &mlx5dr_definer_ib_l4_bth_a_set;
> +		DR_CALC_SET_HDR(fc, ib_l4, ackreq);
> +	}
> +
>  	return 0;
>  }
> 
> diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h
> b/drivers/net/mlx5/hws/mlx5dr_definer.h
> index 6b645f4cf0..bf026fa6bb 100644
> --- a/drivers/net/mlx5/hws/mlx5dr_definer.h
> +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
> @@ -136,6 +136,7 @@ enum mlx5dr_definer_fname {
>  	MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,
>  	MLX5DR_DEFINER_FNAME_IB_L4_OPCODE,
>  	MLX5DR_DEFINER_FNAME_IB_L4_QPN,
> +	MLX5DR_DEFINER_FNAME_IB_L4_A,
>  	MLX5DR_DEFINER_FNAME_MAX,
>  };
> 
> --
> 2.38.1
Raslan Darawsheh Oct. 10, 2023, 9:33 a.m. UTC | #2 
Hi,

> -----Original Message-----
> From: Itamar Gozlan <igozlan@nvidia.com>
> Sent: Monday, September 18, 2023 3:07 PM
> To: Alex Vesker <valex@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> <thomas@monjalon.net>; Suanming Mou <suanmingm@nvidia.com>; Matan
> Azrad <matan@nvidia.com>; Ori Kam <orika@nvidia.com>
> Cc: dev@dpdk.org
> Subject: [PATCH 1/5] net/mlx5/hws: add support for matching on bth_a bit
> 
> RTE_FLOW_ITEM_TYPE_IB_BTH matches an InfiniBand base transport header.
> We extend the match on the acknowledgment bit (BTH_A).
> 
> Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>

Series applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 33d0f2d18e..b82af9d102 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -177,7 +177,8 @@  struct mlx5dr_definer_conv_data {
 	X(SET_BE32,     ipsec_spi,              v->hdr.spi,             rte_flow_item_esp) \
 	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,             rte_flow_item_esp) \
 	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,	rte_flow_item_ib_bth) \
-	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth)
+	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth) \
+	X(SET,		ib_l4_bth_a,		v->hdr.a,		rte_flow_item_ib_bth) \
 
 /* Item set function format */
 #define X(set_type, func_name, value, item_type) \
@@ -2148,7 +2149,7 @@  mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,
 
 	if (m->hdr.se || m->hdr.m || m->hdr.padcnt || m->hdr.tver ||
 		m->hdr.pkey || m->hdr.f || m->hdr.b || m->hdr.rsvd0 ||
-		m->hdr.a || m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {
+		m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {
 		rte_errno = ENOTSUP;
 		return rte_errno;
 	}
@@ -2167,6 +2168,13 @@  mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,
 		DR_CALC_SET_HDR(fc, ib_l4, qp);
 	}
 
+	if (m->hdr.a) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_A];
+		fc->item_idx = item_idx;
+		fc->tag_set = &mlx5dr_definer_ib_l4_bth_a_set;
+		DR_CALC_SET_HDR(fc, ib_l4, ackreq);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 6b645f4cf0..bf026fa6bb 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -136,6 +136,7 @@  enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,
 	MLX5DR_DEFINER_FNAME_IB_L4_OPCODE,
 	MLX5DR_DEFINER_FNAME_IB_L4_QPN,
+	MLX5DR_DEFINER_FNAME_IB_L4_A,
 	MLX5DR_DEFINER_FNAME_MAX,
 };