diff mbox series

[v16,1/8] net/ntnic: initial commit which adds register defines

Message ID 20230908160715.2498821-1-mko-plv@napatech.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers
Series [v16,1/8] net/ntnic: initial commit which adds register defines |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Mykola Kostenok Sept. 8, 2023, 4:07 p.m. UTC 
  From: Christian Koue Muf <ckm@napatech.com>

The NTNIC PMD does not rely on a kernel space Napatech driver,
thus all defines related to the register layout is part of the PMD
code, which will be added in later commits.

Signed-off-by: Christian Koue Muf <ckm@napatech.com>
Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
---
v3:
* Fixed not needed cflags as suggested in comments.
v5:
* Disable build for unsupported platforms.
v7:
* Update unsupported platforms.
v10:
* Update FPGA register defines.
v13:
* Fix typo spelling warnings
v15:
* Update FPGA register defines.
---
 drivers/net/meson.build                       |    1 +
 drivers/net/ntnic/include/fpga_model.h        |   99 +
 drivers/net/ntnic/meson.build                 |   30 +
 drivers/net/ntnic/nthw/nthw_register.h        |   19 +
 .../supported/nthw_fpga_9563_055_024_0000.c   | 4190 ++++++++++
 .../nthw/supported/nthw_fpga_instances.h      |   14 +
 .../nthw/supported/nthw_fpga_modules_defs.h   |  166 +
 .../supported/nthw_fpga_parameters_defs.h     |  209 +
 .../nthw/supported/nthw_fpga_registers_defs.h | 7277 +++++++++++++++++
 9 files changed, 12005 insertions(+)
 create mode 100644 drivers/net/ntnic/include/fpga_model.h
 create mode 100644 drivers/net/ntnic/meson.build
 create mode 100644 drivers/net/ntnic/nthw/nthw_register.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h

Comments

Ferruh Yigit Sept. 15, 2023, 3:54 p.m. UTC | #1 
On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
> From: Christian Koue Muf <ckm@napatech.com>
> 
> The NTNIC PMD does not rely on a kernel space Napatech driver,
> thus all defines related to the register layout is part of the PMD
> code, which will be added in later commits.
> 
> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>

Hi Mykola, Christiam,

This PMD scares me, overall it is a big drop:
"249 files changed, 87128 insertions(+)"

I think it is not possible to review all in one release cycle, and it is
not even possible to say if all code used or not.

I can see code is already developed, and it is difficult to restructure
developed code, but restructure it into small pieces really helps for
reviews.


Driver supports good list of features, can it be possible to distribute
upstream effort into multiple release.
Starting from basic functionality and add features gradually.
Target for this release can be providing datapath, and add more if we
have time in the release, what do you think?


Also there are large amount of base code (HAL / FPGA code), instead of
adding them as a bulk, relevant ones with a feature can be added with
the feature patch, this eliminates dead code in the base code layer,
also helps user/review to understand the link between driver code and
base code.


As far as I understand last patch opens a socket interface and an
external application can sent control commands via this interface.
I am not sure about this side control channel, what is missing in the
DPDK API? Can we try to address them in the DPDK layer instead of a
driver specific solution?


Thanks,
ferruh
Morten Brørup Sept. 15, 2023, 6:37 p.m. UTC | #2 
> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
> Sent: Friday, 15 September 2023 17.55
> 
> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
> > From: Christian Koue Muf <ckm@napatech.com>
> >
> > The NTNIC PMD does not rely on a kernel space Napatech driver,
> > thus all defines related to the register layout is part of the PMD
> > code, which will be added in later commits.
> >
> > Signed-off-by: Christian Koue Muf <ckm@napatech.com>
> > Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
> >
> 
> Hi Mykola, Christiam,
> 
> This PMD scares me, overall it is a big drop:
> "249 files changed, 87128 insertions(+)"
> 
> I think it is not possible to review all in one release cycle, and it is
> not even possible to say if all code used or not.
> 
> I can see code is already developed, and it is difficult to restructure
> developed code, but restructure it into small pieces really helps for
> reviews.
> 
> 
> Driver supports good list of features, can it be possible to distribute
> upstream effort into multiple release.
> Starting from basic functionality and add features gradually.
> Target for this release can be providing datapath, and add more if we
> have time in the release, what do you think?
> 
> 
> Also there are large amount of base code (HAL / FPGA code), instead of
> adding them as a bulk, relevant ones with a feature can be added with
> the feature patch, this eliminates dead code in the base code layer,
> also helps user/review to understand the link between driver code and
> base code.

Jumping in here with an opinion about welcoming new NIC vendors to the community:

Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.

If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.

We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.

> 
> 
> As far as I understand last patch opens a socket interface and an
> external application can sent control commands via this interface.
> I am not sure about this side control channel, what is missing in the
> DPDK API? Can we try to address them in the DPDK layer instead of a
> driver specific solution?

That would be great.

AFAIK, other vendors also has a bunch of out-of-band communication, e.g. magical EAL parameters to the MLX drivers. So let's not be too hard on the newcomers. ;-)

> 
> 
> Thanks,
> ferruh

Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!

Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.

-Morten
Ferruh Yigit Sept. 18, 2023, 9:33 a.m. UTC | #3 
On 9/15/2023 7:37 PM, Morten Brørup wrote:
>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>> Sent: Friday, 15 September 2023 17.55
>>
>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>> From: Christian Koue Muf <ckm@napatech.com>
>>>
>>> The NTNIC PMD does not rely on a kernel space Napatech driver,
>>> thus all defines related to the register layout is part of the PMD
>>> code, which will be added in later commits.
>>>
>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>
>>
>> Hi Mykola, Christiam,
>>
>> This PMD scares me, overall it is a big drop:
>> "249 files changed, 87128 insertions(+)"
>>
>> I think it is not possible to review all in one release cycle, and it is
>> not even possible to say if all code used or not.
>>
>> I can see code is already developed, and it is difficult to restructure
>> developed code, but restructure it into small pieces really helps for
>> reviews.
>>
>>
>> Driver supports good list of features, can it be possible to distribute
>> upstream effort into multiple release.
>> Starting from basic functionality and add features gradually.
>> Target for this release can be providing datapath, and add more if we
>> have time in the release, what do you think?
>>
>>
>> Also there are large amount of base code (HAL / FPGA code), instead of
>> adding them as a bulk, relevant ones with a feature can be added with
>> the feature patch, this eliminates dead code in the base code layer,
>> also helps user/review to understand the link between driver code and
>> base code.
> 
> Jumping in here with an opinion about welcoming new NIC vendors to the community:
> 
> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
> 
> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
> 

Hi Morten,

I was thinking same before making my above comment, what happens if
vendors submit as one big patch and when a problem occurs we can ask
owner to fix. Probably this makes vendor happy and makes my life (or any
other maintainer's life) easier, it is always easier to say yes.


But I come up with two main reasons to ask for a rework:

1- Technically any vendor can deliver their software to their customers
via a public git repository, they don't have to upstream to dpdk.org,
but upstreaming has many benefits.

One of those benefits is upstreaming provides a quality assurance for
vendor's customers (that is why customer can be asking for this, as we
are having in many cases), and this quality assurance comes from
additional eyes reviewing the code and guiding vendors for the DPDK
quality standards (some vendors already doing pretty good, but new ones
sometimes requires hand-holding).

If driver is one big patch series, it is practically not possible to
review it, I can catch a few bits here or there, you may some others,
but practically it will be merged without review, and we will fail on
our quality assurance task.

2- Make code more accessible to the rest of the world.

When it is a big patch, code can be functional but lots of details,
reasoning, relation between components gets lost, which makes it even
harder for an external developer, like me, to understand it (I am a mere
guinea pig here :).

If a customer would like to add a feature themselves, or fix something,
even after vendor no more working on that product anymore, customer
needs to understand the code or some reasoning in the code.
Or if someone wants to backport the driver to rust, or a DPDK developer
wants to do a rework that requires updating all drivers, or a tester
would like to analyze the code to figure out behavior difference of the
devices. I think I have witness all above cases in real life.

If driver is split into more patches, it makes patch easier to
understand which makes code practically more accessible to other
developers that are not expert in driver.


Overall, yes splitting patch takes time and effort, and yes this is an
overhead for a code that is already developed, but I think benefit is
big so it worth doing the task.


> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
> 

Agree to not make upstreaming difficult for new vendors, and indeed we
are encouraging more vendors to be upstream their code, this is in best
interest of both sides.

Distributing upstreaming effort to a year was just a suggestion, it can
go in earlier as it is becomes ready but I can see it will take time to
split driver into features and upstream them.

As I am from a vendor too, I can understand the product/customer
pressure, but I hope this approach can encourage vendors start
upstreaming early or even better upstream as they develop the code.


>>
>>
>> As far as I understand last patch opens a socket interface and an
>> external application can sent control commands via this interface.
>> I am not sure about this side control channel, what is missing in the
>> DPDK API? Can we try to address them in the DPDK layer instead of a
>> driver specific solution?
> 
> That would be great.
> 
> AFAIK, other vendors also has a bunch of out-of-band communication, e.g. magical EAL parameters to the MLX drivers. So let's not be too hard on the newcomers. ;-)
> 

I did some thinking for this one too,

As we are in userspace, it is easy to have side control channel, and
this can make users life easy, so this is a practical thing to do.
(Indeed there are already some ways to do this, without PMD exposing a
socket interface.)

But this also reduces effort developers putting on DPDK layer solution,
because it is always easier to add more support to the driver only.
And overall this reduces portability of the DPDK application, each
application becomes unique to a device (This is a bad thing, but I also
need some feedback how bad it is in real life.)

To balance this, we said if a feature is too specific to a device, it
can add device specific API and this is better than device specific
features pollute the common, most used code. And push back to introduce
more new PMD specific APIs unless it is really needed.

But creating a socket interface directly from the driver is more than
PMD specific API. Technically application control interface can rely
completely to this. Even we assume this is not for control, but just for
debug, I can see it can be useful for debug and again practical thing to
do, I am still not sure how much it hurts if each driver has a custom
socket interface for their debug needs.

Overall it makes more sense to me to have a unified/common interface
from drivers to DPDK applications, which is through the ethdev layer.
And improve and extend the ethdev layer to satisfy driver needs.

In this specific example, I am for rejecting the socket interface patch,
but I would like to get more feedback from @techboard.


And related to not being too hard on the newcomers, unrelated to being a
newcomer or not, if a process/feature/approach approved once, some
others will point to it and will ask to do the same which is fair in
their perspective. I had multiple instance of this in the past.

Of course we are being easy to newcomers but not in a way to allow code
that we believe is not good thing to do, but going easy on process may be :)


>>
>>
>> Thanks,
>> ferruh
> 
> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
> 
> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
> 
> -Morten
>
Christian Koue Muf Sept. 19, 2023, 9:06 a.m. UTC | #4 
On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>On 9/15/2023 7:37 PM, Morten Brørup wrote:
>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>>> Sent: Friday, 15 September 2023 17.55
>>>
>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>>> From: Christian Koue Muf <ckm@napatech.com>
>>>>
>>>> The NTNIC PMD does not rely on a kernel space Napatech driver, thus 
>>>> all defines related to the register layout is part of the PMD code, 
>>>> which will be added in later commits.
>>>>
>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>>
>>>
>>> Hi Mykola, Christiam,
>>>
>>> This PMD scares me, overall it is a big drop:
>>> "249 files changed, 87128 insertions(+)"
>>>
>>> I think it is not possible to review all in one release cycle, and it 
>>> is not even possible to say if all code used or not.
>>>
>>> I can see code is already developed, and it is difficult to 
>>> restructure developed code, but restructure it into small pieces 
>>> really helps for reviews.
>>>
>>>
>>> Driver supports good list of features, can it be possible to 
>>> distribute upstream effort into multiple release.
>>> Starting from basic functionality and add features gradually.
>>> Target for this release can be providing datapath, and add more if we 
>>> have time in the release, what do you think?
>>>
>>>
>>> Also there are large amount of base code (HAL / FPGA code), instead 
>>> of adding them as a bulk, relevant ones with a feature can be added 
>>> with the feature patch, this eliminates dead code in the base code 
>>> layer, also helps user/review to understand the link between driver 
>>> code and base code.
>> 
>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>> 
>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>> 
>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>> 
>
>Hi Morten,
>
>I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>
>
>But I come up with two main reasons to ask for a rework:
>
>1- Technically any vendor can deliver their software to their customers via a public git repository, they don't have to upstream to https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E,1,NpoJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9bOLlnhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>but upstreaming has many benefits.
>
>One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>
>If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>
>2- Make code more accessible to the rest of the world.
>
>When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>
>If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>
>If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
>
>
>Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
>
>
>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
>> 
>
>Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>
>Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
>
>As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.

Hi Ferruh,

First of all, thank you for starting the work to review our code.

As Morten said Napatech plans to take all responsibility for the
quality of the PMD source code. We expect to provide all fixes
needed in the future. If for some reason Napatech stops maintaining
the code, then we have been informed that the DPDK community
might delete the PMD from the repository, and we understand that.

In regards to splitting the code, I don't see this a good option. While
I of cause agree it would be easier to review and understand, the
code should also result in a meaningful product. Of the 87k lines
of code, 53k lines is needed to start-up the FPGA to a state the it is ready
to receive traffic. But at this point all packets would simply be discarded,
and to be honest, there are better and cheaper options out there,
if nothing more than basic functionality is needed. 34k lines are
used to setup filters based on rte_flow. The thing is, that you need
to initialize all modules in the FPGA TX- and RX-pipelines with valid
data, even if you don't need the features those modules provide.
As a result, if you split up the 34k lines, then the product would not
be functional. Of cause some of the top level logic could be split out,
but at this point we are talking about splitting 87k lines into 80k and 7k,
which I don't think is worth it.

>>>
>>>
>>> As far as I understand last patch opens a socket interface and an 
>>> external application can sent control commands via this interface.
>>> I am not sure about this side control channel, what is missing in the 
>>> DPDK API? Can we try to address them in the DPDK layer instead of a 
>>> driver specific solution?
>> 
>> That would be great.
>> 
>> AFAIK, other vendors also has a bunch of out-of-band communication, 
>> e.g. magical EAL parameters to the MLX drivers. So let's not be too 
>> hard on the newcomers. ;-)
>> 
>
>I did some thinking for this one too,
>
>As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>(Indeed there are already some ways to do this, without PMD exposing a socket interface.)
>
>But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>And overall this reduces portability of the DPDK application, each application becomes unique to a device (This is a bad thing, but I also need some feedback how bad it is in real life.)
>
>To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>
>But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>
>Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>And improve and extend the ethdev layer to satisfy driver needs.
>
>In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>

The reason we have the addition control channel is not provide
additional functionality. We have customers with use-cases that
require multiple processes. Since Napatech adapters do not support
configuration through VFs, then secondary applications must send
their rte_flow to a main application, which will then setup the flow
through it's PF. This control channel "hides" these details, and
make the product easier for users to adapt to their existing solutions.

If you stand firm on rejecting the control channel, then we have
to go back to the drawing board on this issue. We did look at
DPDK's multi-process support, and actually had some support
for this, but we determined that for our use-case it was better
to have a communication channel, and no shared memory.

>
>And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>
>Of course we are being easy to newcomers but not in a way to allow code that we believe is not good thing to do, but going easy on process may be :)
>

We are grateful for any leniency you may show us ;-)

Thanks again,
Christian

>
>>>
>>>
>>> Thanks,
>>> ferruh
>> 
>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>> 
>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>> 
>> -Morten
>>
Ferruh Yigit Sept. 20, 2023, 9:48 a.m. UTC | #5 
On 9/19/2023 10:06 AM, Christian Koue Muf wrote:
> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>>>> Sent: Friday, 15 September 2023 17.55
>>>>
>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>>>> From: Christian Koue Muf <ckm@napatech.com>
>>>>>
>>>>> The NTNIC PMD does not rely on a kernel space Napatech driver, thus
>>>>> all defines related to the register layout is part of the PMD code,
>>>>> which will be added in later commits.
>>>>>
>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>>>
>>>>
>>>> Hi Mykola, Christiam,
>>>>
>>>> This PMD scares me, overall it is a big drop:
>>>> "249 files changed, 87128 insertions(+)"
>>>>
>>>> I think it is not possible to review all in one release cycle, and it
>>>> is not even possible to say if all code used or not.
>>>>
>>>> I can see code is already developed, and it is difficult to
>>>> restructure developed code, but restructure it into small pieces
>>>> really helps for reviews.
>>>>
>>>>
>>>> Driver supports good list of features, can it be possible to
>>>> distribute upstream effort into multiple release.
>>>> Starting from basic functionality and add features gradually.
>>>> Target for this release can be providing datapath, and add more if we
>>>> have time in the release, what do you think?
>>>>
>>>>
>>>> Also there are large amount of base code (HAL / FPGA code), instead
>>>> of adding them as a bulk, relevant ones with a feature can be added
>>>> with the feature patch, this eliminates dead code in the base code
>>>> layer, also helps user/review to understand the link between driver
>>>> code and base code.
>>>
>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>>>
>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>>>
>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>>>
>>
>> Hi Morten,
>>
>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>>
>>
>> But I come up with two main reasons to ask for a rework:
>>
>> 1- Technically any vendor can deliver their software to their customers via a public git repository, they don't have to upstream to https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E,1,NpoJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9bOLlnhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>> but upstreaming has many benefits.
>>
>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>>
>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>>
>> 2- Make code more accessible to the rest of the world.
>>
>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>>
>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>>
>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
>>
>>
>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
>>
>>
>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
>>>
>>
>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>>
>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
>>
>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
> 
> Hi Ferruh,
> 
> First of all, thank you for starting the work to review our code.
> 
> As Morten said Napatech plans to take all responsibility for the
> quality of the PMD source code. We expect to provide all fixes
> needed in the future. If for some reason Napatech stops maintaining
> the code, then we have been informed that the DPDK community
> might delete the PMD from the repository, and we understand that.
> 

Deleting PMD is easy, maintaining it when company is not around is a
challenge.


> In regards to splitting the code, I don't see this a good option. While
> I of cause agree it would be easier to review and understand, the
> code should also result in a meaningful product. Of the 87k lines
> of code, 53k lines is needed to start-up the FPGA to a state the it is ready
> to receive traffic. But at this point all packets would simply be discarded,
> and to be honest, there are better and cheaper options out there,
> if nothing more than basic functionality is needed. 34k lines are
> used to setup filters based on rte_flow. The thing is, that you need
> to initialize all modules in the FPGA TX- and RX-pipelines with valid
> data, even if you don't need the features those modules provide.
> As a result, if you split up the 34k lines, then the product would not
> be functional. Of cause some of the top level logic could be split out,
> but at this point we are talking about splitting 87k lines into 80k and 7k,
> which I don't think is worth it.
> 

We had similar code base in DPDK before, heavy and multi-platform
supported HAL layer approach is not unique to this drier, we can figure
out details and can find a sweat spot for the case.


>>>>
>>>>
>>>> As far as I understand last patch opens a socket interface and an
>>>> external application can sent control commands via this interface.
>>>> I am not sure about this side control channel, what is missing in the
>>>> DPDK API? Can we try to address them in the DPDK layer instead of a
>>>> driver specific solution?
>>>
>>> That would be great.
>>>
>>> AFAIK, other vendors also has a bunch of out-of-band communication,
>>> e.g. magical EAL parameters to the MLX drivers. So let's not be too
>>> hard on the newcomers. ;-)
>>>
>>
>> I did some thinking for this one too,
>>
>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>> (Indeed there are already some ways to do this, without PMD exposing a socket interface.)
>>
>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>> And overall this reduces portability of the DPDK application, each application becomes unique to a device (This is a bad thing, but I also need some feedback how bad it is in real life.)
>>
>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>>
>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>>
>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>> And improve and extend the ethdev layer to satisfy driver needs.
>>
>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>>
> 
> The reason we have the addition control channel is not provide
> additional functionality. We have customers with use-cases that
> require multiple processes. Since Napatech adapters do not support
> configuration through VFs, then secondary applications must send
> their rte_flow to a main application, which will then setup the flow
> through it's PF. This control channel "hides" these details, and
> make the product easier for users to adapt to their existing solutions.
> 
> If you stand firm on rejecting the control channel, then we have
> to go back to the drawing board on this issue. We did look at
> DPDK's multi-process support, and actually had some support
> for this, but we determined that for our use-case it was better
> to have a communication channel, and no shared memory.
> 

This is about individual drivers have custom interface for the specific
application needs, or they use common interfaces.
And how much custom interfaces hurts in long run. A wider discussion.

Like if you want to use your device and VFs by OvS, how you will do it
with this specific interface?


And specific to this driver,
if it is about primary/secondary process communication, as you mentioned
there is already a socket interface for it.

Or did you investigate VF representors, does it work for this case?

Another common approach is VF-PF mailbox communication that VF passes
requests to the PF in device, of course this requires device/FW support.


>>
>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>>
>> Of course we are being easy to newcomers but not in a way to allow code that we believe is not good thing to do, but going easy on process may be :)
>>
> 
> We are grateful for any leniency you may show us ;-)
> 
> Thanks again,
> Christian
> 
>>
>>>>
>>>>
>>>> Thanks,
>>>> ferruh
>>>
>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>>>
>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>>>
>>> -Morten
>>>
> Disclaimer: This email and any files transmitted with it may contain confidential information intended for the addressee(s) only. The information is not to be surrendered or copied to unauthorized persons. If you have received this communication in error, please notify the sender immediately and delete this e-mail from your system.
Thomas Monjalon Sept. 20, 2023, 1:17 p.m. UTC | #6 
Hello,

19/09/2023 11:06, Christian Koue Muf:
> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
> >On 9/15/2023 7:37 PM, Morten Brørup wrote:
> >>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
> >>> Sent: Friday, 15 September 2023 17.55
> >>>
> >>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
> >>>> From: Christian Koue Muf <ckm@napatech.com>
> >>>>
> >>>> The NTNIC PMD does not rely on a kernel space Napatech driver, thus 
> >>>> all defines related to the register layout is part of the PMD code, 
> >>>> which will be added in later commits.
> >>>>
> >>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
> >>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
> >>>>
> >>>
> >>> Hi Mykola, Christiam,
> >>>
> >>> This PMD scares me, overall it is a big drop:
> >>> "249 files changed, 87128 insertions(+)"
> >>>
> >>> I think it is not possible to review all in one release cycle, and it 
> >>> is not even possible to say if all code used or not.
> >>>
> >>> I can see code is already developed, and it is difficult to 
> >>> restructure developed code, but restructure it into small pieces 
> >>> really helps for reviews.
> >>>
> >>>
> >>> Driver supports good list of features, can it be possible to 
> >>> distribute upstream effort into multiple release.
> >>> Starting from basic functionality and add features gradually.
> >>> Target for this release can be providing datapath, and add more if we 
> >>> have time in the release, what do you think?

I was expecting to get only Rx/Tx in this release, not really more.

I agree it may be interesting to discuss some design
and check whether we need more features in ethdev
as part of the driver upstreaming process.


> >>> Also there are large amount of base code (HAL / FPGA code), instead 
> >>> of adding them as a bulk, relevant ones with a feature can be added 
> >>> with the feature patch, this eliminates dead code in the base code 
> >>> layer, also helps user/review to understand the link between driver 
> >>> code and base code.

Yes it would be interesting to see what is really needed for the basic initialization
and what is linked to a specific offload or configuration feature.

As a maintainer, I have to do some changes across all drivers sometimes,
and I use git blame a lot to understand why something was added.


> >> Jumping in here with an opinion about welcoming new NIC vendors to the community:
> >> 
> >> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
> >> 
> >> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
> >> 
> >
> >Hi Morten,
> >
> >I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
> >
> >
> >But I come up with two main reasons to ask for a rework:
> >
> >1- Technically any vendor can deliver their software to their customers via a public git repository, they don't have to upstream to https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E,1,NpoJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9bOLlnhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
> >but upstreaming has many benefits.
> >
> >One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
> >
> >If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
> >
> >2- Make code more accessible to the rest of the world.
> >
> >When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
> >
> >If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
> >Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
> >
> >If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.

I fully agree about the 2 reasons for upstreaming piece by piece.


> >Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.

In the meantime, if some features are not yet upstreamed in a release,
a user can apply the missing patches from the mailing list to get the features.


> >> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.

You're right Morten, we try to be as welcoming as possible,
but as Ferruh said, we want to be able to understand how a driver is built,
even if not understanding all details.

In Open Source, I think not only the code should be available,
we must also take care of explanations and documentation.


> >Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
> >
> >Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.

Driver features can be added until -rc2 (in one month).


> >As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
> 
> Hi Ferruh,
> 
> First of all, thank you for starting the work to review our code.
> 
> As Morten said Napatech plans to take all responsibility for the
> quality of the PMD source code. We expect to provide all fixes
> needed in the future. If for some reason Napatech stops maintaining
> the code, then we have been informed that the DPDK community
> might delete the PMD from the repository, and we understand that.
> 
> In regards to splitting the code, I don't see this a good option. While
> I of cause agree it would be easier to review and understand, the
> code should also result in a meaningful product. Of the 87k lines
> of code, 53k lines is needed to start-up the FPGA to a state the it is ready
> to receive traffic. But at this point all packets would simply be discarded,
> and to be honest, there are better and cheaper options out there,
> if nothing more than basic functionality is needed. 34k lines are
> used to setup filters based on rte_flow. The thing is, that you need
> to initialize all modules in the FPGA TX- and RX-pipelines with valid
> data, even if you don't need the features those modules provide.
> As a result, if you split up the 34k lines, then the product would not
> be functional. Of cause some of the top level logic could be split out,
> but at this point we are talking about splitting 87k lines into 80k and 7k,
> which I don't think is worth it.

Actually I think it is worth.
There is a benefit in isolating the small basic init part
from the more complex features.


> >>> As far as I understand last patch opens a socket interface and an 
> >>> external application can sent control commands via this interface.
> >>> I am not sure about this side control channel, what is missing in the 
> >>> DPDK API? Can we try to address them in the DPDK layer instead of a 
> >>> driver specific solution?
> >> 
> >> That would be great.
> >> 
> >> AFAIK, other vendors also has a bunch of out-of-band communication, 
> >> e.g. magical EAL parameters to the MLX drivers. So let's not be too 
> >> hard on the newcomers. ;-)
> >> 
> >
> >I did some thinking for this one too,
> >
> >As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
> >(Indeed there are already some ways to do this, without PMD exposing a socket interface.)
> >
> >But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
> >And overall this reduces portability of the DPDK application, each application becomes unique to a device (This is a bad thing, but I also need some feedback how bad it is in real life.)
> >
> >To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
> >
> >But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
> >
> >Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
> >And improve and extend the ethdev layer to satisfy driver needs.
> >
> >In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
> >
> 
> The reason we have the addition control channel is not provide
> additional functionality. We have customers with use-cases that
> require multiple processes. Since Napatech adapters do not support
> configuration through VFs, then secondary applications must send
> their rte_flow to a main application, which will then setup the flow
> through it's PF. This control channel "hides" these details, and
> make the product easier for users to adapt to their existing solutions.

I think you need to explore VF representors.
This is what is done with other drivers, and it make them compatible.

> If you stand firm on rejecting the control channel, then we have
> to go back to the drawing board on this issue. We did look at
> DPDK's multi-process support, and actually had some support
> for this, but we determined that for our use-case it was better
> to have a communication channel, and no shared memory.

I'm not sure your need is about secondary process.
Let's discuss this need in a meeting if needed.
Anyway, the message is that we want to be part of such design decision.


> >And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
> >
> >Of course we are being easy to newcomers but not in a way to allow code that we believe is not good thing to do, but going easy on process may be :)
> >
> 
> We are grateful for any leniency you may show us ;-)
> 
> Thanks again,
> Christian
> 
> >
> >>>
> >>>
> >>> Thanks,
> >>> ferruh
> >> 
> >> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
> >> 
> >> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
> >> 
> >> -Morten


We are going to discuss the process in the technical board today.
Ferruh Yigit Sept. 21, 2023, 2:04 p.m. UTC | #7 
On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
> Hello,
> 
> 19/09/2023 11:06, Christian Koue Muf:
>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>>>>> Sent: Friday, 15 September 2023 17.55
>>>>>
>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>>>>> From: Christian Koue Muf <ckm@napatech.com>
>>>>>>
>>>>>> The NTNIC PMD does not rely on a kernel space Napatech driver, thus 
>>>>>> all defines related to the register layout is part of the PMD code, 
>>>>>> which will be added in later commits.
>>>>>>
>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>>>>
>>>>>
>>>>> Hi Mykola, Christiam,
>>>>>
>>>>> This PMD scares me, overall it is a big drop:
>>>>> "249 files changed, 87128 insertions(+)"
>>>>>
>>>>> I think it is not possible to review all in one release cycle, and it 
>>>>> is not even possible to say if all code used or not.
>>>>>
>>>>> I can see code is already developed, and it is difficult to 
>>>>> restructure developed code, but restructure it into small pieces 
>>>>> really helps for reviews.
>>>>>
>>>>>
>>>>> Driver supports good list of features, can it be possible to 
>>>>> distribute upstream effort into multiple release.
>>>>> Starting from basic functionality and add features gradually.
>>>>> Target for this release can be providing datapath, and add more if we 
>>>>> have time in the release, what do you think?
> 
> I was expecting to get only Rx/Tx in this release, not really more.
> 
> I agree it may be interesting to discuss some design
> and check whether we need more features in ethdev
> as part of the driver upstreaming process.
> 
> 
>>>>> Also there are large amount of base code (HAL / FPGA code), instead 
>>>>> of adding them as a bulk, relevant ones with a feature can be added 
>>>>> with the feature patch, this eliminates dead code in the base code 
>>>>> layer, also helps user/review to understand the link between driver 
>>>>> code and base code.
> 
> Yes it would be interesting to see what is really needed for the basic initialization
> and what is linked to a specific offload or configuration feature.
> 
> As a maintainer, I have to do some changes across all drivers sometimes,
> and I use git blame a lot to understand why something was added.
> 
> 
>>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>>>>
>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>>>>
>>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>>>>
>>>
>>> Hi Morten,
>>>
>>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>>>
>>>
>>> But I come up with two main reasons to ask for a rework:
>>>
>>> 1- Technically any vendor can deliver their software to their customers via a public git repository, they don't have to upstream to https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E,1,NpoJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9bOLlnhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>>> but upstreaming has many benefits.
>>>
>>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>>>
>>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>>>
>>> 2- Make code more accessible to the rest of the world.
>>>
>>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>>>
>>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>>>
>>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
> 
> I fully agree about the 2 reasons for upstreaming piece by piece.
> 
> 
>>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
> 
> In the meantime, if some features are not yet upstreamed in a release,
> a user can apply the missing patches from the mailing list to get the features.
> 
> 
>>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
> 
> You're right Morten, we try to be as welcoming as possible,
> but as Ferruh said, we want to be able to understand how a driver is built,
> even if not understanding all details.
> 
> In Open Source, I think not only the code should be available,
> we must also take care of explanations and documentation.
> 
> 
>>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>>>
>>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
> 
> Driver features can be added until -rc2 (in one month).
> 
> 
>>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
>>
>> Hi Ferruh,
>>
>> First of all, thank you for starting the work to review our code.
>>
>> As Morten said Napatech plans to take all responsibility for the
>> quality of the PMD source code. We expect to provide all fixes
>> needed in the future. If for some reason Napatech stops maintaining
>> the code, then we have been informed that the DPDK community
>> might delete the PMD from the repository, and we understand that.
>>
>> In regards to splitting the code, I don't see this a good option. While
>> I of cause agree it would be easier to review and understand, the
>> code should also result in a meaningful product. Of the 87k lines
>> of code, 53k lines is needed to start-up the FPGA to a state the it is ready
>> to receive traffic. But at this point all packets would simply be discarded,
>> and to be honest, there are better and cheaper options out there,
>> if nothing more than basic functionality is needed. 34k lines are
>> used to setup filters based on rte_flow. The thing is, that you need
>> to initialize all modules in the FPGA TX- and RX-pipelines with valid
>> data, even if you don't need the features those modules provide.
>> As a result, if you split up the 34k lines, then the product would not
>> be functional. Of cause some of the top level logic could be split out,
>> but at this point we are talking about splitting 87k lines into 80k and 7k,
>> which I don't think is worth it.
> 
> Actually I think it is worth.
> There is a benefit in isolating the small basic init part
> from the more complex features.
> 
> 
>>>>> As far as I understand last patch opens a socket interface and an 
>>>>> external application can sent control commands via this interface.
>>>>> I am not sure about this side control channel, what is missing in the 
>>>>> DPDK API? Can we try to address them in the DPDK layer instead of a 
>>>>> driver specific solution?
>>>>
>>>> That would be great.
>>>>
>>>> AFAIK, other vendors also has a bunch of out-of-band communication, 
>>>> e.g. magical EAL parameters to the MLX drivers. So let's not be too 
>>>> hard on the newcomers. ;-)
>>>>
>>>
>>> I did some thinking for this one too,
>>>
>>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>>> (Indeed there are already some ways to do this, without PMD exposing a socket interface.)
>>>
>>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>>> And overall this reduces portability of the DPDK application, each application becomes unique to a device (This is a bad thing, but I also need some feedback how bad it is in real life.)
>>>
>>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>>>
>>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>>>
>>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>>> And improve and extend the ethdev layer to satisfy driver needs.
>>>
>>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>>>
>>
>> The reason we have the addition control channel is not provide
>> additional functionality. We have customers with use-cases that
>> require multiple processes. Since Napatech adapters do not support
>> configuration through VFs, then secondary applications must send
>> their rte_flow to a main application, which will then setup the flow
>> through it's PF. This control channel "hides" these details, and
>> make the product easier for users to adapt to their existing solutions.
> 
> I think you need to explore VF representors.
> This is what is done with other drivers, and it make them compatible.
> 
>> If you stand firm on rejecting the control channel, then we have
>> to go back to the drawing board on this issue. We did look at
>> DPDK's multi-process support, and actually had some support
>> for this, but we determined that for our use-case it was better
>> to have a communication channel, and no shared memory.
> 
> I'm not sure your need is about secondary process.
> Let's discuss this need in a meeting if needed.
> Anyway, the message is that we want to be part of such design decision.
> 
> 
>>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>>>
>>> Of course we are being easy to newcomers but not in a way to allow code that we believe is not good thing to do, but going easy on process may be :)
>>>
>>
>> We are grateful for any leniency you may show us ;-)
>>
>> Thanks again,
>> Christian
>>
>>>
>>>>>
>>>>>
>>>>> Thanks,
>>>>> ferruh
>>>>
>>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>>>>
>>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>>>>
>>>> -Morten
> 
> 
> We are going to discuss the process in the technical board today.
> 
> 

Hi Mykola, Christiam,

As discussed, following are a few good examples from the DPDK history,
there is no "fits all, fixed guidelines", but they can serve as samples:

Marvell cnxk:
https://patchwork.dpdk.org/project/dpdk/list/?series=17449&state=%2A&archive=both


Solarflare sfc (before patchwork series support):
https://patchwork.dpdk.org/project/dpdk/patch/1480436367-20749-2-git-send-email-arybchenko@solarflare.com/
to
https://patchwork.dpdk.org/project/dpdk/patch/1480436367-20749-56-git-send-email-arybchenko@solarflare.com/


Intel ice:
https://patchwork.dpdk.org/project/dpdk/list/?series=2842&state=%2A&archive=both
Christian Koue Muf Sept. 29, 2023, 9:21 a.m. UTC | #8 
On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
>On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
>> Hello,
>> 
>> 19/09/2023 11:06, Christian Koue Muf:
>>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
>>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>>>>>> Sent: Friday, 15 September 2023 17.55
>>>>>>
>>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>>>>>> From: Christian Koue Muf <ckm@napatech.com>
>>>>>>>
>>>>>>> The NTNIC PMD does not rely on a kernel space Napatech driver, 
>>>>>>> thus all defines related to the register layout is part of the 
>>>>>>> PMD code, which will be added in later commits.
>>>>>>>
>>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>>>>>
>>>>>>
>>>>>> Hi Mykola, Christiam,
>>>>>>
>>>>>> This PMD scares me, overall it is a big drop:
>>>>>> "249 files changed, 87128 insertions(+)"
>>>>>>
>>>>>> I think it is not possible to review all in one release cycle, and 
>>>>>> it is not even possible to say if all code used or not.
>>>>>>
>>>>>> I can see code is already developed, and it is difficult to 
>>>>>> restructure developed code, but restructure it into small pieces 
>>>>>> really helps for reviews.
>>>>>>
>>>>>>
>>>>>> Driver supports good list of features, can it be possible to 
>>>>>> distribute upstream effort into multiple release.
>>>>>> Starting from basic functionality and add features gradually.
>>>>>> Target for this release can be providing datapath, and add more if 
>>>>>> we have time in the release, what do you think?
>> 
>> I was expecting to get only Rx/Tx in this release, not really more.
>> 
>> I agree it may be interesting to discuss some design and check whether 
>> we need more features in ethdev as part of the driver upstreaming 
>> process.
>> 
>> 
>>>>>> Also there are large amount of base code (HAL / FPGA code), 
>>>>>> instead of adding them as a bulk, relevant ones with a feature can 
>>>>>> be added with the feature patch, this eliminates dead code in the 
>>>>>> base code layer, also helps user/review to understand the link 
>>>>>> between driver code and base code.
>> 
>> Yes it would be interesting to see what is really needed for the basic 
>> initialization and what is linked to a specific offload or configuration feature.
>> 
>> As a maintainer, I have to do some changes across all drivers 
>> sometimes, and I use git blame a lot to understand why something was added.
>> 
>> 
>>>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>>>>>
>>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>>>>>
>>>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>>>>>
>>>>
>>>> Hi Morten,
>>>>
>>>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>>>>
>>>>
>>>> But I come up with two main reasons to ask for a rework:
>>>>
>>>> 1- Technically any vendor can deliver their software to their 
>>>> customers via a public git repository, they don't have to upstream 
>>>> to 
>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E,1,N
>>>> poJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9bOLl
>>>> nhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>>>> but upstreaming has many benefits.
>>>>
>>>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>>>>
>>>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>>>>
>>>> 2- Make code more accessible to the rest of the world.
>>>>
>>>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>>>>
>>>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>>>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>>>>
>>>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
>> 
>> I fully agree about the 2 reasons for upstreaming piece by piece.
>> 
>> 
>>>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
>> 
>> In the meantime, if some features are not yet upstreamed in a release, 
>> a user can apply the missing patches from the mailing list to get the features.
>> 
>> 
>>>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
>> 
>> You're right Morten, we try to be as welcoming as possible, but as 
>> Ferruh said, we want to be able to understand how a driver is built, 
>> even if not understanding all details.
>> 
>> In Open Source, I think not only the code should be available, we must 
>> also take care of explanations and documentation.
>> 
>> 
>>>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>>>>
>>>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
>> 
>> Driver features can be added until -rc2 (in one month).
>> 
>> 
>>>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
>>>
>>> Hi Ferruh,
>>>
>>> First of all, thank you for starting the work to review our code.
>>>
>>> As Morten said Napatech plans to take all responsibility for the 
>>> quality of the PMD source code. We expect to provide all fixes needed 
>>> in the future. If for some reason Napatech stops maintaining the 
>>> code, then we have been informed that the DPDK community might delete 
>>> the PMD from the repository, and we understand that.
>>>
>>> In regards to splitting the code, I don't see this a good option. 
>>> While I of cause agree it would be easier to review and understand, 
>>> the code should also result in a meaningful product. Of the 87k lines 
>>> of code, 53k lines is needed to start-up the FPGA to a state the it 
>>> is ready to receive traffic. But at this point all packets would 
>>> simply be discarded, and to be honest, there are better and cheaper 
>>> options out there, if nothing more than basic functionality is 
>>> needed. 34k lines are used to setup filters based on rte_flow. The 
>>> thing is, that you need to initialize all modules in the FPGA TX- and 
>>> RX-pipelines with valid data, even if you don't need the features those modules provide.
>>> As a result, if you split up the 34k lines, then the product would 
>>> not be functional. Of cause some of the top level logic could be 
>>> split out, but at this point we are talking about splitting 87k lines 
>>> into 80k and 7k, which I don't think is worth it.
>> 
>> Actually I think it is worth.
>> There is a benefit in isolating the small basic init part from the 
>> more complex features.
>> 
>> 
>>>>>> As far as I understand last patch opens a socket interface and an 
>>>>>> external application can sent control commands via this interface.
>>>>>> I am not sure about this side control channel, what is missing in 
>>>>>> the DPDK API? Can we try to address them in the DPDK layer instead 
>>>>>> of a driver specific solution?
>>>>>
>>>>> That would be great.
>>>>>
>>>>> AFAIK, other vendors also has a bunch of out-of-band communication, 
>>>>> e.g. magical EAL parameters to the MLX drivers. So let's not be too 
>>>>> hard on the newcomers. ;-)
>>>>>
>>>>
>>>> I did some thinking for this one too,
>>>>
>>>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>>>> (Indeed there are already some ways to do this, without PMD exposing 
>>>> a socket interface.)
>>>>
>>>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>>>> And overall this reduces portability of the DPDK application, each 
>>>> application becomes unique to a device (This is a bad thing, but I 
>>>> also need some feedback how bad it is in real life.)
>>>>
>>>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>>>>
>>>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>>>>
>>>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>>>> And improve and extend the ethdev layer to satisfy driver needs.
>>>>
>>>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>>>>
>>>
>>> The reason we have the addition control channel is not provide 
>>> additional functionality. We have customers with use-cases that 
>>> require multiple processes. Since Napatech adapters do not support 
>>> configuration through VFs, then secondary applications must send 
>>> their rte_flow to a main application, which will then setup the flow 
>>> through it's PF. This control channel "hides" these details, and make 
>>> the product easier for users to adapt to their existing solutions.
>> 
>> I think you need to explore VF representors.
>> This is what is done with other drivers, and it make them compatible.
>> 
>>> If you stand firm on rejecting the control channel, then we have to 
>>> go back to the drawing board on this issue. We did look at DPDK's 
>>> multi-process support, and actually had some support for this, but we 
>>> determined that for our use-case it was better to have a 
>>> communication channel, and no shared memory.
>> 
>> I'm not sure your need is about secondary process.
>> Let's discuss this need in a meeting if needed.
>> Anyway, the message is that we want to be part of such design decision.
>> 
>> 
>>>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>>>>
>>>> Of course we are being easy to newcomers but not in a way to allow 
>>>> code that we believe is not good thing to do, but going easy on 
>>>> process may be :)
>>>>
>>>
>>> We are grateful for any leniency you may show us ;-)
>>>
>>> Thanks again,
>>> Christian
>>>
>>>>
>>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>> ferruh
>>>>>
>>>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>>>>>
>>>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>>>>>
>>>>> -Morten
>> 
>> 
>> We are going to discuss the process in the technical board today.
>> 
>> 
>
>Hi Mykola, Christiam,
>
>As discussed, following are a few good examples from the DPDK history, there is no "fits all, fixed guidelines", but they can serve as samples:
>
>Marvell cnxk:
>https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2flist%2f%3fseries%3d17449%26state%3d%252A%26archive%3dboth&c=E,1,DmXU0iHwXoSaZ4bKn-yhX9J8XmFBispd2ut7pxLNBkK3Q4LVpG_zmOf1jnWSS-Y0Fx-TNbPnQDHyBZkDj23Gu7zjPZ5nsA7pid5CsE2vxNk,&typo=1
>
>
>Solarflare sfc (before patchwork series support):
>https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-2-git-send-email-arybchenko%40solarflare.com%2f&c=E,1,E9oUT_1WuNC2JA8x7an3rC_Pm5g1L5cxJKQ6pTwSbCWSJpiLH2GnmgfFkUqViOOwkpS2df8kgBvHjmulKaWhyr4BBizUT-sL5LJv21Hx4RtHtK3vjhcKpg,,&typo=1
>to
>https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-56-git-send-email-arybchenko%40solarflare.com%2f&c=E,1,GByF_TiC_q11iVPpiPgpCMlSge-J0XfT0zHkriK0rde1Qt1RG7uf6mETQkTSQ-1V86Z7EtRcxlvSsed1sqn8RWfN8KFSbd7NaAkfbDiehn_vSRzja45rQgv53Q,,&typo=1
>
>
>Intel ice:
>https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2flist%2f%3fseries%3d2842%26state%3d%252A%26archive%3dboth&c=E,1,zQwvAIR3ToLIhT09bVxm_HEF-dp8eyTqhsKB3eOYgIJdd2WS_0ZlTbQKfr9KLyTA3A2A2HzBbjIlz21D_hWVgS_INmmC5eew1J0QBH-PoRNd&typo=1
>

Thank you for the links, they have been very helpful.

After a lot of internal discussion, Napatech has decided to implement some architectural changes to our PMD that will allow us to easier split up the code into smaller features. The work will require some time, which means that we will not be ready for the 23.11 release. The current goal is to attempt to upstream a quite basic PMD in time for 24.7, and a fully featured PMD for 24.11.

Best regards
Christian Muf
Ferruh Yigit Sept. 29, 2023, 9:46 a.m. UTC | #9 
On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
> On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
>> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
>>> Hello,
>>>
>>> 19/09/2023 11:06, Christian Koue Muf:
>>>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>>>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
>>>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>>>>>>> Sent: Friday, 15 September 2023 17.55
>>>>>>>
>>>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>>>>>>> From: Christian Koue Muf <ckm@napatech.com>
>>>>>>>>
>>>>>>>> The NTNIC PMD does not rely on a kernel space Napatech driver,
>>>>>>>> thus all defines related to the register layout is part of the
>>>>>>>> PMD code, which will be added in later commits.
>>>>>>>>
>>>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>>>>>>
>>>>>>>
>>>>>>> Hi Mykola, Christiam,
>>>>>>>
>>>>>>> This PMD scares me, overall it is a big drop:
>>>>>>> "249 files changed, 87128 insertions(+)"
>>>>>>>
>>>>>>> I think it is not possible to review all in one release cycle, and
>>>>>>> it is not even possible to say if all code used or not.
>>>>>>>
>>>>>>> I can see code is already developed, and it is difficult to
>>>>>>> restructure developed code, but restructure it into small pieces
>>>>>>> really helps for reviews.
>>>>>>>
>>>>>>>
>>>>>>> Driver supports good list of features, can it be possible to
>>>>>>> distribute upstream effort into multiple release.
>>>>>>> Starting from basic functionality and add features gradually.
>>>>>>> Target for this release can be providing datapath, and add more if
>>>>>>> we have time in the release, what do you think?
>>>
>>> I was expecting to get only Rx/Tx in this release, not really more.
>>>
>>> I agree it may be interesting to discuss some design and check whether
>>> we need more features in ethdev as part of the driver upstreaming
>>> process.
>>>
>>>
>>>>>>> Also there are large amount of base code (HAL / FPGA code),
>>>>>>> instead of adding them as a bulk, relevant ones with a feature can
>>>>>>> be added with the feature patch, this eliminates dead code in the
>>>>>>> base code layer, also helps user/review to understand the link
>>>>>>> between driver code and base code.
>>>
>>> Yes it would be interesting to see what is really needed for the basic
>>> initialization and what is linked to a specific offload or configuration feature.
>>>
>>> As a maintainer, I have to do some changes across all drivers
>>> sometimes, and I use git blame a lot to understand why something was added.
>>>
>>>
>>>>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>>>>>>
>>>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>>>>>>
>>>>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>>>>>>
>>>>>
>>>>> Hi Morten,
>>>>>
>>>>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>>>>>
>>>>>
>>>>> But I come up with two main reasons to ask for a rework:
>>>>>
>>>>> 1- Technically any vendor can deliver their software to their
>>>>> customers via a public git repository, they don't have to upstream
>>>>> to
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E,1,N
>>>>> poJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9bOLl
>>>>> nhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>>>>> but upstreaming has many benefits.
>>>>>
>>>>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>>>>>
>>>>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>>>>>
>>>>> 2- Make code more accessible to the rest of the world.
>>>>>
>>>>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>>>>>
>>>>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>>>>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>>>>>
>>>>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
>>>
>>> I fully agree about the 2 reasons for upstreaming piece by piece.
>>>
>>>
>>>>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
>>>
>>> In the meantime, if some features are not yet upstreamed in a release,
>>> a user can apply the missing patches from the mailing list to get the features.
>>>
>>>
>>>>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
>>>
>>> You're right Morten, we try to be as welcoming as possible, but as
>>> Ferruh said, we want to be able to understand how a driver is built,
>>> even if not understanding all details.
>>>
>>> In Open Source, I think not only the code should be available, we must
>>> also take care of explanations and documentation.
>>>
>>>
>>>>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>>>>>
>>>>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
>>>
>>> Driver features can be added until -rc2 (in one month).
>>>
>>>
>>>>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
>>>>
>>>> Hi Ferruh,
>>>>
>>>> First of all, thank you for starting the work to review our code.
>>>>
>>>> As Morten said Napatech plans to take all responsibility for the
>>>> quality of the PMD source code. We expect to provide all fixes needed
>>>> in the future. If for some reason Napatech stops maintaining the
>>>> code, then we have been informed that the DPDK community might delete
>>>> the PMD from the repository, and we understand that.
>>>>
>>>> In regards to splitting the code, I don't see this a good option.
>>>> While I of cause agree it would be easier to review and understand,
>>>> the code should also result in a meaningful product. Of the 87k lines
>>>> of code, 53k lines is needed to start-up the FPGA to a state the it
>>>> is ready to receive traffic. But at this point all packets would
>>>> simply be discarded, and to be honest, there are better and cheaper
>>>> options out there, if nothing more than basic functionality is
>>>> needed. 34k lines are used to setup filters based on rte_flow. The
>>>> thing is, that you need to initialize all modules in the FPGA TX- and
>>>> RX-pipelines with valid data, even if you don't need the features those modules provide.
>>>> As a result, if you split up the 34k lines, then the product would
>>>> not be functional. Of cause some of the top level logic could be
>>>> split out, but at this point we are talking about splitting 87k lines
>>>> into 80k and 7k, which I don't think is worth it.
>>>
>>> Actually I think it is worth.
>>> There is a benefit in isolating the small basic init part from the
>>> more complex features.
>>>
>>>
>>>>>>> As far as I understand last patch opens a socket interface and an
>>>>>>> external application can sent control commands via this interface.
>>>>>>> I am not sure about this side control channel, what is missing in
>>>>>>> the DPDK API? Can we try to address them in the DPDK layer instead
>>>>>>> of a driver specific solution?
>>>>>>
>>>>>> That would be great.
>>>>>>
>>>>>> AFAIK, other vendors also has a bunch of out-of-band communication,
>>>>>> e.g. magical EAL parameters to the MLX drivers. So let's not be too
>>>>>> hard on the newcomers. ;-)
>>>>>>
>>>>>
>>>>> I did some thinking for this one too,
>>>>>
>>>>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>>>>> (Indeed there are already some ways to do this, without PMD exposing
>>>>> a socket interface.)
>>>>>
>>>>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>>>>> And overall this reduces portability of the DPDK application, each
>>>>> application becomes unique to a device (This is a bad thing, but I
>>>>> also need some feedback how bad it is in real life.)
>>>>>
>>>>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>>>>>
>>>>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>>>>>
>>>>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>>>>> And improve and extend the ethdev layer to satisfy driver needs.
>>>>>
>>>>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>>>>>
>>>>
>>>> The reason we have the addition control channel is not provide
>>>> additional functionality. We have customers with use-cases that
>>>> require multiple processes. Since Napatech adapters do not support
>>>> configuration through VFs, then secondary applications must send
>>>> their rte_flow to a main application, which will then setup the flow
>>>> through it's PF. This control channel "hides" these details, and make
>>>> the product easier for users to adapt to their existing solutions.
>>>
>>> I think you need to explore VF representors.
>>> This is what is done with other drivers, and it make them compatible.
>>>
>>>> If you stand firm on rejecting the control channel, then we have to
>>>> go back to the drawing board on this issue. We did look at DPDK's
>>>> multi-process support, and actually had some support for this, but we
>>>> determined that for our use-case it was better to have a
>>>> communication channel, and no shared memory.
>>>
>>> I'm not sure your need is about secondary process.
>>> Let's discuss this need in a meeting if needed.
>>> Anyway, the message is that we want to be part of such design decision.
>>>
>>>
>>>>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>>>>>
>>>>> Of course we are being easy to newcomers but not in a way to allow
>>>>> code that we believe is not good thing to do, but going easy on
>>>>> process may be :)
>>>>>
>>>>
>>>> We are grateful for any leniency you may show us ;-)
>>>>
>>>> Thanks again,
>>>> Christian
>>>>
>>>>>
>>>>>>>
>>>>>>>
>>>>>>> Thanks,
>>>>>>> ferruh
>>>>>>
>>>>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>>>>>>
>>>>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>>>>>>
>>>>>> -Morten
>>>
>>>
>>> We are going to discuss the process in the technical board today.
>>>
>>>
>>
>> Hi Mykola, Christiam,
>>
>> As discussed, following are a few good examples from the DPDK history, there is no "fits all, fixed guidelines", but they can serve as samples:
>>
>> Marvell cnxk:
>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2flist%2f%3fseries%3d17449%26state%3d%252A%26archive%3dboth&c=E,1,DmXU0iHwXoSaZ4bKn-yhX9J8XmFBispd2ut7pxLNBkK3Q4LVpG_zmOf1jnWSS-Y0Fx-TNbPnQDHyBZkDj23Gu7zjPZ5nsA7pid5CsE2vxNk,&typo=1
>>
>>
>> Solarflare sfc (before patchwork series support):
>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-2-git-send-email-arybchenko%40solarflare.com%2f&c=E,1,E9oUT_1WuNC2JA8x7an3rC_Pm5g1L5cxJKQ6pTwSbCWSJpiLH2GnmgfFkUqViOOwkpS2df8kgBvHjmulKaWhyr4BBizUT-sL5LJv21Hx4RtHtK3vjhcKpg,,&typo=1
>> to
>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-56-git-send-email-arybchenko%40solarflare.com%2f&c=E,1,GByF_TiC_q11iVPpiPgpCMlSge-J0XfT0zHkriK0rde1Qt1RG7uf6mETQkTSQ-1V86Z7EtRcxlvSsed1sqn8RWfN8KFSbd7NaAkfbDiehn_vSRzja45rQgv53Q,,&typo=1
>>
>>
>> Intel ice:
>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2flist%2f%3fseries%3d2842%26state%3d%252A%26archive%3dboth&c=E,1,zQwvAIR3ToLIhT09bVxm_HEF-dp8eyTqhsKB3eOYgIJdd2WS_0ZlTbQKfr9KLyTA3A2A2HzBbjIlz21D_hWVgS_INmmC5eew1J0QBH-PoRNd&typo=1
>>
> 
> Thank you for the links, they have been very helpful.
> 
> After a lot of internal discussion, Napatech has decided to implement some architectural changes to our PMD that will allow us to easier split up the code into smaller features. The work will require some time, which means that we will not be ready for the 23.11 release. The current goal is to attempt to upstream a quite basic PMD in time for 24.7, and a fully featured PMD for 24.11.
> 
> 

Hi Christiam,

Good to see there is a solid plan for upstreaming but also not that good
that it is postponed,

I am aware it is all tied to your internal planning/resourcing etc, but
since the effort already started, can it be possible to squeeze very
basic driver in this release, which just does link up and most basic Rx/Tx?
It gives opportunity to experiment on device to users.

We can accept it up to -rc3, which is end of October, so there is still
some time?

This is just a suggestion though, no pressure intended.
Thomas Monjalon Sept. 29, 2023, 10:23 a.m. UTC | #10 
29/09/2023 11:46, Ferruh Yigit:
> On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
> > On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
> >> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
> >>> Hello,
> >>>
> >>> 19/09/2023 11:06, Christian Koue Muf:
> >>>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
> >>>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
> >>>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
> >>>>>>> Sent: Friday, 15 September 2023 17.55
> >>>>>>>
> >>>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
> >>>>>>>> From: Christian Koue Muf <ckm@napatech.com>
> >>>>>>>>
> >>>>>>>> The NTNIC PMD does not rely on a kernel space Napatech driver,
> >>>>>>>> thus all defines related to the register layout is part of the
> >>>>>>>> PMD code, which will be added in later commits.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
> >>>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
> >>>>>>>>
> >>>>>>>
> >>>>>>> Hi Mykola, Christiam,
> >>>>>>>
> >>>>>>> This PMD scares me, overall it is a big drop:
> >>>>>>> "249 files changed, 87128 insertions(+)"
> >>>>>>>
> >>>>>>> I think it is not possible to review all in one release cycle, and
> >>>>>>> it is not even possible to say if all code used or not.
> >>>>>>>
> >>>>>>> I can see code is already developed, and it is difficult to
> >>>>>>> restructure developed code, but restructure it into small pieces
> >>>>>>> really helps for reviews.
> >>>>>>>
> >>>>>>>
> >>>>>>> Driver supports good list of features, can it be possible to
> >>>>>>> distribute upstream effort into multiple release.
> >>>>>>> Starting from basic functionality and add features gradually.
> >>>>>>> Target for this release can be providing datapath, and add more if
> >>>>>>> we have time in the release, what do you think?
> >>>
> >>> I was expecting to get only Rx/Tx in this release, not really more.
> >>>
> >>> I agree it may be interesting to discuss some design and check whether
> >>> we need more features in ethdev as part of the driver upstreaming
> >>> process.
> >>>
> >>>
> >>>>>>> Also there are large amount of base code (HAL / FPGA code),
> >>>>>>> instead of adding them as a bulk, relevant ones with a feature can
> >>>>>>> be added with the feature patch, this eliminates dead code in the
> >>>>>>> base code layer, also helps user/review to understand the link
> >>>>>>> between driver code and base code.
> >>>
> >>> Yes it would be interesting to see what is really needed for the basic
> >>> initialization and what is linked to a specific offload or configuration feature.
> >>>
> >>> As a maintainer, I have to do some changes across all drivers
> >>> sometimes, and I use git blame a lot to understand why something was added.
> >>>
> >>>
> >>>>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
> >>>>>>
> >>>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
> >>>>>>
> >>>>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
> >>>>>>
> >>>>>
> >>>>> Hi Morten,
> >>>>>
> >>>>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
> >>>>>
> >>>>>
> >>>>> But I come up with two main reasons to ask for a rework:
> >>>>>
> >>>>> 1- Technically any vendor can deliver their software to their
> >>>>> customers via a public git repository, they don't have to upstream
> >>>>> to
> >>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E,1,N
> >>>>> poJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9bOLl
> >>>>> nhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
> >>>>> but upstreaming has many benefits.
> >>>>>
> >>>>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
> >>>>>
> >>>>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
> >>>>>
> >>>>> 2- Make code more accessible to the rest of the world.
> >>>>>
> >>>>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
> >>>>>
> >>>>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
> >>>>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
> >>>>>
> >>>>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
> >>>
> >>> I fully agree about the 2 reasons for upstreaming piece by piece.
> >>>
> >>>
> >>>>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
> >>>
> >>> In the meantime, if some features are not yet upstreamed in a release,
> >>> a user can apply the missing patches from the mailing list to get the features.
> >>>
> >>>
> >>>>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
> >>>
> >>> You're right Morten, we try to be as welcoming as possible, but as
> >>> Ferruh said, we want to be able to understand how a driver is built,
> >>> even if not understanding all details.
> >>>
> >>> In Open Source, I think not only the code should be available, we must
> >>> also take care of explanations and documentation.
> >>>
> >>>
> >>>>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
> >>>>>
> >>>>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
> >>>
> >>> Driver features can be added until -rc2 (in one month).
> >>>
> >>>
> >>>>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
> >>>>
> >>>> Hi Ferruh,
> >>>>
> >>>> First of all, thank you for starting the work to review our code.
> >>>>
> >>>> As Morten said Napatech plans to take all responsibility for the
> >>>> quality of the PMD source code. We expect to provide all fixes needed
> >>>> in the future. If for some reason Napatech stops maintaining the
> >>>> code, then we have been informed that the DPDK community might delete
> >>>> the PMD from the repository, and we understand that.
> >>>>
> >>>> In regards to splitting the code, I don't see this a good option.
> >>>> While I of cause agree it would be easier to review and understand,
> >>>> the code should also result in a meaningful product. Of the 87k lines
> >>>> of code, 53k lines is needed to start-up the FPGA to a state the it
> >>>> is ready to receive traffic. But at this point all packets would
> >>>> simply be discarded, and to be honest, there are better and cheaper
> >>>> options out there, if nothing more than basic functionality is
> >>>> needed. 34k lines are used to setup filters based on rte_flow. The
> >>>> thing is, that you need to initialize all modules in the FPGA TX- and
> >>>> RX-pipelines with valid data, even if you don't need the features those modules provide.
> >>>> As a result, if you split up the 34k lines, then the product would
> >>>> not be functional. Of cause some of the top level logic could be
> >>>> split out, but at this point we are talking about splitting 87k lines
> >>>> into 80k and 7k, which I don't think is worth it.
> >>>
> >>> Actually I think it is worth.
> >>> There is a benefit in isolating the small basic init part from the
> >>> more complex features.
> >>>
> >>>
> >>>>>>> As far as I understand last patch opens a socket interface and an
> >>>>>>> external application can sent control commands via this interface.
> >>>>>>> I am not sure about this side control channel, what is missing in
> >>>>>>> the DPDK API? Can we try to address them in the DPDK layer instead
> >>>>>>> of a driver specific solution?
> >>>>>>
> >>>>>> That would be great.
> >>>>>>
> >>>>>> AFAIK, other vendors also has a bunch of out-of-band communication,
> >>>>>> e.g. magical EAL parameters to the MLX drivers. So let's not be too
> >>>>>> hard on the newcomers. ;-)
> >>>>>>
> >>>>>
> >>>>> I did some thinking for this one too,
> >>>>>
> >>>>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
> >>>>> (Indeed there are already some ways to do this, without PMD exposing
> >>>>> a socket interface.)
> >>>>>
> >>>>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
> >>>>> And overall this reduces portability of the DPDK application, each
> >>>>> application becomes unique to a device (This is a bad thing, but I
> >>>>> also need some feedback how bad it is in real life.)
> >>>>>
> >>>>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
> >>>>>
> >>>>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
> >>>>>
> >>>>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
> >>>>> And improve and extend the ethdev layer to satisfy driver needs.
> >>>>>
> >>>>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
> >>>>>
> >>>>
> >>>> The reason we have the addition control channel is not provide
> >>>> additional functionality. We have customers with use-cases that
> >>>> require multiple processes. Since Napatech adapters do not support
> >>>> configuration through VFs, then secondary applications must send
> >>>> their rte_flow to a main application, which will then setup the flow
> >>>> through it's PF. This control channel "hides" these details, and make
> >>>> the product easier for users to adapt to their existing solutions.
> >>>
> >>> I think you need to explore VF representors.
> >>> This is what is done with other drivers, and it make them compatible.
> >>>
> >>>> If you stand firm on rejecting the control channel, then we have to
> >>>> go back to the drawing board on this issue. We did look at DPDK's
> >>>> multi-process support, and actually had some support for this, but we
> >>>> determined that for our use-case it was better to have a
> >>>> communication channel, and no shared memory.
> >>>
> >>> I'm not sure your need is about secondary process.
> >>> Let's discuss this need in a meeting if needed.
> >>> Anyway, the message is that we want to be part of such design decision.
> >>>
> >>>
> >>>>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
> >>>>>
> >>>>> Of course we are being easy to newcomers but not in a way to allow
> >>>>> code that we believe is not good thing to do, but going easy on
> >>>>> process may be :)
> >>>>>
> >>>>
> >>>> We are grateful for any leniency you may show us ;-)
> >>>>
> >>>> Thanks again,
> >>>> Christian
> >>>>
> >>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>> Thanks,
> >>>>>>> ferruh
> >>>>>>
> >>>>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
> >>>>>>
> >>>>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
> >>>>>>
> >>>>>> -Morten
> >>>
> >>>
> >>> We are going to discuss the process in the technical board today.
> >>>
> >>>
> >>
> >> Hi Mykola, Christiam,
> >>
> >> As discussed, following are a few good examples from the DPDK history, there is no "fits all, fixed guidelines", but they can serve as samples:
> >>
> >> Marvell cnxk:
> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2flist%2f%3fseries%3d17449%26state%3d%252A%26archive%3dboth&c=E,1,DmXU0iHwXoSaZ4bKn-yhX9J8XmFBispd2ut7pxLNBkK3Q4LVpG_zmOf1jnWSS-Y0Fx-TNbPnQDHyBZkDj23Gu7zjPZ5nsA7pid5CsE2vxNk,&typo=1
> >>
> >>
> >> Solarflare sfc (before patchwork series support):
> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-2-git-send-email-arybchenko%40solarflare.com%2f&c=E,1,E9oUT_1WuNC2JA8x7an3rC_Pm5g1L5cxJKQ6pTwSbCWSJpiLH2GnmgfFkUqViOOwkpS2df8kgBvHjmulKaWhyr4BBizUT-sL5LJv21Hx4RtHtK3vjhcKpg,,&typo=1
> >> to
> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-56-git-send-email-arybchenko%40solarflare.com%2f&c=E,1,GByF_TiC_q11iVPpiPgpCMlSge-J0XfT0zHkriK0rde1Qt1RG7uf6mETQkTSQ-1V86Z7EtRcxlvSsed1sqn8RWfN8KFSbd7NaAkfbDiehn_vSRzja45rQgv53Q,,&typo=1
> >>
> >>
> >> Intel ice:
> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.org%2fproject%2fdpdk%2flist%2f%3fseries%3d2842%26state%3d%252A%26archive%3dboth&c=E,1,zQwvAIR3ToLIhT09bVxm_HEF-dp8eyTqhsKB3eOYgIJdd2WS_0ZlTbQKfr9KLyTA3A2A2HzBbjIlz21D_hWVgS_INmmC5eew1J0QBH-PoRNd&typo=1
> >>
> > 
> > Thank you for the links, they have been very helpful.
> > 
> > After a lot of internal discussion, Napatech has decided to implement some architectural changes to our PMD that will allow us to easier split up the code into smaller features. The work will require some time, which means that we will not be ready for the 23.11 release. The current goal is to attempt to upstream a quite basic PMD in time for 24.7, and a fully featured PMD for 24.11.
> > 
> > 
> 
> Hi Christiam,
> 
> Good to see there is a solid plan for upstreaming but also not that good
> that it is postponed,
> 
> I am aware it is all tied to your internal planning/resourcing etc, but
> since the effort already started, can it be possible to squeeze very
> basic driver in this release, which just does link up and most basic Rx/Tx?
> It gives opportunity to experiment on device to users.
> 
> We can accept it up to -rc3, which is end of October, so there is still
> some time?
> 
> This is just a suggestion though, no pressure intended.

I agree with Ferruh, better to start early and small.
It shouldn't be too hard to introduce the skeleton of the driver.
Christian Koue Muf Oct. 9, 2023, 7:57 a.m. UTC | #11 
On 9/29/2023 12:24 PM, Thomas Monjalon wrote:
>29/09/2023 11:46, Ferruh Yigit:
>> On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
>> > On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
>> >> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
>> >>> Hello,
>> >>>
>> >>> 19/09/2023 11:06, Christian Koue Muf:
>> >>>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>> >>>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
>> >>>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>> >>>>>>> Sent: Friday, 15 September 2023 17.55
>> >>>>>>>
>> >>>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>> >>>>>>>> From: Christian Koue Muf <ckm@napatech.com>
>> >>>>>>>>
>> >>>>>>>> The NTNIC PMD does not rely on a kernel space Napatech 
>> >>>>>>>> driver, thus all defines related to the register layout is 
>> >>>>>>>> part of the PMD code, which will be added in later commits.
>> >>>>>>>>
>> >>>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>> >>>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>> >>>>>>>>
>> >>>>>>>
>> >>>>>>> Hi Mykola, Christiam,
>> >>>>>>>
>> >>>>>>> This PMD scares me, overall it is a big drop:
>> >>>>>>> "249 files changed, 87128 insertions(+)"
>> >>>>>>>
>> >>>>>>> I think it is not possible to review all in one release cycle, 
>> >>>>>>> and it is not even possible to say if all code used or not.
>> >>>>>>>
>> >>>>>>> I can see code is already developed, and it is difficult to 
>> >>>>>>> restructure developed code, but restructure it into small 
>> >>>>>>> pieces really helps for reviews.
>> >>>>>>>
>> >>>>>>>
>> >>>>>>> Driver supports good list of features, can it be possible to 
>> >>>>>>> distribute upstream effort into multiple release.
>> >>>>>>> Starting from basic functionality and add features gradually.
>> >>>>>>> Target for this release can be providing datapath, and add 
>> >>>>>>> more if we have time in the release, what do you think?
>> >>>
>> >>> I was expecting to get only Rx/Tx in this release, not really more.
>> >>>
>> >>> I agree it may be interesting to discuss some design and check 
>> >>> whether we need more features in ethdev as part of the driver 
>> >>> upstreaming process.
>> >>>
>> >>>
>> >>>>>>> Also there are large amount of base code (HAL / FPGA code), 
>> >>>>>>> instead of adding them as a bulk, relevant ones with a feature 
>> >>>>>>> can be added with the feature patch, this eliminates dead code 
>> >>>>>>> in the base code layer, also helps user/review to understand 
>> >>>>>>> the link between driver code and base code.
>> >>>
>> >>> Yes it would be interesting to see what is really needed for the 
>> >>> basic initialization and what is linked to a specific offload or configuration feature.
>> >>>
>> >>> As a maintainer, I have to do some changes across all drivers 
>> >>> sometimes, and I use git blame a lot to understand why something was added.
>> >>>
>> >>>
>> >>>>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>> >>>>>>
>> >>>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>> >>>>>>
>> >>>>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>> >>>>>>
>> >>>>>
>> >>>>> Hi Morten,
>> >>>>>
>> >>>>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>> >>>>>
>> >>>>>
>> >>>>> But I come up with two main reasons to ask for a rework:
>> >>>>>
>> >>>>> 1- Technically any vendor can deliver their software to their 
>> >>>>> customers via a public git repository, they don't have to 
>> >>>>> upstream to 
>> >>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E
>> >>>>> ,1,N 
>> >>>>> poJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9
>> >>>>> bOLl nhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>> >>>>> but upstreaming has many benefits.
>> >>>>>
>> >>>>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>> >>>>>
>> >>>>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>> >>>>>
>> >>>>> 2- Make code more accessible to the rest of the world.
>> >>>>>
>> >>>>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>> >>>>>
>> >>>>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>> >>>>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>> >>>>>
>> >>>>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
>> >>>
>> >>> I fully agree about the 2 reasons for upstreaming piece by piece.
>> >>>
>> >>>
>> >>>>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
>> >>>
>> >>> In the meantime, if some features are not yet upstreamed in a 
>> >>> release, a user can apply the missing patches from the mailing list to get the features.
>> >>>
>> >>>
>> >>>>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
>> >>>
>> >>> You're right Morten, we try to be as welcoming as possible, but as 
>> >>> Ferruh said, we want to be able to understand how a driver is 
>> >>> built, even if not understanding all details.
>> >>>
>> >>> In Open Source, I think not only the code should be available, we 
>> >>> must also take care of explanations and documentation.
>> >>>
>> >>>
>> >>>>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>> >>>>>
>> >>>>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
>> >>>
>> >>> Driver features can be added until -rc2 (in one month).
>> >>>
>> >>>
>> >>>>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
>> >>>>
>> >>>> Hi Ferruh,
>> >>>>
>> >>>> First of all, thank you for starting the work to review our code.
>> >>>>
>> >>>> As Morten said Napatech plans to take all responsibility for the 
>> >>>> quality of the PMD source code. We expect to provide all fixes 
>> >>>> needed in the future. If for some reason Napatech stops 
>> >>>> maintaining the code, then we have been informed that the DPDK 
>> >>>> community might delete the PMD from the repository, and we understand that.
>> >>>>
>> >>>> In regards to splitting the code, I don't see this a good option.
>> >>>> While I of cause agree it would be easier to review and 
>> >>>> understand, the code should also result in a meaningful product. 
>> >>>> Of the 87k lines of code, 53k lines is needed to start-up the 
>> >>>> FPGA to a state the it is ready to receive traffic. But at this 
>> >>>> point all packets would simply be discarded, and to be honest, 
>> >>>> there are better and cheaper options out there, if nothing more 
>> >>>> than basic functionality is needed. 34k lines are used to setup 
>> >>>> filters based on rte_flow. The thing is, that you need to 
>> >>>> initialize all modules in the FPGA TX- and RX-pipelines with valid data, even if you don't need the features those modules provide.
>> >>>> As a result, if you split up the 34k lines, then the product 
>> >>>> would not be functional. Of cause some of the top level logic 
>> >>>> could be split out, but at this point we are talking about 
>> >>>> splitting 87k lines into 80k and 7k, which I don't think is worth it.
>> >>>
>> >>> Actually I think it is worth.
>> >>> There is a benefit in isolating the small basic init part from the 
>> >>> more complex features.
>> >>>
>> >>>
>> >>>>>>> As far as I understand last patch opens a socket interface and 
>> >>>>>>> an external application can sent control commands via this interface.
>> >>>>>>> I am not sure about this side control channel, what is missing 
>> >>>>>>> in the DPDK API? Can we try to address them in the DPDK layer 
>> >>>>>>> instead of a driver specific solution?
>> >>>>>>
>> >>>>>> That would be great.
>> >>>>>>
>> >>>>>> AFAIK, other vendors also has a bunch of out-of-band 
>> >>>>>> communication, e.g. magical EAL parameters to the MLX drivers. 
>> >>>>>> So let's not be too hard on the newcomers. ;-)
>> >>>>>>
>> >>>>>
>> >>>>> I did some thinking for this one too,
>> >>>>>
>> >>>>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>> >>>>> (Indeed there are already some ways to do this, without PMD 
>> >>>>> exposing a socket interface.)
>> >>>>>
>> >>>>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>> >>>>> And overall this reduces portability of the DPDK application, 
>> >>>>> each application becomes unique to a device (This is a bad 
>> >>>>> thing, but I also need some feedback how bad it is in real 
>> >>>>> life.)
>> >>>>>
>> >>>>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>> >>>>>
>> >>>>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>> >>>>>
>> >>>>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>> >>>>> And improve and extend the ethdev layer to satisfy driver needs.
>> >>>>>
>> >>>>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>> >>>>>
>> >>>>
>> >>>> The reason we have the addition control channel is not provide 
>> >>>> additional functionality. We have customers with use-cases that 
>> >>>> require multiple processes. Since Napatech adapters do not 
>> >>>> support configuration through VFs, then secondary applications 
>> >>>> must send their rte_flow to a main application, which will then 
>> >>>> setup the flow through it's PF. This control channel "hides" 
>> >>>> these details, and make the product easier for users to adapt to their existing solutions.
>> >>>
>> >>> I think you need to explore VF representors.
>> >>> This is what is done with other drivers, and it make them compatible.
>> >>>
>> >>>> If you stand firm on rejecting the control channel, then we have 
>> >>>> to go back to the drawing board on this issue. We did look at 
>> >>>> DPDK's multi-process support, and actually had some support for 
>> >>>> this, but we determined that for our use-case it was better to 
>> >>>> have a communication channel, and no shared memory.
>> >>>
>> >>> I'm not sure your need is about secondary process.
>> >>> Let's discuss this need in a meeting if needed.
>> >>> Anyway, the message is that we want to be part of such design decision.
>> >>>
>> >>>
>> >>>>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>> >>>>>
>> >>>>> Of course we are being easy to newcomers but not in a way to 
>> >>>>> allow code that we believe is not good thing to do, but going 
>> >>>>> easy on process may be :)
>> >>>>>
>> >>>>
>> >>>> We are grateful for any leniency you may show us ;-)
>> >>>>
>> >>>> Thanks again,
>> >>>> Christian
>> >>>>
>> >>>>>
>> >>>>>>>
>> >>>>>>>
>> >>>>>>> Thanks,
>> >>>>>>> ferruh
>> >>>>>>
>> >>>>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>> >>>>>>
>> >>>>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>> >>>>>>
>> >>>>>> -Morten
>> >>>
>> >>>
>> >>> We are going to discuss the process in the technical board today.
>> >>>
>> >>>
>> >>
>> >> Hi Mykola, Christiam,
>> >>
>> >> As discussed, following are a few good examples from the DPDK history, there is no "fits all, fixed guidelines", but they can serve as samples:
>> >>
>> >> Marvell cnxk:
>> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>> >> org%2fproject%2fdpdk%2flist%2f%3fseries%3d17449%26state%3d%252A%26a
>> >> rchive%3dboth&c=E,1,DmXU0iHwXoSaZ4bKn-yhX9J8XmFBispd2ut7pxLNBkK3Q4L
>> >> VpG_zmOf1jnWSS-Y0Fx-TNbPnQDHyBZkDj23Gu7zjPZ5nsA7pid5CsE2vxNk,&typo=
>> >> 1
>> >>
>> >>
>> >> Solarflare sfc (before patchwork series support):
>> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>> >> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-2-git-send-email-ar
>> >> ybchenko%40solarflare.com%2f&c=E,1,E9oUT_1WuNC2JA8x7an3rC_Pm5g1L5cx
>> >> JKQ6pTwSbCWSJpiLH2GnmgfFkUqViOOwkpS2df8kgBvHjmulKaWhyr4BBizUT-sL5LJ
>> >> v21Hx4RtHtK3vjhcKpg,,&typo=1
>> >> to
>> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>> >> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-56-git-send-email-a
>> >> rybchenko%40solarflare.com%2f&c=E,1,GByF_TiC_q11iVPpiPgpCMlSge-J0Xf
>> >> T0zHkriK0rde1Qt1RG7uf6mETQkTSQ-1V86Z7EtRcxlvSsed1sqn8RWfN8KFSbd7NaA
>> >> kfbDiehn_vSRzja45rQgv53Q,,&typo=1
>> >>
>> >>
>> >> Intel ice:
>> >> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>> >> org%2fproject%2fdpdk%2flist%2f%3fseries%3d2842%26state%3d%252A%26ar
>> >> chive%3dboth&c=E,1,zQwvAIR3ToLIhT09bVxm_HEF-dp8eyTqhsKB3eOYgIJdd2WS
>> >> _0ZlTbQKfr9KLyTA3A2A2HzBbjIlz21D_hWVgS_INmmC5eew1J0QBH-PoRNd&typo=1
>> >>
>> > 
>> > Thank you for the links, they have been very helpful.
>> > 
>> > After a lot of internal discussion, Napatech has decided to implement some architectural changes to our PMD that will allow us to easier split up the code into smaller features. The work will require some time, which means that we will not be ready for the 23.11 release. The current goal is to attempt to upstream a quite basic PMD in time for 24.7, and a fully featured PMD for 24.11.
>> > 
>> > 
>> 
>> Hi Christiam,
>> 
>> Good to see there is a solid plan for upstreaming but also not that 
>> good that it is postponed,
>> 
>> I am aware it is all tied to your internal planning/resourcing etc, 
>> but since the effort already started, can it be possible to squeeze 
>> very basic driver in this release, which just does link up and most basic Rx/Tx?
>> It gives opportunity to experiment on device to users.
>> 
>> We can accept it up to -rc3, which is end of October, so there is 
>> still some time?
>> 
>> This is just a suggestion though, no pressure intended.
>
> I agree with Ferruh, better to start early and small.
> It shouldn't be too hard to introduce the skeleton of the driver.

Hi Ferruh and Thomas,

My apologies for the late response, I have been sick the last week.

We can try to create a small PMD in time. The reason I'm cautious is because Napatech plan to make quite large changes to the PMD, to achieve a more stable and modular code-base. This means that future updates will have quite large diffs, until these changes are in place.
Ferruh Yigit Oct. 9, 2023, 9:52 a.m. UTC | #12 
On 10/9/2023 8:57 AM, Christian Koue Muf wrote:
> On 9/29/2023 12:24 PM, Thomas Monjalon wrote:
>> 29/09/2023 11:46, Ferruh Yigit:
>>> On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
>>>> On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
>>>>> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
>>>>>> Hello,
>>>>>>
>>>>>> 19/09/2023 11:06, Christian Koue Muf:
>>>>>>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>>>>>>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
>>>>>>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>>>>>>>>>> Sent: Friday, 15 September 2023 17.55
>>>>>>>>>>
>>>>>>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>>>>>>>>>> From: Christian Koue Muf <ckm@napatech.com>
>>>>>>>>>>>
>>>>>>>>>>> The NTNIC PMD does not rely on a kernel space Napatech
>>>>>>>>>>> driver, thus all defines related to the register layout is
>>>>>>>>>>> part of the PMD code, which will be added in later commits.
>>>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>>>>>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Hi Mykola, Christiam,
>>>>>>>>>>
>>>>>>>>>> This PMD scares me, overall it is a big drop:
>>>>>>>>>> "249 files changed, 87128 insertions(+)"
>>>>>>>>>>
>>>>>>>>>> I think it is not possible to review all in one release cycle,
>>>>>>>>>> and it is not even possible to say if all code used or not.
>>>>>>>>>>
>>>>>>>>>> I can see code is already developed, and it is difficult to
>>>>>>>>>> restructure developed code, but restructure it into small
>>>>>>>>>> pieces really helps for reviews.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Driver supports good list of features, can it be possible to
>>>>>>>>>> distribute upstream effort into multiple release.
>>>>>>>>>> Starting from basic functionality and add features gradually.
>>>>>>>>>> Target for this release can be providing datapath, and add
>>>>>>>>>> more if we have time in the release, what do you think?
>>>>>>
>>>>>> I was expecting to get only Rx/Tx in this release, not really more.
>>>>>>
>>>>>> I agree it may be interesting to discuss some design and check
>>>>>> whether we need more features in ethdev as part of the driver
>>>>>> upstreaming process.
>>>>>>
>>>>>>
>>>>>>>>>> Also there are large amount of base code (HAL / FPGA code),
>>>>>>>>>> instead of adding them as a bulk, relevant ones with a feature
>>>>>>>>>> can be added with the feature patch, this eliminates dead code
>>>>>>>>>> in the base code layer, also helps user/review to understand
>>>>>>>>>> the link between driver code and base code.
>>>>>>
>>>>>> Yes it would be interesting to see what is really needed for the
>>>>>> basic initialization and what is linked to a specific offload or configuration feature.
>>>>>>
>>>>>> As a maintainer, I have to do some changes across all drivers
>>>>>> sometimes, and I use git blame a lot to understand why something was added.
>>>>>>
>>>>>>
>>>>>>>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>>>>>>>>>
>>>>>>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>>>>>>>>>
>>>>>>>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>>>>>>>>>
>>>>>>>>
>>>>>>>> Hi Morten,
>>>>>>>>
>>>>>>>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>>>>>>>>
>>>>>>>>
>>>>>>>> But I come up with two main reasons to ask for a rework:
>>>>>>>>
>>>>>>>> 1- Technically any vendor can deliver their software to their
>>>>>>>> customers via a public git repository, they don't have to
>>>>>>>> upstream to
>>>>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E
>>>>>>>> ,1,N
>>>>>>>> poJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9
>>>>>>>> bOLl nhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>>>>>>>> but upstreaming has many benefits.
>>>>>>>>
>>>>>>>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>>>>>>>>
>>>>>>>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>>>>>>>>
>>>>>>>> 2- Make code more accessible to the rest of the world.
>>>>>>>>
>>>>>>>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>>>>>>>>
>>>>>>>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>>>>>>>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>>>>>>>>
>>>>>>>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
>>>>>>
>>>>>> I fully agree about the 2 reasons for upstreaming piece by piece.
>>>>>>
>>>>>>
>>>>>>>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
>>>>>>
>>>>>> In the meantime, if some features are not yet upstreamed in a
>>>>>> release, a user can apply the missing patches from the mailing list to get the features.
>>>>>>
>>>>>>
>>>>>>>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
>>>>>>
>>>>>> You're right Morten, we try to be as welcoming as possible, but as
>>>>>> Ferruh said, we want to be able to understand how a driver is
>>>>>> built, even if not understanding all details.
>>>>>>
>>>>>> In Open Source, I think not only the code should be available, we
>>>>>> must also take care of explanations and documentation.
>>>>>>
>>>>>>
>>>>>>>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>>>>>>>>
>>>>>>>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
>>>>>>
>>>>>> Driver features can be added until -rc2 (in one month).
>>>>>>
>>>>>>
>>>>>>>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
>>>>>>>
>>>>>>> Hi Ferruh,
>>>>>>>
>>>>>>> First of all, thank you for starting the work to review our code.
>>>>>>>
>>>>>>> As Morten said Napatech plans to take all responsibility for the
>>>>>>> quality of the PMD source code. We expect to provide all fixes
>>>>>>> needed in the future. If for some reason Napatech stops
>>>>>>> maintaining the code, then we have been informed that the DPDK
>>>>>>> community might delete the PMD from the repository, and we understand that.
>>>>>>>
>>>>>>> In regards to splitting the code, I don't see this a good option.
>>>>>>> While I of cause agree it would be easier to review and
>>>>>>> understand, the code should also result in a meaningful product.
>>>>>>> Of the 87k lines of code, 53k lines is needed to start-up the
>>>>>>> FPGA to a state the it is ready to receive traffic. But at this
>>>>>>> point all packets would simply be discarded, and to be honest,
>>>>>>> there are better and cheaper options out there, if nothing more
>>>>>>> than basic functionality is needed. 34k lines are used to setup
>>>>>>> filters based on rte_flow. The thing is, that you need to
>>>>>>> initialize all modules in the FPGA TX- and RX-pipelines with valid data, even if you don't need the features those modules provide.
>>>>>>> As a result, if you split up the 34k lines, then the product
>>>>>>> would not be functional. Of cause some of the top level logic
>>>>>>> could be split out, but at this point we are talking about
>>>>>>> splitting 87k lines into 80k and 7k, which I don't think is worth it.
>>>>>>
>>>>>> Actually I think it is worth.
>>>>>> There is a benefit in isolating the small basic init part from the
>>>>>> more complex features.
>>>>>>
>>>>>>
>>>>>>>>>> As far as I understand last patch opens a socket interface and
>>>>>>>>>> an external application can sent control commands via this interface.
>>>>>>>>>> I am not sure about this side control channel, what is missing
>>>>>>>>>> in the DPDK API? Can we try to address them in the DPDK layer
>>>>>>>>>> instead of a driver specific solution?
>>>>>>>>>
>>>>>>>>> That would be great.
>>>>>>>>>
>>>>>>>>> AFAIK, other vendors also has a bunch of out-of-band
>>>>>>>>> communication, e.g. magical EAL parameters to the MLX drivers.
>>>>>>>>> So let's not be too hard on the newcomers. ;-)
>>>>>>>>>
>>>>>>>>
>>>>>>>> I did some thinking for this one too,
>>>>>>>>
>>>>>>>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>>>>>>>> (Indeed there are already some ways to do this, without PMD
>>>>>>>> exposing a socket interface.)
>>>>>>>>
>>>>>>>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>>>>>>>> And overall this reduces portability of the DPDK application,
>>>>>>>> each application becomes unique to a device (This is a bad
>>>>>>>> thing, but I also need some feedback how bad it is in real
>>>>>>>> life.)
>>>>>>>>
>>>>>>>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>>>>>>>>
>>>>>>>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>>>>>>>>
>>>>>>>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>>>>>>>> And improve and extend the ethdev layer to satisfy driver needs.
>>>>>>>>
>>>>>>>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>>>>>>>>
>>>>>>>
>>>>>>> The reason we have the addition control channel is not provide
>>>>>>> additional functionality. We have customers with use-cases that
>>>>>>> require multiple processes. Since Napatech adapters do not
>>>>>>> support configuration through VFs, then secondary applications
>>>>>>> must send their rte_flow to a main application, which will then
>>>>>>> setup the flow through it's PF. This control channel "hides"
>>>>>>> these details, and make the product easier for users to adapt to their existing solutions.
>>>>>>
>>>>>> I think you need to explore VF representors.
>>>>>> This is what is done with other drivers, and it make them compatible.
>>>>>>
>>>>>>> If you stand firm on rejecting the control channel, then we have
>>>>>>> to go back to the drawing board on this issue. We did look at
>>>>>>> DPDK's multi-process support, and actually had some support for
>>>>>>> this, but we determined that for our use-case it was better to
>>>>>>> have a communication channel, and no shared memory.
>>>>>>
>>>>>> I'm not sure your need is about secondary process.
>>>>>> Let's discuss this need in a meeting if needed.
>>>>>> Anyway, the message is that we want to be part of such design decision.
>>>>>>
>>>>>>
>>>>>>>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>>>>>>>>
>>>>>>>> Of course we are being easy to newcomers but not in a way to
>>>>>>>> allow code that we believe is not good thing to do, but going
>>>>>>>> easy on process may be :)
>>>>>>>>
>>>>>>>
>>>>>>> We are grateful for any leniency you may show us ;-)
>>>>>>>
>>>>>>> Thanks again,
>>>>>>> Christian
>>>>>>>
>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Thanks,
>>>>>>>>>> ferruh
>>>>>>>>>
>>>>>>>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>>>>>>>>>
>>>>>>>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>>>>>>>>>
>>>>>>>>> -Morten
>>>>>>
>>>>>>
>>>>>> We are going to discuss the process in the technical board today.
>>>>>>
>>>>>>
>>>>>
>>>>> Hi Mykola, Christiam,
>>>>>
>>>>> As discussed, following are a few good examples from the DPDK history, there is no "fits all, fixed guidelines", but they can serve as samples:
>>>>>
>>>>> Marvell cnxk:
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2flist%2f%3fseries%3d17449%26state%3d%252A%26a
>>>>> rchive%3dboth&c=E,1,DmXU0iHwXoSaZ4bKn-yhX9J8XmFBispd2ut7pxLNBkK3Q4L
>>>>> VpG_zmOf1jnWSS-Y0Fx-TNbPnQDHyBZkDj23Gu7zjPZ5nsA7pid5CsE2vxNk,&typo=
>>>>> 1
>>>>>
>>>>>
>>>>> Solarflare sfc (before patchwork series support):
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-2-git-send-email-ar
>>>>> ybchenko%40solarflare.com%2f&c=E,1,E9oUT_1WuNC2JA8x7an3rC_Pm5g1L5cx
>>>>> JKQ6pTwSbCWSJpiLH2GnmgfFkUqViOOwkpS2df8kgBvHjmulKaWhyr4BBizUT-sL5LJ
>>>>> v21Hx4RtHtK3vjhcKpg,,&typo=1
>>>>> to
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-56-git-send-email-a
>>>>> rybchenko%40solarflare.com%2f&c=E,1,GByF_TiC_q11iVPpiPgpCMlSge-J0Xf
>>>>> T0zHkriK0rde1Qt1RG7uf6mETQkTSQ-1V86Z7EtRcxlvSsed1sqn8RWfN8KFSbd7NaA
>>>>> kfbDiehn_vSRzja45rQgv53Q,,&typo=1
>>>>>
>>>>>
>>>>> Intel ice:
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2flist%2f%3fseries%3d2842%26state%3d%252A%26ar
>>>>> chive%3dboth&c=E,1,zQwvAIR3ToLIhT09bVxm_HEF-dp8eyTqhsKB3eOYgIJdd2WS
>>>>> _0ZlTbQKfr9KLyTA3A2A2HzBbjIlz21D_hWVgS_INmmC5eew1J0QBH-PoRNd&typo=1
>>>>>
>>>>
>>>> Thank you for the links, they have been very helpful.
>>>>
>>>> After a lot of internal discussion, Napatech has decided to implement some architectural changes to our PMD that will allow us to easier split up the code into smaller features. The work will require some time, which means that we will not be ready for the 23.11 release. The current goal is to attempt to upstream a quite basic PMD in time for 24.7, and a fully featured PMD for 24.11.
>>>>
>>>>
>>>
>>> Hi Christiam,
>>>
>>> Good to see there is a solid plan for upstreaming but also not that
>>> good that it is postponed,
>>>
>>> I am aware it is all tied to your internal planning/resourcing etc,
>>> but since the effort already started, can it be possible to squeeze
>>> very basic driver in this release, which just does link up and most basic Rx/Tx?
>>> It gives opportunity to experiment on device to users.
>>>
>>> We can accept it up to -rc3, which is end of October, so there is
>>> still some time?
>>>
>>> This is just a suggestion though, no pressure intended.
>>
>> I agree with Ferruh, better to start early and small.
>> It shouldn't be too hard to introduce the skeleton of the driver.
> 
> Hi Ferruh and Thomas,
> 
> My apologies for the late response, I have been sick the last week.
> 
> We can try to create a small PMD in time. The reason I'm cautious is because Napatech plan to make quite large changes to the PMD, to achieve a more stable and modular code-base. This means that future updates will have quite large diffs, until these changes are in place.
> 

I think upstreaming in this release makes more sense if it is the first
step of the gradually improving/growing the driver process.

If you will need to scratch what exists in this release and replace it
with something completely new, I agree these is less value to upstream
in this release.
Ferruh Yigit March 29, 2024, 11:24 a.m. UTC | #13 
On 10/9/2023 8:57 AM, Christian Koue Muf wrote:
> On 9/29/2023 12:24 PM, Thomas Monjalon wrote:
>> 29/09/2023 11:46, Ferruh Yigit:
>>> On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
>>>> On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
>>>>> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
>>>>>> Hello,
>>>>>>
>>>>>> 19/09/2023 11:06, Christian Koue Muf:
>>>>>>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
>>>>>>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
>>>>>>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
>>>>>>>>>> Sent: Friday, 15 September 2023 17.55
>>>>>>>>>>
>>>>>>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
>>>>>>>>>>> From: Christian Koue Muf <ckm@napatech.com>
>>>>>>>>>>>
>>>>>>>>>>> The NTNIC PMD does not rely on a kernel space Napatech
>>>>>>>>>>> driver, thus all defines related to the register layout is
>>>>>>>>>>> part of the PMD code, which will be added in later commits.
>>>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
>>>>>>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Hi Mykola, Christiam,
>>>>>>>>>>
>>>>>>>>>> This PMD scares me, overall it is a big drop:
>>>>>>>>>> "249 files changed, 87128 insertions(+)"
>>>>>>>>>>
>>>>>>>>>> I think it is not possible to review all in one release cycle,
>>>>>>>>>> and it is not even possible to say if all code used or not.
>>>>>>>>>>
>>>>>>>>>> I can see code is already developed, and it is difficult to
>>>>>>>>>> restructure developed code, but restructure it into small
>>>>>>>>>> pieces really helps for reviews.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Driver supports good list of features, can it be possible to
>>>>>>>>>> distribute upstream effort into multiple release.
>>>>>>>>>> Starting from basic functionality and add features gradually.
>>>>>>>>>> Target for this release can be providing datapath, and add
>>>>>>>>>> more if we have time in the release, what do you think?
>>>>>>
>>>>>> I was expecting to get only Rx/Tx in this release, not really more.
>>>>>>
>>>>>> I agree it may be interesting to discuss some design and check
>>>>>> whether we need more features in ethdev as part of the driver
>>>>>> upstreaming process.
>>>>>>
>>>>>>
>>>>>>>>>> Also there are large amount of base code (HAL / FPGA code),
>>>>>>>>>> instead of adding them as a bulk, relevant ones with a feature
>>>>>>>>>> can be added with the feature patch, this eliminates dead code
>>>>>>>>>> in the base code layer, also helps user/review to understand
>>>>>>>>>> the link between driver code and base code.
>>>>>>
>>>>>> Yes it would be interesting to see what is really needed for the
>>>>>> basic initialization and what is linked to a specific offload or configuration feature.
>>>>>>
>>>>>> As a maintainer, I have to do some changes across all drivers
>>>>>> sometimes, and I use git blame a lot to understand why something was added.
>>>>>>
>>>>>>
>>>>>>>>> Jumping in here with an opinion about welcoming new NIC vendors to the community:
>>>>>>>>>
>>>>>>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the vendor to take responsibility for the quality of the PMD, including providing a maintainer and support backporting of fixes to the PMD in LTS releases. This should align with the vendor's business case for upstreaming their driver.
>>>>>>>>>
>>>>>>>>> If the vendor provides one big patch series, which may be difficult to understand/review, the fallout mainly hits the vendor's customers (and thus the vendor's support organization), not the community as a whole.
>>>>>>>>>
>>>>>>>>
>>>>>>>> Hi Morten,
>>>>>>>>
>>>>>>>> I was thinking same before making my above comment, what happens if vendors submit as one big patch and when a problem occurs we can ask owner to fix. Probably this makes vendor happy and makes my life (or any other maintainer's life) easier, it is always easier to say yes.
>>>>>>>>
>>>>>>>>
>>>>>>>> But I come up with two main reasons to ask for a rework:
>>>>>>>>
>>>>>>>> 1- Technically any vendor can deliver their software to their
>>>>>>>> customers via a public git repository, they don't have to
>>>>>>>> upstream to
>>>>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=E
>>>>>>>> ,1,N
>>>>>>>> poJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J9
>>>>>>>> bOLl nhoR6fFAzWtCzOhRCzVruYj520zZORv6-MjJeSC5TrGnIFL&typo=1,
>>>>>>>> but upstreaming has many benefits.
>>>>>>>>
>>>>>>>> One of those benefits is upstreaming provides a quality assurance for vendor's customers (that is why customer can be asking for this, as we are having in many cases), and this quality assurance comes from additional eyes reviewing the code and guiding vendors for the DPDK quality standards (some vendors already doing pretty good, but new ones sometimes requires hand-holding).
>>>>>>>>
>>>>>>>> If driver is one big patch series, it is practically not possible to review it, I can catch a few bits here or there, you may some others, but practically it will be merged without review, and we will fail on our quality assurance task.
>>>>>>>>
>>>>>>>> 2- Make code more accessible to the rest of the world.
>>>>>>>>
>>>>>>>> When it is a big patch, code can be functional but lots of details, reasoning, relation between components gets lost, which makes it even harder for an external developer, like me, to understand it (I am a mere guinea pig here :).
>>>>>>>>
>>>>>>>> If a customer would like to add a feature themselves, or fix something, even after vendor no more working on that product anymore, customer needs to understand the code or some reasoning in the code.
>>>>>>>> Or if someone wants to backport the driver to rust, or a DPDK developer wants to do a rework that requires updating all drivers, or a tester would like to analyze the code to figure out behavior difference of the devices. I think I have witness all above cases in real life.
>>>>>>>>
>>>>>>>> If driver is split into more patches, it makes patch easier to understand which makes code practically more accessible to other developers that are not expert in driver.
>>>>>>
>>>>>> I fully agree about the 2 reasons for upstreaming piece by piece.
>>>>>>
>>>>>>
>>>>>>>> Overall, yes splitting patch takes time and effort, and yes this is an overhead for a code that is already developed, but I think benefit is big so it worth doing the task.
>>>>>>
>>>>>> In the meantime, if some features are not yet upstreamed in a
>>>>>> release, a user can apply the missing patches from the mailing list to get the features.
>>>>>>
>>>>>>
>>>>>>>>> We, the community, should not make it too difficult for vendors trying to upstream their drivers. I certainly consider it unreasonable to ask a vendor to postpone the release of some existing features by effectively an entire year (considering that only LTS releases are relevant for most of us) because we want the vendor to refactor the patch series to match our preferences within an unrealistic timeframe.
>>>>>>
>>>>>> You're right Morten, we try to be as welcoming as possible, but as
>>>>>> Ferruh said, we want to be able to understand how a driver is
>>>>>> built, even if not understanding all details.
>>>>>>
>>>>>> In Open Source, I think not only the code should be available, we
>>>>>> must also take care of explanations and documentation.
>>>>>>
>>>>>>
>>>>>>>> Agree to not make upstreaming difficult for new vendors, and indeed we are encouraging more vendors to be upstream their code, this is in best interest of both sides.
>>>>>>>>
>>>>>>>> Distributing upstreaming effort to a year was just a suggestion, it can go in earlier as it is becomes ready but I can see it will take time to split driver into features and upstream them.
>>>>>>
>>>>>> Driver features can be added until -rc2 (in one month).
>>>>>>
>>>>>>
>>>>>>>> As I am from a vendor too, I can understand the product/customer pressure, but I hope this approach can encourage vendors start upstreaming early or even better upstream as they develop the code.
>>>>>>>
>>>>>>> Hi Ferruh,
>>>>>>>
>>>>>>> First of all, thank you for starting the work to review our code.
>>>>>>>
>>>>>>> As Morten said Napatech plans to take all responsibility for the
>>>>>>> quality of the PMD source code. We expect to provide all fixes
>>>>>>> needed in the future. If for some reason Napatech stops
>>>>>>> maintaining the code, then we have been informed that the DPDK
>>>>>>> community might delete the PMD from the repository, and we understand that.
>>>>>>>
>>>>>>> In regards to splitting the code, I don't see this a good option.
>>>>>>> While I of cause agree it would be easier to review and
>>>>>>> understand, the code should also result in a meaningful product.
>>>>>>> Of the 87k lines of code, 53k lines is needed to start-up the
>>>>>>> FPGA to a state the it is ready to receive traffic. But at this
>>>>>>> point all packets would simply be discarded, and to be honest,
>>>>>>> there are better and cheaper options out there, if nothing more
>>>>>>> than basic functionality is needed. 34k lines are used to setup
>>>>>>> filters based on rte_flow. The thing is, that you need to
>>>>>>> initialize all modules in the FPGA TX- and RX-pipelines with valid data, even if you don't need the features those modules provide.
>>>>>>> As a result, if you split up the 34k lines, then the product
>>>>>>> would not be functional. Of cause some of the top level logic
>>>>>>> could be split out, but at this point we are talking about
>>>>>>> splitting 87k lines into 80k and 7k, which I don't think is worth it.
>>>>>>
>>>>>> Actually I think it is worth.
>>>>>> There is a benefit in isolating the small basic init part from the
>>>>>> more complex features.
>>>>>>
>>>>>>
>>>>>>>>>> As far as I understand last patch opens a socket interface and
>>>>>>>>>> an external application can sent control commands via this interface.
>>>>>>>>>> I am not sure about this side control channel, what is missing
>>>>>>>>>> in the DPDK API? Can we try to address them in the DPDK layer
>>>>>>>>>> instead of a driver specific solution?
>>>>>>>>>
>>>>>>>>> That would be great.
>>>>>>>>>
>>>>>>>>> AFAIK, other vendors also has a bunch of out-of-band
>>>>>>>>> communication, e.g. magical EAL parameters to the MLX drivers.
>>>>>>>>> So let's not be too hard on the newcomers. ;-)
>>>>>>>>>
>>>>>>>>
>>>>>>>> I did some thinking for this one too,
>>>>>>>>
>>>>>>>> As we are in userspace, it is easy to have side control channel, and this can make users life easy, so this is a practical thing to do.
>>>>>>>> (Indeed there are already some ways to do this, without PMD
>>>>>>>> exposing a socket interface.)
>>>>>>>>
>>>>>>>> But this also reduces effort developers putting on DPDK layer solution, because it is always easier to add more support to the driver only.
>>>>>>>> And overall this reduces portability of the DPDK application,
>>>>>>>> each application becomes unique to a device (This is a bad
>>>>>>>> thing, but I also need some feedback how bad it is in real
>>>>>>>> life.)
>>>>>>>>
>>>>>>>> To balance this, we said if a feature is too specific to a device, it can add device specific API and this is better than device specific features pollute the common, most used code. And push back to introduce more new PMD specific APIs unless it is really needed.
>>>>>>>>
>>>>>>>> But creating a socket interface directly from the driver is more than PMD specific API. Technically application control interface can rely completely to this. Even we assume this is not for control, but just for debug, I can see it can be useful for debug and again practical thing to do, I am still not sure how much it hurts if each driver has a custom socket interface for their debug needs.
>>>>>>>>
>>>>>>>> Overall it makes more sense to me to have a unified/common interface from drivers to DPDK applications, which is through the ethdev layer.
>>>>>>>> And improve and extend the ethdev layer to satisfy driver needs.
>>>>>>>>
>>>>>>>> In this specific example, I am for rejecting the socket interface patch, but I would like to get more feedback from @techboard.
>>>>>>>>
>>>>>>>
>>>>>>> The reason we have the addition control channel is not provide
>>>>>>> additional functionality. We have customers with use-cases that
>>>>>>> require multiple processes. Since Napatech adapters do not
>>>>>>> support configuration through VFs, then secondary applications
>>>>>>> must send their rte_flow to a main application, which will then
>>>>>>> setup the flow through it's PF. This control channel "hides"
>>>>>>> these details, and make the product easier for users to adapt to their existing solutions.
>>>>>>
>>>>>> I think you need to explore VF representors.
>>>>>> This is what is done with other drivers, and it make them compatible.
>>>>>>
>>>>>>> If you stand firm on rejecting the control channel, then we have
>>>>>>> to go back to the drawing board on this issue. We did look at
>>>>>>> DPDK's multi-process support, and actually had some support for
>>>>>>> this, but we determined that for our use-case it was better to
>>>>>>> have a communication channel, and no shared memory.
>>>>>>
>>>>>> I'm not sure your need is about secondary process.
>>>>>> Let's discuss this need in a meeting if needed.
>>>>>> Anyway, the message is that we want to be part of such design decision.
>>>>>>
>>>>>>
>>>>>>>> And related to not being too hard on the newcomers, unrelated to being a newcomer or not, if a process/feature/approach approved once, some others will point to it and will ask to do the same which is fair in their perspective. I had multiple instance of this in the past.
>>>>>>>>
>>>>>>>> Of course we are being easy to newcomers but not in a way to
>>>>>>>> allow code that we believe is not good thing to do, but going
>>>>>>>> easy on process may be :)
>>>>>>>>
>>>>>>>
>>>>>>> We are grateful for any leniency you may show us ;-)
>>>>>>>
>>>>>>> Thanks again,
>>>>>>> Christian
>>>>>>>
>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Thanks,
>>>>>>>>>> ferruh
>>>>>>>>>
>>>>>>>>> Thank you, Ferruh, for taking good care of the community by providing constructive feedback like this to new NIC vendors!
>>>>>>>>>
>>>>>>>>> Please note that my feedback is entirely process related. I didn’t review the driver, so I have no technical comments to the patch series.
>>>>>>>>>
>>>>>>>>> -Morten
>>>>>>
>>>>>>
>>>>>> We are going to discuss the process in the technical board today.
>>>>>>
>>>>>>
>>>>>
>>>>> Hi Mykola, Christiam,
>>>>>
>>>>> As discussed, following are a few good examples from the DPDK history, there is no "fits all, fixed guidelines", but they can serve as samples:
>>>>>
>>>>> Marvell cnxk:
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2flist%2f%3fseries%3d17449%26state%3d%252A%26a
>>>>> rchive%3dboth&c=E,1,DmXU0iHwXoSaZ4bKn-yhX9J8XmFBispd2ut7pxLNBkK3Q4L
>>>>> VpG_zmOf1jnWSS-Y0Fx-TNbPnQDHyBZkDj23Gu7zjPZ5nsA7pid5CsE2vxNk,&typo=
>>>>> 1
>>>>>
>>>>>
>>>>> Solarflare sfc (before patchwork series support):
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-2-git-send-email-ar
>>>>> ybchenko%40solarflare.com%2f&c=E,1,E9oUT_1WuNC2JA8x7an3rC_Pm5g1L5cx
>>>>> JKQ6pTwSbCWSJpiLH2GnmgfFkUqViOOwkpS2df8kgBvHjmulKaWhyr4BBizUT-sL5LJ
>>>>> v21Hx4RtHtK3vjhcKpg,,&typo=1
>>>>> to
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-56-git-send-email-a
>>>>> rybchenko%40solarflare.com%2f&c=E,1,GByF_TiC_q11iVPpiPgpCMlSge-J0Xf
>>>>> T0zHkriK0rde1Qt1RG7uf6mETQkTSQ-1V86Z7EtRcxlvSsed1sqn8RWfN8KFSbd7NaA
>>>>> kfbDiehn_vSRzja45rQgv53Q,,&typo=1
>>>>>
>>>>>
>>>>> Intel ice:
>>>>> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
>>>>> org%2fproject%2fdpdk%2flist%2f%3fseries%3d2842%26state%3d%252A%26ar
>>>>> chive%3dboth&c=E,1,zQwvAIR3ToLIhT09bVxm_HEF-dp8eyTqhsKB3eOYgIJdd2WS
>>>>> _0ZlTbQKfr9KLyTA3A2A2HzBbjIlz21D_hWVgS_INmmC5eew1J0QBH-PoRNd&typo=1
>>>>>
>>>>
>>>> Thank you for the links, they have been very helpful.
>>>>
>>>> After a lot of internal discussion, Napatech has decided to implement some architectural changes to our PMD that will allow us to easier split up the code into smaller features. The work will require some time, which means that we will not be ready for the 23.11 release. The current goal is to attempt to upstream a quite basic PMD in time for 24.7, and a fully featured PMD for 24.11.
>>>>
>>>>
>>>
>>> Hi Christiam,
>>>
>>> Good to see there is a solid plan for upstreaming but also not that
>>> good that it is postponed,
>>>
>>> I am aware it is all tied to your internal planning/resourcing etc,
>>> but since the effort already started, can it be possible to squeeze
>>> very basic driver in this release, which just does link up and most basic Rx/Tx?
>>> It gives opportunity to experiment on device to users.
>>>
>>> We can accept it up to -rc3, which is end of October, so there is
>>> still some time?
>>>
>>> This is just a suggestion though, no pressure intended.
>>
>> I agree with Ferruh, better to start early and small.
>> It shouldn't be too hard to introduce the skeleton of the driver.
> 
> Hi Ferruh and Thomas,
> 
> My apologies for the late response, I have been sick the last week.
> 
> We can try to create a small PMD in time. The reason I'm cautious is because Napatech plan to make quite large changes to the PMD, to achieve a more stable and modular code-base. This means that future updates will have quite large diffs, until these changes are in place.
> 
> 

Hi Christian, Mykola,

What is the status of the 'ntnic'?
Will there be some upstreaming effort for v24.07?
Mykola Kostenok April 3, 2024, 10:55 a.m. UTC | #14 
Hi, Ferruh.
Yes, we plan to send new 'ntnic' patch series into v24.07
Right now, we are doing refactoring of 'ntnic' code to make it modular. So, we will send it split into smaller patches.

Best regards, 
Mykola Kostenok.

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@amd.com>
> Sent: Friday, March 29, 2024 1:25 PM
> To: Christian Koue Muf <ckm@napatech.com>; Thomas Monjalon
> <thomas@monjalon.net>; Morten Brørup <mb@smartsharesystems.com>;
> Mykola Kostenok <mko-plv@napatech.com>
> Cc: dev@dpdk.org; andrew.rybchenko@oktetlabs.ru; techboard@dpdk.org
> Subject: Re: [PATCH v16 1/8] net/ntnic: initial commit which adds register
> defines
> 
> On 10/9/2023 8:57 AM, Christian Koue Muf wrote:
> > On 9/29/2023 12:24 PM, Thomas Monjalon wrote:
> >> 29/09/2023 11:46, Ferruh Yigit:
> >>> On 9/29/2023 10:21 AM, Christian Koue Muf wrote:
> >>>> On 9/21/2023 4:05 PM, Ferruh Yigit wrote:
> >>>>> On 9/20/2023 2:17 PM, Thomas Monjalon wrote:
> >>>>>> Hello,
> >>>>>>
> >>>>>> 19/09/2023 11:06, Christian Koue Muf:
> >>>>>>> On 9/18/23 10:34 AM, Ferruh Yigit wrote:
> >>>>>>>> On 9/15/2023 7:37 PM, Morten Brørup wrote:
> >>>>>>>>>> From: Ferruh Yigit [mailto:ferruh.yigit@amd.com]
> >>>>>>>>>> Sent: Friday, 15 September 2023 17.55
> >>>>>>>>>>
> >>>>>>>>>> On 9/8/2023 5:07 PM, Mykola Kostenok wrote:
> >>>>>>>>>>> From: Christian Koue Muf <ckm@napatech.com>
> >>>>>>>>>>>
> >>>>>>>>>>> The NTNIC PMD does not rely on a kernel space Napatech
> >>>>>>>>>>> driver, thus all defines related to the register layout is
> >>>>>>>>>>> part of the PMD code, which will be added in later commits.
> >>>>>>>>>>>
> >>>>>>>>>>> Signed-off-by: Christian Koue Muf <ckm@napatech.com>
> >>>>>>>>>>> Reviewed-by: Mykola Kostenok <mko-plv@napatech.com>
> >>>>>>>>>>>
> >>>>>>>>>>
> >>>>>>>>>> Hi Mykola, Christiam,
> >>>>>>>>>>
> >>>>>>>>>> This PMD scares me, overall it is a big drop:
> >>>>>>>>>> "249 files changed, 87128 insertions(+)"
> >>>>>>>>>>
> >>>>>>>>>> I think it is not possible to review all in one release
> >>>>>>>>>> cycle, and it is not even possible to say if all code used or not.
> >>>>>>>>>>
> >>>>>>>>>> I can see code is already developed, and it is difficult to
> >>>>>>>>>> restructure developed code, but restructure it into small
> >>>>>>>>>> pieces really helps for reviews.
> >>>>>>>>>>
> >>>>>>>>>>
> >>>>>>>>>> Driver supports good list of features, can it be possible to
> >>>>>>>>>> distribute upstream effort into multiple release.
> >>>>>>>>>> Starting from basic functionality and add features gradually.
> >>>>>>>>>> Target for this release can be providing datapath, and add
> >>>>>>>>>> more if we have time in the release, what do you think?
> >>>>>>
> >>>>>> I was expecting to get only Rx/Tx in this release, not really more.
> >>>>>>
> >>>>>> I agree it may be interesting to discuss some design and check
> >>>>>> whether we need more features in ethdev as part of the driver
> >>>>>> upstreaming process.
> >>>>>>
> >>>>>>
> >>>>>>>>>> Also there are large amount of base code (HAL / FPGA code),
> >>>>>>>>>> instead of adding them as a bulk, relevant ones with a
> >>>>>>>>>> feature can be added with the feature patch, this eliminates
> >>>>>>>>>> dead code in the base code layer, also helps user/review to
> >>>>>>>>>> understand the link between driver code and base code.
> >>>>>>
> >>>>>> Yes it would be interesting to see what is really needed for the
> >>>>>> basic initialization and what is linked to a specific offload or
> configuration feature.
> >>>>>>
> >>>>>> As a maintainer, I have to do some changes across all drivers
> >>>>>> sometimes, and I use git blame a lot to understand why something
> was added.
> >>>>>>
> >>>>>>
> >>>>>>>>> Jumping in here with an opinion about welcoming new NIC
> vendors to the community:
> >>>>>>>>>
> >>>>>>>>> Generally, if a NIC vendor supplies a PMD for their NIC, I expect the
> vendor to take responsibility for the quality of the PMD, including providing a
> maintainer and support backporting of fixes to the PMD in LTS releases. This
> should align with the vendor's business case for upstreaming their driver.
> >>>>>>>>>
> >>>>>>>>> If the vendor provides one big patch series, which may be difficult
> to understand/review, the fallout mainly hits the vendor's customers (and
> thus the vendor's support organization), not the community as a whole.
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> Hi Morten,
> >>>>>>>>
> >>>>>>>> I was thinking same before making my above comment, what
> happens if vendors submit as one big patch and when a problem occurs we
> can ask owner to fix. Probably this makes vendor happy and makes my life (or
> any other maintainer's life) easier, it is always easier to say yes.
> >>>>>>>>
> >>>>>>>>
> >>>>>>>> But I come up with two main reasons to ask for a rework:
> >>>>>>>>
> >>>>>>>> 1- Technically any vendor can deliver their software to their
> >>>>>>>> customers via a public git repository, they don't have to
> >>>>>>>> upstream to
> >>>>>>>>
> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fdpdk.org&c=
> >>>>>>>> E
> >>>>>>>> ,1,N
> >>>>>>>>
> poJejuuvPdOPfcFJYtsmkQF6PVrDjGsZ8x_gi5xDrTyZokK_nM11u4ZpzHgM10J
> >>>>>>>> 9 bOLl nhoR6fFAzWtCzOhRCzVruYj520zZORv6-
> MjJeSC5TrGnIFL&typo=1,
> >>>>>>>> but upstreaming has many benefits.
> >>>>>>>>
> >>>>>>>> One of those benefits is upstreaming provides a quality assurance
> for vendor's customers (that is why customer can be asking for this, as we are
> having in many cases), and this quality assurance comes from additional eyes
> reviewing the code and guiding vendors for the DPDK quality standards (some
> vendors already doing pretty good, but new ones sometimes requires hand-
> holding).
> >>>>>>>>
> >>>>>>>> If driver is one big patch series, it is practically not possible to review
> it, I can catch a few bits here or there, you may some others, but practically it
> will be merged without review, and we will fail on our quality assurance task.
> >>>>>>>>
> >>>>>>>> 2- Make code more accessible to the rest of the world.
> >>>>>>>>
> >>>>>>>> When it is a big patch, code can be functional but lots of details,
> reasoning, relation between components gets lost, which makes it even harder
> for an external developer, like me, to understand it (I am a mere guinea pig
> here :).
> >>>>>>>>
> >>>>>>>> If a customer would like to add a feature themselves, or fix
> something, even after vendor no more working on that product anymore,
> customer needs to understand the code or some reasoning in the code.
> >>>>>>>> Or if someone wants to backport the driver to rust, or a DPDK
> developer wants to do a rework that requires updating all drivers, or a tester
> would like to analyze the code to figure out behavior difference of the devices.
> I think I have witness all above cases in real life.
> >>>>>>>>
> >>>>>>>> If driver is split into more patches, it makes patch easier to
> understand which makes code practically more accessible to other developers
> that are not expert in driver.
> >>>>>>
> >>>>>> I fully agree about the 2 reasons for upstreaming piece by piece.
> >>>>>>
> >>>>>>
> >>>>>>>> Overall, yes splitting patch takes time and effort, and yes this is an
> overhead for a code that is already developed, but I think benefit is big so it
> worth doing the task.
> >>>>>>
> >>>>>> In the meantime, if some features are not yet upstreamed in a
> >>>>>> release, a user can apply the missing patches from the mailing list to
> get the features.
> >>>>>>
> >>>>>>
> >>>>>>>>> We, the community, should not make it too difficult for vendors
> trying to upstream their drivers. I certainly consider it unreasonable to ask a
> vendor to postpone the release of some existing features by effectively an
> entire year (considering that only LTS releases are relevant for most of us)
> because we want the vendor to refactor the patch series to match our
> preferences within an unrealistic timeframe.
> >>>>>>
> >>>>>> You're right Morten, we try to be as welcoming as possible, but
> >>>>>> as Ferruh said, we want to be able to understand how a driver is
> >>>>>> built, even if not understanding all details.
> >>>>>>
> >>>>>> In Open Source, I think not only the code should be available, we
> >>>>>> must also take care of explanations and documentation.
> >>>>>>
> >>>>>>
> >>>>>>>> Agree to not make upstreaming difficult for new vendors, and
> indeed we are encouraging more vendors to be upstream their code, this is in
> best interest of both sides.
> >>>>>>>>
> >>>>>>>> Distributing upstreaming effort to a year was just a suggestion, it can
> go in earlier as it is becomes ready but I can see it will take time to split driver
> into features and upstream them.
> >>>>>>
> >>>>>> Driver features can be added until -rc2 (in one month).
> >>>>>>
> >>>>>>
> >>>>>>>> As I am from a vendor too, I can understand the product/customer
> pressure, but I hope this approach can encourage vendors start upstreaming
> early or even better upstream as they develop the code.
> >>>>>>>
> >>>>>>> Hi Ferruh,
> >>>>>>>
> >>>>>>> First of all, thank you for starting the work to review our code.
> >>>>>>>
> >>>>>>> As Morten said Napatech plans to take all responsibility for the
> >>>>>>> quality of the PMD source code. We expect to provide all fixes
> >>>>>>> needed in the future. If for some reason Napatech stops
> >>>>>>> maintaining the code, then we have been informed that the DPDK
> >>>>>>> community might delete the PMD from the repository, and we
> understand that.
> >>>>>>>
> >>>>>>> In regards to splitting the code, I don't see this a good option.
> >>>>>>> While I of cause agree it would be easier to review and
> >>>>>>> understand, the code should also result in a meaningful product.
> >>>>>>> Of the 87k lines of code, 53k lines is needed to start-up the
> >>>>>>> FPGA to a state the it is ready to receive traffic. But at this
> >>>>>>> point all packets would simply be discarded, and to be honest,
> >>>>>>> there are better and cheaper options out there, if nothing more
> >>>>>>> than basic functionality is needed. 34k lines are used to setup
> >>>>>>> filters based on rte_flow. The thing is, that you need to
> >>>>>>> initialize all modules in the FPGA TX- and RX-pipelines with valid data,
> even if you don't need the features those modules provide.
> >>>>>>> As a result, if you split up the 34k lines, then the product
> >>>>>>> would not be functional. Of cause some of the top level logic
> >>>>>>> could be split out, but at this point we are talking about
> >>>>>>> splitting 87k lines into 80k and 7k, which I don't think is worth it.
> >>>>>>
> >>>>>> Actually I think it is worth.
> >>>>>> There is a benefit in isolating the small basic init part from
> >>>>>> the more complex features.
> >>>>>>
> >>>>>>
> >>>>>>>>>> As far as I understand last patch opens a socket interface
> >>>>>>>>>> and an external application can sent control commands via this
> interface.
> >>>>>>>>>> I am not sure about this side control channel, what is
> >>>>>>>>>> missing in the DPDK API? Can we try to address them in the
> >>>>>>>>>> DPDK layer instead of a driver specific solution?
> >>>>>>>>>
> >>>>>>>>> That would be great.
> >>>>>>>>>
> >>>>>>>>> AFAIK, other vendors also has a bunch of out-of-band
> >>>>>>>>> communication, e.g. magical EAL parameters to the MLX drivers.
> >>>>>>>>> So let's not be too hard on the newcomers. ;-)
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> I did some thinking for this one too,
> >>>>>>>>
> >>>>>>>> As we are in userspace, it is easy to have side control channel, and
> this can make users life easy, so this is a practical thing to do.
> >>>>>>>> (Indeed there are already some ways to do this, without PMD
> >>>>>>>> exposing a socket interface.)
> >>>>>>>>
> >>>>>>>> But this also reduces effort developers putting on DPDK layer
> solution, because it is always easier to add more support to the driver only.
> >>>>>>>> And overall this reduces portability of the DPDK application,
> >>>>>>>> each application becomes unique to a device (This is a bad
> >>>>>>>> thing, but I also need some feedback how bad it is in real
> >>>>>>>> life.)
> >>>>>>>>
> >>>>>>>> To balance this, we said if a feature is too specific to a device, it can
> add device specific API and this is better than device specific features pollute
> the common, most used code. And push back to introduce more new PMD
> specific APIs unless it is really needed.
> >>>>>>>>
> >>>>>>>> But creating a socket interface directly from the driver is more than
> PMD specific API. Technically application control interface can rely completely
> to this. Even we assume this is not for control, but just for debug, I can see it
> can be useful for debug and again practical thing to do, I am still not sure how
> much it hurts if each driver has a custom socket interface for their debug
> needs.
> >>>>>>>>
> >>>>>>>> Overall it makes more sense to me to have a unified/common
> interface from drivers to DPDK applications, which is through the ethdev layer.
> >>>>>>>> And improve and extend the ethdev layer to satisfy driver needs.
> >>>>>>>>
> >>>>>>>> In this specific example, I am for rejecting the socket interface patch,
> but I would like to get more feedback from @techboard.
> >>>>>>>>
> >>>>>>>
> >>>>>>> The reason we have the addition control channel is not provide
> >>>>>>> additional functionality. We have customers with use-cases that
> >>>>>>> require multiple processes. Since Napatech adapters do not
> >>>>>>> support configuration through VFs, then secondary applications
> >>>>>>> must send their rte_flow to a main application, which will then
> >>>>>>> setup the flow through it's PF. This control channel "hides"
> >>>>>>> these details, and make the product easier for users to adapt to their
> existing solutions.
> >>>>>>
> >>>>>> I think you need to explore VF representors.
> >>>>>> This is what is done with other drivers, and it make them compatible.
> >>>>>>
> >>>>>>> If you stand firm on rejecting the control channel, then we have
> >>>>>>> to go back to the drawing board on this issue. We did look at
> >>>>>>> DPDK's multi-process support, and actually had some support for
> >>>>>>> this, but we determined that for our use-case it was better to
> >>>>>>> have a communication channel, and no shared memory.
> >>>>>>
> >>>>>> I'm not sure your need is about secondary process.
> >>>>>> Let's discuss this need in a meeting if needed.
> >>>>>> Anyway, the message is that we want to be part of such design
> decision.
> >>>>>>
> >>>>>>
> >>>>>>>> And related to not being too hard on the newcomers, unrelated to
> being a newcomer or not, if a process/feature/approach approved once, some
> others will point to it and will ask to do the same which is fair in their
> perspective. I had multiple instance of this in the past.
> >>>>>>>>
> >>>>>>>> Of course we are being easy to newcomers but not in a way to
> >>>>>>>> allow code that we believe is not good thing to do, but going
> >>>>>>>> easy on process may be :)
> >>>>>>>>
> >>>>>>>
> >>>>>>> We are grateful for any leniency you may show us ;-)
> >>>>>>>
> >>>>>>> Thanks again,
> >>>>>>> Christian
> >>>>>>>
> >>>>>>>>
> >>>>>>>>>>
> >>>>>>>>>>
> >>>>>>>>>> Thanks,
> >>>>>>>>>> ferruh
> >>>>>>>>>
> >>>>>>>>> Thank you, Ferruh, for taking good care of the community by
> providing constructive feedback like this to new NIC vendors!
> >>>>>>>>>
> >>>>>>>>> Please note that my feedback is entirely process related. I didn’t
> review the driver, so I have no technical comments to the patch series.
> >>>>>>>>>
> >>>>>>>>> -Morten
> >>>>>>
> >>>>>>
> >>>>>> We are going to discuss the process in the technical board today.
> >>>>>>
> >>>>>>
> >>>>>
> >>>>> Hi Mykola, Christiam,
> >>>>>
> >>>>> As discussed, following are a few good examples from the DPDK history,
> there is no "fits all, fixed guidelines", but they can serve as samples:
> >>>>>
> >>>>> Marvell cnxk:
> >>>>>
> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
> >>>>>
> org%2fproject%2fdpdk%2flist%2f%3fseries%3d17449%26state%3d%252A%
> 26
> >>>>> a
> >>>>> rchive%3dboth&c=E,1,DmXU0iHwXoSaZ4bKn-
> yhX9J8XmFBispd2ut7pxLNBkK3Q4
> >>>>> L
> >>>>> VpG_zmOf1jnWSS-Y0Fx-
> TNbPnQDHyBZkDj23Gu7zjPZ5nsA7pid5CsE2vxNk,&typo
> >>>>> =
> >>>>> 1
> >>>>>
> >>>>>
> >>>>> Solarflare sfc (before patchwork series support):
> >>>>>
> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
> >>>>> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-2-git-send-
> email-a
> >>>>> r
> >>>>>
> ybchenko%40solarflare.com%2f&c=E,1,E9oUT_1WuNC2JA8x7an3rC_Pm5g1
> L5c
> >>>>> x
> >>>>>
> JKQ6pTwSbCWSJpiLH2GnmgfFkUqViOOwkpS2df8kgBvHjmulKaWhyr4BBizUT
> -sL5L
> >>>>> J
> >>>>> v21Hx4RtHtK3vjhcKpg,,&typo=1
> >>>>> to
> >>>>>
> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
> >>>>> org%2fproject%2fdpdk%2fpatch%2f1480436367-20749-56-git-send-
> email-
> >>>>> a
> >>>>>
> rybchenko%40solarflare.com%2f&c=E,1,GByF_TiC_q11iVPpiPgpCMlSge-J0X
> >>>>> f
> >>>>> T0zHkriK0rde1Qt1RG7uf6mETQkTSQ-
> 1V86Z7EtRcxlvSsed1sqn8RWfN8KFSbd7Na
> >>>>> A
> >>>>> kfbDiehn_vSRzja45rQgv53Q,,&typo=1
> >>>>>
> >>>>>
> >>>>> Intel ice:
> >>>>>
> https://linkprotect.cudasvc.com/url?a=https%3a%2f%2fpatchwork.dpdk.
> >>>>>
> org%2fproject%2fdpdk%2flist%2f%3fseries%3d2842%26state%3d%252A%2
> 6a
> >>>>> r
> >>>>> chive%3dboth&c=E,1,zQwvAIR3ToLIhT09bVxm_HEF-
> dp8eyTqhsKB3eOYgIJdd2W
> >>>>> S
> >>>>> _0ZlTbQKfr9KLyTA3A2A2HzBbjIlz21D_hWVgS_INmmC5eew1J0QBH-
> PoRNd&typo=
> >>>>> 1
> >>>>>
> >>>>
> >>>> Thank you for the links, they have been very helpful.
> >>>>
> >>>> After a lot of internal discussion, Napatech has decided to implement
> some architectural changes to our PMD that will allow us to easier split up the
> code into smaller features. The work will require some time, which means that
> we will not be ready for the 23.11 release. The current goal is to attempt to
> upstream a quite basic PMD in time for 24.7, and a fully featured PMD for
> 24.11.
> >>>>
> >>>>
> >>>
> >>> Hi Christiam,
> >>>
> >>> Good to see there is a solid plan for upstreaming but also not that
> >>> good that it is postponed,
> >>>
> >>> I am aware it is all tied to your internal planning/resourcing etc,
> >>> but since the effort already started, can it be possible to squeeze
> >>> very basic driver in this release, which just does link up and most basic
> Rx/Tx?
> >>> It gives opportunity to experiment on device to users.
> >>>
> >>> We can accept it up to -rc3, which is end of October, so there is
> >>> still some time?
> >>>
> >>> This is just a suggestion though, no pressure intended.
> >>
> >> I agree with Ferruh, better to start early and small.
> >> It shouldn't be too hard to introduce the skeleton of the driver.
> >
> > Hi Ferruh and Thomas,
> >
> > My apologies for the late response, I have been sick the last week.
> >
> > We can try to create a small PMD in time. The reason I'm cautious is because
> Napatech plan to make quite large changes to the PMD, to achieve a more
> stable and modular code-base. This means that future updates will have quite
> large diffs, until these changes are in place.
> >
> >
> 
> Hi Christian, Mykola,
> 
> What is the status of the 'ntnic'?
> Will there be some upstreaming effort for v24.07?
Ferruh Yigit April 4, 2024, 12:49 p.m. UTC | #15 
On 4/3/2024 11:55 AM, Mykola Kostenok wrote:

<...>

>>
>> Hi Christian, Mykola,
>>
>> What is the status of the 'ntnic'?
>> Will there be some upstreaming effort for v24.07?
> 
> Hi, Ferruh.
> Yes, we plan to send new 'ntnic' patch series into v24.07
> Right now, we are doing refactoring of 'ntnic' code to make it modular. So, we will send it split into smaller patches.
> 
> 

Great, thanks for the update.
Just a reminder that you can start small, no need to wait all features
to be ready.
diff mbox series

Patch

diff --git a/drivers/net/meson.build b/drivers/net/meson.build
index bd38b533c5..fb6d34b782 100644
--- a/drivers/net/meson.build
+++ b/drivers/net/meson.build
@@ -45,6 +45,7 @@  drivers = [
         'nfb',
         'nfp',
         'ngbe',
+        'ntnic',
         'null',
         'octeontx',
         'octeon_ep',
diff --git a/drivers/net/ntnic/include/fpga_model.h b/drivers/net/ntnic/include/fpga_model.h
new file mode 100644
index 0000000000..89f1ae9736
--- /dev/null
+++ b/drivers/net/ntnic/include/fpga_model.h
@@ -0,0 +1,99 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef FPGA_MODEL_H_
+#define FPGA_MODEL_H_
+
+#include <unistd.h>
+#include <stdint.h>
+#include <inttypes.h>
+
+enum nt_fpga_bus_type {
+	BUS_TYPE_UNKNOWN =
+		0, /* Unknown/uninitialized - keep this as the first enum element */
+	BUS_TYPE_BAR,
+	BUS_TYPE_PCI,
+	BUS_TYPE_CCIP,
+	BUS_TYPE_RAB0,
+	BUS_TYPE_RAB1,
+	BUS_TYPE_RAB2,
+	BUS_TYPE_NMB,
+	BUS_TYPE_NDM,
+	BUS_TYPE_SPI0,
+	BUS_TYPE_SPI = BUS_TYPE_SPI0,
+};
+
+typedef enum nt_fpga_bus_type nt_fpga_bus_type_t;
+
+enum nt_fpga_register_type {
+	REGISTER_TYPE_UNKNOWN =
+		0, /* Unknown/uninitialized - keep this as the first enum element */
+	REGISTER_TYPE_RW,
+	REGISTER_TYPE_RO,
+	REGISTER_TYPE_WO,
+	REGISTER_TYPE_RC1,
+	REGISTER_TYPE_MIXED,
+};
+
+typedef enum nt_fpga_register_type nt_fpga_register_type_t;
+
+struct nt_fpga_field_init {
+	int id;
+	uint16_t bw;
+	uint16_t low;
+	uint64_t reset_val;
+};
+
+typedef struct nt_fpga_field_init nt_fpga_field_init_t;
+
+struct nt_fpga_register_init {
+	int id;
+	uint32_t addr_rel;
+	uint16_t bw;
+	nt_fpga_register_type_t type;
+	uint64_t reset_val;
+	int nb_fields;
+	struct nt_fpga_field_init *fields;
+};
+
+typedef struct nt_fpga_register_init nt_fpga_register_init_t;
+
+struct nt_fpga_module_init {
+	int id;
+	int instance;
+	int def_id;
+	int major_version;
+	int minor_version;
+	nt_fpga_bus_type_t bus_id;
+	uint32_t addr_base;
+	int nb_registers;
+	struct nt_fpga_register_init *registers;
+};
+
+typedef struct nt_fpga_module_init nt_fpga_module_init_t;
+
+struct nt_fpga_prod_param {
+	const int param_id;
+	const int param_value;
+};
+
+typedef struct nt_fpga_prod_param nt_fpga_prod_param_t;
+
+struct nt_fpga_prod_init {
+	int fpga_item_id;
+	int fpga_product_id;
+	int fpga_version;
+	int fpga_revision;
+	int fpga_patch_no;
+	int fpga_build_no;
+	uint32_t fpga_build_time;
+	int nb_prod_params;
+	struct nt_fpga_prod_param *product_params;
+	int nb_modules;
+	struct nt_fpga_module_init *modules;
+};
+
+typedef struct nt_fpga_prod_init nt_fpga_prod_init_t;
+
+#endif /* FPGA_MODEL_H_ */
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
new file mode 100644
index 0000000000..1194ce6aea
--- /dev/null
+++ b/drivers/net/ntnic/meson.build
@@ -0,0 +1,30 @@ 
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2020-2023 Napatech A/S
+
+if not is_linux or not dpdk_conf.has('RTE_ARCH_X86_64')
+    build = false
+    reason = 'only supported on x86_64 Linux'
+    subdir_done()
+endif
+
+# includes
+includes = [
+    include_directories('.'),
+    include_directories('include'),
+    include_directories('nthw'),
+    include_directories('nthw/supported'),
+]
+
+# all sources
+sources = files(
+    'nthw/supported/nthw_fpga_9563_055_024_0000.c',
+)
+
+if is_variable('default_cflags')
+      cflags += default_cflags
+else
+      cflags += machine_args
+      cflags += ['-DALLOW_INTERNAL_API']
+endif
+
+# END
diff --git a/drivers/net/ntnic/nthw/nthw_register.h b/drivers/net/ntnic/nthw/nthw_register.h
new file mode 100644
index 0000000000..5cdbd9fc5d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_register.h
@@ -0,0 +1,19 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_REGISTER_H_
+#define NTHW_REGISTER_H_
+
+#include <unistd.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <inttypes.h>
+
+#include "fpga_model.h"
+
+#include "nthw_fpga_modules_defs.h"
+#include "nthw_fpga_parameters_defs.h"
+#include "nthw_fpga_registers_defs.h"
+
+#endif /* NTHW_REGISTER_H_ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c
new file mode 100644
index 0000000000..6d8916db14
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c
@@ -0,0 +1,4190 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "nthw_register.h"
+
+static nt_fpga_field_init_t cat_cct_ctrl_fields[] = {
+	{ CAT_CCT_CTRL_ADR, 8, 0, 0x0000 },
+	{ CAT_CCT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cct_data_fields[] = {
+	{ CAT_CCT_DATA_COLOR, 32, 0, 0x0000 },
+	{ CAT_CCT_DATA_KM, 4, 32, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cfn_ctrl_fields[] = {
+	{ CAT_CFN_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_CFN_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cfn_data_fields[] = {
+	{ CAT_CFN_DATA_ENABLE, 1, 0, 0x0000 },
+	{ CAT_CFN_DATA_ERR_CV, 2, 99, 0x0000 },
+	{ CAT_CFN_DATA_ERR_FCS, 2, 101, 0x0000 },
+	{ CAT_CFN_DATA_ERR_INV, 1, 98, 0x0000 },
+	{ CAT_CFN_DATA_ERR_L3_CS, 2, 105, 0x0000 },
+	{ CAT_CFN_DATA_ERR_L4_CS, 2, 107, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TNL_L3_CS, 2, 109, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TNL_L4_CS, 2, 111, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TNL_TTL_EXP, 2, 115, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TRUNC, 2, 103, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TTL_EXP, 2, 113, 0x0000 },
+	{ CAT_CFN_DATA_INV, 1, 1, 0x0000 },
+	{ CAT_CFN_DATA_KM0_OR, 3, 173, 0x0000 },
+	{ CAT_CFN_DATA_KM1_OR, 3, 176, 0x0000 },
+	{ CAT_CFN_DATA_LC, 8, 164, 0x0000 },
+	{ CAT_CFN_DATA_LC_INV, 1, 172, 0x0000 },
+	{ CAT_CFN_DATA_MAC_PORT, 2, 117, 0x0000 },
+	{ CAT_CFN_DATA_PM_AND_INV, 1, 161, 0x0000 },
+	{ CAT_CFN_DATA_PM_CMB, 4, 157, 0x0000 },
+	{ CAT_CFN_DATA_PM_CMP, 32, 119, 0x0000 },
+	{ CAT_CFN_DATA_PM_DCT, 2, 151, 0x0000 },
+	{ CAT_CFN_DATA_PM_EXT_INV, 4, 153, 0x0000 },
+	{ CAT_CFN_DATA_PM_INV, 1, 163, 0x0000 },
+	{ CAT_CFN_DATA_PM_OR_INV, 1, 162, 0x0000 },
+	{ CAT_CFN_DATA_PTC_CFP, 2, 5, 0x0000 },
+	{ CAT_CFN_DATA_PTC_FRAG, 4, 36, 0x0000 },
+	{ CAT_CFN_DATA_PTC_INV, 1, 2, 0x0000 },
+	{ CAT_CFN_DATA_PTC_IP_PROT, 8, 40, 0x0000 },
+	{ CAT_CFN_DATA_PTC_ISL, 2, 3, 0x0000 },
+	{ CAT_CFN_DATA_PTC_L2, 7, 12, 0x0000 },
+	{ CAT_CFN_DATA_PTC_L3, 3, 33, 0x0000 },
+	{ CAT_CFN_DATA_PTC_L4, 5, 48, 0x0000 },
+	{ CAT_CFN_DATA_PTC_MAC, 5, 7, 0x0000 },
+	{ CAT_CFN_DATA_PTC_MPLS, 8, 25, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_FRAG, 4, 81, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_IP_PROT, 8, 85, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_L2, 2, 64, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_L3, 3, 78, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_L4, 5, 93, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_MPLS, 8, 70, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_VLAN, 4, 66, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TUNNEL, 11, 53, 0x0000 },
+	{ CAT_CFN_DATA_PTC_VLAN, 4, 21, 0x0000 },
+	{ CAT_CFN_DATA_PTC_VNTAG, 2, 19, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cot_ctrl_fields[] = {
+	{ CAT_COT_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_COT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cot_data_fields[] = {
+	{ CAT_COT_DATA_COLOR, 32, 0, 0x0000 },
+	{ CAT_COT_DATA_KM, 4, 32, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cte_ctrl_fields[] = {
+	{ CAT_CTE_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_CTE_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cte_data_fields[] = {
+	{ CAT_CTE_DATA_COL_ENABLE, 1, 0, 0x0000 },
+	{ CAT_CTE_DATA_COR_ENABLE, 1, 1, 0x0000 },
+	{ CAT_CTE_DATA_EPP_ENABLE, 1, 9, 0x0000 },
+	{ CAT_CTE_DATA_HSH_ENABLE, 1, 2, 0x0000 },
+	{ CAT_CTE_DATA_HST_ENABLE, 1, 8, 0x0000 },
+	{ CAT_CTE_DATA_IPF_ENABLE, 1, 4, 0x0000 },
+	{ CAT_CTE_DATA_MSK_ENABLE, 1, 7, 0x0000 },
+	{ CAT_CTE_DATA_PDB_ENABLE, 1, 6, 0x0000 },
+	{ CAT_CTE_DATA_QSL_ENABLE, 1, 3, 0x0000 },
+	{ CAT_CTE_DATA_SLC_ENABLE, 1, 5, 0x0000 },
+	{ CAT_CTE_DATA_TPE_ENABLE, 1, 10, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cts_ctrl_fields[] = {
+	{ CAT_CTS_CTRL_ADR, 9, 0, 0x0000 },
+	{ CAT_CTS_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_cts_data_fields[] = {
+	{ CAT_CTS_DATA_CAT_A, 6, 0, 0x0000 },
+	{ CAT_CTS_DATA_CAT_B, 6, 6, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_dct_ctrl_fields[] = {
+	{ CAT_DCT_CTRL_ADR, 13, 0, 0x0000 },
+	{ CAT_DCT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_dct_data_fields[] = {
+	{ CAT_DCT_DATA_RES, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_dct_sel_fields[] = {
+	{ CAT_DCT_SEL_LU, 2, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_exo_ctrl_fields[] = {
+	{ CAT_EXO_CTRL_ADR, 2, 0, 0x0000 },
+	{ CAT_EXO_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_exo_data_fields[] = {
+	{ CAT_EXO_DATA_DYN, 5, 0, 0x0000 },
+	{ CAT_EXO_DATA_OFS, 11, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_fte0_ctrl_fields[] = {
+	{ CAT_FTE0_CTRL_ADR, 9, 0, 0x0000 },
+	{ CAT_FTE0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_fte0_data_fields[] = {
+	{ CAT_FTE0_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_fte1_ctrl_fields[] = {
+	{ CAT_FTE1_CTRL_ADR, 9, 0, 0x0000 },
+	{ CAT_FTE1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_fte1_data_fields[] = {
+	{ CAT_FTE1_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_join_fields[] = {
+	{ CAT_JOIN_J1, 2, 0, 0x0000 },
+	{ CAT_JOIN_J2, 1, 8, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kcc_ctrl_fields[] = {
+	{ CAT_KCC_CTRL_ADR, 11, 0, 0x0000 },
+	{ CAT_KCC_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kcc_data_fields[] = {
+	{ CAT_KCC_DATA_CATEGORY, 8, 64, 0x0000 },
+	{ CAT_KCC_DATA_ID, 12, 72, 0x0000 },
+	{ CAT_KCC_DATA_KEY, 64, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kce0_ctrl_fields[] = {
+	{ CAT_KCE0_CTRL_ADR, 3, 0, 0x0000 },
+	{ CAT_KCE0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kce0_data_fields[] = {
+	{ CAT_KCE0_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kce1_ctrl_fields[] = {
+	{ CAT_KCE1_CTRL_ADR, 3, 0, 0x0000 },
+	{ CAT_KCE1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kce1_data_fields[] = {
+	{ CAT_KCE1_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kcs0_ctrl_fields[] = {
+	{ CAT_KCS0_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_KCS0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kcs0_data_fields[] = {
+	{ CAT_KCS0_DATA_CATEGORY, 6, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kcs1_ctrl_fields[] = {
+	{ CAT_KCS1_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_KCS1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_kcs1_data_fields[] = {
+	{ CAT_KCS1_DATA_CATEGORY, 6, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_len_ctrl_fields[] = {
+	{ CAT_LEN_CTRL_ADR, 3, 0, 0x0000 },
+	{ CAT_LEN_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_len_data_fields[] = {
+	{ CAT_LEN_DATA_DYN1, 5, 28, 0x0000 },
+	{ CAT_LEN_DATA_DYN2, 5, 33, 0x0000 },
+	{ CAT_LEN_DATA_INV, 1, 38, 0x0000 },
+	{ CAT_LEN_DATA_LOWER, 14, 0, 0x0000 },
+	{ CAT_LEN_DATA_UPPER, 14, 14, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_rck_ctrl_fields[] = {
+	{ CAT_RCK_CTRL_ADR, 8, 0, 0x0000 },
+	{ CAT_RCK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cat_rck_data_fields[] = {
+	{ CAT_RCK_DATA_CM0U, 1, 1, 0x0000 },
+	{ CAT_RCK_DATA_CM1U, 1, 5, 0x0000 },
+	{ CAT_RCK_DATA_CM2U, 1, 9, 0x0000 },
+	{ CAT_RCK_DATA_CM3U, 1, 13, 0x0000 },
+	{ CAT_RCK_DATA_CM4U, 1, 17, 0x0000 },
+	{ CAT_RCK_DATA_CM5U, 1, 21, 0x0000 },
+	{ CAT_RCK_DATA_CM6U, 1, 25, 0x0000 },
+	{ CAT_RCK_DATA_CM7U, 1, 29, 0x0000 },
+	{ CAT_RCK_DATA_CML0, 1, 0, 0x0000 },
+	{ CAT_RCK_DATA_CML1, 1, 4, 0x0000 },
+	{ CAT_RCK_DATA_CML2, 1, 8, 0x0000 },
+	{ CAT_RCK_DATA_CML3, 1, 12, 0x0000 },
+	{ CAT_RCK_DATA_CML4, 1, 16, 0x0000 },
+	{ CAT_RCK_DATA_CML5, 1, 20, 0x0000 },
+	{ CAT_RCK_DATA_CML6, 1, 24, 0x0000 },
+	{ CAT_RCK_DATA_CML7, 1, 28, 0x0000 },
+	{ CAT_RCK_DATA_SEL0, 1, 2, 0x0000 },
+	{ CAT_RCK_DATA_SEL1, 1, 6, 0x0000 },
+	{ CAT_RCK_DATA_SEL2, 1, 10, 0x0000 },
+	{ CAT_RCK_DATA_SEL3, 1, 14, 0x0000 },
+	{ CAT_RCK_DATA_SEL4, 1, 18, 0x0000 },
+	{ CAT_RCK_DATA_SEL5, 1, 22, 0x0000 },
+	{ CAT_RCK_DATA_SEL6, 1, 26, 0x0000 },
+	{ CAT_RCK_DATA_SEL7, 1, 30, 0x0000 },
+	{ CAT_RCK_DATA_SEU0, 1, 3, 0x0000 },
+	{ CAT_RCK_DATA_SEU1, 1, 7, 0x0000 },
+	{ CAT_RCK_DATA_SEU2, 1, 11, 0x0000 },
+	{ CAT_RCK_DATA_SEU3, 1, 15, 0x0000 },
+	{ CAT_RCK_DATA_SEU4, 1, 19, 0x0000 },
+	{ CAT_RCK_DATA_SEU5, 1, 23, 0x0000 },
+	{ CAT_RCK_DATA_SEU6, 1, 27, 0x0000 },
+	{ CAT_RCK_DATA_SEU7, 1, 31, 0x0000 },
+};
+
+static nt_fpga_register_init_t cat_registers[] = {
+	{ CAT_CCT_CTRL, 30, 32, REGISTER_TYPE_WO, 0, 2, cat_cct_ctrl_fields },
+	{ CAT_CCT_DATA, 31, 36, REGISTER_TYPE_WO, 0, 2, cat_cct_data_fields },
+	{ CAT_CFN_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2, cat_cfn_ctrl_fields },
+	{ CAT_CFN_DATA, 11, 179, REGISTER_TYPE_WO, 0, 44, cat_cfn_data_fields },
+	{ CAT_COT_CTRL, 28, 32, REGISTER_TYPE_WO, 0, 2, cat_cot_ctrl_fields },
+	{ CAT_COT_DATA, 29, 36, REGISTER_TYPE_WO, 0, 2, cat_cot_data_fields },
+	{ CAT_CTE_CTRL, 24, 32, REGISTER_TYPE_WO, 0, 2, cat_cte_ctrl_fields },
+	{ CAT_CTE_DATA, 25, 11, REGISTER_TYPE_WO, 0, 11, cat_cte_data_fields },
+	{ CAT_CTS_CTRL, 26, 32, REGISTER_TYPE_WO, 0, 2, cat_cts_ctrl_fields },
+	{ CAT_CTS_DATA, 27, 12, REGISTER_TYPE_WO, 0, 2, cat_cts_data_fields },
+	{ CAT_DCT_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2, cat_dct_ctrl_fields },
+	{ CAT_DCT_DATA, 7, 16, REGISTER_TYPE_WO, 0, 1, cat_dct_data_fields },
+	{ CAT_DCT_SEL, 4, 2, REGISTER_TYPE_WO, 0, 1, cat_dct_sel_fields },
+	{ CAT_EXO_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, cat_exo_ctrl_fields },
+	{ CAT_EXO_DATA, 1, 27, REGISTER_TYPE_WO, 0, 2, cat_exo_data_fields },
+	{ CAT_FTE0_CTRL, 16, 32, REGISTER_TYPE_WO, 0, 2, cat_fte0_ctrl_fields },
+	{ CAT_FTE0_DATA, 17, 8, REGISTER_TYPE_WO, 0, 1, cat_fte0_data_fields },
+	{ CAT_FTE1_CTRL, 22, 32, REGISTER_TYPE_WO, 0, 2, cat_fte1_ctrl_fields },
+	{ CAT_FTE1_DATA, 23, 8, REGISTER_TYPE_WO, 0, 1, cat_fte1_data_fields },
+	{ CAT_JOIN, 5, 9, REGISTER_TYPE_WO, 0, 2, cat_join_fields },
+	{ CAT_KCC_CTRL, 32, 32, REGISTER_TYPE_WO, 0, 2, cat_kcc_ctrl_fields },
+	{ CAT_KCC_DATA, 33, 84, REGISTER_TYPE_WO, 0, 3, cat_kcc_data_fields },
+	{ CAT_KCE0_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2, cat_kce0_ctrl_fields },
+	{ CAT_KCE0_DATA, 13, 8, REGISTER_TYPE_WO, 0, 1, cat_kce0_data_fields },
+	{ CAT_KCE1_CTRL, 18, 32, REGISTER_TYPE_WO, 0, 2, cat_kce1_ctrl_fields },
+	{ CAT_KCE1_DATA, 19, 8, REGISTER_TYPE_WO, 0, 1, cat_kce1_data_fields },
+	{ CAT_KCS0_CTRL, 14, 32, REGISTER_TYPE_WO, 0, 2, cat_kcs0_ctrl_fields },
+	{ CAT_KCS0_DATA, 15, 6, REGISTER_TYPE_WO, 0, 1, cat_kcs0_data_fields },
+	{ CAT_KCS1_CTRL, 20, 32, REGISTER_TYPE_WO, 0, 2, cat_kcs1_ctrl_fields },
+	{ CAT_KCS1_DATA, 21, 6, REGISTER_TYPE_WO, 0, 1, cat_kcs1_data_fields },
+	{ CAT_LEN_CTRL, 8, 32, REGISTER_TYPE_WO, 0, 2, cat_len_ctrl_fields },
+	{ CAT_LEN_DATA, 9, 39, REGISTER_TYPE_WO, 0, 5, cat_len_data_fields },
+	{ CAT_RCK_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, cat_rck_ctrl_fields },
+	{ CAT_RCK_DATA, 3, 32, REGISTER_TYPE_WO, 0, 32, cat_rck_data_fields },
+};
+
+static nt_fpga_field_init_t cpy_writer0_ctrl_fields[] = {
+	{ CPY_WRITER0_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer0_data_fields[] = {
+	{ CPY_WRITER0_DATA_DYN, 5, 17, 0x0000 },
+	{ CPY_WRITER0_DATA_LEN, 4, 22, 0x0000 },
+	{ CPY_WRITER0_DATA_MASK_POINTER, 4, 26, 0x0000 },
+	{ CPY_WRITER0_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER0_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer0_mask_ctrl_fields[] = {
+	{ CPY_WRITER0_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER0_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer0_mask_data_fields[] = {
+	{ CPY_WRITER0_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer1_ctrl_fields[] = {
+	{ CPY_WRITER1_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer1_data_fields[] = {
+	{ CPY_WRITER1_DATA_DYN, 5, 17, 0x0000 },
+	{ CPY_WRITER1_DATA_LEN, 4, 22, 0x0000 },
+	{ CPY_WRITER1_DATA_MASK_POINTER, 4, 26, 0x0000 },
+	{ CPY_WRITER1_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER1_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer1_mask_ctrl_fields[] = {
+	{ CPY_WRITER1_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER1_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer1_mask_data_fields[] = {
+	{ CPY_WRITER1_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer2_ctrl_fields[] = {
+	{ CPY_WRITER2_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER2_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer2_data_fields[] = {
+	{ CPY_WRITER2_DATA_DYN, 5, 17, 0x0000 },
+	{ CPY_WRITER2_DATA_LEN, 4, 22, 0x0000 },
+	{ CPY_WRITER2_DATA_MASK_POINTER, 4, 26, 0x0000 },
+	{ CPY_WRITER2_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER2_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer2_mask_ctrl_fields[] = {
+	{ CPY_WRITER2_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER2_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer2_mask_data_fields[] = {
+	{ CPY_WRITER2_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer3_ctrl_fields[] = {
+	{ CPY_WRITER3_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER3_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer3_data_fields[] = {
+	{ CPY_WRITER3_DATA_DYN, 5, 17, 0x0000 },
+	{ CPY_WRITER3_DATA_LEN, 4, 22, 0x0000 },
+	{ CPY_WRITER3_DATA_MASK_POINTER, 4, 26, 0x0000 },
+	{ CPY_WRITER3_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER3_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer3_mask_ctrl_fields[] = {
+	{ CPY_WRITER3_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER3_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer3_mask_data_fields[] = {
+	{ CPY_WRITER3_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer4_ctrl_fields[] = {
+	{ CPY_WRITER4_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER4_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer4_data_fields[] = {
+	{ CPY_WRITER4_DATA_DYN, 5, 17, 0x0000 },
+	{ CPY_WRITER4_DATA_LEN, 4, 22, 0x0000 },
+	{ CPY_WRITER4_DATA_MASK_POINTER, 4, 26, 0x0000 },
+	{ CPY_WRITER4_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER4_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer4_mask_ctrl_fields[] = {
+	{ CPY_WRITER4_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER4_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t cpy_writer4_mask_data_fields[] = {
+	{ CPY_WRITER4_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t cpy_registers[] = {
+	{	CPY_WRITER0_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer0_ctrl_fields
+	},
+	{	CPY_WRITER0_DATA, 1, 30, REGISTER_TYPE_WO, 0, 5,
+		cpy_writer0_data_fields
+	},
+	{	CPY_WRITER0_MASK_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer0_mask_ctrl_fields
+	},
+	{	CPY_WRITER0_MASK_DATA, 3, 16, REGISTER_TYPE_WO, 0, 1,
+		cpy_writer0_mask_data_fields
+	},
+	{	CPY_WRITER1_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer1_ctrl_fields
+	},
+	{	CPY_WRITER1_DATA, 5, 30, REGISTER_TYPE_WO, 0, 5,
+		cpy_writer1_data_fields
+	},
+	{	CPY_WRITER1_MASK_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer1_mask_ctrl_fields
+	},
+	{	CPY_WRITER1_MASK_DATA, 7, 16, REGISTER_TYPE_WO, 0, 1,
+		cpy_writer1_mask_data_fields
+	},
+	{	CPY_WRITER2_CTRL, 8, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer2_ctrl_fields
+	},
+	{	CPY_WRITER2_DATA, 9, 30, REGISTER_TYPE_WO, 0, 5,
+		cpy_writer2_data_fields
+	},
+	{	CPY_WRITER2_MASK_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer2_mask_ctrl_fields
+	},
+	{	CPY_WRITER2_MASK_DATA, 11, 16, REGISTER_TYPE_WO, 0, 1,
+		cpy_writer2_mask_data_fields
+	},
+	{	CPY_WRITER3_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer3_ctrl_fields
+	},
+	{	CPY_WRITER3_DATA, 13, 30, REGISTER_TYPE_WO, 0, 5,
+		cpy_writer3_data_fields
+	},
+	{	CPY_WRITER3_MASK_CTRL, 14, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer3_mask_ctrl_fields
+	},
+	{	CPY_WRITER3_MASK_DATA, 15, 16, REGISTER_TYPE_WO, 0, 1,
+		cpy_writer3_mask_data_fields
+	},
+	{	CPY_WRITER4_CTRL, 16, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer4_ctrl_fields
+	},
+	{	CPY_WRITER4_DATA, 17, 30, REGISTER_TYPE_WO, 0, 5,
+		cpy_writer4_data_fields
+	},
+	{	CPY_WRITER4_MASK_CTRL, 18, 32, REGISTER_TYPE_WO, 0, 2,
+		cpy_writer4_mask_ctrl_fields
+	},
+	{	CPY_WRITER4_MASK_DATA, 19, 16, REGISTER_TYPE_WO, 0, 1,
+		cpy_writer4_mask_data_fields
+	},
+};
+
+static nt_fpga_field_init_t csu_rcp_ctrl_fields[] = {
+	{ CSU_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ CSU_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t csu_rcp_data_fields[] = {
+	{ CSU_RCP_DATA_IL3_CMD, 2, 5, 0x0000 },
+	{ CSU_RCP_DATA_IL4_CMD, 3, 7, 0x0000 },
+	{ CSU_RCP_DATA_OL3_CMD, 2, 0, 0x0000 },
+	{ CSU_RCP_DATA_OL4_CMD, 3, 2, 0x0000 },
+};
+
+static nt_fpga_register_init_t csu_registers[] = {
+	{ CSU_RCP_CTRL, 1, 32, REGISTER_TYPE_WO, 0, 2, csu_rcp_ctrl_fields },
+	{ CSU_RCP_DATA, 2, 10, REGISTER_TYPE_WO, 0, 4, csu_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t dbs_rx_am_ctrl_fields[] = {
+	{ DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_am_data_fields[] = {
+	{ DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 },
+	{ DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_RX_AM_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_RX_AM_DATA_INT, 1, 74, 0x0000 },
+	{ DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_control_fields[] = {
+	{ DBS_RX_CONTROL_AME, 1, 7, 0 },  { DBS_RX_CONTROL_AMS, 4, 8, 8 },
+	{ DBS_RX_CONTROL_LQ, 7, 0, 0 },	  { DBS_RX_CONTROL_QE, 1, 17, 0 },
+	{ DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_CONTROL_UWS, 4, 13, 5 },
+};
+
+static nt_fpga_field_init_t dbs_rx_dr_ctrl_fields[] = {
+	{ DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_dr_data_fields[] = {
+	{ DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_RX_DR_DATA_HDR, 1, 88, 0x0000 },
+	{ DBS_RX_DR_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_RX_DR_DATA_PCKED, 1, 87, 0x0000 },
+	{ DBS_RX_DR_DATA_QS, 15, 72, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_idle_fields[] = {
+	{ DBS_RX_IDLE_BUSY, 1, 8, 0 },
+	{ DBS_RX_IDLE_IDLE, 1, 0, 0x0000 },
+	{ DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_init_fields[] = {
+	{ DBS_RX_INIT_BUSY, 1, 8, 0 },
+	{ DBS_RX_INIT_INIT, 1, 0, 0x0000 },
+	{ DBS_RX_INIT_QUEUE, 7, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_init_val_fields[] = {
+	{ DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 },
+	{ DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_ptr_fields[] = {
+	{ DBS_RX_PTR_PTR, 16, 0, 0x0000 },
+	{ DBS_RX_PTR_QUEUE, 7, 16, 0x0000 },
+	{ DBS_RX_PTR_VALID, 1, 23, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_uw_ctrl_fields[] = {
+	{ DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_rx_uw_data_fields[] = {
+	{ DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_RX_UW_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_RX_UW_DATA_INT, 1, 88, 0x0000 },
+	{ DBS_RX_UW_DATA_ISTK, 1, 92, 0x0000 },
+	{ DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 },
+	{ DBS_RX_UW_DATA_QS, 15, 72, 0x0000 },
+	{ DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_am_ctrl_fields[] = {
+	{ DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_am_data_fields[] = {
+	{ DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 },
+	{ DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_TX_AM_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_TX_AM_DATA_INT, 1, 74, 0x0000 },
+	{ DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_control_fields[] = {
+	{ DBS_TX_CONTROL_AME, 1, 7, 0 },  { DBS_TX_CONTROL_AMS, 4, 8, 5 },
+	{ DBS_TX_CONTROL_LQ, 7, 0, 0 },	  { DBS_TX_CONTROL_QE, 1, 17, 0 },
+	{ DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_CONTROL_UWS, 4, 13, 8 },
+};
+
+static nt_fpga_field_init_t dbs_tx_dr_ctrl_fields[] = {
+	{ DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_dr_data_fields[] = {
+	{ DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_TX_DR_DATA_HDR, 1, 88, 0x0000 },
+	{ DBS_TX_DR_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_TX_DR_DATA_PCKED, 1, 87, 0x0000 },
+	{ DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 },
+	{ DBS_TX_DR_DATA_QS, 15, 72, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_idle_fields[] = {
+	{ DBS_TX_IDLE_BUSY, 1, 8, 0 },
+	{ DBS_TX_IDLE_IDLE, 1, 0, 0x0000 },
+	{ DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_init_fields[] = {
+	{ DBS_TX_INIT_BUSY, 1, 8, 0 },
+	{ DBS_TX_INIT_INIT, 1, 0, 0x0000 },
+	{ DBS_TX_INIT_QUEUE, 7, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_init_val_fields[] = {
+	{ DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 },
+	{ DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_ptr_fields[] = {
+	{ DBS_TX_PTR_PTR, 16, 0, 0x0000 },
+	{ DBS_TX_PTR_QUEUE, 7, 16, 0x0000 },
+	{ DBS_TX_PTR_VALID, 1, 23, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_qos_ctrl_fields[] = {
+	{ DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 },
+	{ DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_qos_data_fields[] = {
+	{ DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 },
+	{ DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 },
+	{ DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_qos_rate_fields[] = {
+	{ DBS_TX_QOS_RATE_DIV, 19, 16, 2 },
+	{ DBS_TX_QOS_RATE_MUL, 16, 0, 1 },
+};
+
+static nt_fpga_field_init_t dbs_tx_qp_ctrl_fields[] = {
+	{ DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_qp_data_fields[] = {
+	{ DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_uw_ctrl_fields[] = {
+	{ DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t dbs_tx_uw_data_fields[] = {
+	{ DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_TX_UW_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_TX_UW_DATA_INO, 1, 93, 0x0000 },
+	{ DBS_TX_UW_DATA_INT, 1, 88, 0x0000 },
+	{ DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 },
+	{ DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 },
+	{ DBS_TX_UW_DATA_QS, 15, 72, 0x0000 },
+	{ DBS_TX_UW_DATA_VEC, 3, 89, 0x0000 },
+};
+
+static nt_fpga_register_init_t dbs_registers[] = {
+	{	DBS_RX_AM_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_rx_am_ctrl_fields
+	},
+	{	DBS_RX_AM_DATA, 11, 75, REGISTER_TYPE_WO, 0, 5,
+		dbs_rx_am_data_fields
+	},
+	{	DBS_RX_CONTROL, 0, 18, REGISTER_TYPE_RW, 43008, 6,
+		dbs_rx_control_fields
+	},
+	{	DBS_RX_DR_CTRL, 18, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_rx_dr_ctrl_fields
+	},
+	{	DBS_RX_DR_DATA, 19, 89, REGISTER_TYPE_WO, 0, 5,
+		dbs_rx_dr_data_fields
+	},
+	{ DBS_RX_IDLE, 8, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_rx_idle_fields },
+	{ DBS_RX_INIT, 2, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_rx_init_fields },
+	{	DBS_RX_INIT_VAL, 3, 31, REGISTER_TYPE_WO, 0, 2,
+		dbs_rx_init_val_fields
+	},
+	{ DBS_RX_PTR, 4, 24, REGISTER_TYPE_MIXED, 0, 3, dbs_rx_ptr_fields },
+	{	DBS_RX_UW_CTRL, 14, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_rx_uw_ctrl_fields
+	},
+	{	DBS_RX_UW_DATA, 15, 93, REGISTER_TYPE_WO, 0, 7,
+		dbs_rx_uw_data_fields
+	},
+	{	DBS_TX_AM_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_tx_am_ctrl_fields
+	},
+	{	DBS_TX_AM_DATA, 13, 75, REGISTER_TYPE_WO, 0, 5,
+		dbs_tx_am_data_fields
+	},
+	{	DBS_TX_CONTROL, 1, 18, REGISTER_TYPE_RW, 66816, 6,
+		dbs_tx_control_fields
+	},
+	{	DBS_TX_DR_CTRL, 20, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_tx_dr_ctrl_fields
+	},
+	{	DBS_TX_DR_DATA, 21, 90, REGISTER_TYPE_WO, 0, 6,
+		dbs_tx_dr_data_fields
+	},
+	{ DBS_TX_IDLE, 9, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_tx_idle_fields },
+	{ DBS_TX_INIT, 5, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_tx_init_fields },
+	{	DBS_TX_INIT_VAL, 6, 31, REGISTER_TYPE_WO, 0, 2,
+		dbs_tx_init_val_fields
+	},
+	{ DBS_TX_PTR, 7, 24, REGISTER_TYPE_MIXED, 0, 3, dbs_tx_ptr_fields },
+	{	DBS_TX_QOS_CTRL, 24, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_tx_qos_ctrl_fields
+	},
+	{	DBS_TX_QOS_DATA, 25, 44, REGISTER_TYPE_WO, 0, 3,
+		dbs_tx_qos_data_fields
+	},
+	{	DBS_TX_QOS_RATE, 26, 35, REGISTER_TYPE_RW, 131073, 2,
+		dbs_tx_qos_rate_fields
+	},
+	{	DBS_TX_QP_CTRL, 22, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_tx_qp_ctrl_fields
+	},
+	{	DBS_TX_QP_DATA, 23, 1, REGISTER_TYPE_WO, 0, 1,
+		dbs_tx_qp_data_fields
+	},
+	{	DBS_TX_UW_CTRL, 16, 32, REGISTER_TYPE_WO, 0, 2,
+		dbs_tx_uw_ctrl_fields
+	},
+	{	DBS_TX_UW_DATA, 17, 94, REGISTER_TYPE_WO, 0, 8,
+		dbs_tx_uw_data_fields
+	},
+};
+
+static nt_fpga_field_init_t flm_buf_ctrl_fields[] = {
+	{ FLM_BUF_CTRL_INF_AVAIL, 16, 16, 0x0000 },
+	{ FLM_BUF_CTRL_LRN_FREE, 16, 0, 0x0000 },
+	{ FLM_BUF_CTRL_STA_AVAIL, 16, 32, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_control_fields[] = {
+	{ FLM_CONTROL_CRCRD, 1, 12, 0x0000 },
+	{ FLM_CONTROL_CRCWR, 1, 11, 0x0000 },
+	{ FLM_CONTROL_EAB, 5, 18, 0 },
+	{ FLM_CONTROL_ENABLE, 1, 0, 0 },
+	{ FLM_CONTROL_INIT, 1, 1, 0x0000 },
+	{ FLM_CONTROL_LDS, 1, 2, 0x0000 },
+	{ FLM_CONTROL_LFS, 1, 3, 0x0000 },
+	{ FLM_CONTROL_LIS, 1, 4, 0x0000 },
+	{ FLM_CONTROL_PDS, 1, 9, 0x0000 },
+	{ FLM_CONTROL_PIS, 1, 10, 0x0000 },
+	{ FLM_CONTROL_RBL, 4, 13, 0 },
+	{ FLM_CONTROL_RDS, 1, 7, 0x0000 },
+	{ FLM_CONTROL_RIS, 1, 8, 0x0000 },
+	{ FLM_CONTROL_SPLIT_SDRAM_USAGE, 5, 23, 16 },
+	{ FLM_CONTROL_UDS, 1, 5, 0x0000 },
+	{ FLM_CONTROL_UIS, 1, 6, 0x0000 },
+	{ FLM_CONTROL_WPD, 1, 17, 0 },
+};
+
+static nt_fpga_field_init_t flm_inf_data_fields[] = {
+	{ FLM_INF_DATA_BYTES, 64, 0, 0x0000 },
+	{ FLM_INF_DATA_CAUSE, 3, 264, 0x0000 },
+	{ FLM_INF_DATA_EOR, 1, 287, 0x0000 },
+	{ FLM_INF_DATA_ID, 72, 192, 0x0000 },
+	{ FLM_INF_DATA_PACKETS, 64, 64, 0x0000 },
+	{ FLM_INF_DATA_TS, 64, 128, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_load_aps_fields[] = {
+	{ FLM_LOAD_APS_APS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_load_bin_fields[] = {
+	{ FLM_LOAD_BIN_BIN, 30, 0, 8388607 },
+};
+
+static nt_fpga_field_init_t flm_load_lps_fields[] = {
+	{ FLM_LOAD_LPS_LPS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_load_pps_fields[] = {
+	{ FLM_LOAD_PPS_PPS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_lrn_data_fields[] = {
+	{ FLM_LRN_DATA_ADJ, 32, 480, 0x0000 },
+	{ FLM_LRN_DATA_COLOR, 32, 448, 0x0000 },
+	{ FLM_LRN_DATA_DSCP, 6, 734, 0x0000 },
+	{ FLM_LRN_DATA_ENT, 1, 729, 0x0000 },
+	{ FLM_LRN_DATA_EOR, 1, 767, 0x0000 },
+	{ FLM_LRN_DATA_FILL, 12, 584, 0x0000 },
+	{ FLM_LRN_DATA_FT, 4, 596, 0x0000 },
+	{ FLM_LRN_DATA_FT_MBR, 4, 600, 0x0000 },
+	{ FLM_LRN_DATA_FT_MISS, 4, 604, 0x0000 },
+	{ FLM_LRN_DATA_ID, 72, 512, 0x0000 },
+	{ FLM_LRN_DATA_KID, 8, 328, 0x0000 },
+	{ FLM_LRN_DATA_MBR_ID1, 28, 608, 0x0000 },
+	{ FLM_LRN_DATA_MBR_ID2, 28, 636, 0x0000 },
+	{ FLM_LRN_DATA_MBR_ID3, 28, 664, 0x0000 },
+	{ FLM_LRN_DATA_MBR_ID4, 28, 692, 0x0000 },
+	{ FLM_LRN_DATA_NAT_EN, 1, 747, 0x0000 },
+	{ FLM_LRN_DATA_NAT_IP, 32, 336, 0x0000 },
+	{ FLM_LRN_DATA_NAT_PORT, 16, 400, 0x0000 },
+	{ FLM_LRN_DATA_OP, 4, 730, 0x0000 },
+	{ FLM_LRN_DATA_PRIO, 2, 727, 0x0000 },
+	{ FLM_LRN_DATA_PROT, 8, 320, 0x0000 },
+	{ FLM_LRN_DATA_QFI, 6, 740, 0x0000 },
+	{ FLM_LRN_DATA_QW0, 128, 192, 0x0000 },
+	{ FLM_LRN_DATA_QW4, 128, 64, 0x0000 },
+	{ FLM_LRN_DATA_RATE, 16, 416, 0x0000 },
+	{ FLM_LRN_DATA_RQI, 1, 746, 0x0000 },
+	{ FLM_LRN_DATA_SIZE, 16, 432, 0x0000 },
+	{ FLM_LRN_DATA_STAT_PROF, 4, 723, 0x0000 },
+	{ FLM_LRN_DATA_SW8, 32, 32, 0x0000 },
+	{ FLM_LRN_DATA_SW9, 32, 0, 0x0000 },
+	{ FLM_LRN_DATA_TEID, 32, 368, 0x0000 },
+	{ FLM_LRN_DATA_VOL_IDX, 3, 720, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_prio_fields[] = {
+	{ FLM_PRIO_FT0, 4, 4, 1 },     { FLM_PRIO_FT1, 4, 12, 1 },
+	{ FLM_PRIO_FT2, 4, 20, 1 },    { FLM_PRIO_FT3, 4, 28, 1 },
+	{ FLM_PRIO_LIMIT0, 4, 0, 0 },  { FLM_PRIO_LIMIT1, 4, 8, 0 },
+	{ FLM_PRIO_LIMIT2, 4, 16, 0 }, { FLM_PRIO_LIMIT3, 4, 24, 0 },
+};
+
+static nt_fpga_field_init_t flm_pst_ctrl_fields[] = {
+	{ FLM_PST_CTRL_ADR, 4, 0, 0x0000 },
+	{ FLM_PST_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_pst_data_fields[] = {
+	{ FLM_PST_DATA_BP, 5, 0, 0x0000 },
+	{ FLM_PST_DATA_PP, 5, 5, 0x0000 },
+	{ FLM_PST_DATA_TP, 5, 10, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_rcp_ctrl_fields[] = {
+	{ FLM_RCP_CTRL_ADR, 5, 0, 0x0000 },
+	{ FLM_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_rcp_data_fields[] = {
+	{ FLM_RCP_DATA_AUTO_IPV4_MASK, 1, 402, 0x0000 },
+	{ FLM_RCP_DATA_BYT_DYN, 5, 387, 0x0000 },
+	{ FLM_RCP_DATA_BYT_OFS, 8, 392, 0x0000 },
+	{ FLM_RCP_DATA_IPN, 1, 386, 0x0000 },
+	{ FLM_RCP_DATA_KID, 8, 377, 0x0000 },
+	{ FLM_RCP_DATA_LOOKUP, 1, 0, 0x0000 },
+	{ FLM_RCP_DATA_MASK, 320, 57, 0x0000 },
+	{ FLM_RCP_DATA_OPN, 1, 385, 0x0000 },
+	{ FLM_RCP_DATA_QW0_DYN, 5, 1, 0x0000 },
+	{ FLM_RCP_DATA_QW0_OFS, 8, 6, 0x0000 },
+	{ FLM_RCP_DATA_QW0_SEL, 2, 14, 0x0000 },
+	{ FLM_RCP_DATA_QW4_DYN, 5, 16, 0x0000 },
+	{ FLM_RCP_DATA_QW4_OFS, 8, 21, 0x0000 },
+	{ FLM_RCP_DATA_SW8_DYN, 5, 29, 0x0000 },
+	{ FLM_RCP_DATA_SW8_OFS, 8, 34, 0x0000 },
+	{ FLM_RCP_DATA_SW8_SEL, 2, 42, 0x0000 },
+	{ FLM_RCP_DATA_SW9_DYN, 5, 44, 0x0000 },
+	{ FLM_RCP_DATA_SW9_OFS, 8, 49, 0x0000 },
+	{ FLM_RCP_DATA_TXPLM, 2, 400, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_scrub_fields[] = {
+	{ FLM_SCRUB_I, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t flm_status_fields[] = {
+	{ FLM_STATUS_CALIBDONE, 1, 0, 0x0000 },
+	{ FLM_STATUS_CRCERR, 1, 5, 0x0000 },
+	{ FLM_STATUS_CRITICAL, 1, 3, 0x0000 },
+	{ FLM_STATUS_EFT_BP, 1, 6, 0x0000 },
+	{ FLM_STATUS_IDLE, 1, 2, 0x0000 },
+	{ FLM_STATUS_INITDONE, 1, 1, 0x0000 },
+	{ FLM_STATUS_PANIC, 1, 4, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_aul_done_fields[] = {
+	{ FLM_STAT_AUL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_aul_fail_fields[] = {
+	{ FLM_STAT_AUL_FAIL_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_aul_ignore_fields[] = {
+	{ FLM_STAT_AUL_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_csh_hit_fields[] = {
+	{ FLM_STAT_CSH_HIT_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_csh_miss_fields[] = {
+	{ FLM_STAT_CSH_MISS_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_csh_unh_fields[] = {
+	{ FLM_STAT_CSH_UNH_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_cuc_move_fields[] = {
+	{ FLM_STAT_CUC_MOVE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_cuc_start_fields[] = {
+	{ FLM_STAT_CUC_START_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_flows_fields[] = {
+	{ FLM_STAT_FLOWS_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_inf_done_fields[] = {
+	{ FLM_STAT_INF_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_inf_skip_fields[] = {
+	{ FLM_STAT_INF_SKIP_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_lrn_done_fields[] = {
+	{ FLM_STAT_LRN_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_lrn_fail_fields[] = {
+	{ FLM_STAT_LRN_FAIL_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_lrn_ignore_fields[] = {
+	{ FLM_STAT_LRN_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_pck_dis_fields[] = {
+	{ FLM_STAT_PCK_DIS_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_pck_hit_fields[] = {
+	{ FLM_STAT_PCK_HIT_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_pck_miss_fields[] = {
+	{ FLM_STAT_PCK_MISS_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_pck_unh_fields[] = {
+	{ FLM_STAT_PCK_UNH_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_prb_done_fields[] = {
+	{ FLM_STAT_PRB_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_prb_ignore_fields[] = {
+	{ FLM_STAT_PRB_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_rel_done_fields[] = {
+	{ FLM_STAT_REL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_rel_ignore_fields[] = {
+	{ FLM_STAT_REL_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_sta_done_fields[] = {
+	{ FLM_STAT_STA_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_tul_done_fields[] = {
+	{ FLM_STAT_TUL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_unl_done_fields[] = {
+	{ FLM_STAT_UNL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_stat_unl_ignore_fields[] = {
+	{ FLM_STAT_UNL_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_sta_data_fields[] = {
+	{ FLM_STA_DATA_EOR, 1, 95, 0x0000 },
+	{ FLM_STA_DATA_ID, 72, 0, 0x0000 },
+	{ FLM_STA_DATA_LDS, 1, 72, 0x0000 },
+	{ FLM_STA_DATA_LFS, 1, 73, 0x0000 },
+	{ FLM_STA_DATA_LIS, 1, 74, 0x0000 },
+	{ FLM_STA_DATA_PDS, 1, 79, 0x0000 },
+	{ FLM_STA_DATA_PIS, 1, 80, 0x0000 },
+	{ FLM_STA_DATA_RDS, 1, 77, 0x0000 },
+	{ FLM_STA_DATA_RIS, 1, 78, 0x0000 },
+	{ FLM_STA_DATA_UDS, 1, 75, 0x0000 },
+	{ FLM_STA_DATA_UIS, 1, 76, 0x0000 },
+};
+
+static nt_fpga_field_init_t flm_timeout_fields[] = {
+	{ FLM_TIMEOUT_T, 32, 0, 0 },
+};
+
+static nt_fpga_register_init_t flm_registers[] = {
+	{ FLM_BUF_CTRL, 14, 48, REGISTER_TYPE_RW, 0, 3, flm_buf_ctrl_fields },
+	{	FLM_CONTROL, 0, 28, REGISTER_TYPE_MIXED, 134217728, 17,
+		flm_control_fields
+	},
+	{ FLM_INF_DATA, 16, 288, REGISTER_TYPE_RO, 0, 6, flm_inf_data_fields },
+	{ FLM_LOAD_APS, 7, 32, REGISTER_TYPE_RO, 0, 1, flm_load_aps_fields },
+	{	FLM_LOAD_BIN, 4, 30, REGISTER_TYPE_WO, 8388607, 1,
+		flm_load_bin_fields
+	},
+	{ FLM_LOAD_LPS, 6, 32, REGISTER_TYPE_RO, 0, 1, flm_load_lps_fields },
+	{ FLM_LOAD_PPS, 5, 32, REGISTER_TYPE_RO, 0, 1, flm_load_pps_fields },
+	{ FLM_LRN_DATA, 15, 768, REGISTER_TYPE_WO, 0, 32, flm_lrn_data_fields },
+	{ FLM_PRIO, 8, 32, REGISTER_TYPE_WO, 269488144, 8, flm_prio_fields },
+	{ FLM_PST_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2, flm_pst_ctrl_fields },
+	{ FLM_PST_DATA, 11, 15, REGISTER_TYPE_WO, 0, 3, flm_pst_data_fields },
+	{ FLM_RCP_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2, flm_rcp_ctrl_fields },
+	{ FLM_RCP_DATA, 13, 403, REGISTER_TYPE_WO, 0, 19, flm_rcp_data_fields },
+	{ FLM_SCRUB, 3, 16, REGISTER_TYPE_WO, 0, 1, flm_scrub_fields },
+	{ FLM_STATUS, 1, 12, REGISTER_TYPE_MIXED, 0, 7, flm_status_fields },
+	{	FLM_STAT_AUL_DONE, 41, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_aul_done_fields
+	},
+	{	FLM_STAT_AUL_FAIL, 43, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_aul_fail_fields
+	},
+	{	FLM_STAT_AUL_IGNORE, 42, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_aul_ignore_fields
+	},
+	{	FLM_STAT_CSH_HIT, 52, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_csh_hit_fields
+	},
+	{	FLM_STAT_CSH_MISS, 53, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_csh_miss_fields
+	},
+	{	FLM_STAT_CSH_UNH, 54, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_csh_unh_fields
+	},
+	{	FLM_STAT_CUC_MOVE, 57, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_cuc_move_fields
+	},
+	{	FLM_STAT_CUC_START, 56, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_cuc_start_fields
+	},
+	{	FLM_STAT_FLOWS, 18, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_flows_fields
+	},
+	{	FLM_STAT_INF_DONE, 46, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_inf_done_fields
+	},
+	{	FLM_STAT_INF_SKIP, 47, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_inf_skip_fields
+	},
+	{	FLM_STAT_LRN_DONE, 32, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_lrn_done_fields
+	},
+	{	FLM_STAT_LRN_FAIL, 34, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_lrn_fail_fields
+	},
+	{	FLM_STAT_LRN_IGNORE, 33, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_lrn_ignore_fields
+	},
+	{	FLM_STAT_PCK_DIS, 51, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_pck_dis_fields
+	},
+	{	FLM_STAT_PCK_HIT, 48, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_pck_hit_fields
+	},
+	{	FLM_STAT_PCK_MISS, 49, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_pck_miss_fields
+	},
+	{	FLM_STAT_PCK_UNH, 50, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_pck_unh_fields
+	},
+	{	FLM_STAT_PRB_DONE, 39, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_prb_done_fields
+	},
+	{	FLM_STAT_PRB_IGNORE, 40, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_prb_ignore_fields
+	},
+	{	FLM_STAT_REL_DONE, 37, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_rel_done_fields
+	},
+	{	FLM_STAT_REL_IGNORE, 38, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_rel_ignore_fields
+	},
+	{	FLM_STAT_STA_DONE, 45, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_sta_done_fields
+	},
+	{	FLM_STAT_TUL_DONE, 44, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_tul_done_fields
+	},
+	{	FLM_STAT_UNL_DONE, 35, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_unl_done_fields
+	},
+	{	FLM_STAT_UNL_IGNORE, 36, 32, REGISTER_TYPE_RO, 0, 1,
+		flm_stat_unl_ignore_fields
+	},
+	{ FLM_STA_DATA, 17, 96, REGISTER_TYPE_RO, 0, 11, flm_sta_data_fields },
+	{ FLM_TIMEOUT, 2, 32, REGISTER_TYPE_WO, 0, 1, flm_timeout_fields },
+};
+
+static nt_fpga_field_init_t gfg_burstsize0_fields[] = {
+	{ GFG_BURSTSIZE0_VAL, 24, 0, 0 },
+};
+
+static nt_fpga_field_init_t gfg_burstsize1_fields[] = {
+	{ GFG_BURSTSIZE1_VAL, 24, 0, 0 },
+};
+
+static nt_fpga_field_init_t gfg_ctrl0_fields[] = {
+	{ GFG_CTRL0_ENABLE, 1, 0, 0 },
+	{ GFG_CTRL0_MODE, 3, 1, 0 },
+	{ GFG_CTRL0_PRBS_EN, 1, 4, 0 },
+	{ GFG_CTRL0_SIZE, 14, 16, 64 },
+};
+
+static nt_fpga_field_init_t gfg_ctrl1_fields[] = {
+	{ GFG_CTRL1_ENABLE, 1, 0, 0 },
+	{ GFG_CTRL1_MODE, 3, 1, 0 },
+	{ GFG_CTRL1_PRBS_EN, 1, 4, 0 },
+	{ GFG_CTRL1_SIZE, 14, 16, 64 },
+};
+
+static nt_fpga_field_init_t gfg_run0_fields[] = {
+	{ GFG_RUN0_RUN, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t gfg_run1_fields[] = {
+	{ GFG_RUN1_RUN, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t gfg_sizemask0_fields[] = {
+	{ GFG_SIZEMASK0_VAL, 14, 0, 0 },
+};
+
+static nt_fpga_field_init_t gfg_sizemask1_fields[] = {
+	{ GFG_SIZEMASK1_VAL, 14, 0, 0 },
+};
+
+static nt_fpga_field_init_t gfg_streamid0_fields[] = {
+	{ GFG_STREAMID0_VAL, 8, 0, 0 },
+};
+
+static nt_fpga_field_init_t gfg_streamid1_fields[] = {
+	{ GFG_STREAMID1_VAL, 8, 0, 1 },
+};
+
+static nt_fpga_register_init_t gfg_registers[] = {
+	{	GFG_BURSTSIZE0, 3, 24, REGISTER_TYPE_WO, 0, 1,
+		gfg_burstsize0_fields
+	},
+	{	GFG_BURSTSIZE1, 8, 24, REGISTER_TYPE_WO, 0, 1,
+		gfg_burstsize1_fields
+	},
+	{ GFG_CTRL0, 0, 30, REGISTER_TYPE_WO, 4194304, 4, gfg_ctrl0_fields },
+	{ GFG_CTRL1, 5, 30, REGISTER_TYPE_WO, 4194304, 4, gfg_ctrl1_fields },
+	{ GFG_RUN0, 1, 1, REGISTER_TYPE_WO, 0, 1, gfg_run0_fields },
+	{ GFG_RUN1, 6, 1, REGISTER_TYPE_WO, 0, 1, gfg_run1_fields },
+	{ GFG_SIZEMASK0, 4, 14, REGISTER_TYPE_WO, 0, 1, gfg_sizemask0_fields },
+	{ GFG_SIZEMASK1, 9, 14, REGISTER_TYPE_WO, 0, 1, gfg_sizemask1_fields },
+	{ GFG_STREAMID0, 2, 8, REGISTER_TYPE_WO, 0, 1, gfg_streamid0_fields },
+	{ GFG_STREAMID1, 7, 8, REGISTER_TYPE_WO, 1, 1, gfg_streamid1_fields },
+};
+
+static nt_fpga_field_init_t gmf_ctrl_fields[] = {
+	{ GMF_CTRL_ENABLE, 1, 0, 0 },
+	{ GMF_CTRL_FCS_ALWAYS, 1, 1, 0 },
+	{ GMF_CTRL_IFG_AUTO_ADJUST_ENABLE, 1, 7, 0 },
+	{ GMF_CTRL_IFG_ENABLE, 1, 2, 0 },
+	{ GMF_CTRL_IFG_TX_NOW_ALWAYS, 1, 3, 0 },
+	{ GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE, 1, 5, 0 },
+	{ GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK, 1, 6, 0 },
+	{ GMF_CTRL_IFG_TX_ON_TS_ALWAYS, 1, 4, 0 },
+	{ GMF_CTRL_TS_INJECT_ALWAYS, 1, 8, 0 },
+	{ GMF_CTRL_TS_INJECT_DUAL_STEP, 1, 9, 0 },
+};
+
+static nt_fpga_field_init_t gmf_debug_lane_marker_fields[] = {
+	{ GMF_DEBUG_LANE_MARKER_COMPENSATION, 16, 0, 16384 },
+};
+
+static nt_fpga_field_init_t gmf_ifg_max_adjust_slack_fields[] = {
+	{ GMF_IFG_MAX_ADJUST_SLACK_SLACK, 64, 0, 0 },
+};
+
+static nt_fpga_field_init_t gmf_ifg_set_clock_delta_fields[] = {
+	{ GMF_IFG_SET_CLOCK_DELTA_DELTA, 64, 0, 0 },
+};
+
+static nt_fpga_field_init_t gmf_ifg_set_clock_delta_adjust_fields[] = {
+	{ GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA, 64, 0, 0 },
+};
+
+static nt_fpga_field_init_t gmf_ifg_tx_now_on_ts_fields[] = {
+	{ GMF_IFG_TX_NOW_ON_TS_TS, 64, 0, 0 },
+};
+
+static nt_fpga_field_init_t gmf_speed_fields[] = {
+	{ GMF_SPEED_IFG_SPEED, 64, 0, 0 },
+};
+
+static nt_fpga_field_init_t gmf_stat_data_buffer_fields[] = {
+	{ GMF_STAT_DATA_BUFFER_USED, 15, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t gmf_stat_max_delayed_pkt_fields[] = {
+	{ GMF_STAT_MAX_DELAYED_PKT_NS, 64, 0, 0 },
+};
+
+static nt_fpga_field_init_t gmf_stat_next_pkt_fields[] = {
+	{ GMF_STAT_NEXT_PKT_NS, 64, 0, 0 },
+};
+
+static nt_fpga_field_init_t gmf_stat_sticky_fields[] = {
+	{ GMF_STAT_STICKY_DATA_UNDERFLOWED, 1, 0, 0 },
+	{ GMF_STAT_STICKY_IFG_ADJUSTED, 1, 1, 0 },
+};
+
+static nt_fpga_field_init_t gmf_ts_inject_fields[] = {
+	{ GMF_TS_INJECT_OFFSET, 14, 0, 0 },
+	{ GMF_TS_INJECT_POS, 2, 14, 0 },
+};
+
+static nt_fpga_register_init_t gmf_registers[] = {
+	{ GMF_CTRL, 0, 10, REGISTER_TYPE_WO, 0, 10, gmf_ctrl_fields },
+	{	GMF_DEBUG_LANE_MARKER, 7, 16, REGISTER_TYPE_WO, 16384, 1,
+		gmf_debug_lane_marker_fields
+	},
+	{	GMF_IFG_MAX_ADJUST_SLACK, 4, 64, REGISTER_TYPE_WO, 0, 1,
+		gmf_ifg_max_adjust_slack_fields
+	},
+	{	GMF_IFG_SET_CLOCK_DELTA, 2, 64, REGISTER_TYPE_WO, 0, 1,
+		gmf_ifg_set_clock_delta_fields
+	},
+	{	GMF_IFG_SET_CLOCK_DELTA_ADJUST, 3, 64, REGISTER_TYPE_WO, 0, 1,
+		gmf_ifg_set_clock_delta_adjust_fields
+	},
+	{	GMF_IFG_TX_NOW_ON_TS, 5, 64, REGISTER_TYPE_WO, 0, 1,
+		gmf_ifg_tx_now_on_ts_fields
+	},
+	{ GMF_SPEED, 1, 64, REGISTER_TYPE_WO, 0, 1, gmf_speed_fields },
+	{	GMF_STAT_DATA_BUFFER, 9, 15, REGISTER_TYPE_RO, 0, 1,
+		gmf_stat_data_buffer_fields
+	},
+	{	GMF_STAT_MAX_DELAYED_PKT, 11, 64, REGISTER_TYPE_RC1, 0, 1,
+		gmf_stat_max_delayed_pkt_fields
+	},
+	{	GMF_STAT_NEXT_PKT, 10, 64, REGISTER_TYPE_RO, 0, 1,
+		gmf_stat_next_pkt_fields
+	},
+	{	GMF_STAT_STICKY, 8, 2, REGISTER_TYPE_RC1, 0, 2,
+		gmf_stat_sticky_fields
+	},
+	{ GMF_TS_INJECT, 6, 16, REGISTER_TYPE_WO, 0, 2, gmf_ts_inject_fields },
+};
+
+static nt_fpga_field_init_t gpio_phy_cfg_fields[] = {
+	{ GPIO_PHY_CFG_E_PORT0_RXLOS, 1, 8, 0 },
+	{ GPIO_PHY_CFG_E_PORT1_RXLOS, 1, 9, 0 },
+	{ GPIO_PHY_CFG_PORT0_INT_B, 1, 1, 1 },
+	{ GPIO_PHY_CFG_PORT0_LPMODE, 1, 0, 0 },
+	{ GPIO_PHY_CFG_PORT0_MODPRS_B, 1, 3, 1 },
+	{ GPIO_PHY_CFG_PORT0_RESET_B, 1, 2, 0 },
+	{ GPIO_PHY_CFG_PORT1_INT_B, 1, 5, 1 },
+	{ GPIO_PHY_CFG_PORT1_LPMODE, 1, 4, 0 },
+	{ GPIO_PHY_CFG_PORT1_MODPRS_B, 1, 7, 1 },
+	{ GPIO_PHY_CFG_PORT1_RESET_B, 1, 6, 0 },
+};
+
+static nt_fpga_field_init_t gpio_phy_gpio_fields[] = {
+	{ GPIO_PHY_GPIO_E_PORT0_RXLOS, 1, 8, 0 },
+	{ GPIO_PHY_GPIO_E_PORT1_RXLOS, 1, 9, 0 },
+	{ GPIO_PHY_GPIO_PORT0_INT_B, 1, 1, 0x0000 },
+	{ GPIO_PHY_GPIO_PORT0_LPMODE, 1, 0, 1 },
+	{ GPIO_PHY_GPIO_PORT0_MODPRS_B, 1, 3, 0x0000 },
+	{ GPIO_PHY_GPIO_PORT0_RESET_B, 1, 2, 0 },
+	{ GPIO_PHY_GPIO_PORT1_INT_B, 1, 5, 0x0000 },
+	{ GPIO_PHY_GPIO_PORT1_LPMODE, 1, 4, 1 },
+	{ GPIO_PHY_GPIO_PORT1_MODPRS_B, 1, 7, 0x0000 },
+	{ GPIO_PHY_GPIO_PORT1_RESET_B, 1, 6, 0 },
+};
+
+static nt_fpga_register_init_t gpio_phy_registers[] = {
+	{ GPIO_PHY_CFG, 0, 10, REGISTER_TYPE_RW, 170, 10, gpio_phy_cfg_fields },
+	{	GPIO_PHY_GPIO, 1, 10, REGISTER_TYPE_RW, 17, 10,
+		gpio_phy_gpio_fields
+	},
+};
+
+static nt_fpga_field_init_t hfu_rcp_ctrl_fields[] = {
+	{ HFU_RCP_CTRL_ADR, 6, 0, 0x0000 },
+	{ HFU_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t hfu_rcp_data_fields[] = {
+	{ HFU_RCP_DATA_CSINF, 1, 111, 0x0000 },
+	{ HFU_RCP_DATA_IL3OFS, 8, 139, 0x0000 },
+	{ HFU_RCP_DATA_IL4OFS, 8, 147, 0x0000 },
+	{ HFU_RCP_DATA_L3FRAG, 2, 114, 0x0000 },
+	{ HFU_RCP_DATA_L3PRT, 2, 112, 0x0000 },
+	{ HFU_RCP_DATA_L4PRT, 3, 120, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_ADD_DYN, 5, 15, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_ADD_OFS, 8, 20, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_OL4LEN, 1, 1, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_POS_DYN, 5, 2, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_POS_OFS, 8, 7, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_SUB_DYN, 5, 28, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_WR, 1, 0, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_ADD_DYN, 5, 47, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_ADD_OFS, 8, 52, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_POS_DYN, 5, 34, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_POS_OFS, 8, 39, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_SUB_DYN, 5, 60, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_WR, 1, 33, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_ADD_DYN, 5, 79, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_ADD_OFS, 8, 84, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_POS_DYN, 5, 66, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_POS_OFS, 8, 71, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_SUB_DYN, 5, 92, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_WR, 1, 65, 0x0000 },
+	{ HFU_RCP_DATA_OL3OFS, 8, 123, 0x0000 },
+	{ HFU_RCP_DATA_OL4OFS, 8, 131, 0x0000 },
+	{ HFU_RCP_DATA_TTL_POS_DYN, 5, 98, 0x0000 },
+	{ HFU_RCP_DATA_TTL_POS_OFS, 8, 103, 0x0000 },
+	{ HFU_RCP_DATA_TTL_WR, 1, 97, 0x0000 },
+	{ HFU_RCP_DATA_TUNNEL, 4, 116, 0x0000 },
+};
+
+static nt_fpga_register_init_t hfu_registers[] = {
+	{ HFU_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, hfu_rcp_ctrl_fields },
+	{ HFU_RCP_DATA, 1, 155, REGISTER_TYPE_WO, 0, 31, hfu_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t hif_build_time_fields[] = {
+	{ HIF_BUILD_TIME_TIME, 32, 0, 1693492863 },
+};
+
+static nt_fpga_field_init_t hif_config_fields[] = {
+	{ HIF_CONFIG_EXT_TAG, 1, 6, 0x0000 },
+	{ HIF_CONFIG_MAX_READ, 3, 3, 0x0000 },
+	{ HIF_CONFIG_MAX_TLP, 3, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t hif_control_fields[] = {
+	{ HIF_CONTROL_BLESSED, 8, 4, 0 },
+	{ HIF_CONTROL_WRAW, 4, 0, 1 },
+};
+
+static nt_fpga_field_init_t hif_prod_id_ex_fields[] = {
+	{ HIF_PROD_ID_EX_LAYOUT, 1, 31, 0 },
+	{ HIF_PROD_ID_EX_LAYOUT_VERSION, 8, 0, 1 },
+	{ HIF_PROD_ID_EX_RESERVED, 23, 8, 0 },
+};
+
+static nt_fpga_field_init_t hif_prod_id_lsb_fields[] = {
+	{ HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 },
+	{ HIF_PROD_ID_LSB_REV_ID, 8, 0, 24 },
+	{ HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 },
+};
+
+static nt_fpga_field_init_t hif_prod_id_msb_fields[] = {
+	{ HIF_PROD_ID_MSB_BUILD_NO, 10, 12, 0 },
+	{ HIF_PROD_ID_MSB_TYPE_ID, 12, 0, 200 },
+};
+
+static nt_fpga_field_init_t hif_sample_time_fields[] = {
+	{ HIF_SAMPLE_TIME_SAMPLE_TIME, 1, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t hif_status_fields[] = {
+	{ HIF_STATUS_RD_ERR, 1, 9, 0 },
+	{ HIF_STATUS_TAGS_IN_USE, 8, 0, 0 },
+	{ HIF_STATUS_WR_ERR, 1, 8, 0 },
+};
+
+static nt_fpga_field_init_t hif_stat_ctrl_fields[] = {
+	{ HIF_STAT_CTRL_STAT_ENA, 1, 1, 0 },
+	{ HIF_STAT_CTRL_STAT_REQ, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t hif_stat_refclk_fields[] = {
+	{ HIF_STAT_REFCLK_REFCLK250, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t hif_stat_rx_fields[] = {
+	{ HIF_STAT_RX_COUNTER, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t hif_stat_tx_fields[] = {
+	{ HIF_STAT_TX_COUNTER, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t hif_test0_fields[] = {
+	{ HIF_TEST0_DATA, 32, 0, 287454020 },
+};
+
+static nt_fpga_field_init_t hif_test1_fields[] = {
+	{ HIF_TEST1_DATA, 32, 0, 2864434397 },
+};
+
+static nt_fpga_field_init_t hif_uuid0_fields[] = {
+	{ HIF_UUID0_UUID0, 32, 0, 3215833203 },
+};
+
+static nt_fpga_field_init_t hif_uuid1_fields[] = {
+	{ HIF_UUID1_UUID1, 32, 0, 2947535663 },
+};
+
+static nt_fpga_field_init_t hif_uuid2_fields[] = {
+	{ HIF_UUID2_UUID2, 32, 0, 1243492979 },
+};
+
+static nt_fpga_field_init_t hif_uuid3_fields[] = {
+	{ HIF_UUID3_UUID3, 32, 0, 2500373735 },
+};
+
+static nt_fpga_register_init_t hif_registers[] = {
+	{	HIF_BUILD_TIME, 16, 32, REGISTER_TYPE_RO, 1693492863, 1,
+		hif_build_time_fields
+	},
+	{ HIF_CONFIG, 24, 7, REGISTER_TYPE_RW, 0, 3, hif_config_fields },
+	{ HIF_CONTROL, 40, 12, REGISTER_TYPE_RW, 1, 2, hif_control_fields },
+	{	HIF_PROD_ID_EX, 112, 32, REGISTER_TYPE_RO, 1, 3,
+		hif_prod_id_ex_fields
+	},
+	{	HIF_PROD_ID_LSB, 0, 32, REGISTER_TYPE_RO, 626734872, 3,
+		hif_prod_id_lsb_fields
+	},
+	{	HIF_PROD_ID_MSB, 8, 22, REGISTER_TYPE_RO, 200, 2,
+		hif_prod_id_msb_fields
+	},
+	{	HIF_SAMPLE_TIME, 96, 1, REGISTER_TYPE_WO, 0, 1,
+		hif_sample_time_fields
+	},
+	{ HIF_STATUS, 32, 10, REGISTER_TYPE_MIXED, 0, 3, hif_status_fields },
+	{ HIF_STAT_CTRL, 64, 2, REGISTER_TYPE_WO, 0, 2, hif_stat_ctrl_fields },
+	{	HIF_STAT_REFCLK, 72, 32, REGISTER_TYPE_RO, 0, 1,
+		hif_stat_refclk_fields
+	},
+	{ HIF_STAT_RX, 88, 32, REGISTER_TYPE_RO, 0, 1, hif_stat_rx_fields },
+	{ HIF_STAT_TX, 80, 32, REGISTER_TYPE_RO, 0, 1, hif_stat_tx_fields },
+	{ HIF_TEST0, 48, 32, REGISTER_TYPE_RW, 287454020, 1, hif_test0_fields },
+	{	HIF_TEST1, 56, 32, REGISTER_TYPE_RW, 2864434397, 1,
+		hif_test1_fields
+	},
+	{	HIF_UUID0, 128, 32, REGISTER_TYPE_RO, 3215833203, 1,
+		hif_uuid0_fields
+	},
+	{	HIF_UUID1, 144, 32, REGISTER_TYPE_RO, 2947535663, 1,
+		hif_uuid1_fields
+	},
+	{	HIF_UUID2, 160, 32, REGISTER_TYPE_RO, 1243492979, 1,
+		hif_uuid2_fields
+	},
+	{	HIF_UUID3, 176, 32, REGISTER_TYPE_RO, 2500373735, 1,
+		hif_uuid3_fields
+	},
+};
+
+static nt_fpga_field_init_t hsh_rcp_ctrl_fields[] = {
+	{ HSH_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ HSH_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t hsh_rcp_data_fields[] = {
+	{ HSH_RCP_DATA_AUTO_IPV4_MASK, 1, 742, 0x0000 },
+	{ HSH_RCP_DATA_HSH_TYPE, 5, 416, 0x0000 },
+	{ HSH_RCP_DATA_HSH_VALID, 1, 415, 0x0000 },
+	{ HSH_RCP_DATA_K, 320, 422, 0x0000 },
+	{ HSH_RCP_DATA_LOAD_DIST_TYPE, 2, 0, 0x0000 },
+	{ HSH_RCP_DATA_MAC_PORT_MASK, 2, 2, 0x0000 },
+	{ HSH_RCP_DATA_P_MASK, 1, 61, 0x0000 },
+	{ HSH_RCP_DATA_QW0_OFS, 8, 11, 0x0000 },
+	{ HSH_RCP_DATA_QW0_PE, 5, 6, 0x0000 },
+	{ HSH_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },
+	{ HSH_RCP_DATA_QW4_PE, 5, 19, 0x0000 },
+	{ HSH_RCP_DATA_SEED, 32, 382, 0x0000 },
+	{ HSH_RCP_DATA_SORT, 2, 4, 0x0000 },
+	{ HSH_RCP_DATA_TNL_P, 1, 414, 0x0000 },
+	{ HSH_RCP_DATA_TOEPLITZ, 1, 421, 0x0000 },
+	{ HSH_RCP_DATA_W8_OFS, 8, 37, 0x0000 },
+	{ HSH_RCP_DATA_W8_PE, 5, 32, 0x0000 },
+	{ HSH_RCP_DATA_W8_SORT, 1, 45, 0x0000 },
+	{ HSH_RCP_DATA_W9_OFS, 8, 51, 0x0000 },
+	{ HSH_RCP_DATA_W9_P, 1, 60, 0x0000 },
+	{ HSH_RCP_DATA_W9_PE, 5, 46, 0x0000 },
+	{ HSH_RCP_DATA_W9_SORT, 1, 59, 0x0000 },
+	{ HSH_RCP_DATA_WORD_MASK, 320, 62, 0x0000 },
+};
+
+static nt_fpga_register_init_t hsh_registers[] = {
+	{ HSH_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, hsh_rcp_ctrl_fields },
+	{ HSH_RCP_DATA, 1, 743, REGISTER_TYPE_WO, 0, 23, hsh_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t hst_rcp_ctrl_fields[] = {
+	{ HST_RCP_CTRL_ADR, 5, 0, 0x0000 },
+	{ HST_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t hst_rcp_data_fields[] = {
+	{ HST_RCP_DATA_END_DYN, 5, 16, 0x0000 },
+	{ HST_RCP_DATA_END_OFS, 10, 21, 0x0000 },
+	{ HST_RCP_DATA_MODIF0_CMD, 3, 31, 0x0000 },
+	{ HST_RCP_DATA_MODIF0_DYN, 5, 34, 0x0000 },
+	{ HST_RCP_DATA_MODIF0_OFS, 10, 39, 0x0000 },
+	{ HST_RCP_DATA_MODIF0_VALUE, 16, 49, 0x0000 },
+	{ HST_RCP_DATA_MODIF1_CMD, 3, 65, 0x0000 },
+	{ HST_RCP_DATA_MODIF1_DYN, 5, 68, 0x0000 },
+	{ HST_RCP_DATA_MODIF1_OFS, 10, 73, 0x0000 },
+	{ HST_RCP_DATA_MODIF1_VALUE, 16, 83, 0x0000 },
+	{ HST_RCP_DATA_MODIF2_CMD, 3, 99, 0x0000 },
+	{ HST_RCP_DATA_MODIF2_DYN, 5, 102, 0x0000 },
+	{ HST_RCP_DATA_MODIF2_OFS, 10, 107, 0x0000 },
+	{ HST_RCP_DATA_MODIF2_VALUE, 16, 117, 0x0000 },
+	{ HST_RCP_DATA_START_DYN, 5, 1, 0x0000 },
+	{ HST_RCP_DATA_START_OFS, 10, 6, 0x0000 },
+	{ HST_RCP_DATA_STRIP_MODE, 1, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t hst_registers[] = {
+	{ HST_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, hst_rcp_ctrl_fields },
+	{ HST_RCP_DATA, 1, 133, REGISTER_TYPE_WO, 0, 17, hst_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t ifr_rcp_ctrl_fields[] = {
+	{ IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t ifr_rcp_data_fields[] = {
+	{ IFR_RCP_DATA_EN, 1, 0, 0x0000 },
+	{ IFR_RCP_DATA_MTU, 14, 1, 0x0000 },
+};
+
+static nt_fpga_register_init_t ifr_registers[] = {
+	{ IFR_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, ifr_rcp_ctrl_fields },
+	{ IFR_RCP_DATA, 1, 15, REGISTER_TYPE_WO, 0, 2, ifr_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t iic_adr_fields[] = {
+	{ IIC_ADR_SLV_ADR, 7, 1, 0 },
+};
+
+static nt_fpga_field_init_t iic_cr_fields[] = {
+	{ IIC_CR_EN, 1, 0, 0 },	  { IIC_CR_GC_EN, 1, 6, 0 },
+	{ IIC_CR_MSMS, 1, 2, 0 }, { IIC_CR_RST, 1, 7, 0 },
+	{ IIC_CR_RSTA, 1, 5, 0 }, { IIC_CR_TX, 1, 3, 0 },
+	{ IIC_CR_TXAK, 1, 4, 0 }, { IIC_CR_TXFIFO_RESET, 1, 1, 0 },
+};
+
+static nt_fpga_field_init_t iic_dgie_fields[] = {
+	{ IIC_DGIE_GIE, 1, 31, 0 },
+};
+
+static nt_fpga_field_init_t iic_gpo_fields[] = {
+	{ IIC_GPO_GPO_VAL, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_ier_fields[] = {
+	{ IIC_IER_INT0, 1, 0, 0 }, { IIC_IER_INT1, 1, 1, 0 },
+	{ IIC_IER_INT2, 1, 2, 0 }, { IIC_IER_INT3, 1, 3, 0 },
+	{ IIC_IER_INT4, 1, 4, 0 }, { IIC_IER_INT5, 1, 5, 0 },
+	{ IIC_IER_INT6, 1, 6, 0 }, { IIC_IER_INT7, 1, 7, 0 },
+};
+
+static nt_fpga_field_init_t iic_isr_fields[] = {
+	{ IIC_ISR_INT0, 1, 0, 0 }, { IIC_ISR_INT1, 1, 1, 0 },
+	{ IIC_ISR_INT2, 1, 2, 0 }, { IIC_ISR_INT3, 1, 3, 0 },
+	{ IIC_ISR_INT4, 1, 4, 0 }, { IIC_ISR_INT5, 1, 5, 0 },
+	{ IIC_ISR_INT6, 1, 6, 0 }, { IIC_ISR_INT7, 1, 7, 0 },
+};
+
+static nt_fpga_field_init_t iic_rx_fifo_fields[] = {
+	{ IIC_RX_FIFO_RXDATA, 8, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_rx_fifo_ocy_fields[] = {
+	{ IIC_RX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_rx_fifo_pirq_fields[] = {
+	{ IIC_RX_FIFO_PIRQ_CMP_VAL, 4, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_softr_fields[] = {
+	{ IIC_SOFTR_RKEY, 4, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t iic_sr_fields[] = {
+	{ IIC_SR_AAS, 1, 1, 0 },	  { IIC_SR_ABGC, 1, 0, 0 },
+	{ IIC_SR_BB, 1, 2, 0 },		  { IIC_SR_RXFIFO_EMPTY, 1, 6, 1 },
+	{ IIC_SR_RXFIFO_FULL, 1, 5, 0 },  { IIC_SR_SRW, 1, 3, 0 },
+	{ IIC_SR_TXFIFO_EMPTY, 1, 7, 1 }, { IIC_SR_TXFIFO_FULL, 1, 4, 0 },
+};
+
+static nt_fpga_field_init_t iic_tbuf_fields[] = {
+	{ IIC_TBUF_TBUF_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_ten_adr_fields[] = {
+	{ IIC_TEN_ADR_MSB_SLV_ADR, 3, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_thddat_fields[] = {
+	{ IIC_THDDAT_THDDAT_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_thdsta_fields[] = {
+	{ IIC_THDSTA_THDSTA_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_thigh_fields[] = {
+	{ IIC_THIGH_THIGH_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_tlow_fields[] = {
+	{ IIC_TLOW_TLOW_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_tsudat_fields[] = {
+	{ IIC_TSUDAT_TSUDAT_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_tsusta_fields[] = {
+	{ IIC_TSUSTA_TSUSTA_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_tsusto_fields[] = {
+	{ IIC_TSUSTO_TSUSTO_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_tx_fifo_fields[] = {
+	{ IIC_TX_FIFO_START, 1, 8, 0 },
+	{ IIC_TX_FIFO_STOP, 1, 9, 0 },
+	{ IIC_TX_FIFO_TXDATA, 8, 0, 0 },
+};
+
+static nt_fpga_field_init_t iic_tx_fifo_ocy_fields[] = {
+	{ IIC_TX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
+};
+
+static nt_fpga_register_init_t iic_registers[] = {
+	{ IIC_ADR, 68, 8, REGISTER_TYPE_RW, 0, 1, iic_adr_fields },
+	{ IIC_CR, 64, 8, REGISTER_TYPE_RW, 0, 8, iic_cr_fields },
+	{ IIC_DGIE, 7, 32, REGISTER_TYPE_RW, 0, 1, iic_dgie_fields },
+	{ IIC_GPO, 73, 1, REGISTER_TYPE_RW, 0, 1, iic_gpo_fields },
+	{ IIC_IER, 10, 8, REGISTER_TYPE_RW, 0, 8, iic_ier_fields },
+	{ IIC_ISR, 8, 8, REGISTER_TYPE_RW, 0, 8, iic_isr_fields },
+	{ IIC_RX_FIFO, 67, 8, REGISTER_TYPE_RO, 0, 1, iic_rx_fifo_fields },
+	{	IIC_RX_FIFO_OCY, 70, 4, REGISTER_TYPE_RO, 0, 1,
+		iic_rx_fifo_ocy_fields
+	},
+	{	IIC_RX_FIFO_PIRQ, 72, 4, REGISTER_TYPE_RW, 0, 1,
+		iic_rx_fifo_pirq_fields
+	},
+	{ IIC_SOFTR, 16, 4, REGISTER_TYPE_WO, 0, 1, iic_softr_fields },
+	{ IIC_SR, 65, 8, REGISTER_TYPE_RO, 192, 8, iic_sr_fields },
+	{ IIC_TBUF, 78, 32, REGISTER_TYPE_RW, 0, 1, iic_tbuf_fields },
+	{ IIC_TEN_ADR, 71, 3, REGISTER_TYPE_RO, 0, 1, iic_ten_adr_fields },
+	{ IIC_THDDAT, 81, 32, REGISTER_TYPE_RW, 0, 1, iic_thddat_fields },
+	{ IIC_THDSTA, 76, 32, REGISTER_TYPE_RW, 0, 1, iic_thdsta_fields },
+	{ IIC_THIGH, 79, 32, REGISTER_TYPE_RW, 0, 1, iic_thigh_fields },
+	{ IIC_TLOW, 80, 32, REGISTER_TYPE_RW, 0, 1, iic_tlow_fields },
+	{ IIC_TSUDAT, 77, 32, REGISTER_TYPE_RW, 0, 1, iic_tsudat_fields },
+	{ IIC_TSUSTA, 74, 32, REGISTER_TYPE_RW, 0, 1, iic_tsusta_fields },
+	{ IIC_TSUSTO, 75, 32, REGISTER_TYPE_RW, 0, 1, iic_tsusto_fields },
+	{ IIC_TX_FIFO, 66, 10, REGISTER_TYPE_WO, 0, 3, iic_tx_fifo_fields },
+	{	IIC_TX_FIFO_OCY, 69, 4, REGISTER_TYPE_RO, 0, 1,
+		iic_tx_fifo_ocy_fields
+	},
+};
+
+static nt_fpga_field_init_t ins_rcp_ctrl_fields[] = {
+	{ INS_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ INS_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t ins_rcp_data_fields[] = {
+	{ INS_RCP_DATA_DYN, 5, 0, 0x0000 },
+	{ INS_RCP_DATA_LEN, 8, 15, 0x0000 },
+	{ INS_RCP_DATA_OFS, 10, 5, 0x0000 },
+};
+
+static nt_fpga_register_init_t ins_registers[] = {
+	{ INS_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, ins_rcp_ctrl_fields },
+	{ INS_RCP_DATA, 1, 23, REGISTER_TYPE_WO, 0, 3, ins_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t km_cam_ctrl_fields[] = {
+	{ KM_CAM_CTRL_ADR, 13, 0, 0x0000 },
+	{ KM_CAM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_cam_data_fields[] = {
+	{ KM_CAM_DATA_FT0, 4, 192, 0x0000 },
+	{ KM_CAM_DATA_FT1, 4, 196, 0x0000 },
+	{ KM_CAM_DATA_FT2, 4, 200, 0x0000 },
+	{ KM_CAM_DATA_FT3, 4, 204, 0x0000 },
+	{ KM_CAM_DATA_FT4, 4, 208, 0x0000 },
+	{ KM_CAM_DATA_FT5, 4, 212, 0x0000 },
+	{ KM_CAM_DATA_W0, 32, 0, 0x0000 },
+	{ KM_CAM_DATA_W1, 32, 32, 0x0000 },
+	{ KM_CAM_DATA_W2, 32, 64, 0x0000 },
+	{ KM_CAM_DATA_W3, 32, 96, 0x0000 },
+	{ KM_CAM_DATA_W4, 32, 128, 0x0000 },
+	{ KM_CAM_DATA_W5, 32, 160, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_rcp_ctrl_fields[] = {
+	{ KM_RCP_CTRL_ADR, 5, 0, 0x0000 },
+	{ KM_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_rcp_data_fields[] = {
+	{ KM_RCP_DATA_BANK_A, 12, 694, 0x0000 },
+	{ KM_RCP_DATA_BANK_B, 12, 706, 0x0000 },
+	{ KM_RCP_DATA_DUAL, 1, 651, 0x0000 },
+	{ KM_RCP_DATA_DW0_B_DYN, 5, 729, 0x0000 },
+	{ KM_RCP_DATA_DW0_B_OFS, 8, 734, 0x0000 },
+	{ KM_RCP_DATA_DW10_DYN, 5, 55, 0x0000 },
+	{ KM_RCP_DATA_DW10_OFS, 8, 60, 0x0000 },
+	{ KM_RCP_DATA_DW10_SEL_A, 2, 68, 0x0000 },
+	{ KM_RCP_DATA_DW10_SEL_B, 2, 70, 0x0000 },
+	{ KM_RCP_DATA_DW2_B_DYN, 5, 742, 0x0000 },
+	{ KM_RCP_DATA_DW2_B_OFS, 8, 747, 0x0000 },
+	{ KM_RCP_DATA_DW8_DYN, 5, 36, 0x0000 },
+	{ KM_RCP_DATA_DW8_OFS, 8, 41, 0x0000 },
+	{ KM_RCP_DATA_DW8_SEL_A, 3, 49, 0x0000 },
+	{ KM_RCP_DATA_DW8_SEL_B, 3, 52, 0x0000 },
+	{ KM_RCP_DATA_EL_A, 4, 653, 0x0000 },
+	{ KM_RCP_DATA_EL_B, 3, 657, 0x0000 },
+	{ KM_RCP_DATA_FTM_A, 16, 662, 0x0000 },
+	{ KM_RCP_DATA_FTM_B, 16, 678, 0x0000 },
+	{ KM_RCP_DATA_INFO_A, 1, 660, 0x0000 },
+	{ KM_RCP_DATA_INFO_B, 1, 661, 0x0000 },
+	{ KM_RCP_DATA_KEYWAY_A, 1, 725, 0x0000 },
+	{ KM_RCP_DATA_KEYWAY_B, 1, 726, 0x0000 },
+	{ KM_RCP_DATA_KL_A, 4, 718, 0x0000 },
+	{ KM_RCP_DATA_KL_B, 3, 722, 0x0000 },
+	{ KM_RCP_DATA_MASK_A, 384, 75, 0x0000 },
+	{ KM_RCP_DATA_MASK_B, 192, 459, 0x0000 },
+	{ KM_RCP_DATA_PAIRED, 1, 652, 0x0000 },
+	{ KM_RCP_DATA_QW0_DYN, 5, 0, 0x0000 },
+	{ KM_RCP_DATA_QW0_OFS, 8, 5, 0x0000 },
+	{ KM_RCP_DATA_QW0_SEL_A, 3, 13, 0x0000 },
+	{ KM_RCP_DATA_QW0_SEL_B, 3, 16, 0x0000 },
+	{ KM_RCP_DATA_QW4_DYN, 5, 19, 0x0000 },
+	{ KM_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },
+	{ KM_RCP_DATA_QW4_SEL_A, 2, 32, 0x0000 },
+	{ KM_RCP_DATA_QW4_SEL_B, 2, 34, 0x0000 },
+	{ KM_RCP_DATA_SW4_B_DYN, 5, 755, 0x0000 },
+	{ KM_RCP_DATA_SW4_B_OFS, 8, 760, 0x0000 },
+	{ KM_RCP_DATA_SW5_B_DYN, 5, 768, 0x0000 },
+	{ KM_RCP_DATA_SW5_B_OFS, 8, 773, 0x0000 },
+	{ KM_RCP_DATA_SWX_CCH, 1, 72, 0x0000 },
+	{ KM_RCP_DATA_SWX_SEL_A, 1, 73, 0x0000 },
+	{ KM_RCP_DATA_SWX_SEL_B, 1, 74, 0x0000 },
+	{ KM_RCP_DATA_SYNERGY_MODE, 2, 727, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_status_fields[] = {
+	{ KM_STATUS_TCQ_RDY, 1, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_tcam_ctrl_fields[] = {
+	{ KM_TCAM_CTRL_ADR, 14, 0, 0x0000 },
+	{ KM_TCAM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_tcam_data_fields[] = {
+	{ KM_TCAM_DATA_T, 72, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_tci_ctrl_fields[] = {
+	{ KM_TCI_CTRL_ADR, 10, 0, 0x0000 },
+	{ KM_TCI_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_tci_data_fields[] = {
+	{ KM_TCI_DATA_COLOR, 32, 0, 0x0000 },
+	{ KM_TCI_DATA_FT, 4, 32, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_tcq_ctrl_fields[] = {
+	{ KM_TCQ_CTRL_ADR, 7, 0, 0x0000 },
+	{ KM_TCQ_CTRL_CNT, 5, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t km_tcq_data_fields[] = {
+	{ KM_TCQ_DATA_BANK_MASK, 12, 0, 0x0000 },
+	{ KM_TCQ_DATA_QUAL, 3, 12, 0x0000 },
+};
+
+static nt_fpga_register_init_t km_registers[] = {
+	{ KM_CAM_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, km_cam_ctrl_fields },
+	{ KM_CAM_DATA, 3, 216, REGISTER_TYPE_WO, 0, 12, km_cam_data_fields },
+	{ KM_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, km_rcp_ctrl_fields },
+	{ KM_RCP_DATA, 1, 781, REGISTER_TYPE_WO, 0, 44, km_rcp_data_fields },
+	{ KM_STATUS, 10, 1, REGISTER_TYPE_RO, 0, 1, km_status_fields },
+	{ KM_TCAM_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2, km_tcam_ctrl_fields },
+	{ KM_TCAM_DATA, 5, 72, REGISTER_TYPE_WO, 0, 1, km_tcam_data_fields },
+	{ KM_TCI_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2, km_tci_ctrl_fields },
+	{ KM_TCI_DATA, 7, 36, REGISTER_TYPE_WO, 0, 2, km_tci_data_fields },
+	{ KM_TCQ_CTRL, 8, 21, REGISTER_TYPE_WO, 0, 2, km_tcq_ctrl_fields },
+	{ KM_TCQ_DATA, 9, 15, REGISTER_TYPE_WO, 0, 2, km_tcq_data_fields },
+};
+
+static nt_fpga_field_init_t mac_pcs_bad_code_fields[] = {
+	{ MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_bip_err_fields[] = {
+	{ MAC_PCS_BIP_ERR_BIP_ERR, 640, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_block_lock_fields[] = {
+	{ MAC_PCS_BLOCK_LOCK_LOCK, 20, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_block_lock_chg_fields[] = {
+	{ MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG, 20, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_debounce_ctrl_fields[] = {
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY, 8, 8, 10 },
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN, 1, 16, 0 },
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY, 8, 0, 10 },
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL, 2, 17, 2 },
+};
+
+static nt_fpga_field_init_t mac_pcs_drp_ctrl_fields[] = {
+	{ MAC_PCS_DRP_CTRL_ADR, 10, 16, 0 },
+	{ MAC_PCS_DRP_CTRL_DATA, 16, 0, 0 },
+	{ MAC_PCS_DRP_CTRL_DBG_BUSY, 1, 30, 0x0000 },
+	{ MAC_PCS_DRP_CTRL_DONE, 1, 31, 0x0000 },
+	{ MAC_PCS_DRP_CTRL_MOD_ADR, 3, 26, 0 },
+	{ MAC_PCS_DRP_CTRL_WREN, 1, 29, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_ctrl_fields[] = {
+	{ MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN, 5, 0, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_cw_cnt_fields[] = {
+	{ MAC_PCS_FEC_CW_CNT_CW_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_0_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_0_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_1_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_1_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_2_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_2_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_3_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_3_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_0_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_0_DLY, 14, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_1_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_1_DLY, 14, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_2_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_2_DLY, 14, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_3_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_3_DLY, 14, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_lane_map_fields[] = {
+	{ MAC_PCS_FEC_LANE_MAP_MAPPING, 8, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_stat_fields[] = {
+	{ MAC_PCS_FEC_STAT_AM_LOCK, 1, 10, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_0, 1, 3, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_1, 1, 4, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_2, 1, 5, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_3, 1, 6, 0x0000 },
+	{ MAC_PCS_FEC_STAT_BLOCK_LOCK, 1, 9, 0x0000 },
+	{ MAC_PCS_FEC_STAT_BYPASS, 1, 0, 0x0000 },
+	{ MAC_PCS_FEC_STAT_FEC_LANE_ALGN, 1, 7, 0x0000 },
+	{ MAC_PCS_FEC_STAT_HI_SER, 1, 2, 0x0000 },
+	{ MAC_PCS_FEC_STAT_PCS_LANE_ALGN, 1, 8, 0x0000 },
+	{ MAC_PCS_FEC_STAT_VALID, 1, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_fec_ucw_cnt_fields[] = {
+	{ MAC_PCS_FEC_UCW_CNT_UCW_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_ctl_rx_fields[] = {
+	{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_0, 1, 24, 0 },
+	{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_1, 1, 25, 0 },
+	{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_2, 1, 26, 0 },
+	{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_3, 1, 27, 0 },
+	{ MAC_PCS_GTY_CTL_RX_EQUA_RST_0, 1, 20, 0 },
+	{ MAC_PCS_GTY_CTL_RX_EQUA_RST_1, 1, 21, 0 },
+	{ MAC_PCS_GTY_CTL_RX_EQUA_RST_2, 1, 22, 0 },
+	{ MAC_PCS_GTY_CTL_RX_EQUA_RST_3, 1, 23, 0 },
+	{ MAC_PCS_GTY_CTL_RX_LPM_EN_0, 1, 16, 0 },
+	{ MAC_PCS_GTY_CTL_RX_LPM_EN_1, 1, 17, 0 },
+	{ MAC_PCS_GTY_CTL_RX_LPM_EN_2, 1, 18, 0 },
+	{ MAC_PCS_GTY_CTL_RX_LPM_EN_3, 1, 19, 0 },
+	{ MAC_PCS_GTY_CTL_RX_POLARITY_0, 1, 0, 0 },
+	{ MAC_PCS_GTY_CTL_RX_POLARITY_1, 1, 1, 0 },
+	{ MAC_PCS_GTY_CTL_RX_POLARITY_2, 1, 2, 0 },
+	{ MAC_PCS_GTY_CTL_RX_POLARITY_3, 1, 3, 0 },
+	{ MAC_PCS_GTY_CTL_RX_RATE_0, 3, 4, 0 },
+	{ MAC_PCS_GTY_CTL_RX_RATE_1, 3, 7, 0 },
+	{ MAC_PCS_GTY_CTL_RX_RATE_2, 3, 10, 0 },
+	{ MAC_PCS_GTY_CTL_RX_RATE_3, 3, 13, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_ctl_tx_fields[] = {
+	{ MAC_PCS_GTY_CTL_TX_INHIBIT_0, 1, 4, 0 },
+	{ MAC_PCS_GTY_CTL_TX_INHIBIT_1, 1, 5, 0 },
+	{ MAC_PCS_GTY_CTL_TX_INHIBIT_2, 1, 6, 0 },
+	{ MAC_PCS_GTY_CTL_TX_INHIBIT_3, 1, 7, 0 },
+	{ MAC_PCS_GTY_CTL_TX_POLARITY_0, 1, 0, 0 },
+	{ MAC_PCS_GTY_CTL_TX_POLARITY_1, 1, 1, 0 },
+	{ MAC_PCS_GTY_CTL_TX_POLARITY_2, 1, 2, 0 },
+	{ MAC_PCS_GTY_CTL_TX_POLARITY_3, 1, 3, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_diff_ctl_fields[] = {
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0, 5, 0, 24 },
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1, 5, 5, 24 },
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2, 5, 10, 24 },
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3, 5, 15, 24 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_loop_fields[] = {
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_0, 3, 0, 0 },
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_1, 3, 3, 0 },
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_2, 3, 6, 0 },
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_3, 3, 9, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_post_cursor_fields[] = {
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0, 5, 0, 20 },
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1, 5, 5, 20 },
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2, 5, 10, 20 },
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3, 5, 15, 20 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_prbs_sel_fields[] = {
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0, 4, 16, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1, 4, 20, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2, 4, 24, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3, 4, 28, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0, 4, 0, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1, 4, 4, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2, 4, 8, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3, 4, 12, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_pre_cursor_fields[] = {
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0, 5, 0, 0 },
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1, 5, 5, 0 },
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2, 5, 10, 0 },
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3, 5, 15, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_rx_buf_stat_fields[] = {
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0, 3, 0, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1, 3, 3, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2, 3, 6, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3, 3, 9, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0, 3, 12, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1, 3, 15, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2, 3, 18, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3, 3, 21, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_scan_ctl_fields[] = {
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0, 1, 0, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1, 1, 1, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2, 1, 2, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3, 1, 3, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0, 1, 4, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1, 1, 5, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2, 1, 6, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3, 1, 7, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0, 1, 12, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1, 1, 13, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2, 1, 14, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3, 1, 15, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0, 1, 8, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1, 1, 9, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2, 1, 10, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3, 1, 11, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_scan_stat_fields[] = {
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0, 1, 0, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1, 1, 1, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2, 1, 2, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3, 1, 3, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0, 1, 4, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1, 1, 5, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2, 1, 6, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3, 1, 7, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_gty_stat_fields[] = {
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_0, 1, 4, 0x0000 },
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_1, 1, 5, 0x0000 },
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_2, 1, 6, 0x0000 },
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_3, 1, 7, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_0, 2, 8, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_1, 2, 10, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_2, 2, 12, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_3, 2, 14, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_0, 1, 0, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_1, 1, 1, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_2, 1, 2, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_3, 1, 3, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_link_summary_fields[] = {
+	{ MAC_PCS_LINK_SUMMARY_ABS, 1, 0, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_LH_ABS, 1, 2, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT, 1, 13, 0 },
+	{ MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT, 1, 14, 0 },
+	{ MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT, 8, 4, 0 },
+	{ MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE, 1, 3, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_LOCAL_FAULT, 1, 17, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_NIM_INTERR, 1, 12, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE, 1, 1, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_REMOTE_FAULT, 1, 18, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_RESERVED, 2, 15, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_mac_pcs_config_fields[] = {
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST, 1, 3, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE, 1, 5, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC, 1, 6, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST, 1, 1, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN, 1, 7, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST, 1, 2, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE, 1, 8, 1 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE, 1, 4, 1 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST, 1, 0, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE, 1, 9, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI, 1, 10, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN, 1, 11, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_max_pkt_len_fields[] = {
+	{ MAC_PCS_MAX_PKT_LEN_MAX_LEN, 14, 0, 10000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_phymac_misc_fields[] = {
+	{ MAC_PCS_PHYMAC_MISC_TS_EOP, 1, 3, 1 },
+	{ MAC_PCS_PHYMAC_MISC_TX_MUX_STATE, 4, 4, 0x0000 },
+	{ MAC_PCS_PHYMAC_MISC_TX_SEL_HOST, 1, 0, 1 },
+	{ MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP, 1, 2, 0 },
+	{ MAC_PCS_PHYMAC_MISC_TX_SEL_TFG, 1, 1, 0 },
+};
+
+static nt_fpga_field_init_t mac_pcs_phy_stat_fields[] = {
+	{ MAC_PCS_PHY_STAT_ALARM, 1, 2, 0x0000 },
+	{ MAC_PCS_PHY_STAT_MOD_PRS, 1, 1, 0x0000 },
+	{ MAC_PCS_PHY_STAT_RX_LOS, 1, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_stat_pcs_rx_fields[] = {
+	{ MAC_PCS_STAT_PCS_RX_ALIGNED, 1, 1, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_ALIGNED_ERR, 1, 2, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS, 1, 9, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_HI_BER, 1, 8, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LOCAL_FAULT, 1, 6, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_MISALIGNED, 1, 3, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_REMOTE_FAULT, 1, 7, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_STATUS, 1, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_stat_pcs_rx_latch_fields[] = {
+	{ MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED, 1, 1, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR, 1, 2, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS, 1, 9, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_HI_BER, 1, 8, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT, 1, 6, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED, 1, 3, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT, 1, 7, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_STATUS, 1, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_stat_pcs_tx_fields[] = {
+	{ MAC_PCS_STAT_PCS_TX_LOCAL_FAULT, 1, 0, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED, 1, 5, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR, 1, 4, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED, 1, 9, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR, 1, 3, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED, 1, 8, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_OVFOUT, 1, 2, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED, 1, 7, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_UNFOUT, 1, 1, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED, 1, 6, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_synced_fields[] = {
+	{ MAC_PCS_SYNCED_SYNC, 20, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_synced_err_fields[] = {
+	{ MAC_PCS_SYNCED_ERR_SYNC_ERROR, 20, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_test_err_fields[] = {
+	{ MAC_PCS_TEST_ERR_CODE_ERR, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_timestamp_comp_fields[] = {
+	{ MAC_PCS_TIMESTAMP_COMP_RX_DLY, 16, 0, 1451 },
+	{ MAC_PCS_TIMESTAMP_COMP_TX_DLY, 16, 16, 1440 },
+};
+
+static nt_fpga_field_init_t mac_pcs_vl_demuxed_fields[] = {
+	{ MAC_PCS_VL_DEMUXED_LOCK, 20, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_pcs_vl_demuxed_chg_fields[] = {
+	{ MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG, 20, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t mac_pcs_registers[] = {
+	{	MAC_PCS_BAD_CODE, 26, 16, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_bad_code_fields
+	},
+	{	MAC_PCS_BIP_ERR, 31, 640, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_bip_err_fields
+	},
+	{	MAC_PCS_BLOCK_LOCK, 27, 20, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_block_lock_fields
+	},
+	{	MAC_PCS_BLOCK_LOCK_CHG, 28, 20, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_block_lock_chg_fields
+	},
+	{	MAC_PCS_DEBOUNCE_CTRL, 1, 19, REGISTER_TYPE_RW, 264714, 4,
+		mac_pcs_debounce_ctrl_fields
+	},
+	{	MAC_PCS_DRP_CTRL, 43, 32, REGISTER_TYPE_MIXED, 0, 6,
+		mac_pcs_drp_ctrl_fields
+	},
+	{	MAC_PCS_FEC_CTRL, 2, 5, REGISTER_TYPE_RW, 0, 1,
+		mac_pcs_fec_ctrl_fields
+	},
+	{	MAC_PCS_FEC_CW_CNT, 9, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_cw_cnt_fields
+	},
+	{	MAC_PCS_FEC_ERR_CNT_0, 11, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_0_fields
+	},
+	{	MAC_PCS_FEC_ERR_CNT_1, 12, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_1_fields
+	},
+	{	MAC_PCS_FEC_ERR_CNT_2, 13, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_2_fields
+	},
+	{	MAC_PCS_FEC_ERR_CNT_3, 14, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_3_fields
+	},
+	{	MAC_PCS_FEC_LANE_DLY_0, 5, 14, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_0_fields
+	},
+	{	MAC_PCS_FEC_LANE_DLY_1, 6, 14, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_1_fields
+	},
+	{	MAC_PCS_FEC_LANE_DLY_2, 7, 14, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_2_fields
+	},
+	{	MAC_PCS_FEC_LANE_DLY_3, 8, 14, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_3_fields
+	},
+	{	MAC_PCS_FEC_LANE_MAP, 4, 8, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_map_fields
+	},
+	{	MAC_PCS_FEC_STAT, 3, 11, REGISTER_TYPE_RO, 0, 11,
+		mac_pcs_fec_stat_fields
+	},
+	{	MAC_PCS_FEC_UCW_CNT, 10, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_fec_ucw_cnt_fields
+	},
+	{	MAC_PCS_GTY_CTL_RX, 38, 28, REGISTER_TYPE_RW, 0, 20,
+		mac_pcs_gty_ctl_rx_fields
+	},
+	{	MAC_PCS_GTY_CTL_TX, 39, 8, REGISTER_TYPE_RW, 0, 8,
+		mac_pcs_gty_ctl_tx_fields
+	},
+	{	MAC_PCS_GTY_DIFF_CTL, 35, 20, REGISTER_TYPE_RW, 811800, 4,
+		mac_pcs_gty_diff_ctl_fields
+	},
+	{	MAC_PCS_GTY_LOOP, 20, 12, REGISTER_TYPE_RW, 0, 4,
+		mac_pcs_gty_loop_fields
+	},
+	{	MAC_PCS_GTY_POST_CURSOR, 36, 20, REGISTER_TYPE_RW, 676500, 4,
+		mac_pcs_gty_post_cursor_fields
+	},
+	{	MAC_PCS_GTY_PRBS_SEL, 40, 32, REGISTER_TYPE_RW, 0, 8,
+		mac_pcs_gty_prbs_sel_fields
+	},
+	{	MAC_PCS_GTY_PRE_CURSOR, 37, 20, REGISTER_TYPE_RW, 0, 4,
+		mac_pcs_gty_pre_cursor_fields
+	},
+	{	MAC_PCS_GTY_RX_BUF_STAT, 34, 24, REGISTER_TYPE_RO, 0, 8,
+		mac_pcs_gty_rx_buf_stat_fields
+	},
+	{	MAC_PCS_GTY_SCAN_CTL, 41, 16, REGISTER_TYPE_RW, 0, 16,
+		mac_pcs_gty_scan_ctl_fields
+	},
+	{	MAC_PCS_GTY_SCAN_STAT, 42, 8, REGISTER_TYPE_RO, 0, 8,
+		mac_pcs_gty_scan_stat_fields
+	},
+	{	MAC_PCS_GTY_STAT, 33, 16, REGISTER_TYPE_RO, 0, 12,
+		mac_pcs_gty_stat_fields
+	},
+	{	MAC_PCS_LINK_SUMMARY, 0, 19, REGISTER_TYPE_RO, 0, 11,
+		mac_pcs_link_summary_fields
+	},
+	{	MAC_PCS_MAC_PCS_CONFIG, 19, 12, REGISTER_TYPE_RW, 272, 12,
+		mac_pcs_mac_pcs_config_fields
+	},
+	{	MAC_PCS_MAX_PKT_LEN, 17, 14, REGISTER_TYPE_RW, 10000, 1,
+		mac_pcs_max_pkt_len_fields
+	},
+	{	MAC_PCS_PHYMAC_MISC, 16, 8, REGISTER_TYPE_MIXED, 9, 5,
+		mac_pcs_phymac_misc_fields
+	},
+	{	MAC_PCS_PHY_STAT, 15, 3, REGISTER_TYPE_RO, 0, 3,
+		mac_pcs_phy_stat_fields
+	},
+	{	MAC_PCS_STAT_PCS_RX, 21, 10, REGISTER_TYPE_RO, 0, 10,
+		mac_pcs_stat_pcs_rx_fields
+	},
+	{	MAC_PCS_STAT_PCS_RX_LATCH, 22, 10, REGISTER_TYPE_RO, 0, 10,
+		mac_pcs_stat_pcs_rx_latch_fields
+	},
+	{	MAC_PCS_STAT_PCS_TX, 23, 10, REGISTER_TYPE_RO, 0, 10,
+		mac_pcs_stat_pcs_tx_fields
+	},
+	{	MAC_PCS_SYNCED, 24, 20, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_synced_fields
+	},
+	{	MAC_PCS_SYNCED_ERR, 25, 20, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_synced_err_fields
+	},
+	{	MAC_PCS_TEST_ERR, 32, 16, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_test_err_fields
+	},
+	{	MAC_PCS_TIMESTAMP_COMP, 18, 32, REGISTER_TYPE_RW, 94373291, 2,
+		mac_pcs_timestamp_comp_fields
+	},
+	{	MAC_PCS_VL_DEMUXED, 29, 20, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_vl_demuxed_fields
+	},
+	{	MAC_PCS_VL_DEMUXED_CHG, 30, 20, REGISTER_TYPE_RO, 0, 1,
+		mac_pcs_vl_demuxed_chg_fields
+	},
+};
+
+static nt_fpga_field_init_t mac_rx_bad_fcs_fields[] = {
+	{ MAC_RX_BAD_FCS_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_fragment_fields[] = {
+	{ MAC_RX_FRAGMENT_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_packet_bad_fcs_fields[] = {
+	{ MAC_RX_PACKET_BAD_FCS_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_packet_small_fields[] = {
+	{ MAC_RX_PACKET_SMALL_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_total_bytes_fields[] = {
+	{ MAC_RX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_total_good_bytes_fields[] = {
+	{ MAC_RX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_total_good_packets_fields[] = {
+	{ MAC_RX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_total_packets_fields[] = {
+	{ MAC_RX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_rx_undersize_fields[] = {
+	{ MAC_RX_UNDERSIZE_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t mac_rx_registers[] = {
+	{	MAC_RX_BAD_FCS, 0, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_bad_fcs_fields
+	},
+	{	MAC_RX_FRAGMENT, 6, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_fragment_fields
+	},
+	{	MAC_RX_PACKET_BAD_FCS, 7, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_packet_bad_fcs_fields
+	},
+	{	MAC_RX_PACKET_SMALL, 3, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_packet_small_fields
+	},
+	{	MAC_RX_TOTAL_BYTES, 4, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_total_bytes_fields
+	},
+	{	MAC_RX_TOTAL_GOOD_BYTES, 5, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_total_good_bytes_fields
+	},
+	{	MAC_RX_TOTAL_GOOD_PACKETS, 2, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_total_good_packets_fields
+	},
+	{	MAC_RX_TOTAL_PACKETS, 1, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_total_packets_fields
+	},
+	{	MAC_RX_UNDERSIZE, 8, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_rx_undersize_fields
+	},
+};
+
+static nt_fpga_field_init_t mac_tx_packet_small_fields[] = {
+	{ MAC_TX_PACKET_SMALL_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_tx_total_bytes_fields[] = {
+	{ MAC_TX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_tx_total_good_bytes_fields[] = {
+	{ MAC_TX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_tx_total_good_packets_fields[] = {
+	{ MAC_TX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t mac_tx_total_packets_fields[] = {
+	{ MAC_TX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t mac_tx_registers[] = {
+	{	MAC_TX_PACKET_SMALL, 2, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_tx_packet_small_fields
+	},
+	{	MAC_TX_TOTAL_BYTES, 3, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_tx_total_bytes_fields
+	},
+	{	MAC_TX_TOTAL_GOOD_BYTES, 4, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_tx_total_good_bytes_fields
+	},
+	{	MAC_TX_TOTAL_GOOD_PACKETS, 1, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_tx_total_good_packets_fields
+	},
+	{	MAC_TX_TOTAL_PACKETS, 0, 32, REGISTER_TYPE_RO, 0, 1,
+		mac_tx_total_packets_fields
+	},
+};
+
+static nt_fpga_field_init_t pci_rd_tg_tg_ctrl_fields[] = {
+	{ PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_rd_tg_tg_rdaddr_fields[] = {
+	{ PCI_RD_TG_TG_RDADDR_RAM_ADDR, 9, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_rd_tg_tg_rddata0_fields[] = {
+	{ PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_rd_tg_tg_rddata1_fields[] = {
+	{ PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_rd_tg_tg_rddata2_fields[] = {
+	{ PCI_RD_TG_TG_RDDATA2_REQ_HID, 6, 22, 0 },
+	{ PCI_RD_TG_TG_RDDATA2_REQ_SIZE, 22, 0, 0 },
+	{ PCI_RD_TG_TG_RDDATA2_WAIT, 1, 30, 0 },
+	{ PCI_RD_TG_TG_RDDATA2_WRAP, 1, 31, 0 },
+};
+
+static nt_fpga_field_init_t pci_rd_tg_tg_rd_run_fields[] = {
+	{ PCI_RD_TG_TG_RD_RUN_RD_ITERATION, 16, 0, 0 },
+};
+
+static nt_fpga_register_init_t pci_rd_tg_registers[] = {
+	{	PCI_RD_TG_TG_CTRL, 5, 1, REGISTER_TYPE_RO, 0, 1,
+		pci_rd_tg_tg_ctrl_fields
+	},
+	{	PCI_RD_TG_TG_RDADDR, 3, 9, REGISTER_TYPE_WO, 0, 1,
+		pci_rd_tg_tg_rdaddr_fields
+	},
+	{	PCI_RD_TG_TG_RDDATA0, 0, 32, REGISTER_TYPE_WO, 0, 1,
+		pci_rd_tg_tg_rddata0_fields
+	},
+	{	PCI_RD_TG_TG_RDDATA1, 1, 32, REGISTER_TYPE_WO, 0, 1,
+		pci_rd_tg_tg_rddata1_fields
+	},
+	{	PCI_RD_TG_TG_RDDATA2, 2, 32, REGISTER_TYPE_WO, 0, 4,
+		pci_rd_tg_tg_rddata2_fields
+	},
+	{	PCI_RD_TG_TG_RD_RUN, 4, 16, REGISTER_TYPE_WO, 0, 1,
+		pci_rd_tg_tg_rd_run_fields
+	},
+};
+
+static nt_fpga_field_init_t pci_ta_control_fields[] = {
+	{ PCI_TA_CONTROL_ENABLE, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_ta_length_error_fields[] = {
+	{ PCI_TA_LENGTH_ERROR_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t pci_ta_packet_bad_fields[] = {
+	{ PCI_TA_PACKET_BAD_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t pci_ta_packet_good_fields[] = {
+	{ PCI_TA_PACKET_GOOD_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t pci_ta_payload_error_fields[] = {
+	{ PCI_TA_PAYLOAD_ERROR_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t pci_ta_registers[] = {
+	{ PCI_TA_CONTROL, 0, 1, REGISTER_TYPE_WO, 0, 1, pci_ta_control_fields },
+	{	PCI_TA_LENGTH_ERROR, 3, 32, REGISTER_TYPE_RO, 0, 1,
+		pci_ta_length_error_fields
+	},
+	{	PCI_TA_PACKET_BAD, 2, 32, REGISTER_TYPE_RO, 0, 1,
+		pci_ta_packet_bad_fields
+	},
+	{	PCI_TA_PACKET_GOOD, 1, 32, REGISTER_TYPE_RO, 0, 1,
+		pci_ta_packet_good_fields
+	},
+	{	PCI_TA_PAYLOAD_ERROR, 4, 32, REGISTER_TYPE_RO, 0, 1,
+		pci_ta_payload_error_fields
+	},
+};
+
+static nt_fpga_field_init_t pci_wr_tg_tg_ctrl_fields[] = {
+	{ PCI_WR_TG_TG_CTRL_TG_WR_RDY, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_wr_tg_tg_seq_fields[] = {
+	{ PCI_WR_TG_TG_SEQ_SEQUENCE, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_wr_tg_tg_wraddr_fields[] = {
+	{ PCI_WR_TG_TG_WRADDR_RAM_ADDR, 9, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_wr_tg_tg_wrdata0_fields[] = {
+	{ PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_wr_tg_tg_wrdata1_fields[] = {
+	{ PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t pci_wr_tg_tg_wrdata2_fields[] = {
+	{ PCI_WR_TG_TG_WRDATA2_INC_MODE, 1, 29, 0 },
+	{ PCI_WR_TG_TG_WRDATA2_REQ_HID, 6, 22, 0 },
+	{ PCI_WR_TG_TG_WRDATA2_REQ_SIZE, 22, 0, 0 },
+	{ PCI_WR_TG_TG_WRDATA2_WAIT, 1, 30, 0 },
+	{ PCI_WR_TG_TG_WRDATA2_WRAP, 1, 31, 0 },
+};
+
+static nt_fpga_field_init_t pci_wr_tg_tg_wr_run_fields[] = {
+	{ PCI_WR_TG_TG_WR_RUN_WR_ITERATION, 16, 0, 0 },
+};
+
+static nt_fpga_register_init_t pci_wr_tg_registers[] = {
+	{	PCI_WR_TG_TG_CTRL, 5, 1, REGISTER_TYPE_RO, 0, 1,
+		pci_wr_tg_tg_ctrl_fields
+	},
+	{	PCI_WR_TG_TG_SEQ, 6, 16, REGISTER_TYPE_RW, 0, 1,
+		pci_wr_tg_tg_seq_fields
+	},
+	{	PCI_WR_TG_TG_WRADDR, 3, 9, REGISTER_TYPE_WO, 0, 1,
+		pci_wr_tg_tg_wraddr_fields
+	},
+	{	PCI_WR_TG_TG_WRDATA0, 0, 32, REGISTER_TYPE_WO, 0, 1,
+		pci_wr_tg_tg_wrdata0_fields
+	},
+	{	PCI_WR_TG_TG_WRDATA1, 1, 32, REGISTER_TYPE_WO, 0, 1,
+		pci_wr_tg_tg_wrdata1_fields
+	},
+	{	PCI_WR_TG_TG_WRDATA2, 2, 32, REGISTER_TYPE_WO, 0, 5,
+		pci_wr_tg_tg_wrdata2_fields
+	},
+	{	PCI_WR_TG_TG_WR_RUN, 4, 16, REGISTER_TYPE_WO, 0, 1,
+		pci_wr_tg_tg_wr_run_fields
+	},
+};
+
+static nt_fpga_field_init_t pdb_config_fields[] = {
+	{ PDB_CONFIG_PORT_OFS, 6, 3, 0 },
+	{ PDB_CONFIG_TS_FORMAT, 3, 0, 0 },
+};
+
+static nt_fpga_field_init_t pdb_rcp_ctrl_fields[] = {
+	{ PDB_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ PDB_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t pdb_rcp_data_fields[] = {
+	{ PDB_RCP_DATA_ALIGN, 1, 17, 0x0000 },
+	{ PDB_RCP_DATA_CRC_OVERWRITE, 1, 16, 0x0000 },
+	{ PDB_RCP_DATA_DESCRIPTOR, 4, 0, 0x0000 },
+	{ PDB_RCP_DATA_DESC_LEN, 5, 4, 0 },
+	{ PDB_RCP_DATA_DUPLICATE_BIT, 5, 61, 0x0000 },
+	{ PDB_RCP_DATA_DUPLICATE_EN, 1, 60, 0x0000 },
+	{ PDB_RCP_DATA_IP_PROT_TNL, 1, 57, 0x0000 },
+	{ PDB_RCP_DATA_OFS0_DYN, 5, 18, 0x0000 },
+	{ PDB_RCP_DATA_OFS0_REL, 8, 23, 0x0000 },
+	{ PDB_RCP_DATA_OFS1_DYN, 5, 31, 0x0000 },
+	{ PDB_RCP_DATA_OFS1_REL, 8, 36, 0x0000 },
+	{ PDB_RCP_DATA_OFS2_DYN, 5, 44, 0x0000 },
+	{ PDB_RCP_DATA_OFS2_REL, 8, 49, 0x0000 },
+	{ PDB_RCP_DATA_PCAP_KEEP_FCS, 1, 66, 0x0000 },
+	{ PDB_RCP_DATA_PPC_HSH, 2, 58, 0x0000 },
+	{ PDB_RCP_DATA_TX_IGNORE, 1, 14, 0x0000 },
+	{ PDB_RCP_DATA_TX_NOW, 1, 15, 0x0000 },
+	{ PDB_RCP_DATA_TX_PORT, 5, 9, 0x0000 },
+};
+
+static nt_fpga_register_init_t pdb_registers[] = {
+	{ PDB_CONFIG, 2, 10, REGISTER_TYPE_WO, 0, 2, pdb_config_fields },
+	{ PDB_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, pdb_rcp_ctrl_fields },
+	{ PDB_RCP_DATA, 1, 67, REGISTER_TYPE_WO, 0, 18, pdb_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t pdi_cr_fields[] = {
+	{ PDI_CR_EN, 1, 0, 0 },	  { PDI_CR_PARITY, 1, 4, 0 },
+	{ PDI_CR_RST, 1, 1, 0 },  { PDI_CR_RXRST, 1, 2, 0 },
+	{ PDI_CR_STOP, 1, 5, 0 }, { PDI_CR_TXRST, 1, 3, 0 },
+};
+
+static nt_fpga_field_init_t pdi_drr_fields[] = {
+	{ PDI_DRR_DRR, 8, 0, 0 },
+};
+
+static nt_fpga_field_init_t pdi_dtr_fields[] = {
+	{ PDI_DTR_DTR, 8, 0, 0 },
+};
+
+static nt_fpga_field_init_t pdi_pre_fields[] = {
+	{ PDI_PRE_PRE, 7, 0, 3 },
+};
+
+static nt_fpga_field_init_t pdi_sr_fields[] = {
+	{ PDI_SR_DISABLE_BUSY, 1, 2, 0 }, { PDI_SR_DONE, 1, 0, 0 },
+	{ PDI_SR_ENABLE_BUSY, 1, 1, 0 },  { PDI_SR_FRAME_ERR, 1, 5, 0 },
+	{ PDI_SR_OVERRUN_ERR, 1, 7, 0 },  { PDI_SR_PARITY_ERR, 1, 6, 0 },
+	{ PDI_SR_RXLVL, 7, 8, 0 },	  { PDI_SR_RX_BUSY, 1, 4, 0 },
+	{ PDI_SR_TXLVL, 7, 15, 0 },	  { PDI_SR_TX_BUSY, 1, 3, 0 },
+};
+
+static nt_fpga_field_init_t pdi_srr_fields[] = {
+	{ PDI_SRR_RST, 4, 0, 0 },
+};
+
+static nt_fpga_register_init_t pdi_registers[] = {
+	{ PDI_CR, 1, 6, REGISTER_TYPE_WO, 0, 6, pdi_cr_fields },
+	{ PDI_DRR, 4, 8, REGISTER_TYPE_RO, 0, 1, pdi_drr_fields },
+	{ PDI_DTR, 3, 8, REGISTER_TYPE_WO, 0, 1, pdi_dtr_fields },
+	{ PDI_PRE, 5, 7, REGISTER_TYPE_WO, 3, 1, pdi_pre_fields },
+	{ PDI_SR, 2, 22, REGISTER_TYPE_RO, 0, 10, pdi_sr_fields },
+	{ PDI_SRR, 0, 4, REGISTER_TYPE_WO, 0, 1, pdi_srr_fields },
+};
+
+static nt_fpga_field_init_t ptp1588_conf_fields[] = {
+	{ PTP1588_CONF_MII_RX_TX_LOOP, 1, 0, 0 },
+	{ PTP1588_CONF_MII_TX_RX_LOOP, 1, 1, 0 },
+	{ PTP1588_CONF_PHY_RST1, 1, 10, 1 },
+	{ PTP1588_CONF_PHY_RST2, 1, 11, 1 },
+	{ PTP1588_CONF_PTP_CTRL_LOCAL, 1, 24, 0 },
+	{ PTP1588_CONF_PTP_RX_CTRL, 2, 19, 0 },
+	{ PTP1588_CONF_PTP_TX_CTRL, 2, 21, 0 },
+	{ PTP1588_CONF_PTP_TX_CTRL_OS, 1, 23, 0 },
+	{ PTP1588_CONF_RX_IGNORE_DEST_ADDR, 1, 25, 0 },
+	{ PTP1588_CONF_TG_CMD, 2, 13, 0 },
+	{ PTP1588_CONF_TG_MODE, 1, 12, 0 },
+	{ PTP1588_CONF_TSM_MI_ACK, 1, 16, 0 },
+	{ PTP1588_CONF_TSM_MI_BUSY, 1, 15, 0 },
+	{ PTP1588_CONF_TSM_MI_ENA, 1, 18, 0 },
+	{ PTP1588_CONF_TSM_MI_REQ, 1, 17, 0 },
+	{ PTP1588_CONF_TX_IFG, 8, 2, 0 },
+	{ PTP1588_CONF_TX_IGNORE_DEST_ADDR, 1, 26, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_gp_data_fields[] = {
+	{ PTP1588_GP_DATA_GPIO, 9, 1, 0 },
+	{ PTP1588_GP_DATA_PWRDOWN_INTN, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_gp_data_lh_fields[] = {
+	{ PTP1588_GP_DATA_LH_GPIO, 9, 1, 0 },
+	{ PTP1588_GP_DATA_LH_PWRDOWN_INTN, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_gp_data_ll_fields[] = {
+	{ PTP1588_GP_DATA_LL_GPIO, 9, 1, 511 },
+	{ PTP1588_GP_DATA_LL_PWRDOWN_INTN, 1, 0, 1 },
+};
+
+static nt_fpga_field_init_t ptp1588_gp_oe_fields[] = {
+	{ PTP1588_GP_OE_GPIO, 9, 1, 0 },
+	{ PTP1588_GP_OE_PWRDOWN_INTN, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_mac_inband_stat_fields[] = {
+	{ PTP1588_MAC_INBAND_STAT_DUPLEX, 1, 3, 0x0000 },
+	{ PTP1588_MAC_INBAND_STAT_LINK, 1, 0, 0x0000 },
+	{ PTP1588_MAC_INBAND_STAT_SPEED, 2, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_mac_mi_conf_fields[] = {
+	{ PTP1588_MAC_MI_CONF_ACCESS_TYPE, 1, 16, 0 },
+	{ PTP1588_MAC_MI_CONF_ADDRESS, 16, 0, 0 },
+	{ PTP1588_MAC_MI_CONF_RDY, 1, 17, 1 },
+};
+
+static nt_fpga_field_init_t ptp1588_mac_mi_data_fields[] = {
+	{ PTP1588_MAC_MI_DATA_DATA, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_rx_host_adr_lsb_fields[] = {
+	{ PTP1588_RX_HOST_ADR_LSB_LSB, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_rx_host_adr_msb_fields[] = {
+	{ PTP1588_RX_HOST_ADR_MSB_MSB, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_rx_host_conf_fields[] = {
+	{ PTP1588_RX_HOST_CONF_ENA, 1, 11, 0 },
+	{ PTP1588_RX_HOST_CONF_RDPTR, 11, 0, 0 },
+	{ PTP1588_RX_HOST_CONF_REDUCED, 1, 12, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_stat_fields[] = {
+	{ PTP1588_STAT_DATA, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_stat_conf_fields[] = {
+	{ PTP1588_STAT_CONF_INDEX, 5, 0, 0 },
+	{ PTP1588_STAT_CONF_LOCK, 1, 5, 0 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_first_dat_fields[] = {
+	{ PTP1588_TX_FIRST_DAT_DAT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_last1_dat_fields[] = {
+	{ PTP1588_TX_LAST1_DAT_DAT, 8, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_last2_dat_fields[] = {
+	{ PTP1588_TX_LAST2_DAT_DAT, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_last3_dat_fields[] = {
+	{ PTP1588_TX_LAST3_DAT_DAT, 24, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_last4_dat_fields[] = {
+	{ PTP1588_TX_LAST4_DAT_DAT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_mid_dat_fields[] = {
+	{ PTP1588_TX_MID_DAT_DAT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_packet_state_fields[] = {
+	{ PTP1588_TX_PACKET_STATE_MSG_TYPE, 4, 16, 0x0000 },
+	{ PTP1588_TX_PACKET_STATE_PCK_TYPE, 3, 20, 0x0000 },
+	{ PTP1588_TX_PACKET_STATE_SEQ_ID, 16, 0, 0x0000 },
+	{ PTP1588_TX_PACKET_STATE_TEST_MARGIN, 7, 23, 0x0000 },
+	{ PTP1588_TX_PACKET_STATE_VALID, 1, 30, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_status_fields[] = {
+	{ PTP1588_TX_STATUS_DB_ERR, 1, 10, 1 },
+	{ PTP1588_TX_STATUS_DB_FULL, 1, 9, 1 },
+	{ PTP1588_TX_STATUS_FIFO_STATUS, 9, 0, 0 },
+	{ PTP1588_TX_STATUS_RDY, 1, 11, 1 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_timestamp_ns_fields[] = {
+	{ PTP1588_TX_TIMESTAMP_NS_TIMESTAMP, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t ptp1588_tx_timestamp_sec_fields[] = {
+	{ PTP1588_TX_TIMESTAMP_SEC_TIMESTAMP, 32, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t ptp1588_registers[] = {
+	{	PTP1588_CONF, 0, 27, REGISTER_TYPE_MIXED, 3072, 17,
+		ptp1588_conf_fields
+	},
+	{	PTP1588_GP_DATA, 20, 10, REGISTER_TYPE_RW, 0, 2,
+		ptp1588_gp_data_fields
+	},
+	{	PTP1588_GP_DATA_LH, 22, 10, REGISTER_TYPE_RO, 0, 2,
+		ptp1588_gp_data_lh_fields
+	},
+	{	PTP1588_GP_DATA_LL, 21, 10, REGISTER_TYPE_RO, 1023, 2,
+		ptp1588_gp_data_ll_fields
+	},
+	{ PTP1588_GP_OE, 19, 10, REGISTER_TYPE_WO, 0, 2, ptp1588_gp_oe_fields },
+	{	PTP1588_MAC_INBAND_STAT, 3, 4, REGISTER_TYPE_RO, 0, 3,
+		ptp1588_mac_inband_stat_fields
+	},
+	{	PTP1588_MAC_MI_CONF, 17, 18, REGISTER_TYPE_MIXED, 131072, 3,
+		ptp1588_mac_mi_conf_fields
+	},
+	{	PTP1588_MAC_MI_DATA, 18, 32, REGISTER_TYPE_RW, 0, 1,
+		ptp1588_mac_mi_data_fields
+	},
+	{	PTP1588_RX_HOST_ADR_LSB, 8, 32, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_rx_host_adr_lsb_fields
+	},
+	{	PTP1588_RX_HOST_ADR_MSB, 9, 32, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_rx_host_adr_msb_fields
+	},
+	{	PTP1588_RX_HOST_CONF, 7, 13, REGISTER_TYPE_RW, 0, 3,
+		ptp1588_rx_host_conf_fields
+	},
+	{ PTP1588_STAT, 6, 32, REGISTER_TYPE_RO, 0, 1, ptp1588_stat_fields },
+	{	PTP1588_STAT_CONF, 5, 6, REGISTER_TYPE_WO, 0, 2,
+		ptp1588_stat_conf_fields
+	},
+	{	PTP1588_TX_FIRST_DAT, 10, 32, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_tx_first_dat_fields
+	},
+	{	PTP1588_TX_LAST1_DAT, 12, 8, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_tx_last1_dat_fields
+	},
+	{	PTP1588_TX_LAST2_DAT, 13, 16, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_tx_last2_dat_fields
+	},
+	{	PTP1588_TX_LAST3_DAT, 14, 24, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_tx_last3_dat_fields
+	},
+	{	PTP1588_TX_LAST4_DAT, 15, 32, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_tx_last4_dat_fields
+	},
+	{	PTP1588_TX_MID_DAT, 11, 32, REGISTER_TYPE_WO, 0, 1,
+		ptp1588_tx_mid_dat_fields
+	},
+	{	PTP1588_TX_PACKET_STATE, 4, 31, REGISTER_TYPE_RO, 0, 5,
+		ptp1588_tx_packet_state_fields
+	},
+	{	PTP1588_TX_STATUS, 16, 12, REGISTER_TYPE_RO, 3584, 4,
+		ptp1588_tx_status_fields
+	},
+	{	PTP1588_TX_TIMESTAMP_NS, 2, 32, REGISTER_TYPE_RO, 0, 1,
+		ptp1588_tx_timestamp_ns_fields
+	},
+	{	PTP1588_TX_TIMESTAMP_SEC, 1, 32, REGISTER_TYPE_RO, 0, 1,
+		ptp1588_tx_timestamp_sec_fields
+	},
+};
+
+static nt_fpga_field_init_t qsl_qen_ctrl_fields[] = {
+	{ QSL_QEN_CTRL_ADR, 5, 0, 0x0000 },
+	{ QSL_QEN_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t qsl_qen_data_fields[] = {
+	{ QSL_QEN_DATA_EN, 4, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t qsl_qst_ctrl_fields[] = {
+	{ QSL_QST_CTRL_ADR, 12, 0, 0x0000 },
+	{ QSL_QST_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t qsl_qst_data_fields[] = {
+	{ QSL_QST_DATA_LRE, 1, 9, 0x0000 },
+	{ QSL_QST_DATA_QEN, 1, 7, 0x0000 },
+	{ QSL_QST_DATA_QUEUE, 7, 0, 0x0000 },
+	{ QSL_QST_DATA_TCI, 16, 10, 0x0000 },
+	{ QSL_QST_DATA_TX_PORT, 1, 8, 0x0000 },
+	{ QSL_QST_DATA_VEN, 1, 26, 0x0000 },
+};
+
+static nt_fpga_field_init_t qsl_rcp_ctrl_fields[] = {
+	{ QSL_RCP_CTRL_ADR, 5, 0, 0x0000 },
+	{ QSL_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t qsl_rcp_data_fields[] = {
+	{ QSL_RCP_DATA_DISCARD, 1, 0, 0x0000 },
+	{ QSL_RCP_DATA_DROP, 2, 1, 0x0000 },
+	{ QSL_RCP_DATA_LR, 2, 51, 0x0000 },
+	{ QSL_RCP_DATA_TBL_HI, 12, 15, 0x0000 },
+	{ QSL_RCP_DATA_TBL_IDX, 12, 27, 0x0000 },
+	{ QSL_RCP_DATA_TBL_LO, 12, 3, 0x0000 },
+	{ QSL_RCP_DATA_TBL_MSK, 12, 39, 0x0000 },
+	{ QSL_RCP_DATA_TSA, 1, 53, 0x0000 },
+	{ QSL_RCP_DATA_VLI, 2, 54, 0x0000 },
+};
+
+static nt_fpga_field_init_t qsl_unmq_ctrl_fields[] = {
+	{ QSL_UNMQ_CTRL_ADR, 1, 0, 0x0000 },
+	{ QSL_UNMQ_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t qsl_unmq_data_fields[] = {
+	{ QSL_UNMQ_DATA_DEST_QUEUE, 7, 0, 0x0000 },
+	{ QSL_UNMQ_DATA_EN, 1, 7, 0x0000 },
+};
+
+static nt_fpga_register_init_t qsl_registers[] = {
+	{ QSL_QEN_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2, qsl_qen_ctrl_fields },
+	{ QSL_QEN_DATA, 5, 4, REGISTER_TYPE_WO, 0, 1, qsl_qen_data_fields },
+	{ QSL_QST_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, qsl_qst_ctrl_fields },
+	{ QSL_QST_DATA, 3, 27, REGISTER_TYPE_WO, 0, 6, qsl_qst_data_fields },
+	{ QSL_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, qsl_rcp_ctrl_fields },
+	{ QSL_RCP_DATA, 1, 56, REGISTER_TYPE_WO, 0, 9, qsl_rcp_data_fields },
+	{ QSL_UNMQ_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2, qsl_unmq_ctrl_fields },
+	{ QSL_UNMQ_DATA, 7, 8, REGISTER_TYPE_WO, 0, 2, qsl_unmq_data_fields },
+};
+
+static nt_fpga_field_init_t qspi_cr_fields[] = {
+	{ QSPI_CR_CPHA, 1, 4, 0 },  { QSPI_CR_CPOL, 1, 3, 0 },
+	{ QSPI_CR_LOOP, 1, 0, 0 },  { QSPI_CR_LSBF, 1, 9, 0 },
+	{ QSPI_CR_MSSAE, 1, 7, 1 }, { QSPI_CR_MST, 1, 2, 0 },
+	{ QSPI_CR_MTI, 1, 8, 1 },   { QSPI_CR_RXFIFO_RST, 1, 6, 0 },
+	{ QSPI_CR_SPE, 1, 1, 0 },   { QSPI_CR_TXFIFO_RST, 1, 5, 0 },
+};
+
+static nt_fpga_field_init_t qspi_dgie_fields[] = {
+	{ QSPI_DGIE_GIE, 1, 31, 0 },
+};
+
+static nt_fpga_field_init_t qspi_drr_fields[] = {
+	{ QSPI_DRR_DATA_VAL, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t qspi_dtr_fields[] = {
+	{ QSPI_DTR_DATA_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t qspi_ier_fields[] = {
+	{ QSPI_IER_CMD_ERR, 1, 13, 0 }, { QSPI_IER_CPOL_CPHA_ERR, 1, 9, 0 },
+	{ QSPI_IER_DRR_FULL, 1, 4, 0 }, { QSPI_IER_DRR_NEMPTY, 1, 8, 0 },
+	{ QSPI_IER_DRR_OR, 1, 5, 0 },	{ QSPI_IER_DTR_EMPTY, 1, 2, 0 },
+	{ QSPI_IER_DTR_UR, 1, 3, 0 },	{ QSPI_IER_LOOP_ERR, 1, 12, 0 },
+	{ QSPI_IER_MODF, 1, 0, 0 },	{ QSPI_IER_MSB_ERR, 1, 11, 0 },
+	{ QSPI_IER_SLV_ERR, 1, 10, 0 }, { QSPI_IER_SLV_MODF, 1, 1, 0 },
+	{ QSPI_IER_SLV_MS, 1, 7, 0 },	{ QSPI_IER_TXFIFO_HEMPTY, 1, 6, 0 },
+};
+
+static nt_fpga_field_init_t qspi_isr_fields[] = {
+	{ QSPI_ISR_CMD_ERR, 1, 13, 0 }, { QSPI_ISR_CPOL_CPHA_ERR, 1, 9, 0 },
+	{ QSPI_ISR_DRR_FULL, 1, 4, 0 }, { QSPI_ISR_DRR_NEMPTY, 1, 8, 0 },
+	{ QSPI_ISR_DRR_OR, 1, 5, 0 },	{ QSPI_ISR_DTR_EMPTY, 1, 2, 0 },
+	{ QSPI_ISR_DTR_UR, 1, 3, 0 },	{ QSPI_ISR_LOOP_ERR, 1, 12, 0 },
+	{ QSPI_ISR_MODF, 1, 0, 0 },	{ QSPI_ISR_MSB_ERR, 1, 11, 0 },
+	{ QSPI_ISR_SLV_ERR, 1, 10, 0 }, { QSPI_ISR_SLV_MODF, 1, 1, 0 },
+	{ QSPI_ISR_SLV_MS, 1, 7, 0 },	{ QSPI_ISR_TXFIFO_HEMPTY, 1, 6, 0 },
+};
+
+static nt_fpga_field_init_t qspi_rx_fifo_ocy_fields[] = {
+	{ QSPI_RX_FIFO_OCY_OCY_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t qspi_sr_fields[] = {
+	{ QSPI_SR_CMD_ERR, 1, 10, 0 }, { QSPI_SR_CPOL_CPHA_ERR, 1, 6, 0 },
+	{ QSPI_SR_LOOP_ERR, 1, 9, 0 }, { QSPI_SR_MODF, 1, 4, 0 },
+	{ QSPI_SR_MSB_ERR, 1, 8, 0 },  { QSPI_SR_RXEMPTY, 1, 0, 1 },
+	{ QSPI_SR_RXFULL, 1, 1, 0 },   { QSPI_SR_SLVMS, 1, 5, 1 },
+	{ QSPI_SR_SLV_ERR, 1, 7, 0 },  { QSPI_SR_TXEMPTY, 1, 2, 1 },
+	{ QSPI_SR_TXFULL, 1, 3, 0 },
+};
+
+static nt_fpga_field_init_t qspi_srr_fields[] = {
+	{ QSPI_SRR_RST, 4, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t qspi_ssr_fields[] = {
+	{ QSPI_SSR_SEL_SLV, 32, 0, 4294967295 },
+};
+
+static nt_fpga_field_init_t qspi_tx_fifo_ocy_fields[] = {
+	{ QSPI_TX_FIFO_OCY_OCY_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_register_init_t qspi_registers[] = {
+	{ QSPI_CR, 24, 10, REGISTER_TYPE_RW, 384, 10, qspi_cr_fields },
+	{ QSPI_DGIE, 7, 32, REGISTER_TYPE_RW, 0, 1, qspi_dgie_fields },
+	{ QSPI_DRR, 27, 32, REGISTER_TYPE_RO, 0, 1, qspi_drr_fields },
+	{ QSPI_DTR, 26, 32, REGISTER_TYPE_WO, 0, 1, qspi_dtr_fields },
+	{ QSPI_IER, 10, 14, REGISTER_TYPE_RW, 0, 14, qspi_ier_fields },
+	{ QSPI_ISR, 8, 14, REGISTER_TYPE_RW, 0, 14, qspi_isr_fields },
+	{	QSPI_RX_FIFO_OCY, 30, 32, REGISTER_TYPE_RO, 0, 1,
+		qspi_rx_fifo_ocy_fields
+	},
+	{ QSPI_SR, 25, 11, REGISTER_TYPE_RO, 37, 11, qspi_sr_fields },
+	{ QSPI_SRR, 16, 4, REGISTER_TYPE_WO, 0, 1, qspi_srr_fields },
+	{ QSPI_SSR, 28, 32, REGISTER_TYPE_RW, 4294967295, 1, qspi_ssr_fields },
+	{	QSPI_TX_FIFO_OCY, 29, 32, REGISTER_TYPE_RO, 0, 1,
+		qspi_tx_fifo_ocy_fields
+	},
+};
+
+static nt_fpga_field_init_t rac_dbg_ctrl_fields[] = {
+	{ RAC_DBG_CTRL_C, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t rac_dbg_data_fields[] = {
+	{ RAC_DBG_DATA_D, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t rac_rab_buf_free_fields[] = {
+	{ RAC_RAB_BUF_FREE_IB_FREE, 9, 0, 511 },
+	{ RAC_RAB_BUF_FREE_IB_OVF, 1, 12, 0 },
+	{ RAC_RAB_BUF_FREE_OB_FREE, 9, 16, 511 },
+	{ RAC_RAB_BUF_FREE_OB_OVF, 1, 28, 0 },
+	{ RAC_RAB_BUF_FREE_TIMEOUT, 1, 31, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_buf_used_fields[] = {
+	{ RAC_RAB_BUF_USED_FLUSH, 1, 31, 0 },
+	{ RAC_RAB_BUF_USED_IB_USED, 9, 0, 0 },
+	{ RAC_RAB_BUF_USED_OB_USED, 9, 16, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_dma_ib_hi_fields[] = {
+	{ RAC_RAB_DMA_IB_HI_PHYADDR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_dma_ib_lo_fields[] = {
+	{ RAC_RAB_DMA_IB_LO_PHYADDR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_dma_ib_rd_fields[] = {
+	{ RAC_RAB_DMA_IB_RD_PTR, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_dma_ib_wr_fields[] = {
+	{ RAC_RAB_DMA_IB_WR_PTR, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_dma_ob_hi_fields[] = {
+	{ RAC_RAB_DMA_OB_HI_PHYADDR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_dma_ob_lo_fields[] = {
+	{ RAC_RAB_DMA_OB_LO_PHYADDR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_dma_ob_wr_fields[] = {
+	{ RAC_RAB_DMA_OB_WR_PTR, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t rac_rab_ib_data_fields[] = {
+	{ RAC_RAB_IB_DATA_D, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t rac_rab_init_fields[] = {
+	{ RAC_RAB_INIT_RAB, 3, 0, 7 },
+};
+
+static nt_fpga_field_init_t rac_rab_ob_data_fields[] = {
+	{ RAC_RAB_OB_DATA_D, 32, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t rac_registers[] = {
+	{ RAC_DBG_CTRL, 4200, 32, REGISTER_TYPE_RW, 0, 1, rac_dbg_ctrl_fields },
+	{ RAC_DBG_DATA, 4208, 32, REGISTER_TYPE_RW, 0, 1, rac_dbg_data_fields },
+	{	RAC_RAB_BUF_FREE, 4176, 32, REGISTER_TYPE_MIXED, 33489407, 5,
+		rac_rab_buf_free_fields
+	},
+	{	RAC_RAB_BUF_USED, 4184, 32, REGISTER_TYPE_MIXED, 0, 3,
+		rac_rab_buf_used_fields
+	},
+	{	RAC_RAB_DMA_IB_HI, 4360, 32, REGISTER_TYPE_WO, 0, 1,
+		rac_rab_dma_ib_hi_fields
+	},
+	{	RAC_RAB_DMA_IB_LO, 4352, 32, REGISTER_TYPE_WO, 0, 1,
+		rac_rab_dma_ib_lo_fields
+	},
+	{	RAC_RAB_DMA_IB_RD, 4424, 16, REGISTER_TYPE_RO, 0, 1,
+		rac_rab_dma_ib_rd_fields
+	},
+	{	RAC_RAB_DMA_IB_WR, 4416, 16, REGISTER_TYPE_WO, 0, 1,
+		rac_rab_dma_ib_wr_fields
+	},
+	{	RAC_RAB_DMA_OB_HI, 4376, 32, REGISTER_TYPE_WO, 0, 1,
+		rac_rab_dma_ob_hi_fields
+	},
+	{	RAC_RAB_DMA_OB_LO, 4368, 32, REGISTER_TYPE_WO, 0, 1,
+		rac_rab_dma_ob_lo_fields
+	},
+	{	RAC_RAB_DMA_OB_WR, 4480, 16, REGISTER_TYPE_RO, 0, 1,
+		rac_rab_dma_ob_wr_fields
+	},
+	{	RAC_RAB_IB_DATA, 4160, 32, REGISTER_TYPE_WO, 0, 1,
+		rac_rab_ib_data_fields
+	},
+	{ RAC_RAB_INIT, 4192, 3, REGISTER_TYPE_RW, 7, 1, rac_rab_init_fields },
+	{	RAC_RAB_OB_DATA, 4168, 32, REGISTER_TYPE_RC1, 0, 1,
+		rac_rab_ob_data_fields
+	},
+};
+
+static nt_fpga_field_init_t rfd_ctrl_fields[] = {
+	{ RFD_CTRL_CFP, 1, 2, 1 },
+	{ RFD_CTRL_ISL, 1, 0, 1 },
+	{ RFD_CTRL_PWMCW, 1, 1, 1 },
+};
+
+static nt_fpga_field_init_t rfd_max_frame_size_fields[] = {
+	{ RFD_MAX_FRAME_SIZE_MAX, 14, 0, 9018 },
+};
+
+static nt_fpga_field_init_t rfd_tnl_vlan_fields[] = {
+	{ RFD_TNL_VLAN_TPID0, 16, 0, 33024 },
+	{ RFD_TNL_VLAN_TPID1, 16, 16, 33024 },
+};
+
+static nt_fpga_field_init_t rfd_vlan_fields[] = {
+	{ RFD_VLAN_TPID0, 16, 0, 33024 },
+	{ RFD_VLAN_TPID1, 16, 16, 33024 },
+};
+
+static nt_fpga_field_init_t rfd_vxlan_fields[] = {
+	{ RFD_VXLAN_DP0, 16, 0, 4789 },
+	{ RFD_VXLAN_DP1, 16, 16, 4789 },
+};
+
+static nt_fpga_register_init_t rfd_registers[] = {
+	{ RFD_CTRL, 0, 3, REGISTER_TYPE_WO, 7, 3, rfd_ctrl_fields },
+	{	RFD_MAX_FRAME_SIZE, 1, 14, REGISTER_TYPE_WO, 9018, 1,
+		rfd_max_frame_size_fields
+	},
+	{	RFD_TNL_VLAN, 3, 32, REGISTER_TYPE_WO, 2164293888, 2,
+		rfd_tnl_vlan_fields
+	},
+	{ RFD_VLAN, 2, 32, REGISTER_TYPE_WO, 2164293888, 2, rfd_vlan_fields },
+	{ RFD_VXLAN, 4, 32, REGISTER_TYPE_WO, 313856693, 2, rfd_vxlan_fields },
+};
+
+static nt_fpga_field_init_t rmc_ctrl_fields[] = {
+	{ RMC_CTRL_BLOCK_KEEPA, 1, 1, 1 },
+	{ RMC_CTRL_BLOCK_MAC_PORT, 2, 8, 3 },
+	{ RMC_CTRL_BLOCK_RPP_SLICE, 8, 10, 0 },
+	{ RMC_CTRL_BLOCK_STATT, 1, 0, 1 },
+	{ RMC_CTRL_LAG_PHY_ODD_EVEN, 1, 24, 0 },
+};
+
+static nt_fpga_field_init_t rmc_dbg_fields[] = {
+	{ RMC_DBG_MERGE, 31, 0, 0 },
+};
+
+static nt_fpga_field_init_t rmc_mac_if_fields[] = {
+	{ RMC_MAC_IF_ERR, 31, 0, 0 },
+};
+
+static nt_fpga_field_init_t rmc_status_fields[] = {
+	{ RMC_STATUS_DESCR_FIFO_OF, 1, 16, 0 },
+	{ RMC_STATUS_SF_RAM_OF, 1, 0, 0 },
+};
+
+static nt_fpga_register_init_t rmc_registers[] = {
+	{ RMC_CTRL, 0, 25, REGISTER_TYPE_RW, 771, 5, rmc_ctrl_fields },
+	{ RMC_DBG, 2, 31, REGISTER_TYPE_RO, 0, 1, rmc_dbg_fields },
+	{ RMC_MAC_IF, 3, 31, REGISTER_TYPE_RO, 0, 1, rmc_mac_if_fields },
+	{ RMC_STATUS, 1, 17, REGISTER_TYPE_RO, 0, 2, rmc_status_fields },
+};
+
+static nt_fpga_field_init_t rpl_ext_ctrl_fields[] = {
+	{ RPL_EXT_CTRL_ADR, 10, 0, 0x0000 },
+	{ RPL_EXT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpl_ext_data_fields[] = {
+	{ RPL_EXT_DATA_RPL_PTR, 12, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpl_rcp_ctrl_fields[] = {
+	{ RPL_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ RPL_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpl_rcp_data_fields[] = {
+	{ RPL_RCP_DATA_DYN, 5, 0, 0x0000 },
+	{ RPL_RCP_DATA_EXT_PRIO, 1, 35, 0x0000 },
+	{ RPL_RCP_DATA_LEN, 8, 15, 0x0000 },
+	{ RPL_RCP_DATA_OFS, 10, 5, 0x0000 },
+	{ RPL_RCP_DATA_RPL_PTR, 12, 23, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpl_rpl_ctrl_fields[] = {
+	{ RPL_RPL_CTRL_ADR, 12, 0, 0x0000 },
+	{ RPL_RPL_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpl_rpl_data_fields[] = {
+	{ RPL_RPL_DATA_VALUE, 128, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t rpl_registers[] = {
+	{ RPL_EXT_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, rpl_ext_ctrl_fields },
+	{ RPL_EXT_DATA, 3, 12, REGISTER_TYPE_WO, 0, 1, rpl_ext_data_fields },
+	{ RPL_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, rpl_rcp_ctrl_fields },
+	{ RPL_RCP_DATA, 1, 36, REGISTER_TYPE_WO, 0, 5, rpl_rcp_data_fields },
+	{ RPL_RPL_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2, rpl_rpl_ctrl_fields },
+	{ RPL_RPL_DATA, 5, 128, REGISTER_TYPE_WO, 0, 1, rpl_rpl_data_fields },
+};
+
+static nt_fpga_field_init_t rpp_lr_ifr_rcp_ctrl_fields[] = {
+	{ RPP_LR_IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ RPP_LR_IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpp_lr_ifr_rcp_data_fields[] = {
+	{ RPP_LR_IFR_RCP_DATA_EN, 1, 0, 0x0000 },
+	{ RPP_LR_IFR_RCP_DATA_MTU, 14, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpp_lr_rcp_ctrl_fields[] = {
+	{ RPP_LR_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ RPP_LR_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t rpp_lr_rcp_data_fields[] = {
+	{ RPP_LR_RCP_DATA_EXP, 14, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t rpp_lr_registers[] = {
+	{	RPP_LR_IFR_RCP_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2,
+		rpp_lr_ifr_rcp_ctrl_fields
+	},
+	{	RPP_LR_IFR_RCP_DATA, 3, 15, REGISTER_TYPE_WO, 0, 2,
+		rpp_lr_ifr_rcp_data_fields
+	},
+	{	RPP_LR_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2,
+		rpp_lr_rcp_ctrl_fields
+	},
+	{	RPP_LR_RCP_DATA, 1, 14, REGISTER_TYPE_WO, 0, 1,
+		rpp_lr_rcp_data_fields
+	},
+};
+
+static nt_fpga_field_init_t rst9563_ctrl_fields[] = {
+	{ RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 },
+	{ RST9563_CTRL_TS_CLKSEL, 1, 1, 1 },
+	{ RST9563_CTRL_TS_CLKSEL_OVERRIDE, 1, 0, 1 },
+};
+
+static nt_fpga_field_init_t rst9563_power_fields[] = {
+	{ RST9563_POWER_PU_NSEB, 1, 1, 0 },
+	{ RST9563_POWER_PU_PHY, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t rst9563_rst_fields[] = {
+	{ RST9563_RST_CORE_MMCM, 1, 15, 0 }, { RST9563_RST_DDR4, 3, 3, 7 },
+	{ RST9563_RST_MAC_RX, 2, 9, 3 },     { RST9563_RST_PERIPH, 1, 13, 0 },
+	{ RST9563_RST_PHY, 2, 7, 3 },	     { RST9563_RST_PTP, 1, 11, 1 },
+	{ RST9563_RST_PTP_MMCM, 1, 16, 0 },  { RST9563_RST_RPP, 1, 2, 1 },
+	{ RST9563_RST_SDC, 1, 6, 1 },	     { RST9563_RST_SYS, 1, 0, 1 },
+	{ RST9563_RST_SYS_MMCM, 1, 14, 0 },  { RST9563_RST_TMC, 1, 1, 1 },
+	{ RST9563_RST_TS, 1, 12, 1 },	     { RST9563_RST_TS_MMCM, 1, 17, 0 },
+};
+
+static nt_fpga_field_init_t rst9563_stat_fields[] = {
+	{ RST9563_STAT_CORE_MMCM_LOCKED, 1, 5, 0x0000 },
+	{ RST9563_STAT_DDR4_MMCM_LOCKED, 1, 2, 0x0000 },
+	{ RST9563_STAT_DDR4_PLL_LOCKED, 1, 3, 0x0000 },
+	{ RST9563_STAT_PTP_MMCM_LOCKED, 1, 0, 0x0000 },
+	{ RST9563_STAT_SYS_MMCM_LOCKED, 1, 4, 0x0000 },
+	{ RST9563_STAT_TS_MMCM_LOCKED, 1, 1, 0x0000 },
+};
+
+static nt_fpga_field_init_t rst9563_sticky_fields[] = {
+	{ RST9563_STICKY_CORE_MMCM_UNLOCKED, 1, 5, 0x0000 },
+	{ RST9563_STICKY_DDR4_MMCM_UNLOCKED, 1, 2, 0x0000 },
+	{ RST9563_STICKY_DDR4_PLL_UNLOCKED, 1, 3, 0x0000 },
+	{ RST9563_STICKY_PTP_MMCM_UNLOCKED, 1, 0, 0x0000 },
+	{ RST9563_STICKY_SYS_MMCM_UNLOCKED, 1, 4, 0x0000 },
+	{ RST9563_STICKY_TS_MMCM_UNLOCKED, 1, 1, 0x0000 },
+};
+
+static nt_fpga_register_init_t rst9563_registers[] = {
+	{ RST9563_CTRL, 1, 3, REGISTER_TYPE_RW, 7, 3, rst9563_ctrl_fields },
+	{ RST9563_POWER, 4, 2, REGISTER_TYPE_RW, 0, 2, rst9563_power_fields },
+	{ RST9563_RST, 0, 18, REGISTER_TYPE_RW, 8191, 14, rst9563_rst_fields },
+	{ RST9563_STAT, 2, 6, REGISTER_TYPE_RO, 0, 6, rst9563_stat_fields },
+	{	RST9563_STICKY, 3, 6, REGISTER_TYPE_RC1, 0, 6,
+		rst9563_sticky_fields
+	},
+};
+
+static nt_fpga_field_init_t slc_rcp_ctrl_fields[] = {
+	{ SLC_RCP_CTRL_ADR, 6, 0, 0x0000 },
+	{ SLC_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nt_fpga_field_init_t slc_rcp_data_fields[] = {
+	{ SLC_RCP_DATA_PCAP, 1, 35, 0x0000 },
+	{ SLC_RCP_DATA_TAIL_DYN, 5, 15, 0x0000 },
+	{ SLC_RCP_DATA_TAIL_OFS, 15, 20, 0x0000 },
+	{ SLC_RCP_DATA_TAIL_SLC_EN, 1, 14, 0x0000 },
+};
+
+static nt_fpga_register_init_t slc_registers[] = {
+	{ SLC_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, slc_rcp_ctrl_fields },
+	{ SLC_RCP_DATA, 1, 36, REGISTER_TYPE_WO, 0, 4, slc_rcp_data_fields },
+};
+
+static nt_fpga_field_init_t spim_cfg_fields[] = {
+	{ SPIM_CFG_PRE, 3, 0, 5 },
+};
+
+static nt_fpga_field_init_t spim_cr_fields[] = {
+	{ SPIM_CR_EN, 1, 1, 0 },
+	{ SPIM_CR_LOOP, 1, 0, 0 },
+	{ SPIM_CR_RXRST, 1, 3, 0 },
+	{ SPIM_CR_TXRST, 1, 2, 0 },
+};
+
+static nt_fpga_field_init_t spim_drr_fields[] = {
+	{ SPIM_DRR_DRR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t spim_dtr_fields[] = {
+	{ SPIM_DTR_DTR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t spim_sr_fields[] = {
+	{ SPIM_SR_DONE, 1, 0, 0 },    { SPIM_SR_RXEMPTY, 1, 2, 1 },
+	{ SPIM_SR_RXFULL, 1, 4, 0 },  { SPIM_SR_RXLVL, 8, 16, 0 },
+	{ SPIM_SR_TXEMPTY, 1, 1, 1 }, { SPIM_SR_TXFULL, 1, 3, 0 },
+	{ SPIM_SR_TXLVL, 8, 8, 0 },
+};
+
+static nt_fpga_field_init_t spim_srr_fields[] = {
+	{ SPIM_SRR_RST, 4, 0, 0 },
+};
+
+static nt_fpga_register_init_t spim_registers[] = {
+	{ SPIM_CFG, 5, 3, REGISTER_TYPE_WO, 5, 1, spim_cfg_fields },
+	{ SPIM_CR, 1, 4, REGISTER_TYPE_WO, 0, 4, spim_cr_fields },
+	{ SPIM_DRR, 4, 32, REGISTER_TYPE_RO, 0, 1, spim_drr_fields },
+	{ SPIM_DTR, 3, 32, REGISTER_TYPE_WO, 0, 1, spim_dtr_fields },
+	{ SPIM_SR, 2, 24, REGISTER_TYPE_RO, 6, 7, spim_sr_fields },
+	{ SPIM_SRR, 0, 4, REGISTER_TYPE_WO, 0, 1, spim_srr_fields },
+};
+
+static nt_fpga_field_init_t spis_cr_fields[] = {
+	{ SPIS_CR_DEBUG, 1, 4, 0 }, { SPIS_CR_EN, 1, 1, 0 },
+	{ SPIS_CR_LOOP, 1, 0, 0 },  { SPIS_CR_RXRST, 1, 3, 0 },
+	{ SPIS_CR_TXRST, 1, 2, 0 },
+};
+
+static nt_fpga_field_init_t spis_drr_fields[] = {
+	{ SPIS_DRR_DRR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t spis_dtr_fields[] = {
+	{ SPIS_DTR_DTR, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t spis_ram_ctrl_fields[] = {
+	{ SPIS_RAM_CTRL_ADR, 6, 0, 0 },
+	{ SPIS_RAM_CTRL_CNT, 6, 6, 0 },
+};
+
+static nt_fpga_field_init_t spis_ram_data_fields[] = {
+	{ SPIS_RAM_DATA_DATA, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t spis_sr_fields[] = {
+	{ SPIS_SR_DONE, 1, 0, 0 },	{ SPIS_SR_FRAME_ERR, 1, 24, 0 },
+	{ SPIS_SR_READ_ERR, 1, 25, 0 }, { SPIS_SR_RXEMPTY, 1, 2, 1 },
+	{ SPIS_SR_RXFULL, 1, 4, 0 },	{ SPIS_SR_RXLVL, 8, 16, 0 },
+	{ SPIS_SR_TXEMPTY, 1, 1, 1 },	{ SPIS_SR_TXFULL, 1, 3, 0 },
+	{ SPIS_SR_TXLVL, 8, 8, 0 },	{ SPIS_SR_WRITE_ERR, 1, 26, 0 },
+};
+
+static nt_fpga_field_init_t spis_srr_fields[] = {
+	{ SPIS_SRR_RST, 4, 0, 0 },
+};
+
+static nt_fpga_register_init_t spis_registers[] = {
+	{ SPIS_CR, 1, 5, REGISTER_TYPE_WO, 0, 5, spis_cr_fields },
+	{ SPIS_DRR, 4, 32, REGISTER_TYPE_RO, 0, 1, spis_drr_fields },
+	{ SPIS_DTR, 3, 32, REGISTER_TYPE_WO, 0, 1, spis_dtr_fields },
+	{ SPIS_RAM_CTRL, 5, 12, REGISTER_TYPE_RW, 0, 2, spis_ram_ctrl_fields },
+	{ SPIS_RAM_DATA, 6, 32, REGISTER_TYPE_RW, 0, 1, spis_ram_data_fields },
+	{ SPIS_SR, 2, 27, REGISTER_TYPE_RO, 6, 10, spis_sr_fields },
+	{ SPIS_SRR, 0, 4, REGISTER_TYPE_WO, 0, 1, spis_srr_fields },
+};
+
+static nt_fpga_field_init_t sta_byte_fields[] = {
+	{ STA_BYTE_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t sta_cfg_fields[] = {
+	{ STA_CFG_CNT_CLEAR, 1, 1, 0 },
+	{ STA_CFG_DMA_ENA, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t sta_cv_err_fields[] = {
+	{ STA_CV_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t sta_fcs_err_fields[] = {
+	{ STA_FCS_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t sta_host_adr_lsb_fields[] = {
+	{ STA_HOST_ADR_LSB_LSB, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t sta_host_adr_msb_fields[] = {
+	{ STA_HOST_ADR_MSB_MSB, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t sta_pckt_fields[] = {
+	{ STA_PCKT_CNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t sta_status_fields[] = {
+	{ STA_STATUS_STAT_TOGGLE_MISSED, 1, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t sta_registers[] = {
+	{ STA_BYTE, 4, 32, REGISTER_TYPE_RO, 0, 1, sta_byte_fields },
+	{ STA_CFG, 0, 2, REGISTER_TYPE_RW, 0, 2, sta_cfg_fields },
+	{ STA_CV_ERR, 5, 32, REGISTER_TYPE_RO, 0, 1, sta_cv_err_fields },
+	{ STA_FCS_ERR, 6, 32, REGISTER_TYPE_RO, 0, 1, sta_fcs_err_fields },
+	{	STA_HOST_ADR_LSB, 1, 32, REGISTER_TYPE_WO, 0, 1,
+		sta_host_adr_lsb_fields
+	},
+	{	STA_HOST_ADR_MSB, 2, 32, REGISTER_TYPE_WO, 0, 1,
+		sta_host_adr_msb_fields
+	},
+	{ STA_PCKT, 3, 32, REGISTER_TYPE_RO, 0, 1, sta_pckt_fields },
+	{ STA_STATUS, 7, 1, REGISTER_TYPE_RC1, 0, 1, sta_status_fields },
+};
+
+static nt_fpga_field_init_t tempmon_alarms_fields[] = {
+	{ TEMPMON_ALARMS_OT, 1, 1, 0x0000 },
+	{ TEMPMON_ALARMS_OT_OVERWR, 1, 2, 0 },
+	{ TEMPMON_ALARMS_OT_OVERWRVAL, 1, 3, 0 },
+	{ TEMPMON_ALARMS_TEMP, 1, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tempmon_stat_fields[] = {
+	{ TEMPMON_STAT_TEMP, 12, 0, 0x0000 },
+};
+
+static nt_fpga_register_init_t tempmon_registers[] = {
+	{	TEMPMON_ALARMS, 1, 4, REGISTER_TYPE_MIXED, 0, 4,
+		tempmon_alarms_fields
+	},
+	{ TEMPMON_STAT, 0, 12, REGISTER_TYPE_RO, 0, 1, tempmon_stat_fields },
+};
+
+static nt_fpga_field_init_t tint_ctrl_fields[] = {
+	{ TINT_CTRL_INTERVAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tint_status_fields[] = {
+	{ TINT_STATUS_DELAYED, 8, 8, 0 },
+	{ TINT_STATUS_SKIPPED, 8, 0, 0 },
+};
+
+static nt_fpga_register_init_t tint_registers[] = {
+	{ TINT_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 1, tint_ctrl_fields },
+	{ TINT_STATUS, 1, 16, REGISTER_TYPE_RC1, 0, 2, tint_status_fields },
+};
+
+static nt_fpga_field_init_t tmc_port_rpl_fields[] = {
+	{ TMC_PORT_RPL_P0, 1, 0, 0 },
+	{ TMC_PORT_RPL_P1, 1, 1, 1 },
+};
+
+static nt_fpga_register_init_t tmc_registers[] = {
+	{ TMC_PORT_RPL, 0, 2, REGISTER_TYPE_WO, 2, 2, tmc_port_rpl_fields },
+};
+
+static nt_fpga_field_init_t tsm_con0_config_fields[] = {
+	{ TSM_CON0_CONFIG_BLIND, 5, 8, 9 },
+	{ TSM_CON0_CONFIG_DC_SRC, 3, 5, 0 },
+	{ TSM_CON0_CONFIG_PORT, 3, 0, 0 },
+	{ TSM_CON0_CONFIG_PPSIN_2_5V, 1, 13, 0 },
+	{ TSM_CON0_CONFIG_SAMPLE_EDGE, 2, 3, 2 },
+};
+
+static nt_fpga_field_init_t tsm_con0_interface_fields[] = {
+	{ TSM_CON0_INTERFACE_EX_TERM, 2, 0, 3 },
+	{ TSM_CON0_INTERFACE_IN_REF_PWM, 8, 12, 128 },
+	{ TSM_CON0_INTERFACE_PWM_ENA, 1, 2, 0 },
+	{ TSM_CON0_INTERFACE_RESERVED, 1, 3, 0 },
+	{ TSM_CON0_INTERFACE_VTERM_PWM, 8, 4, 0 },
+};
+
+static nt_fpga_field_init_t tsm_con0_sample_hi_fields[] = {
+	{ TSM_CON0_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con0_sample_lo_fields[] = {
+	{ TSM_CON0_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con1_config_fields[] = {
+	{ TSM_CON1_CONFIG_BLIND, 5, 8, 9 },
+	{ TSM_CON1_CONFIG_DC_SRC, 3, 5, 0 },
+	{ TSM_CON1_CONFIG_PORT, 3, 0, 0 },
+	{ TSM_CON1_CONFIG_PPSIN_2_5V, 1, 13, 0 },
+	{ TSM_CON1_CONFIG_SAMPLE_EDGE, 2, 3, 2 },
+};
+
+static nt_fpga_field_init_t tsm_con1_sample_hi_fields[] = {
+	{ TSM_CON1_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con1_sample_lo_fields[] = {
+	{ TSM_CON1_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con2_config_fields[] = {
+	{ TSM_CON2_CONFIG_BLIND, 5, 8, 9 },
+	{ TSM_CON2_CONFIG_DC_SRC, 3, 5, 0 },
+	{ TSM_CON2_CONFIG_PORT, 3, 0, 0 },
+	{ TSM_CON2_CONFIG_PPSIN_2_5V, 1, 13, 0 },
+	{ TSM_CON2_CONFIG_SAMPLE_EDGE, 2, 3, 2 },
+};
+
+static nt_fpga_field_init_t tsm_con2_sample_hi_fields[] = {
+	{ TSM_CON2_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con2_sample_lo_fields[] = {
+	{ TSM_CON2_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con3_config_fields[] = {
+	{ TSM_CON3_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON3_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON3_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nt_fpga_field_init_t tsm_con3_sample_hi_fields[] = {
+	{ TSM_CON3_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con3_sample_lo_fields[] = {
+	{ TSM_CON3_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con4_config_fields[] = {
+	{ TSM_CON4_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON4_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON4_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nt_fpga_field_init_t tsm_con4_sample_hi_fields[] = {
+	{ TSM_CON4_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con4_sample_lo_fields[] = {
+	{ TSM_CON4_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con5_config_fields[] = {
+	{ TSM_CON5_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON5_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON5_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nt_fpga_field_init_t tsm_con5_sample_hi_fields[] = {
+	{ TSM_CON5_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con5_sample_lo_fields[] = {
+	{ TSM_CON5_SAMPLE_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con6_config_fields[] = {
+	{ TSM_CON6_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON6_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON6_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nt_fpga_field_init_t tsm_con6_sample_hi_fields[] = {
+	{ TSM_CON6_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con6_sample_lo_fields[] = {
+	{ TSM_CON6_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con7_host_sample_hi_fields[] = {
+	{ TSM_CON7_HOST_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_con7_host_sample_lo_fields[] = {
+	{ TSM_CON7_HOST_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_config_fields[] = {
+	{ TSM_CONFIG_NTTS_SRC, 2, 5, 0 },
+	{ TSM_CONFIG_NTTS_SYNC, 1, 4, 0 },
+	{ TSM_CONFIG_TIMESET_EDGE, 2, 8, 1 },
+	{ TSM_CONFIG_TIMESET_SRC, 3, 10, 0 },
+	{ TSM_CONFIG_TIMESET_UP, 1, 7, 0 },
+	{ TSM_CONFIG_TS_FORMAT, 4, 0, 1 },
+};
+
+static nt_fpga_field_init_t tsm_int_config_fields[] = {
+	{ TSM_INT_CONFIG_AUTO_DISABLE, 1, 0, 0 },
+	{ TSM_INT_CONFIG_MASK, 19, 1, 0 },
+};
+
+static nt_fpga_field_init_t tsm_int_stat_fields[] = {
+	{ TSM_INT_STAT_CAUSE, 19, 1, 0 },
+	{ TSM_INT_STAT_ENABLE, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_led_fields[] = {
+	{ TSM_LED_LED0_BG_COLOR, 2, 3, 0 },  { TSM_LED_LED0_COLOR, 2, 1, 0 },
+	{ TSM_LED_LED0_MODE, 1, 0, 0 },	     { TSM_LED_LED0_SRC, 4, 5, 0 },
+	{ TSM_LED_LED1_BG_COLOR, 2, 12, 0 }, { TSM_LED_LED1_COLOR, 2, 10, 0 },
+	{ TSM_LED_LED1_MODE, 1, 9, 0 },	     { TSM_LED_LED1_SRC, 4, 14, 1 },
+	{ TSM_LED_LED2_BG_COLOR, 2, 21, 0 }, { TSM_LED_LED2_COLOR, 2, 19, 0 },
+	{ TSM_LED_LED2_MODE, 1, 18, 0 },     { TSM_LED_LED2_SRC, 4, 23, 2 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_config_fields[] = {
+	{ TSM_NTTS_CONFIG_AUTO_HARDSET, 1, 5, 1 },
+	{ TSM_NTTS_CONFIG_EXT_CLK_ADJ, 1, 6, 0 },
+	{ TSM_NTTS_CONFIG_HIGH_SAMPLE, 1, 4, 0 },
+	{ TSM_NTTS_CONFIG_TS_SRC_FORMAT, 4, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_ext_stat_fields[] = {
+	{ TSM_NTTS_EXT_STAT_PRIMARY_ID, 8, 16, 0x0000 },
+	{ TSM_NTTS_EXT_STAT_PRIMARY_REV, 8, 24, 0x0000 },
+	{ TSM_NTTS_EXT_STAT_PRIMARY_STAT, 16, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_limit_hi_fields[] = {
+	{ TSM_NTTS_LIMIT_HI_SEC, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_limit_lo_fields[] = {
+	{ TSM_NTTS_LIMIT_LO_NS, 32, 0, 100000 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_offset_fields[] = {
+	{ TSM_NTTS_OFFSET_NS, 30, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_sample_hi_fields[] = {
+	{ TSM_NTTS_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_sample_lo_fields[] = {
+	{ TSM_NTTS_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_stat_fields[] = {
+	{ TSM_NTTS_STAT_NTTS_VALID, 1, 0, 0 },
+	{ TSM_NTTS_STAT_SIGNAL_LOST, 8, 1, 0 },
+	{ TSM_NTTS_STAT_SYNC_LOST, 8, 9, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_ts_t0_hi_fields[] = {
+	{ TSM_NTTS_TS_T0_HI_TIME, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_ts_t0_lo_fields[] = {
+	{ TSM_NTTS_TS_T0_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_ntts_ts_t0_offset_fields[] = {
+	{ TSM_NTTS_TS_T0_OFFSET_COUNT, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_pb_ctrl_fields[] = {
+	{ TSM_PB_CTRL_INSTMEM_WR, 1, 1, 0 },
+	{ TSM_PB_CTRL_RST, 1, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_pb_instmem_fields[] = {
+	{ TSM_PB_INSTMEM_MEM_ADDR, 14, 0, 0 },
+	{ TSM_PB_INSTMEM_MEM_DATA, 18, 14, 0 },
+};
+
+static nt_fpga_field_init_t tsm_pi_ctrl_i_fields[] = {
+	{ TSM_PI_CTRL_I_VAL, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_pi_ctrl_ki_fields[] = {
+	{ TSM_PI_CTRL_KI_GAIN, 24, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_pi_ctrl_kp_fields[] = {
+	{ TSM_PI_CTRL_KP_GAIN, 24, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_pi_ctrl_shl_fields[] = {
+	{ TSM_PI_CTRL_SHL_VAL, 4, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_stat_fields[] = {
+	{ TSM_STAT_HARD_SYNC, 8, 8, 0 },      { TSM_STAT_LINK_CON0, 1, 0, 0 },
+	{ TSM_STAT_LINK_CON1, 1, 1, 0 },      { TSM_STAT_LINK_CON2, 1, 2, 0 },
+	{ TSM_STAT_LINK_CON3, 1, 3, 0 },      { TSM_STAT_LINK_CON4, 1, 4, 0 },
+	{ TSM_STAT_LINK_CON5, 1, 5, 0 },      { TSM_STAT_NTTS_INSYNC, 1, 6, 0 },
+	{ TSM_STAT_PTP_MI_PRESENT, 1, 7, 0 },
+};
+
+static nt_fpga_field_init_t tsm_timer_ctrl_fields[] = {
+	{ TSM_TIMER_CTRL_TIMER_EN_T0, 1, 0, 0 },
+	{ TSM_TIMER_CTRL_TIMER_EN_T1, 1, 1, 0 },
+};
+
+static nt_fpga_field_init_t tsm_timer_t0_fields[] = {
+	{ TSM_TIMER_T0_MAX_COUNT, 30, 0, 50000 },
+};
+
+static nt_fpga_field_init_t tsm_timer_t1_fields[] = {
+	{ TSM_TIMER_T1_MAX_COUNT, 30, 0, 50000 },
+};
+
+static nt_fpga_field_init_t tsm_time_hardset_hi_fields[] = {
+	{ TSM_TIME_HARDSET_HI_TIME, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_time_hardset_lo_fields[] = {
+	{ TSM_TIME_HARDSET_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_time_hi_fields[] = {
+	{ TSM_TIME_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_time_lo_fields[] = {
+	{ TSM_TIME_LO_NS, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_time_rate_adj_fields[] = {
+	{ TSM_TIME_RATE_ADJ_FRACTION, 29, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_hi_fields[] = {
+	{ TSM_TS_HI_TIME, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_ts_lo_fields[] = {
+	{ TSM_TS_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nt_fpga_field_init_t tsm_ts_offset_fields[] = {
+	{ TSM_TS_OFFSET_NS, 30, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_fields[] = {
+	{ TSM_TS_STAT_OVERRUN, 1, 16, 0 },
+	{ TSM_TS_STAT_SAMPLES, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_hi_offset_fields[] = {
+	{ TSM_TS_STAT_HI_OFFSET_NS, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_lo_offset_fields[] = {
+	{ TSM_TS_STAT_LO_OFFSET_NS, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_tar_hi_fields[] = {
+	{ TSM_TS_STAT_TAR_HI_SEC, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_tar_lo_fields[] = {
+	{ TSM_TS_STAT_TAR_LO_NS, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_x_fields[] = {
+	{ TSM_TS_STAT_X_NS, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_x2_hi_fields[] = {
+	{ TSM_TS_STAT_X2_HI_NS, 16, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_ts_stat_x2_lo_fields[] = {
+	{ TSM_TS_STAT_X2_LO_NS, 32, 0, 0 },
+};
+
+static nt_fpga_field_init_t tsm_utc_offset_fields[] = {
+	{ TSM_UTC_OFFSET_SEC, 8, 0, 0 },
+};
+
+static nt_fpga_register_init_t tsm_registers[] = {
+	{	TSM_CON0_CONFIG, 24, 14, REGISTER_TYPE_RW, 2320, 5,
+		tsm_con0_config_fields
+	},
+	{	TSM_CON0_INTERFACE, 25, 20, REGISTER_TYPE_RW, 524291, 5,
+		tsm_con0_interface_fields
+	},
+	{	TSM_CON0_SAMPLE_HI, 27, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con0_sample_hi_fields
+	},
+	{	TSM_CON0_SAMPLE_LO, 26, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con0_sample_lo_fields
+	},
+	{	TSM_CON1_CONFIG, 28, 14, REGISTER_TYPE_RW, 2320, 5,
+		tsm_con1_config_fields
+	},
+	{	TSM_CON1_SAMPLE_HI, 30, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con1_sample_hi_fields
+	},
+	{	TSM_CON1_SAMPLE_LO, 29, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con1_sample_lo_fields
+	},
+	{	TSM_CON2_CONFIG, 31, 14, REGISTER_TYPE_RW, 2320, 5,
+		tsm_con2_config_fields
+	},
+	{	TSM_CON2_SAMPLE_HI, 33, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con2_sample_hi_fields
+	},
+	{	TSM_CON2_SAMPLE_LO, 32, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con2_sample_lo_fields
+	},
+	{	TSM_CON3_CONFIG, 34, 10, REGISTER_TYPE_RW, 841, 3,
+		tsm_con3_config_fields
+	},
+	{	TSM_CON3_SAMPLE_HI, 36, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con3_sample_hi_fields
+	},
+	{	TSM_CON3_SAMPLE_LO, 35, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con3_sample_lo_fields
+	},
+	{	TSM_CON4_CONFIG, 37, 10, REGISTER_TYPE_RW, 841, 3,
+		tsm_con4_config_fields
+	},
+	{	TSM_CON4_SAMPLE_HI, 39, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con4_sample_hi_fields
+	},
+	{	TSM_CON4_SAMPLE_LO, 38, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con4_sample_lo_fields
+	},
+	{	TSM_CON5_CONFIG, 40, 10, REGISTER_TYPE_RW, 841, 3,
+		tsm_con5_config_fields
+	},
+	{	TSM_CON5_SAMPLE_HI, 42, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con5_sample_hi_fields
+	},
+	{	TSM_CON5_SAMPLE_LO, 41, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con5_sample_lo_fields
+	},
+	{	TSM_CON6_CONFIG, 43, 10, REGISTER_TYPE_RW, 841, 3,
+		tsm_con6_config_fields
+	},
+	{	TSM_CON6_SAMPLE_HI, 45, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con6_sample_hi_fields
+	},
+	{	TSM_CON6_SAMPLE_LO, 44, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con6_sample_lo_fields
+	},
+	{	TSM_CON7_HOST_SAMPLE_HI, 47, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con7_host_sample_hi_fields
+	},
+	{	TSM_CON7_HOST_SAMPLE_LO, 46, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_con7_host_sample_lo_fields
+	},
+	{ TSM_CONFIG, 0, 13, REGISTER_TYPE_RW, 257, 6, tsm_config_fields },
+	{	TSM_INT_CONFIG, 2, 20, REGISTER_TYPE_RW, 0, 2,
+		tsm_int_config_fields
+	},
+	{ TSM_INT_STAT, 3, 20, REGISTER_TYPE_MIXED, 0, 2, tsm_int_stat_fields },
+	{ TSM_LED, 4, 27, REGISTER_TYPE_RW, 16793600, 12, tsm_led_fields },
+	{	TSM_NTTS_CONFIG, 13, 7, REGISTER_TYPE_RW, 32, 4,
+		tsm_ntts_config_fields
+	},
+	{	TSM_NTTS_EXT_STAT, 15, 32, REGISTER_TYPE_MIXED, 0, 3,
+		tsm_ntts_ext_stat_fields
+	},
+	{	TSM_NTTS_LIMIT_HI, 23, 16, REGISTER_TYPE_RW, 0, 1,
+		tsm_ntts_limit_hi_fields
+	},
+	{	TSM_NTTS_LIMIT_LO, 22, 32, REGISTER_TYPE_RW, 100000, 1,
+		tsm_ntts_limit_lo_fields
+	},
+	{	TSM_NTTS_OFFSET, 21, 30, REGISTER_TYPE_RW, 0, 1,
+		tsm_ntts_offset_fields
+	},
+	{	TSM_NTTS_SAMPLE_HI, 19, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ntts_sample_hi_fields
+	},
+	{	TSM_NTTS_SAMPLE_LO, 18, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ntts_sample_lo_fields
+	},
+	{ TSM_NTTS_STAT, 14, 17, REGISTER_TYPE_RO, 0, 3, tsm_ntts_stat_fields },
+	{	TSM_NTTS_TS_T0_HI, 17, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ntts_ts_t0_hi_fields
+	},
+	{	TSM_NTTS_TS_T0_LO, 16, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ntts_ts_t0_lo_fields
+	},
+	{	TSM_NTTS_TS_T0_OFFSET, 20, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ntts_ts_t0_offset_fields
+	},
+	{ TSM_PB_CTRL, 63, 2, REGISTER_TYPE_WO, 0, 2, tsm_pb_ctrl_fields },
+	{	TSM_PB_INSTMEM, 64, 32, REGISTER_TYPE_WO, 0, 2,
+		tsm_pb_instmem_fields
+	},
+	{ TSM_PI_CTRL_I, 54, 32, REGISTER_TYPE_WO, 0, 1, tsm_pi_ctrl_i_fields },
+	{	TSM_PI_CTRL_KI, 52, 24, REGISTER_TYPE_RW, 0, 1,
+		tsm_pi_ctrl_ki_fields
+	},
+	{	TSM_PI_CTRL_KP, 51, 24, REGISTER_TYPE_RW, 0, 1,
+		tsm_pi_ctrl_kp_fields
+	},
+	{	TSM_PI_CTRL_SHL, 53, 4, REGISTER_TYPE_WO, 0, 1,
+		tsm_pi_ctrl_shl_fields
+	},
+	{ TSM_STAT, 1, 16, REGISTER_TYPE_RO, 0, 9, tsm_stat_fields },
+	{	TSM_TIMER_CTRL, 48, 2, REGISTER_TYPE_RW, 0, 2,
+		tsm_timer_ctrl_fields
+	},
+	{	TSM_TIMER_T0, 49, 30, REGISTER_TYPE_RW, 50000, 1,
+		tsm_timer_t0_fields
+	},
+	{	TSM_TIMER_T1, 50, 30, REGISTER_TYPE_RW, 50000, 1,
+		tsm_timer_t1_fields
+	},
+	{	TSM_TIME_HARDSET_HI, 12, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_time_hardset_hi_fields
+	},
+	{	TSM_TIME_HARDSET_LO, 11, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_time_hardset_lo_fields
+	},
+	{ TSM_TIME_HI, 9, 32, REGISTER_TYPE_RW, 0, 1, tsm_time_hi_fields },
+	{ TSM_TIME_LO, 8, 32, REGISTER_TYPE_RW, 0, 1, tsm_time_lo_fields },
+	{	TSM_TIME_RATE_ADJ, 10, 29, REGISTER_TYPE_RW, 0, 1,
+		tsm_time_rate_adj_fields
+	},
+	{ TSM_TS_HI, 6, 32, REGISTER_TYPE_RO, 0, 1, tsm_ts_hi_fields },
+	{ TSM_TS_LO, 5, 32, REGISTER_TYPE_RO, 0, 1, tsm_ts_lo_fields },
+	{ TSM_TS_OFFSET, 7, 30, REGISTER_TYPE_RW, 0, 1, tsm_ts_offset_fields },
+	{ TSM_TS_STAT, 55, 17, REGISTER_TYPE_RO, 0, 2, tsm_ts_stat_fields },
+	{	TSM_TS_STAT_HI_OFFSET, 62, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ts_stat_hi_offset_fields
+	},
+	{	TSM_TS_STAT_LO_OFFSET, 61, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ts_stat_lo_offset_fields
+	},
+	{	TSM_TS_STAT_TAR_HI, 57, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ts_stat_tar_hi_fields
+	},
+	{	TSM_TS_STAT_TAR_LO, 56, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ts_stat_tar_lo_fields
+	},
+	{ TSM_TS_STAT_X, 58, 32, REGISTER_TYPE_RO, 0, 1, tsm_ts_stat_x_fields },
+	{	TSM_TS_STAT_X2_HI, 60, 16, REGISTER_TYPE_RO, 0, 1,
+		tsm_ts_stat_x2_hi_fields
+	},
+	{	TSM_TS_STAT_X2_LO, 59, 32, REGISTER_TYPE_RO, 0, 1,
+		tsm_ts_stat_x2_lo_fields
+	},
+	{	TSM_UTC_OFFSET, 65, 8, REGISTER_TYPE_RW, 0, 1,
+		tsm_utc_offset_fields
+	},
+};
+
+static nt_fpga_module_init_t fpga_modules[] = {
+	{	MOD_CAT, 0, MOD_CAT, 0, 21, BUS_TYPE_RAB1, 768, 34,
+		cat_registers
+	}, /* CAT:0 CAT v0.21: CAT @ RAB1,768 (CAT CAT CAT) */
+	{	MOD_CSU, 0, MOD_CSU, 0, 0, BUS_TYPE_RAB1, 9728, 2,
+		csu_registers
+	}, /* CSU:0 CSU v0.0: CSU @ RAB1,9728 (CSU CSU CSU) */
+	{	MOD_DBS, 0, MOD_DBS, 0, 11, BUS_TYPE_RAB2, 12832, 27,
+		dbs_registers
+	}, /* DBS:0 DBS v0.11: DBS @ RAB2,12832 (DBS DBS DBS) */
+	{	MOD_FLM, 0, MOD_FLM, 0, 20, BUS_TYPE_RAB1, 1280, 43,
+		flm_registers
+	}, /* FLM:0 FLM v0.20: FLM @ RAB1,1280 (FLM FLM FLM) */
+	{	MOD_GFG, 0, MOD_GFG, 1, 1, BUS_TYPE_RAB2, 8704, 10,
+		gfg_registers
+	}, /* GFG:0 GFG v1.1: GFG @ RAB2,8704 (GFG GFG GFG) */
+	{	MOD_GMF, 0, MOD_GMF, 2, 5, BUS_TYPE_RAB2, 9216, 12,
+		gmf_registers
+	}, /* GMF:0 GMF v2.5: GMF_0 @ RAB2,9216 (GMF GMF_0 GMF) */
+	{	MOD_GMF, 1, MOD_GMF, 2, 5, BUS_TYPE_RAB2, 9728, 12,
+		gmf_registers
+	}, /* GMF:1 GMF v2.5: GMF_1 @ RAB2,9728 (GMF GMF_1 GMF) */
+	{	MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, BUS_TYPE_RAB0, 16386, 2,
+		gpio_phy_registers
+	}, /* GPIO_PHY:0 GPIO_PHY v1.0: GPIO_PHY @ RAB0,16386 (GPIO_PHY GPIO_PHY GPIO_PHY) */
+	{	MOD_HFU, 0, MOD_HFU, 0, 1, BUS_TYPE_RAB1, 9472, 2,
+		hfu_registers
+	}, /* HFU:0 HFU v0.1: HFU @ RAB1,9472 (HFU HFU HFU) */
+	{	MOD_HIF, 0, MOD_HIF, 0, 0, BUS_TYPE_PCI, 0, 18,
+		hif_registers
+	}, /* HIF:0 HIF v0.0: HIF @ PCI,0 (HIF HIF HIF) */
+	{	MOD_HSH, 0, MOD_HSH, 0, 5, BUS_TYPE_RAB1, 1536, 2,
+		hsh_registers
+	}, /* HSH:0 HSH v0.5: HSH @ RAB1,1536 (HSH HSH HSH) */
+	{	MOD_HST, 0, MOD_HST, 0, 2, BUS_TYPE_RAB1, 2048, 2,
+		hst_registers
+	}, /* HST:0 HST v0.2: HST @ RAB1,2048 (HST HST HST) */
+	{	MOD_IFR, 0, MOD_IFR, 0, 1, BUS_TYPE_RAB1, 9984, 2,
+		ifr_registers
+	}, /* IFR:0 IFR v0.1: IFR @ RAB1,9984 (IFR IFR IFR) */
+	{	MOD_IIC, 0, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 768, 22,
+		iic_registers
+	}, /* IIC:0 IIC v0.1: IIC0 @ RAB0,768 (IIC IIC0 IIC) */
+	{	MOD_IIC, 1, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 896, 22,
+		iic_registers
+	}, /* IIC:1 IIC v0.1: IIC1 @ RAB0,896 (IIC IIC1 IIC) */
+	{	MOD_IIC, 2, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 24832, 22,
+		iic_registers
+	}, /* IIC:2 IIC v0.1: IIC2 @ RAB0,24832 (IIC IIC2 IIC) */
+	{	MOD_IIC, 3, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 24960, 22,
+		iic_registers
+	}, /* IIC:3 IIC v0.1: IIC3 @ RAB0,24960 (IIC IIC3 IIC) */
+	{	MOD_KM, 0, MOD_KM, 0, 7, BUS_TYPE_RAB1, 1024, 11,
+		km_registers
+	}, /* KM:0 KM v0.7: KM @ RAB1,1024 (KM KM KM) */
+	{	MOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2, BUS_TYPE_RAB2, 10240, 44,
+		mac_pcs_registers
+	}, /* MAC_PCS:0 MAC_PCS v0.2: MAC_PCS_0 @ RAB2,10240 (MAC_PCS MAC_PCS_0 MAC_PCS) */
+	{	MOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2, BUS_TYPE_RAB2, 11776, 44,
+		mac_pcs_registers
+	}, /* MAC_PCS:1 MAC_PCS v0.2: MAC_PCS_1 @ RAB2,11776 (MAC_PCS MAC_PCS_1 MAC_PCS) */
+	{	MOD_MAC_RX, 0, MOD_MAC_RX, 0, 0, BUS_TYPE_RAB2, 10752, 9,
+		mac_rx_registers
+	}, /* MAC_RX:0 MAC_RX v0.0: MAC_RX_0 @ RAB2,10752 (MAC_RX MAC_RX_0 MAC_RX) */
+	{	MOD_MAC_RX, 1, MOD_MAC_RX, 0, 0, BUS_TYPE_RAB2, 12288, 9,
+		mac_rx_registers
+	}, /* MAC_RX:1 MAC_RX v0.0: MAC_RX_1 @ RAB2,12288 (MAC_RX MAC_RX_1 MAC_RX) */
+	{	MOD_MAC_TX, 0, MOD_MAC_TX, 0, 0, BUS_TYPE_RAB2, 11264, 5,
+		mac_tx_registers
+	}, /* MAC_TX:0 MAC_TX v0.0: MAC_TX_0 @ RAB2,11264 (MAC_TX MAC_TX_0 MAC_TX) */
+	{	MOD_MAC_TX, 1, MOD_MAC_TX, 0, 0, BUS_TYPE_RAB2, 12800, 5,
+		mac_tx_registers
+	}, /* MAC_TX:1 MAC_TX v0.0: MAC_TX_1 @ RAB2,12800 (MAC_TX MAC_TX_1 MAC_TX) */
+	{	MOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1, BUS_TYPE_RAB0, 2320, 6,
+		pci_rd_tg_registers
+	}, /* PCI_RD_TG:0 PCI_RD_TG v0.1: PCI_RD_TG @ RAB0,2320 (PCI_RD_TG PCI_RD_TG PCI_RD_TG) */
+	{	MOD_PCI_TA, 0, MOD_PCI_TA, 0, 0, BUS_TYPE_RAB0, 2336, 5,
+		pci_ta_registers
+	}, /* PCI_TA:0 PCI_TA v0.0: PCI_TA @ RAB0,2336 (PCI_TA PCI_TA PCI_TA) */
+	{	MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, BUS_TYPE_RAB0, 2304, 7,
+		pci_wr_tg_registers
+	}, /* PCI_WR_TG:0 PCI_WR_TG v0.1: PCI_WR_TG @ RAB0,2304 (PCI_WR_TG PCI_WR_TG PCI_WR_TG) */
+	{	MOD_PDB, 0, MOD_PDB, 0, 9, BUS_TYPE_RAB1, 2816, 3,
+		pdb_registers
+	}, /* PDB:0 PDB v0.9: PDB @ RAB1,2816 (PDB PDB PDB) */
+	{	MOD_PDI, 0, MOD_PDI, 1, 1, BUS_TYPE_RAB0, 64, 6,
+		pdi_registers
+	}, /* PDI:0 PDI v1.1: PDI @ RAB0,64 (PDI PDI PDI) */
+	{	MOD_PTP1588, 0, MOD_PTP1588, 2, 1, BUS_TYPE_RAB2, 512, 23,
+		ptp1588_registers
+	}, /* PTP1588:0 PTP1588 v2.1: PTP1588 @ RAB2,512 (PTP1588 PTP1588 PTP1588) */
+	{	MOD_QSL, 0, MOD_QSL, 0, 7, BUS_TYPE_RAB1, 1792, 8,
+		qsl_registers
+	}, /* QSL:0 QSL v0.7: QSL @ RAB1,1792 (QSL QSL QSL) */
+	{	MOD_QSPI, 0, MOD_QSPI, 0, 0, BUS_TYPE_RAB0, 512, 11,
+		qspi_registers
+	}, /* QSPI:0 QSPI v0.0: QSPI @ RAB0,512 (QSPI QSPI QSPI) */
+	{	MOD_RAC, 0, MOD_RAC, 3, 0, BUS_TYPE_PCI, 8192, 14,
+		rac_registers
+	}, /* RAC:0 RAC v3.0: RAC @ PCI,8192 (RAC RAC RAC) */
+	{	MOD_RFD, 0, MOD_RFD, 0, 4, BUS_TYPE_RAB1, 256, 5,
+		rfd_registers
+	}, /* RFD:0 RFD v0.4: RFD @ RAB1,256 (RFD RFD RFD) */
+	{	MOD_RMC, 0, MOD_RMC, 1, 3, BUS_TYPE_RAB0, 12288, 4,
+		rmc_registers
+	}, /* RMC:0 RMC v1.3: RMC @ RAB0,12288 (RMC RMC RMC) */
+	{	MOD_RPP_LR, 0, MOD_RPP_LR, 0, 1, BUS_TYPE_RAB1, 2560, 4,
+		rpp_lr_registers
+	}, /* RPP_LR:0 RPP_LR v0.1: RPP_LR @ RAB1,2560 (RPP_LR RPP_LR RPP_LR) */
+	{	MOD_RST9563, 0, MOD_RST9563, 0, 5, BUS_TYPE_RAB0, 1024, 5,
+		rst9563_registers
+	}, /* RST9563:0 RST9563 v0.5: RST9563 @ RAB0,1024 (RST9563 RST9563 RST9563) */
+	{	MOD_SLC_LR, 0, MOD_SLC, 0, 2, BUS_TYPE_RAB1, 2304, 2,
+		slc_registers
+	}, /* SLC_LR:0 SLC v0.2: SLC_LR @ RAB1,2304 (SLC SLC_LR SLC_LR) */
+	{	MOD_SPIM, 0, MOD_SPIM, 1, 0, BUS_TYPE_RAB0, 80, 6,
+		spim_registers
+	}, /* SPIM:0 SPIM v1.0: SPIM @ RAB0,80 (SPIM SPIM SPIM) */
+	{	MOD_SPIS, 0, MOD_SPIS, 1, 0, BUS_TYPE_RAB0, 256, 7,
+		spis_registers
+	}, /* SPIS:0 SPIS v1.0: SPIS @ RAB0,256 (SPIS SPIS SPIS) */
+	{	MOD_STA, 0, MOD_STA, 0, 8, BUS_TYPE_RAB0, 2048, 8,
+		sta_registers
+	}, /* STA:0 STA v0.8: STA @ RAB0,2048 (STA STA STA) */
+	{	MOD_TEMPMON, 0, MOD_TEMPMON, 0, 0, BUS_TYPE_RAB0, 16384, 2,
+		tempmon_registers
+	}, /* TEMPMON:0 TEMPMON v0.0: TEMPMON @ RAB0,16384 (TEMPMON TEMPMON TEMPMON) */
+	{	MOD_TINT, 0, MOD_TINT, 0, 0, BUS_TYPE_RAB0, 1280, 2,
+		tint_registers
+	}, /* TINT:0 TINT v0.0: TINT @ RAB0,1280 (TINT TINT TINT) */
+	{	MOD_TMC, 0, MOD_TMC, 0, 1, BUS_TYPE_RAB2, 8192, 1,
+		tmc_registers
+	}, /* TMC:0 TMC v0.1: TMC @ RAB2,8192 (TMC TMC TMC) */
+	{	MOD_TSM, 0, MOD_TSM, 0, 8, BUS_TYPE_RAB2, 1024, 66,
+		tsm_registers
+	}, /* TSM:0 TSM v0.8: TSM @ RAB2,1024 (TSM TSM TSM) */
+	{	MOD_TX_CPY, 0, MOD_CPY, 0, 1, BUS_TYPE_RAB1, 9216, 20,
+		cpy_registers
+	}, /* TX_CPY:0 CPY v0.1: TX_CPY @ RAB1,9216 (CPY TX_CPY TX_CPY) */
+	{	MOD_TX_INS, 0, MOD_INS, 0, 1, BUS_TYPE_RAB1, 8704, 2,
+		ins_registers
+	}, /* TX_INS:0 INS v0.1: TX_INS @ RAB1,8704 (INS TX_INS TX_INS) */
+	{	MOD_TX_RPL, 0, MOD_RPL, 0, 2, BUS_TYPE_RAB1, 8960, 6,
+		rpl_registers
+	}, /* TX_RPL:0 RPL v0.2: TX_RPL @ RAB1,8960 (RPL TX_RPL TX_RPL) */
+};
+
+static nt_fpga_prod_param_t product_parameters[] = {
+	{ NT_BUILD_NUMBER, 0 },
+	{ NT_BUILD_TIME, 1693492863 },
+	{ NT_CATEGORIES, 64 },
+	{ NT_CAT_DCT_PRESENT, 0 },
+	{ NT_CAT_END_OFS_SUPPORT, 0 },
+	{ NT_CAT_FUNCS, 64 },
+	{ NT_CAT_KCC_BANKS, 3 },
+	{ NT_CAT_KCC_PRESENT, 0 },
+	{ NT_CAT_KCC_SIZE, 1536 },
+	{ NT_CAT_KM_IF_CNT, 2 },
+	{ NT_CAT_KM_IF_M0, 0 },
+	{ NT_CAT_KM_IF_M1, 1 },
+	{ NT_CAT_N_CMP, 8 },
+	{ NT_CAT_N_EXT, 4 },
+	{ NT_CAT_N_LEN, 8 },
+	{ NT_CB_DEBUG, 0 },
+	{ NT_COR_CATEGORIES, 16 },
+	{ NT_COR_PRESENT, 0 },
+	{ NT_CSU_PRESENT, 1 },
+	{ NT_DBS_PRESENT, 1 },
+	{ NT_DBS_RX_QUEUES, 128 },
+	{ NT_DBS_TX_PORTS, 2 },
+	{ NT_DBS_TX_QUEUES, 128 },
+	{ NT_DDP_PRESENT, 0 },
+	{ NT_DDP_TBL_DEPTH, 4096 },
+	{ NT_EMI_SPLIT_STEPS, 16 },
+	{ NT_EOF_TIMESTAMP_ONLY, 1 },
+	{ NT_EPP_CATEGORIES, 32 },
+	{ NT_FLM_CACHE, 1 },
+	{ NT_FLM_CATEGORIES, 32 },
+	{ NT_FLM_ENTRY_SIZE, 64 },
+	{ NT_FLM_PRESENT, 1 },
+	{ NT_FLM_PRIOS, 4 },
+	{ NT_FLM_PST_PROFILES, 16 },
+	{ NT_FLM_SIZE_MB, 12288 },
+	{ NT_FLM_STATEFUL, 1 },
+	{ NT_FLM_VARIANT, 2 },
+	{ NT_GFG_PRESENT, 1 },
+	{ NT_GFG_TX_LIVE_RECONFIG_SUPPORT, 1 },
+	{ NT_GMF_FCS_PRESENT, 0 },
+	{ NT_GMF_IFG_SPEED_DIV, 33 },
+	{ NT_GMF_IFG_SPEED_DIV100G, 33 },
+	{ NT_GMF_IFG_SPEED_MUL, 20 },
+	{ NT_GMF_IFG_SPEED_MUL100G, 20 },
+	{ NT_GROUP_ID, 9563 },
+	{ NT_HFU_PRESENT, 1 },
+	{ NT_HIF_MSIX_BAR, 1 },
+	{ NT_HIF_MSIX_PBA_OFS, 8192 },
+	{ NT_HIF_MSIX_PRESENT, 1 },
+	{ NT_HIF_MSIX_TBL_OFS, 0 },
+	{ NT_HIF_MSIX_TBL_SIZE, 8 },
+	{ NT_HIF_PER_PS, 4000 },
+	{ NT_HIF_SRIOV_PRESENT, 1 },
+	{ NT_HSH_CATEGORIES, 16 },
+	{ NT_HSH_TOEPLITZ, 1 },
+	{ NT_HST_CATEGORIES, 32 },
+	{ NT_HST_PRESENT, 1 },
+	{ NT_IOA_CATEGORIES, 1024 },
+	{ NT_IOA_PRESENT, 0 },
+	{ NT_IPF_PRESENT, 0 },
+	{ NT_KM_CAM_BANKS, 3 },
+	{ NT_KM_CAM_RECORDS, 2048 },
+	{ NT_KM_CAM_REC_WORDS, 6 },
+	{ NT_KM_CATEGORIES, 32 },
+	{ NT_KM_END_OFS_SUPPORT, 0 },
+	{ NT_KM_EXT_EXTRACTORS, 0 },
+	{ NT_KM_FLOW_TYPES, 16 },
+	{ NT_KM_PRESENT, 1 },
+	{ NT_KM_SWX_PRESENT, 0 },
+	{ NT_KM_SYNERGY_MATCH, 0 },
+	{ NT_KM_TCAM_BANKS, 12 },
+	{ NT_KM_TCAM_BANK_WIDTH, 72 },
+	{ NT_KM_TCAM_HIT_QUAL, 0 },
+	{ NT_KM_TCAM_KEYWAY, 1 },
+	{ NT_KM_WIDE, 1 },
+	{ NT_LR_PRESENT, 1 },
+	{ NT_MCU_PRESENT, 0 },
+	{ NT_MDG_DEBUG_FLOW_CONTROL, 0 },
+	{ NT_MDG_DEBUG_REG_READ_BACK, 0 },
+	{ NT_MSK_CATEGORIES, 32 },
+	{ NT_MSK_PRESENT, 0 },
+	{ NT_NFV_OVS_PRODUCT, 0 },
+	{ NT_NIMS, 2 },
+	{ NT_PCI_DEVICE_ID, 453 },
+	{ NT_PCI_TA_TG_PRESENT, 1 },
+	{ NT_PCI_VENDOR_ID, 6388 },
+	{ NT_PDB_CATEGORIES, 16 },
+	{ NT_PHY_ANEG_PRESENT, 0 },
+	{ NT_PHY_KRFEC_PRESENT, 0 },
+	{ NT_PHY_PORTS, 2 },
+	{ NT_PHY_PORTS_PER_QUAD, 1 },
+	{ NT_PHY_QUADS, 2 },
+	{ NT_PHY_RSFEC_PRESENT, 1 },
+	{ NT_QM_CELLS, 2097152 },
+	{ NT_QM_CELL_SIZE, 6144 },
+	{ NT_QM_PRESENT, 0 },
+	{ NT_QSL_CATEGORIES, 32 },
+	{ NT_QSL_COLOR_SEL_BW, 7 },
+	{ NT_QSL_QST_SIZE, 4096 },
+	{ NT_QUEUES, 128 },
+	{ NT_RAC_RAB_INTERFACES, 3 },
+	{ NT_RAC_RAB_OB_UPDATE, 0 },
+	{ NT_REVISION_ID, 24 },
+	{ NT_RMC_LAG_GROUPS, 1 },
+	{ NT_ROA_CATEGORIES, 1024 },
+	{ NT_ROA_PRESENT, 0 },
+	{ NT_RPP_PER_PS, 3333 },
+	{ NT_RTX_PRESENT, 0 },
+	{ NT_RX_HOST_BUFFERS, 128 },
+	{ NT_RX_PORTS, 2 },
+	{ NT_RX_PORT_REPLICATE, 0 },
+	{ NT_SLB_PRESENT, 0 },
+	{ NT_SLC_LR_PRESENT, 1 },
+	{ NT_STA_COLORS, 64 },
+	{ NT_STA_RX_PORTS, 2 },
+	{ NT_TBH_DEBUG_DLN, 1 },
+	{ NT_TBH_PRESENT, 0 },
+	{ NT_TFD_PRESENT, 1 },
+	{ NT_TPE_CATEGORIES, 16 },
+	{ NT_TSM_OST_ONLY, 0 },
+	{ NT_TS_APPEND, 0 },
+	{ NT_TS_INJECT_PRESENT, 0 },
+	{ NT_TX_CPY_PACKET_READERS, 0 },
+	{ NT_TX_CPY_PRESENT, 1 },
+	{ NT_TX_CPY_SIDEBAND_READERS, 6 },
+	{ NT_TX_CPY_VARIANT, 0 },
+	{ NT_TX_CPY_WRITERS, 5 },
+	{ NT_TX_HOST_BUFFERS, 128 },
+	{ NT_TX_INS_PRESENT, 1 },
+	{ NT_TX_MTU_PROFILE_IFR, 16 },
+	{ NT_TX_ON_TIMESTAMP, 1 },
+	{ NT_TX_PORTS, 2 },
+	{ NT_TX_PORT_REPLICATE, 1 },
+	{ NT_TX_RPL_DEPTH, 4096 },
+	{ NT_TX_RPL_EXT_CATEGORIES, 1024 },
+	{ NT_TX_RPL_PRESENT, 1 },
+	{ NT_TYPE_ID, 200 },
+	{ NT_USE_TRIPLE_SPEED, 0 },
+	{ NT_VERSION_ID, 55 },
+	{ NT_VLI_PRESENT, 0 },
+	{ 0, -1 }, /* END */
+};
+
+nt_fpga_prod_init_t nthw_fpga_9563_055_024_0000 = {
+	200, /* fpgaTypeId */
+	9563, /* fpga_product_id */
+	55, /* fpga_version */
+	24, /* fpga_revision */
+	0, /* fpga_patch_no */
+	0, /* fpga_build_no */
+	1693492863, /* fpga_build_time */
+	140,	    product_parameters, 48, fpga_modules,
+};
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
new file mode 100644
index 0000000000..1d707d6925
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
@@ -0,0 +1,14 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_FPGA_INSTANCES_H
+#define NTHW_FPGA_INSTANCES_H
+
+#include "fpga_model.h"
+
+extern nt_fpga_prod_init_t *nthw_fpga_instances[];
+
+extern nt_fpga_prod_init_t nthw_fpga_9563_055_024_0000;
+
+#endif /* NTHW_FPGA_INSTANCES_H */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h
new file mode 100644
index 0000000000..38a15bec87
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h
@@ -0,0 +1,166 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_FPGA_MODULES_DEFS_H_
+#define _NTHW_FPGA_MODULES_DEFS_H_
+
+/* Unknown/uninitialized - keep this as the first element */
+#define MOD_UNKNOWN (0L)
+#define MOD_CAT (1L)
+#define MOD_CB (2L)
+#define MOD_CCIP (3L)
+#define MOD_CFP4_CTRL_GBOX (4L)
+#define MOD_COR (5L)
+#define MOD_CPY (6L)
+#define MOD_CSU (7L)
+#define MOD_DBS (8L)
+#define MOD_DDP (9L)
+#define MOD_EPP (10L)
+#define MOD_EQM (11L)
+#define MOD_FHM (12L)
+#define MOD_FLM (13L)
+#define MOD_GFG (14L)
+#define MOD_GMF (15L)
+#define MOD_GPIO_PHY (16L)
+#define MOD_GPIO_PHY_PORTS (17L)
+#define MOD_GPIO_SFPP (18L)
+#define MOD_HFU (19L)
+#define MOD_HIF (20L)
+#define MOD_HSH (21L)
+#define MOD_HST (22L)
+#define MOD_ICORE_10G (23L)
+#define MOD_IFR (24L)
+#define MOD_IIC (25L)
+#define MOD_INS (26L)
+#define MOD_IOA (27L)
+#define MOD_IPF (28L)
+#define MOD_KM (29L)
+#define MOD_LAO (30L)
+#define MOD_MAC (31L)
+#define MOD_MAC100 (33L)
+#define MOD_MAC10G (34L)
+#define MOD_MAC1G (35L)
+#define MOD_MAC_PCS (36L)
+#define MOD_MAC_PCS_XXV (37L)
+#define MOD_MAC_RX (38L)
+#define MOD_MAC_TFG (39L)
+#define MOD_MAC_TX (40L)
+#define MOD_MCU (41L)
+#define MOD_MDG (42L)
+#define MOD_MSK (43L)
+#define MOD_NIF (44L)
+#define MOD_PCIE3 (45L)
+#define MOD_PCI_RD_TG (46L)
+#define MOD_PCI_TA (47L)
+#define MOD_PCI_WR_TG (48L)
+#define MOD_PCM_NT100A01_01 (49L)
+#define MOD_PCM_NT50B01_01 (50L)
+#define MOD_PCS (51L)
+#define MOD_PCS100 (52L)
+#define MOD_PDB (53L)
+#define MOD_PDI (54L)
+#define MOD_PHY10G (55L)
+#define MOD_PHY3S10G (56L)
+#define MOD_PM (57L)
+#define MOD_PRM_NT100A01_01 (58L)
+#define MOD_PRM_NT50B01_01 (59L)
+#define MOD_PTP1588 (60L)
+#define MOD_QM (61L)
+#define MOD_QSL (62L)
+#define MOD_QSPI (63L)
+#define MOD_R2DRP (64L)
+#define MOD_RAC (65L)
+#define MOD_RBH (66L)
+#define MOD_RFD (67L)
+#define MOD_RMC (68L)
+#define MOD_RNTC (69L)
+#define MOD_ROA (70L)
+#define MOD_RPL (71L)
+#define MOD_RPP_LR (72L)
+#define MOD_RST7000 (73L)
+#define MOD_RST7001 (74L)
+#define MOD_RST9500 (75L)
+#define MOD_RST9501 (76L)
+#define MOD_RST9502 (77L)
+#define MOD_RST9503 (78L)
+#define MOD_RST9504 (79L)
+#define MOD_RST9505 (80L)
+#define MOD_RST9506 (81L)
+#define MOD_RST9507 (82L)
+#define MOD_RST9508 (83L)
+#define MOD_RST9509 (84L)
+#define MOD_RST9510 (85L)
+#define MOD_RST9512 (86L)
+#define MOD_RST9513 (87L)
+#define MOD_RST9515 (88L)
+#define MOD_RST9516 (89L)
+#define MOD_RST9517 (90L)
+#define MOD_RST9519 (91L)
+#define MOD_RST9520 (92L)
+#define MOD_RST9521 (93L)
+#define MOD_RST9522 (94L)
+#define MOD_RST9523 (95L)
+#define MOD_RST9524 (96L)
+#define MOD_RST9525 (97L)
+#define MOD_RST9526 (98L)
+#define MOD_RST9527 (99L)
+#define MOD_RST9528 (100L)
+#define MOD_RST9529 (101L)
+#define MOD_RST9530 (102L)
+#define MOD_RST9531 (103L)
+#define MOD_RST9532 (104L)
+#define MOD_RST9533 (105L)
+#define MOD_RST9534 (106L)
+#define MOD_RST9535 (107L)
+#define MOD_RST9536 (108L)
+#define MOD_RST9537 (109L)
+#define MOD_RST9538 (110L)
+#define MOD_RST9539 (111L)
+#define MOD_RST9540 (112L)
+#define MOD_RST9541 (113L)
+#define MOD_RST9542 (114L)
+#define MOD_RST9543 (115L)
+#define MOD_RST9544 (116L)
+#define MOD_RST9545 (117L)
+#define MOD_RST9546 (118L)
+#define MOD_RST9547 (119L)
+#define MOD_RST9548 (120L)
+#define MOD_RST9549 (121L)
+#define MOD_RST9553 (122L)
+#define MOD_RST9555 (123L)
+#define MOD_RST9559 (124L)
+#define MOD_RST9563 (125L)
+#define MOD_RTD (126L)
+#define MOD_RTD_HMP (127L)
+#define MOD_RTX (128L)
+#define MOD_SDC (129L)
+#define MOD_SLC (130L)
+#define MOD_SLC_LR (131L)
+#define MOD_SMM (132L)
+#define MOD_SMM_RX (133L)
+#define MOD_SMM_TX (134L)
+#define MOD_SPIM (135L)
+#define MOD_SPIS (136L)
+#define MOD_STA (137L)
+#define MOD_TBH (138L)
+#define MOD_TEMPMON (139L)
+#define MOD_TINT (140L)
+#define MOD_TMC (141L)
+#define MOD_TSM (142L)
+#define MOD_TX_CPY (143L)
+#define MOD_TX_CSI (144L)
+#define MOD_TX_CSO (145L)
+#define MOD_TX_INS (146L)
+#define MOD_TX_RPL (147L)
+/*
+ * NOTE: Keep this as the last element!
+ * End indicator - keep this as the last element - only aliases go below this point
+ */
+#define MOD_UNKNOWN_MAX (148L)
+/* End indicator - keep this as the last element - only aliases go below this point */
+#define MOD_COUNT_MAX (148L)
+/* aliases */
+#define MOD_MAC10 (MOD_MAC10G) /* alias */
+
+#endif /* _NTHW_FPGA_MODULES_DEFS_H_ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h
new file mode 100644
index 0000000000..b6187a257f
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h
@@ -0,0 +1,209 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_FPGA_PARAMETERS_DEFS_
+#define _NTHW_FPGA_PARAMETERS_DEFS_
+
+#define NT_PARAM_UNKNOWN (0L)
+#define NT_BUILD_NUMBER (1L)
+#define NT_BUILD_TIME (2L)
+#define NT_CATEGORIES (3L)
+#define NT_CAT_CCT_SIZE (4L)
+#define NT_CAT_CTE_SIZE (5L)
+#define NT_CAT_CTS_SIZE (6L)
+#define NT_CAT_DCT_PRESENT (7L)
+#define NT_CAT_DCT_SIZE (8L)
+#define NT_CAT_END_OFS_SUPPORT (9L)
+#define NT_CAT_FPC (10L)
+#define NT_CAT_FTE_SIZE (11L)
+#define NT_CAT_FUNCS (12L)
+#define NT_CAT_KCC_BANKS (13L)
+#define NT_CAT_KCC_PRESENT (14L)
+#define NT_CAT_KCC_SIZE (15L)
+#define NT_CAT_KCE_SIZE (16L)
+#define NT_CAT_KM_IF_CNT (17L)
+#define NT_CAT_KM_IF_M0 (18L)
+#define NT_CAT_KM_IF_M1 (19L)
+#define NT_CAT_N_CMP (20L)
+#define NT_CAT_N_EXT (21L)
+#define NT_CAT_N_LEN (22L)
+#define NT_CAT_RCK_SIZE (23L)
+#define NT_CAT_VALUES (24L)
+#define NT_CB_DEBUG (25L)
+#define NT_COR_CATEGORIES (26L)
+#define NT_COR_PRESENT (27L)
+#define NT_CPY_MASK_MEM (28L)
+#define NT_CSU_PRESENT (29L)
+#define NT_DBS_PRESENT (30L)
+#define NT_DBS_RX_QUEUES (31L)
+#define NT_DBS_TX_PORTS (32L)
+#define NT_DBS_TX_QUEUES (33L)
+#define NT_DDP_PRESENT (34L)
+#define NT_DDP_TBL_DEPTH (35L)
+#define NT_EMI_SPLIT_STEPS (36L)
+#define NT_EOF_TIMESTAMP_ONLY (37L)
+#define NT_EPP_CATEGORIES (38L)
+#define NT_EXT_MEM_NUM (39L)
+#define NT_EXT_MEM_SINGLE_SIZE_GB (40L)
+#define NT_FLM_CACHE (41L)
+#define NT_FLM_CATEGORIES (42L)
+#define NT_FLM_ENTRY_SIZE (43L)
+#define NT_FLM_PRESENT (44L)
+#define NT_FLM_PRIOS (45L)
+#define NT_FLM_PST_PROFILES (46L)
+#define NT_FLM_SIZE_MB (47L)
+#define NT_FLM_STATEFUL (48L)
+#define NT_FLM_VARIANT (49L)
+#define NT_GFG_PRESENT (50L)
+#define NT_GFG_TX_LIVE_RECONFIG_SUPPORT (51L)
+#define NT_GMF_FCS_PRESENT (52L)
+#define NT_GMF_IFG_SPEED_DIV (53L)
+#define NT_GMF_IFG_SPEED_DIV100G (54L)
+#define NT_GMF_IFG_SPEED_DIV100M (55L)
+#define NT_GMF_IFG_SPEED_DIV10G (56L)
+#define NT_GMF_IFG_SPEED_DIV1G (57L)
+#define NT_GMF_IFG_SPEED_DIV2 (58L)
+#define NT_GMF_IFG_SPEED_DIV25G (59L)
+#define NT_GMF_IFG_SPEED_DIV3 (60L)
+#define NT_GMF_IFG_SPEED_DIV4 (61L)
+#define NT_GMF_IFG_SPEED_DIV40G (62L)
+#define NT_GMF_IFG_SPEED_DIV50G (63L)
+#define NT_GMF_IFG_SPEED_MUL (64L)
+#define NT_GMF_IFG_SPEED_MUL100G (65L)
+#define NT_GMF_IFG_SPEED_MUL100M (66L)
+#define NT_GMF_IFG_SPEED_MUL10G (67L)
+#define NT_GMF_IFG_SPEED_MUL1G (68L)
+#define NT_GMF_IFG_SPEED_MUL2 (69L)
+#define NT_GMF_IFG_SPEED_MUL25G (70L)
+#define NT_GMF_IFG_SPEED_MUL3 (71L)
+#define NT_GMF_IFG_SPEED_MUL4 (72L)
+#define NT_GMF_IFG_SPEED_MUL40G (73L)
+#define NT_GMF_IFG_SPEED_MUL50G (74L)
+#define NT_GROUP_ID (75L)
+#define NT_HFU_PRESENT (76L)
+#define NT_HIF_MSIX_BAR (77L)
+#define NT_HIF_MSIX_PBA_OFS (78L)
+#define NT_HIF_MSIX_PRESENT (79L)
+#define NT_HIF_MSIX_TBL_OFS (80L)
+#define NT_HIF_MSIX_TBL_SIZE (81L)
+#define NT_HIF_PER_PS (82L)
+#define NT_HIF_SRIOV_PRESENT (83L)
+#define NT_HSH_CATEGORIES (84L)
+#define NT_HSH_TOEPLITZ (85L)
+#define NT_HST_CATEGORIES (86L)
+#define NT_HST_PRESENT (87L)
+#define NT_IOA_CATEGORIES (88L)
+#define NT_IOA_PRESENT (89L)
+#define NT_IPF_PRESENT (90L)
+#define NT_KM_CAM_BANKS (91L)
+#define NT_KM_CAM_RECORDS (92L)
+#define NT_KM_CAM_REC_WORDS (93L)
+#define NT_KM_CATEGORIES (94L)
+#define NT_KM_END_OFS_SUPPORT (95L)
+#define NT_KM_EXT_EXTRACTORS (96L)
+#define NT_KM_FLOW_SETS (97L)
+#define NT_KM_FLOW_TYPES (98L)
+#define NT_KM_PRESENT (99L)
+#define NT_KM_SWX_PRESENT (100L)
+#define NT_KM_SYNERGY_MATCH (101L)
+#define NT_KM_TCAM_BANKS (102L)
+#define NT_KM_TCAM_BANK_WIDTH (103L)
+#define NT_KM_TCAM_HIT_QUAL (104L)
+#define NT_KM_TCAM_KEYWAY (105L)
+#define NT_KM_WIDE (106L)
+#define NT_LR_PRESENT (107L)
+#define NT_LTX_CATEGORIES (108L)
+#define NT_MCU_DRAM_SIZE (109L)
+#define NT_MCU_PRESENT (110L)
+#define NT_MCU_TYPE (111L)
+#define NT_MDG_DEBUG_FLOW_CONTROL (112L)
+#define NT_MDG_DEBUG_REG_READ_BACK (113L)
+#define NT_MSK_CATEGORIES (114L)
+#define NT_MSK_PRESENT (115L)
+#define NT_NAME (116L)
+#define NT_NFV_OVS_PRODUCT (117L)
+#define NT_NIMS (118L)
+#define NT_PATCH_NUMBER (119L)
+#define NT_PCI_DEVICE_ID (120L)
+#define NT_PCI_INT_AVR (121L)
+#define NT_PCI_INT_EQM (122L)
+#define NT_PCI_INT_IIC0 (123L)
+#define NT_PCI_INT_IIC1 (124L)
+#define NT_PCI_INT_IIC2 (125L)
+#define NT_PCI_INT_IIC3 (126L)
+#define NT_PCI_INT_IIC4 (127L)
+#define NT_PCI_INT_IIC5 (128L)
+#define NT_PCI_INT_PORT (129L)
+#define NT_PCI_INT_PORT0 (130L)
+#define NT_PCI_INT_PORT1 (131L)
+#define NT_PCI_INT_PPS (132L)
+#define NT_PCI_INT_QSPI (133L)
+#define NT_PCI_INT_SPIM (134L)
+#define NT_PCI_INT_SPIS (135L)
+#define NT_PCI_INT_STA (136L)
+#define NT_PCI_INT_TIMER (137L)
+#define NT_PCI_INT_TINT (138L)
+#define NT_PCI_TA_TG_PRESENT (139L)
+#define NT_PCI_VENDOR_ID (140L)
+#define NT_PDB_CATEGORIES (141L)
+#define NT_PHY_ANEG_PRESENT (142L)
+#define NT_PHY_KRFEC_PRESENT (143L)
+#define NT_PHY_PORTS (144L)
+#define NT_PHY_PORTS_PER_QUAD (145L)
+#define NT_PHY_QUADS (146L)
+#define NT_PHY_RSFEC_PRESENT (147L)
+#define NT_PORTS (148L)
+#define NT_PROD_ID_LAYOUT_VERSION (149L)
+#define NT_QM_BLOCKS (150L)
+#define NT_QM_CELLS (151L)
+#define NT_QM_CELL_SIZE (152L)
+#define NT_QM_PRESENT (153L)
+#define NT_QSL_CATEGORIES (154L)
+#define NT_QSL_COLOR_SEL_BW (155L)
+#define NT_QSL_QST_SIZE (156L)
+#define NT_QUEUES (157L)
+#define NT_RAC_RAB_INTERFACES (158L)
+#define NT_RAC_RAB_OB_UPDATE (159L)
+#define NT_REVISION_ID (160L)
+#define NT_RMC_LAG_GROUPS (161L)
+#define NT_ROA_CATEGORIES (162L)
+#define NT_ROA_PRESENT (163L)
+#define NT_RPP_PER_PS (164L)
+#define NT_RTX_PRESENT (165L)
+#define NT_RX_HOST_BUFFERS (166L)
+#define NT_RX_PORTS (167L)
+#define NT_RX_PORT_REPLICATE (168L)
+#define NT_SLB_PRESENT (169L)
+#define NT_SLC_LR_PRESENT (170L)
+#define NT_STA_COLORS (171L)
+#define NT_STA_RX_PORTS (172L)
+#define NT_TBH_DEBUG_DLN (173L)
+#define NT_TBH_PRESENT (174L)
+#define NT_TFD_PRESENT (175L)
+#define NT_TPE_CATEGORIES (176L)
+#define NT_TSM_OST_ONLY (177L)
+#define NT_TS_APPEND (178L)
+#define NT_TS_INJECT_PRESENT (179L)
+#define NT_TX_CPY_PACKET_READERS (180L)
+#define NT_TX_CPY_PRESENT (181L)
+#define NT_TX_CPY_SIDEBAND_READERS (182L)
+#define NT_TX_CPY_VARIANT (183L)
+#define NT_TX_CPY_WRITERS (184L)
+#define NT_TX_HOST_BUFFERS (185L)
+#define NT_TX_INS_PRESENT (186L)
+#define NT_TX_MTU_PROFILE_IFR (187L)
+#define NT_TX_ON_TIMESTAMP (188L)
+#define NT_TX_PORTS (189L)
+#define NT_TX_PORT_REPLICATE (190L)
+#define NT_TX_RPL_DEPTH (191L)
+#define NT_TX_RPL_EXT_CATEGORIES (192L)
+#define NT_TX_RPL_PRESENT (193L)
+#define NT_TYPE_ID (194L)
+#define NT_USE_TRIPLE_SPEED (195L)
+#define NT_UUID (196L)
+#define NT_VERSION (197L)
+#define NT_VERSION_ID (198L)
+#define NT_VLI_PRESENT (199L)
+
+#endif /* _NTHW_FPGA_PARAMETERS_DEFS_ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h
new file mode 100644
index 0000000000..9d0c30b20c
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h
@@ -0,0 +1,7277 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_FPGA_REGISTERS_DEFS_
+#define _NTHW_FPGA_REGISTERS_DEFS_
+
+/* CAT */
+#define CAT_CCE_CTRL (1000L)
+#define CAT_CCE_CTRL_ADR (1001L)
+#define CAT_CCE_CTRL_CNT (1002L)
+#define CAT_CCE_DATA (1003L)
+#define CAT_CCE_DATA_IMM (1004L)
+#define CAT_CCE_DATA_IND (1005L)
+#define CAT_CCS_CTRL (1006L)
+#define CAT_CCS_CTRL_ADR (1007L)
+#define CAT_CCS_CTRL_CNT (1008L)
+#define CAT_CCS_DATA (1009L)
+#define CAT_CCS_DATA_COR (1010L)
+#define CAT_CCS_DATA_COR_EN (1011L)
+#define CAT_CCS_DATA_EPP (1012L)
+#define CAT_CCS_DATA_EPP_EN (1013L)
+#define CAT_CCS_DATA_HSH (1014L)
+#define CAT_CCS_DATA_HSH_EN (1015L)
+#define CAT_CCS_DATA_HST (1016L)
+#define CAT_CCS_DATA_HST_EN (1017L)
+#define CAT_CCS_DATA_IPF (1018L)
+#define CAT_CCS_DATA_IPF_EN (1019L)
+#define CAT_CCS_DATA_MSK (1020L)
+#define CAT_CCS_DATA_MSK_EN (1021L)
+#define CAT_CCS_DATA_PDB (1022L)
+#define CAT_CCS_DATA_PDB_EN (1023L)
+#define CAT_CCS_DATA_QSL (1024L)
+#define CAT_CCS_DATA_QSL_EN (1025L)
+#define CAT_CCS_DATA_RRB (1026L)
+#define CAT_CCS_DATA_RRB_EN (1027L)
+#define CAT_CCS_DATA_SB0_DATA (1028L)
+#define CAT_CCS_DATA_SB0_TYPE (1029L)
+#define CAT_CCS_DATA_SB1_DATA (1030L)
+#define CAT_CCS_DATA_SB1_TYPE (1031L)
+#define CAT_CCS_DATA_SB2_DATA (1032L)
+#define CAT_CCS_DATA_SB2_TYPE (1033L)
+#define CAT_CCS_DATA_SLC (1034L)
+#define CAT_CCS_DATA_SLC_EN (1035L)
+#define CAT_CCS_DATA_TPE (1036L)
+#define CAT_CCS_DATA_TPE_EN (1037L)
+#define CAT_CCT_CTRL (1038L)
+#define CAT_CCT_CTRL_ADR (1039L)
+#define CAT_CCT_CTRL_CNT (1040L)
+#define CAT_CCT_DATA (1041L)
+#define CAT_CCT_DATA_COLOR (1042L)
+#define CAT_CCT_DATA_KM (1043L)
+#define CAT_CFN_CTRL (1044L)
+#define CAT_CFN_CTRL_ADR (1045L)
+#define CAT_CFN_CTRL_CNT (1046L)
+#define CAT_CFN_DATA (1047L)
+#define CAT_CFN_DATA_ENABLE (1048L)
+#define CAT_CFN_DATA_ERR_CV (1049L)
+#define CAT_CFN_DATA_ERR_FCS (1050L)
+#define CAT_CFN_DATA_ERR_INV (1051L)
+#define CAT_CFN_DATA_ERR_L3_CS (1052L)
+#define CAT_CFN_DATA_ERR_L4_CS (1053L)
+#define CAT_CFN_DATA_ERR_TNL_L3_CS (1054L)
+#define CAT_CFN_DATA_ERR_TNL_L4_CS (1055L)
+#define CAT_CFN_DATA_ERR_TNL_TTL_EXP (1056L)
+#define CAT_CFN_DATA_ERR_TRUNC (1057L)
+#define CAT_CFN_DATA_ERR_TTL_EXP (1058L)
+#define CAT_CFN_DATA_FLM_OR (1059L)
+#define CAT_CFN_DATA_INV (1060L)
+#define CAT_CFN_DATA_KM0_OR (1061L)
+#define CAT_CFN_DATA_KM1_OR (1062L)
+#define CAT_CFN_DATA_KM_OR (1063L)
+#define CAT_CFN_DATA_LC (1064L)
+#define CAT_CFN_DATA_LC_INV (1065L)
+#define CAT_CFN_DATA_MAC_PORT (1066L)
+#define CAT_CFN_DATA_PM_AND_INV (1067L)
+#define CAT_CFN_DATA_PM_CMB (1068L)
+#define CAT_CFN_DATA_PM_CMP (1069L)
+#define CAT_CFN_DATA_PM_DCT (1070L)
+#define CAT_CFN_DATA_PM_EXT_INV (1071L)
+#define CAT_CFN_DATA_PM_INV (1072L)
+#define CAT_CFN_DATA_PM_OR_INV (1073L)
+#define CAT_CFN_DATA_PTC_CFP (1074L)
+#define CAT_CFN_DATA_PTC_FRAG (1075L)
+#define CAT_CFN_DATA_PTC_INV (1076L)
+#define CAT_CFN_DATA_PTC_IP_PROT (1077L)
+#define CAT_CFN_DATA_PTC_ISL (1078L)
+#define CAT_CFN_DATA_PTC_L2 (1079L)
+#define CAT_CFN_DATA_PTC_L3 (1080L)
+#define CAT_CFN_DATA_PTC_L4 (1081L)
+#define CAT_CFN_DATA_PTC_MAC (1082L)
+#define CAT_CFN_DATA_PTC_MPLS (1083L)
+#define CAT_CFN_DATA_PTC_TNL_FRAG (1084L)
+#define CAT_CFN_DATA_PTC_TNL_IP_PROT (1085L)
+#define CAT_CFN_DATA_PTC_TNL_L2 (1086L)
+#define CAT_CFN_DATA_PTC_TNL_L3 (1087L)
+#define CAT_CFN_DATA_PTC_TNL_L4 (1088L)
+#define CAT_CFN_DATA_PTC_TNL_MPLS (1089L)
+#define CAT_CFN_DATA_PTC_TNL_VLAN (1090L)
+#define CAT_CFN_DATA_PTC_TUNNEL (1091L)
+#define CAT_CFN_DATA_PTC_VLAN (1092L)
+#define CAT_CFN_DATA_PTC_VNTAG (1093L)
+#define CAT_COT_CTRL (1094L)
+#define CAT_COT_CTRL_ADR (1095L)
+#define CAT_COT_CTRL_CNT (1096L)
+#define CAT_COT_DATA (1097L)
+#define CAT_COT_DATA_COLOR (1098L)
+#define CAT_COT_DATA_KM (1099L)
+#define CAT_COT_DATA_NFV_SB (1100L)
+#define CAT_CTE_CTRL (1101L)
+#define CAT_CTE_CTRL_ADR (1102L)
+#define CAT_CTE_CTRL_CNT (1103L)
+#define CAT_CTE_DATA (1104L)
+#define CAT_CTE_DATA_COL_ENABLE (1105L)
+#define CAT_CTE_DATA_COR_ENABLE (1106L)
+#define CAT_CTE_DATA_EPP_ENABLE (1107L)
+#define CAT_CTE_DATA_HSH_ENABLE (1108L)
+#define CAT_CTE_DATA_HST_ENABLE (1109L)
+#define CAT_CTE_DATA_IPF_ENABLE (1110L)
+#define CAT_CTE_DATA_MSK_ENABLE (1111L)
+#define CAT_CTE_DATA_PDB_ENABLE (1112L)
+#define CAT_CTE_DATA_QSL_ENABLE (1113L)
+#define CAT_CTE_DATA_RRB_ENABLE (1114L)
+#define CAT_CTE_DATA_SLC_ENABLE (1115L)
+#define CAT_CTE_DATA_TPE_ENABLE (1116L)
+#define CAT_CTE_DATA_TX_INS_ENABLE (1117L)
+#define CAT_CTE_DATA_TX_RPL_ENABLE (1118L)
+#define CAT_CTS_CTRL (1119L)
+#define CAT_CTS_CTRL_ADR (1120L)
+#define CAT_CTS_CTRL_CNT (1121L)
+#define CAT_CTS_DATA (1122L)
+#define CAT_CTS_DATA_CAT_A (1123L)
+#define CAT_CTS_DATA_CAT_B (1124L)
+#define CAT_DCT_CTRL (1125L)
+#define CAT_DCT_CTRL_ADR (1126L)
+#define CAT_DCT_CTRL_CNT (1127L)
+#define CAT_DCT_DATA (1128L)
+#define CAT_DCT_DATA_RES (1129L)
+#define CAT_DCT_SEL (1130L)
+#define CAT_DCT_SEL_LU (1131L)
+#define CAT_EXO_CTRL (1132L)
+#define CAT_EXO_CTRL_ADR (1133L)
+#define CAT_EXO_CTRL_CNT (1134L)
+#define CAT_EXO_DATA (1135L)
+#define CAT_EXO_DATA_DYN (1136L)
+#define CAT_EXO_DATA_OFS (1137L)
+#define CAT_FCE_CTRL (1138L)
+#define CAT_FCE_CTRL_ADR (1139L)
+#define CAT_FCE_CTRL_CNT (1140L)
+#define CAT_FCE_DATA (1141L)
+#define CAT_FCE_DATA_ENABLE (1142L)
+#define CAT_FCS_CTRL (1143L)
+#define CAT_FCS_CTRL_ADR (1144L)
+#define CAT_FCS_CTRL_CNT (1145L)
+#define CAT_FCS_DATA (1146L)
+#define CAT_FCS_DATA_CATEGORY (1147L)
+#define CAT_FTE0_CTRL (1148L)
+#define CAT_FTE0_CTRL_ADR (1149L)
+#define CAT_FTE0_CTRL_CNT (1150L)
+#define CAT_FTE0_DATA (1151L)
+#define CAT_FTE0_DATA_ENABLE (1152L)
+#define CAT_FTE1_CTRL (1153L)
+#define CAT_FTE1_CTRL_ADR (1154L)
+#define CAT_FTE1_CTRL_CNT (1155L)
+#define CAT_FTE1_DATA (1156L)
+#define CAT_FTE1_DATA_ENABLE (1157L)
+#define CAT_FTE_CTRL (1158L)
+#define CAT_FTE_CTRL_ADR (1159L)
+#define CAT_FTE_CTRL_CNT (1160L)
+#define CAT_FTE_DATA (1161L)
+#define CAT_FTE_DATA_ENABLE (1162L)
+#define CAT_FTE_FLM_CTRL (1163L)
+#define CAT_FTE_FLM_CTRL_ADR (1164L)
+#define CAT_FTE_FLM_CTRL_CNT (1165L)
+#define CAT_FTE_FLM_DATA (1166L)
+#define CAT_FTE_FLM_DATA_ENABLE (1167L)
+#define CAT_JOIN (1168L)
+#define CAT_JOIN_J1 (1169L)
+#define CAT_JOIN_J2 (1170L)
+#define CAT_KCC (1171L)
+#define CAT_KCC_CTRL (1172L)
+#define CAT_KCC_CTRL_ADR (1173L)
+#define CAT_KCC_CTRL_CNT (1174L)
+#define CAT_KCC_DATA (1175L)
+#define CAT_KCC_DATA_CATEGORY (1176L)
+#define CAT_KCC_DATA_ID (1177L)
+#define CAT_KCC_DATA_KEY (1178L)
+#define CAT_KCE0_CTRL (1179L)
+#define CAT_KCE0_CTRL_ADR (1180L)
+#define CAT_KCE0_CTRL_CNT (1181L)
+#define CAT_KCE0_DATA (1182L)
+#define CAT_KCE0_DATA_ENABLE (1183L)
+#define CAT_KCE1_CTRL (1184L)
+#define CAT_KCE1_CTRL_ADR (1185L)
+#define CAT_KCE1_CTRL_CNT (1186L)
+#define CAT_KCE1_DATA (1187L)
+#define CAT_KCE1_DATA_ENABLE (1188L)
+#define CAT_KCE_CTRL (1189L)
+#define CAT_KCE_CTRL_ADR (1190L)
+#define CAT_KCE_CTRL_CNT (1191L)
+#define CAT_KCE_DATA (1192L)
+#define CAT_KCE_DATA_ENABLE (1193L)
+#define CAT_KCS0_CTRL (1194L)
+#define CAT_KCS0_CTRL_ADR (1195L)
+#define CAT_KCS0_CTRL_CNT (1196L)
+#define CAT_KCS0_DATA (1197L)
+#define CAT_KCS0_DATA_CATEGORY (1198L)
+#define CAT_KCS1_CTRL (1199L)
+#define CAT_KCS1_CTRL_ADR (1200L)
+#define CAT_KCS1_CTRL_CNT (1201L)
+#define CAT_KCS1_DATA (1202L)
+#define CAT_KCS1_DATA_CATEGORY (1203L)
+#define CAT_KCS_CTRL (1204L)
+#define CAT_KCS_CTRL_ADR (1205L)
+#define CAT_KCS_CTRL_CNT (1206L)
+#define CAT_KCS_DATA (1207L)
+#define CAT_KCS_DATA_CATEGORY (1208L)
+#define CAT_LEN_CTRL (1209L)
+#define CAT_LEN_CTRL_ADR (1210L)
+#define CAT_LEN_CTRL_CNT (1211L)
+#define CAT_LEN_DATA (1212L)
+#define CAT_LEN_DATA_DYN1 (1213L)
+#define CAT_LEN_DATA_DYN2 (1214L)
+#define CAT_LEN_DATA_INV (1215L)
+#define CAT_LEN_DATA_LOWER (1216L)
+#define CAT_LEN_DATA_UPPER (1217L)
+#define CAT_RCK_CTRL (1218L)
+#define CAT_RCK_CTRL_ADR (1219L)
+#define CAT_RCK_CTRL_CNT (1220L)
+#define CAT_RCK_DATA (1221L)
+#define CAT_RCK_DATA_CM0U (1222L)
+#define CAT_RCK_DATA_CM1U (1223L)
+#define CAT_RCK_DATA_CM2U (1224L)
+#define CAT_RCK_DATA_CM3U (1225L)
+#define CAT_RCK_DATA_CM4U (1226L)
+#define CAT_RCK_DATA_CM5U (1227L)
+#define CAT_RCK_DATA_CM6U (1228L)
+#define CAT_RCK_DATA_CM7U (1229L)
+#define CAT_RCK_DATA_CML0 (1230L)
+#define CAT_RCK_DATA_CML1 (1231L)
+#define CAT_RCK_DATA_CML2 (1232L)
+#define CAT_RCK_DATA_CML3 (1233L)
+#define CAT_RCK_DATA_CML4 (1234L)
+#define CAT_RCK_DATA_CML5 (1235L)
+#define CAT_RCK_DATA_CML6 (1236L)
+#define CAT_RCK_DATA_CML7 (1237L)
+#define CAT_RCK_DATA_SEL0 (1238L)
+#define CAT_RCK_DATA_SEL1 (1239L)
+#define CAT_RCK_DATA_SEL2 (1240L)
+#define CAT_RCK_DATA_SEL3 (1241L)
+#define CAT_RCK_DATA_SEL4 (1242L)
+#define CAT_RCK_DATA_SEL5 (1243L)
+#define CAT_RCK_DATA_SEL6 (1244L)
+#define CAT_RCK_DATA_SEL7 (1245L)
+#define CAT_RCK_DATA_SEU0 (1246L)
+#define CAT_RCK_DATA_SEU1 (1247L)
+#define CAT_RCK_DATA_SEU2 (1248L)
+#define CAT_RCK_DATA_SEU3 (1249L)
+#define CAT_RCK_DATA_SEU4 (1250L)
+#define CAT_RCK_DATA_SEU5 (1251L)
+#define CAT_RCK_DATA_SEU6 (1252L)
+#define CAT_RCK_DATA_SEU7 (1253L)
+/* CB */
+#define CB_CTRL (1254L)
+#define CB_CTRL_BP (1255L)
+#define CB_CTRL_BYPASS (1256L)
+#define CB_CTRL_ENABLE (1257L)
+#define CB_CTRL_QMA (1258L)
+#define CB_CTRL_QME (1259L)
+#define CB_DBG_BP (1260L)
+#define CB_DBG_BP_CNT (1261L)
+#define CB_DBG_DQ (1262L)
+#define CB_DBG_DQ_MAX (1263L)
+#define CB_DBG_EGS_QUEUE (1264L)
+#define CB_DBG_EGS_QUEUE_ADD (1265L)
+#define CB_DBG_EGS_QUEUE_AND (1266L)
+#define CB_DBG_FREE1200 (1267L)
+#define CB_DBG_FREE1200_CNT (1268L)
+#define CB_DBG_FREE1800 (1269L)
+#define CB_DBG_FREE1800_CNT (1270L)
+#define CB_DBG_FREE600 (1271L)
+#define CB_DBG_FREE600_CNT (1272L)
+#define CB_DBG_H16 (1273L)
+#define CB_DBG_H16_CNT (1274L)
+#define CB_DBG_H32 (1275L)
+#define CB_DBG_H32_CNT (1276L)
+#define CB_DBG_H64 (1277L)
+#define CB_DBG_H64_CNT (1278L)
+#define CB_DBG_HAVE (1279L)
+#define CB_DBG_HAVE_CNT (1280L)
+#define CB_DBG_IGS_QUEUE (1281L)
+#define CB_DBG_IGS_QUEUE_ADD (1282L)
+#define CB_DBG_IGS_QUEUE_AND (1283L)
+#define CB_DBG_QM_CELL_CNT (1284L)
+#define CB_DBG_QM_CELL_CNT_CNT (1285L)
+#define CB_DBG_QM_CELL_XOR (1286L)
+#define CB_DBG_QM_CELL_XOR_XOR (1287L)
+#define CB_QPM_CTRL (1288L)
+#define CB_QPM_CTRL_ADR (1289L)
+#define CB_QPM_CTRL_CNT (1290L)
+#define CB_QPM_DATA (1291L)
+#define CB_QPM_DATA_P (1292L)
+#define CB_QUEUE_MAX (1293L)
+#define CB_QUEUE_MAX_MAX (1294L)
+#define CB_STATUS (1295L)
+#define CB_STATUS_BP (1296L)
+#define CB_STATUS_DB (1297L)
+#define CB_STATUS_EMPTY (1298L)
+#define CB_STATUS_IDLE (1299L)
+#define CB_STATUS_OVF (1300L)
+#define CB_TS_RATE (1301L)
+#define CB_TS_RATE_CNT (1302L)
+#define CB_TS_SAVE (1303L)
+#define CB_TS_SAVE_MAX (1304L)
+/* CCIP */
+#define CCIP_AFU_ID_L (1305L)
+#define CCIP_AFU_ID_L_ID (1306L)
+#define CCIP_AFU_ID_U (1307L)
+#define CCIP_AFU_ID_U_ID (1308L)
+#define CCIP_CONTROL (1309L)
+#define CCIP_CONTROL_FENCE (1310L)
+#define CCIP_DFH (1311L)
+#define CCIP_DFH_AFU_VER_MAJOR (1312L)
+#define CCIP_DFH_AFU_VER_MINOR (1313L)
+#define CCIP_DFH_CCIP_VER (1314L)
+#define CCIP_DFH_END (1315L)
+#define CCIP_DFH_FEATURE_TYPE (1316L)
+#define CCIP_DFH_NEXT (1317L)
+#define CCIP_RSVD0 (1318L)
+#define CCIP_RSVD0_RSVD (1319L)
+#define CCIP_RSVD1 (1320L)
+#define CCIP_RSVD1_RSVD (1321L)
+#define CCIP_STATUS (1322L)
+#define CCIP_STATUS_ERR (1323L)
+#define CCIP_STATUS_PWR (1324L)
+/* CFP4_CTRL_GBOX */
+#define CFP4_CTRL_GBOX_CFG (1325L)
+#define CFP4_CTRL_GBOX_CFG_GLB_ALARMN (1326L)
+#define CFP4_CTRL_GBOX_CFG_INTERR (1327L)
+#define CFP4_CTRL_GBOX_CFG_MOD_ABS (1328L)
+#define CFP4_CTRL_GBOX_CFG_MOD_LOPWR (1329L)
+#define CFP4_CTRL_GBOX_CFG_MOD_RSTN (1330L)
+#define CFP4_CTRL_GBOX_CFG_NRESET (1331L)
+#define CFP4_CTRL_GBOX_CFG_RXLOS (1332L)
+#define CFP4_CTRL_GBOX_CFG_TXDIS (1333L)
+#define CFP4_CTRL_GBOX_CFP4 (1334L)
+#define CFP4_CTRL_GBOX_CFP4_GLB_ALARMN (1335L)
+#define CFP4_CTRL_GBOX_CFP4_MOD_ABS (1336L)
+#define CFP4_CTRL_GBOX_CFP4_MOD_LOPWR (1337L)
+#define CFP4_CTRL_GBOX_CFP4_MOD_RSTN (1338L)
+#define CFP4_CTRL_GBOX_CFP4_RXLOS (1339L)
+#define CFP4_CTRL_GBOX_CFP4_TXDIS (1340L)
+#define CFP4_CTRL_GBOX_GBOX (1341L)
+#define CFP4_CTRL_GBOX_GBOX_INTERR (1342L)
+#define CFP4_CTRL_GBOX_GBOX_NRESET (1343L)
+#define CFP4_CTRL_GBOX_GPIO (1344L)
+#define CFP4_CTRL_GBOX_GPIO_GLB_ALARMN (1345L)
+#define CFP4_CTRL_GBOX_GPIO_INTERR (1346L)
+#define CFP4_CTRL_GBOX_GPIO_MOD_ABS (1347L)
+#define CFP4_CTRL_GBOX_GPIO_MOD_LOPWR (1348L)
+#define CFP4_CTRL_GBOX_GPIO_MOD_RSTN (1349L)
+#define CFP4_CTRL_GBOX_GPIO_NRESET (1350L)
+#define CFP4_CTRL_GBOX_GPIO_RXLOS (1351L)
+#define CFP4_CTRL_GBOX_GPIO_TXDIS (1352L)
+/* COR */
+#define COR_CTRL (1393L)
+#define COR_CTRL_EN (1394L)
+#define COR_DBG_COR_CNT (1395L)
+#define COR_DBG_COR_CNT_VAL (1396L)
+#define COR_DBG_COR_ID (1397L)
+#define COR_DBG_COR_ID_VAL (1398L)
+#define COR_DBG_COR_LO (1399L)
+#define COR_DBG_COR_LO_VAL (1400L)
+#define COR_DBG_COR_UP (1401L)
+#define COR_DBG_COR_UP_VAL (1402L)
+#define COR_DCEO (1403L)
+#define COR_DCEO_VAL (1404L)
+#define COR_DCSO (1405L)
+#define COR_DCSO_VAL (1406L)
+#define COR_DEEO (1407L)
+#define COR_DEEO_VAL (1408L)
+#define COR_DEO (1409L)
+#define COR_DEO_VAL (1410L)
+#define COR_DESO (1411L)
+#define COR_DESO_VAL (1412L)
+#define COR_DSEO (1413L)
+#define COR_DSEO_VAL (1414L)
+#define COR_DSO (1415L)
+#define COR_DSO_VAL (1416L)
+#define COR_DSSO (1417L)
+#define COR_DSSO_VAL (1418L)
+#define COR_RCP_CTRL (1419L)
+#define COR_RCP_CTRL_ADR (1420L)
+#define COR_RCP_CTRL_CNT (1421L)
+#define COR_RCP_DATA (1422L)
+#define COR_RCP_DATA_CBM1 (1423L)
+#define COR_RCP_DATA_EN (1424L)
+#define COR_RCP_DATA_END_PROT (1425L)
+#define COR_RCP_DATA_END_STATIC (1426L)
+#define COR_RCP_DATA_IP_CHK (1427L)
+#define COR_RCP_DATA_IP_DSCP (1428L)
+#define COR_RCP_DATA_IP_DST (1429L)
+#define COR_RCP_DATA_IP_ECN (1430L)
+#define COR_RCP_DATA_IP_FLAGS (1431L)
+#define COR_RCP_DATA_IP_FLOW (1432L)
+#define COR_RCP_DATA_IP_HOP (1433L)
+#define COR_RCP_DATA_IP_IDENT (1434L)
+#define COR_RCP_DATA_IP_NXTHDR (1435L)
+#define COR_RCP_DATA_IP_SRC (1436L)
+#define COR_RCP_DATA_IP_TC (1437L)
+#define COR_RCP_DATA_IP_TTL (1438L)
+#define COR_RCP_DATA_MAX_LEN (1439L)
+#define COR_RCP_DATA_PROT_OFS1 (1440L)
+#define COR_RCP_DATA_START_PROT (1441L)
+#define COR_RCP_DATA_START_STATIC (1442L)
+#define COR_RCP_DATA_STTC_OFS1 (1443L)
+#define COR_RCP_DATA_TCP_CHK (1444L)
+#define COR_RCP_DATA_TCP_DST (1445L)
+#define COR_RCP_DATA_TCP_SEQ (1446L)
+#define COR_RCP_DATA_TCP_SRC (1447L)
+#define COR_RCP_DATA_TNL (1448L)
+#define COR_RCP_DATA_UDP_CHK (1449L)
+#define COR_RCP_DATA_UDP_DST (1450L)
+#define COR_RCP_DATA_UDP_SRC (1451L)
+/* CPY */
+#define CPY_WRITER0_CTRL (1452L)
+#define CPY_WRITER0_CTRL_ADR (1453L)
+#define CPY_WRITER0_CTRL_CNT (1454L)
+#define CPY_WRITER0_DATA (1455L)
+#define CPY_WRITER0_DATA_DYN (1456L)
+#define CPY_WRITER0_DATA_LEN (1457L)
+#define CPY_WRITER0_DATA_MASK_POINTER (1458L)
+#define CPY_WRITER0_DATA_OFS (1459L)
+#define CPY_WRITER0_DATA_READER_SELECT (1460L)
+#define CPY_WRITER0_MASK_CTRL (1461L)
+#define CPY_WRITER0_MASK_CTRL_ADR (1462L)
+#define CPY_WRITER0_MASK_CTRL_CNT (1463L)
+#define CPY_WRITER0_MASK_DATA (1464L)
+#define CPY_WRITER0_MASK_DATA_BYTE_MASK (1465L)
+#define CPY_WRITER1_CTRL (1466L)
+#define CPY_WRITER1_CTRL_ADR (1467L)
+#define CPY_WRITER1_CTRL_CNT (1468L)
+#define CPY_WRITER1_DATA (1469L)
+#define CPY_WRITER1_DATA_DYN (1470L)
+#define CPY_WRITER1_DATA_LEN (1471L)
+#define CPY_WRITER1_DATA_MASK_POINTER (1472L)
+#define CPY_WRITER1_DATA_OFS (1473L)
+#define CPY_WRITER1_DATA_READER_SELECT (1474L)
+#define CPY_WRITER1_MASK_CTRL (1475L)
+#define CPY_WRITER1_MASK_CTRL_ADR (1476L)
+#define CPY_WRITER1_MASK_CTRL_CNT (1477L)
+#define CPY_WRITER1_MASK_DATA (1478L)
+#define CPY_WRITER1_MASK_DATA_BYTE_MASK (1479L)
+#define CPY_WRITER2_CTRL (1480L)
+#define CPY_WRITER2_CTRL_ADR (1481L)
+#define CPY_WRITER2_CTRL_CNT (1482L)
+#define CPY_WRITER2_DATA (1483L)
+#define CPY_WRITER2_DATA_DYN (1484L)
+#define CPY_WRITER2_DATA_LEN (1485L)
+#define CPY_WRITER2_DATA_MASK_POINTER (1486L)
+#define CPY_WRITER2_DATA_OFS (1487L)
+#define CPY_WRITER2_DATA_READER_SELECT (1488L)
+#define CPY_WRITER2_MASK_CTRL (1489L)
+#define CPY_WRITER2_MASK_CTRL_ADR (1490L)
+#define CPY_WRITER2_MASK_CTRL_CNT (1491L)
+#define CPY_WRITER2_MASK_DATA (1492L)
+#define CPY_WRITER2_MASK_DATA_BYTE_MASK (1493L)
+#define CPY_WRITER3_CTRL (1494L)
+#define CPY_WRITER3_CTRL_ADR (1495L)
+#define CPY_WRITER3_CTRL_CNT (1496L)
+#define CPY_WRITER3_DATA (1497L)
+#define CPY_WRITER3_DATA_DYN (1498L)
+#define CPY_WRITER3_DATA_LEN (1499L)
+#define CPY_WRITER3_DATA_MASK_POINTER (1500L)
+#define CPY_WRITER3_DATA_OFS (1501L)
+#define CPY_WRITER3_DATA_READER_SELECT (1502L)
+#define CPY_WRITER3_MASK_CTRL (1503L)
+#define CPY_WRITER3_MASK_CTRL_ADR (1504L)
+#define CPY_WRITER3_MASK_CTRL_CNT (1505L)
+#define CPY_WRITER3_MASK_DATA (1506L)
+#define CPY_WRITER3_MASK_DATA_BYTE_MASK (1507L)
+#define CPY_WRITER4_CTRL (1508L)
+#define CPY_WRITER4_CTRL_ADR (1509L)
+#define CPY_WRITER4_CTRL_CNT (1510L)
+#define CPY_WRITER4_DATA (1511L)
+#define CPY_WRITER4_DATA_DYN (1512L)
+#define CPY_WRITER4_DATA_LEN (1513L)
+#define CPY_WRITER4_DATA_MASK_POINTER (1514L)
+#define CPY_WRITER4_DATA_OFS (1515L)
+#define CPY_WRITER4_DATA_READER_SELECT (1516L)
+#define CPY_WRITER4_MASK_CTRL (1517L)
+#define CPY_WRITER4_MASK_CTRL_ADR (1518L)
+#define CPY_WRITER4_MASK_CTRL_CNT (1519L)
+#define CPY_WRITER4_MASK_DATA (1520L)
+#define CPY_WRITER4_MASK_DATA_BYTE_MASK (1521L)
+#define CPY_WRITER5_CTRL (1522L)
+#define CPY_WRITER5_CTRL_ADR (1523L)
+#define CPY_WRITER5_CTRL_CNT (1524L)
+#define CPY_WRITER5_DATA (1525L)
+#define CPY_WRITER5_DATA_DYN (1526L)
+#define CPY_WRITER5_DATA_LEN (1527L)
+#define CPY_WRITER5_DATA_MASK_POINTER (1528L)
+#define CPY_WRITER5_DATA_OFS (1529L)
+#define CPY_WRITER5_DATA_READER_SELECT (1530L)
+#define CPY_WRITER5_MASK_CTRL (1531L)
+#define CPY_WRITER5_MASK_CTRL_ADR (1532L)
+#define CPY_WRITER5_MASK_CTRL_CNT (1533L)
+#define CPY_WRITER5_MASK_DATA (1534L)
+#define CPY_WRITER5_MASK_DATA_BYTE_MASK (1535L)
+/* CSU */
+#define CSU_RCP_CTRL (1536L)
+#define CSU_RCP_CTRL_ADR (1537L)
+#define CSU_RCP_CTRL_CNT (1538L)
+#define CSU_RCP_DATA (1539L)
+#define CSU_RCP_DATA_IL3_CMD (1540L)
+#define CSU_RCP_DATA_IL4_CMD (1541L)
+#define CSU_RCP_DATA_OL3_CMD (1542L)
+#define CSU_RCP_DATA_OL4_CMD (1543L)
+/* DBS */
+#define DBS_RX_AM_CTRL (1544L)
+#define DBS_RX_AM_CTRL_ADR (1545L)
+#define DBS_RX_AM_CTRL_CNT (1546L)
+#define DBS_RX_AM_DATA (1547L)
+#define DBS_RX_AM_DATA_ENABLE (1548L)
+#define DBS_RX_AM_DATA_GPA (1549L)
+#define DBS_RX_AM_DATA_HID (1550L)
+#define DBS_RX_AM_DATA_INT (1551L)
+#define DBS_RX_AM_DATA_PCKED (1552L)
+#define DBS_RX_CONTROL (1553L)
+#define DBS_RX_CONTROL_AME (1554L)
+#define DBS_RX_CONTROL_AMS (1555L)
+#define DBS_RX_CONTROL_LQ (1556L)
+#define DBS_RX_CONTROL_QE (1557L)
+#define DBS_RX_CONTROL_UWE (1558L)
+#define DBS_RX_CONTROL_UWS (1559L)
+#define DBS_RX_DR_CTRL (1560L)
+#define DBS_RX_DR_CTRL_ADR (1561L)
+#define DBS_RX_DR_CTRL_CNT (1562L)
+#define DBS_RX_DR_DATA (1563L)
+#define DBS_RX_DR_DATA_GPA (1564L)
+#define DBS_RX_DR_DATA_HDR (1565L)
+#define DBS_RX_DR_DATA_HID (1566L)
+#define DBS_RX_DR_DATA_PCKED (1567L)
+#define DBS_RX_DR_DATA_QS (1568L)
+#define DBS_RX_IDLE (1569L)
+#define DBS_RX_IDLE_BUSY (1570L)
+#define DBS_RX_IDLE_IDLE (1571L)
+#define DBS_RX_IDLE_QUEUE (1572L)
+#define DBS_RX_INIT (1573L)
+#define DBS_RX_INIT_BUSY (1574L)
+#define DBS_RX_INIT_INIT (1575L)
+#define DBS_RX_INIT_QUEUE (1576L)
+#define DBS_RX_INIT_VAL (1577L)
+#define DBS_RX_INIT_VAL_IDX (1578L)
+#define DBS_RX_INIT_VAL_PTR (1579L)
+#define DBS_RX_PTR (1580L)
+#define DBS_RX_PTR_PTR (1581L)
+#define DBS_RX_PTR_QUEUE (1582L)
+#define DBS_RX_PTR_VALID (1583L)
+#define DBS_RX_UW_CTRL (1584L)
+#define DBS_RX_UW_CTRL_ADR (1585L)
+#define DBS_RX_UW_CTRL_CNT (1586L)
+#define DBS_RX_UW_DATA (1587L)
+#define DBS_RX_UW_DATA_GPA (1588L)
+#define DBS_RX_UW_DATA_HID (1589L)
+#define DBS_RX_UW_DATA_INT (1590L)
+#define DBS_RX_UW_DATA_ISTK (1591L)
+#define DBS_RX_UW_DATA_PCKED (1592L)
+#define DBS_RX_UW_DATA_QS (1593L)
+#define DBS_RX_UW_DATA_VEC (1594L)
+#define DBS_STATUS (1595L)
+#define DBS_STATUS_OK (1596L)
+#define DBS_TX_AM_CTRL (1597L)
+#define DBS_TX_AM_CTRL_ADR (1598L)
+#define DBS_TX_AM_CTRL_CNT (1599L)
+#define DBS_TX_AM_DATA (1600L)
+#define DBS_TX_AM_DATA_ENABLE (1601L)
+#define DBS_TX_AM_DATA_GPA (1602L)
+#define DBS_TX_AM_DATA_HID (1603L)
+#define DBS_TX_AM_DATA_INT (1604L)
+#define DBS_TX_AM_DATA_PCKED (1605L)
+#define DBS_TX_CONTROL (1606L)
+#define DBS_TX_CONTROL_AME (1607L)
+#define DBS_TX_CONTROL_AMS (1608L)
+#define DBS_TX_CONTROL_LQ (1609L)
+#define DBS_TX_CONTROL_QE (1610L)
+#define DBS_TX_CONTROL_UWE (1611L)
+#define DBS_TX_CONTROL_UWS (1612L)
+#define DBS_TX_DR_CTRL (1613L)
+#define DBS_TX_DR_CTRL_ADR (1614L)
+#define DBS_TX_DR_CTRL_CNT (1615L)
+#define DBS_TX_DR_DATA (1616L)
+#define DBS_TX_DR_DATA_GPA (1617L)
+#define DBS_TX_DR_DATA_HDR (1618L)
+#define DBS_TX_DR_DATA_HID (1619L)
+#define DBS_TX_DR_DATA_PCKED (1620L)
+#define DBS_TX_DR_DATA_PORT (1621L)
+#define DBS_TX_DR_DATA_QS (1622L)
+#define DBS_TX_IDLE (1623L)
+#define DBS_TX_IDLE_BUSY (1624L)
+#define DBS_TX_IDLE_IDLE (1625L)
+#define DBS_TX_IDLE_QUEUE (1626L)
+#define DBS_TX_INIT (1627L)
+#define DBS_TX_INIT_BUSY (1628L)
+#define DBS_TX_INIT_INIT (1629L)
+#define DBS_TX_INIT_QUEUE (1630L)
+#define DBS_TX_INIT_VAL (1631L)
+#define DBS_TX_INIT_VAL_IDX (1632L)
+#define DBS_TX_INIT_VAL_PTR (1633L)
+#define DBS_TX_PTR (1634L)
+#define DBS_TX_PTR_PTR (1635L)
+#define DBS_TX_PTR_QUEUE (1636L)
+#define DBS_TX_PTR_VALID (1637L)
+#define DBS_TX_QOS_CTRL (1638L)
+#define DBS_TX_QOS_CTRL_ADR (1639L)
+#define DBS_TX_QOS_CTRL_CNT (1640L)
+#define DBS_TX_QOS_DATA (1641L)
+#define DBS_TX_QOS_DATA_BS (1642L)
+#define DBS_TX_QOS_DATA_EN (1643L)
+#define DBS_TX_QOS_DATA_IR (1644L)
+#define DBS_TX_QOS_DATA_MUL (1645L)
+#define DBS_TX_QOS_RATE (1646L)
+#define DBS_TX_QOS_RATE_DIV (1647L)
+#define DBS_TX_QOS_RATE_MUL (1648L)
+#define DBS_TX_QP_CTRL (1649L)
+#define DBS_TX_QP_CTRL_ADR (1650L)
+#define DBS_TX_QP_CTRL_CNT (1651L)
+#define DBS_TX_QP_DATA (1652L)
+#define DBS_TX_QP_DATA_VPORT (1653L)
+#define DBS_TX_UW_CTRL (1654L)
+#define DBS_TX_UW_CTRL_ADR (1655L)
+#define DBS_TX_UW_CTRL_CNT (1656L)
+#define DBS_TX_UW_DATA (1657L)
+#define DBS_TX_UW_DATA_GPA (1658L)
+#define DBS_TX_UW_DATA_HID (1659L)
+#define DBS_TX_UW_DATA_INO (1660L)
+#define DBS_TX_UW_DATA_INT (1661L)
+#define DBS_TX_UW_DATA_ISTK (1662L)
+#define DBS_TX_UW_DATA_PCKED (1663L)
+#define DBS_TX_UW_DATA_QS (1664L)
+#define DBS_TX_UW_DATA_VEC (1665L)
+/* DDP */
+#define DDP_AGING_CTRL (1666L)
+#define DDP_AGING_CTRL_AGING_RATE (1667L)
+#define DDP_AGING_CTRL_MAX_CNT (1668L)
+#define DDP_CTRL (1669L)
+#define DDP_CTRL_INIT (1670L)
+#define DDP_CTRL_INIT_DONE (1671L)
+#define DDP_RCP_CTRL (1672L)
+#define DDP_RCP_CTRL_ADR (1673L)
+#define DDP_RCP_CTRL_CNT (1674L)
+#define DDP_RCP_DATA (1675L)
+#define DDP_RCP_DATA_EN (1676L)
+#define DDP_RCP_DATA_GROUPID (1677L)
+/* EPP */
+#define EPP_QUEUE_MTU_CTRL (1755L)
+#define EPP_QUEUE_MTU_CTRL_ADR (1756L)
+#define EPP_QUEUE_MTU_CTRL_CNT (1757L)
+#define EPP_QUEUE_MTU_DATA (1758L)
+#define EPP_QUEUE_MTU_DATA_MAX_MTU (1759L)
+#define EPP_QUEUE_VPORT_CTRL (1760L)
+#define EPP_QUEUE_VPORT_CTRL_ADR (1761L)
+#define EPP_QUEUE_VPORT_CTRL_CNT (1762L)
+#define EPP_QUEUE_VPORT_DATA (1763L)
+#define EPP_QUEUE_VPORT_DATA_VPORT (1764L)
+#define EPP_RCP_CTRL (1765L)
+#define EPP_RCP_CTRL_ADR (1766L)
+#define EPP_RCP_CTRL_CNT (1767L)
+#define EPP_RCP_DATA (1768L)
+#define EPP_RCP_DATA_FIXED_18B_L2_MTU (1769L)
+#define EPP_RCP_DATA_QUEUE_MTU_EPP_EN (1770L)
+#define EPP_RCP_DATA_QUEUE_QOS_EPP_EN (1771L)
+#define EPP_RCP_DATA_SIZE_ADJUST_TXP (1772L)
+#define EPP_RCP_DATA_SIZE_ADJUST_VPORT (1773L)
+#define EPP_RCP_DATA_TX_MTU_EPP_EN (1774L)
+#define EPP_RCP_DATA_TX_QOS_EPP_EN (1775L)
+#define EPP_TXP_MTU_CTRL (1776L)
+#define EPP_TXP_MTU_CTRL_ADR (1777L)
+#define EPP_TXP_MTU_CTRL_CNT (1778L)
+#define EPP_TXP_MTU_DATA (1779L)
+#define EPP_TXP_MTU_DATA_MAX_MTU (1780L)
+#define EPP_TXP_QOS_CTRL (1781L)
+#define EPP_TXP_QOS_CTRL_ADR (1782L)
+#define EPP_TXP_QOS_CTRL_CNT (1783L)
+#define EPP_TXP_QOS_DATA (1784L)
+#define EPP_TXP_QOS_DATA_BS (1785L)
+#define EPP_TXP_QOS_DATA_EN (1786L)
+#define EPP_TXP_QOS_DATA_IR (1787L)
+#define EPP_TXP_QOS_DATA_IR_FRACTION (1788L)
+#define EPP_VPORT_QOS_CTRL (1789L)
+#define EPP_VPORT_QOS_CTRL_ADR (1790L)
+#define EPP_VPORT_QOS_CTRL_CNT (1791L)
+#define EPP_VPORT_QOS_DATA (1792L)
+#define EPP_VPORT_QOS_DATA_BS (1793L)
+#define EPP_VPORT_QOS_DATA_EN (1794L)
+#define EPP_VPORT_QOS_DATA_IR (1795L)
+#define EPP_VPORT_QOS_DATA_IR_FRACTION (1796L)
+/* EQM */
+#define EQM_CTRL (1797L)
+#define EQM_CTRL_DBG_CRC_ERR (1798L)
+#define EQM_CTRL_DBG_FORCE_ERR (1799L)
+#define EQM_CTRL_DBG_RMT_ERR (1800L)
+#define EQM_CTRL_DBG_SYNC_ERR (1801L)
+#define EQM_CTRL_ENABLE (1802L)
+#define EQM_CTRL_MODE (1803L)
+#define EQM_CTRL_PP_RST (1804L)
+#define EQM_DBG (1805L)
+#define EQM_DBG_FIFO_OF (1806L)
+#define EQM_DBG_LCL_EGS_QKA_OF (1807L)
+#define EQM_DBG_LCL_EGS_QLVL_OF (1808L)
+#define EQM_DBG_QBLK_CREDITS (1809L)
+#define EQM_STATUS (1810L)
+#define EQM_STATUS_LCL_EGS_OF_ERR (1811L)
+#define EQM_STATUS_NIF_CRC_ERR (1812L)
+#define EQM_STATUS_NIF_PP_LOOP_LCK (1813L)
+#define EQM_STATUS_NIF_RX_OF_ERR (1814L)
+#define EQM_STATUS_NIF_SYNC_ERR (1815L)
+#define EQM_STATUS_QM_CRC_ERR (1816L)
+#define EQM_STATUS_RMT_EGS_OF_ERR (1817L)
+#define EQM_STATUS_RMT_ERR (1818L)
+#define EQM_STATUS_RMT_IGS_OF_ERR (1819L)
+/* FHM */
+#define FHM_BACK_PRESSURE (1820L)
+#define FHM_BACK_PRESSURE_NIF (1821L)
+#define FHM_BACK_PRESSURE_RMC (1822L)
+#define FHM_BACK_PRESSURE_RMC_S (1823L)
+#define FHM_CRC_ERROR_NIF (1824L)
+#define FHM_CRC_ERROR_NIF_CNT (1825L)
+#define FHM_CRC_ERROR_SDC (1826L)
+#define FHM_CRC_ERROR_SDC_CNT (1827L)
+#define FHM_CTRL (1828L)
+#define FHM_CTRL_CNT_CLR (1829L)
+#define FHM_CTRL_ENABLE (1830L)
+#define FHM_CTRL_MODE (1831L)
+#define FHM_DEBUG_CRC (1832L)
+#define FHM_DEBUG_CRC_FORCE_ERROR (1833L)
+#define FHM_DEBUG_SDRAM_SIZE (1834L)
+#define FHM_DEBUG_SDRAM_SIZE_MASK (1835L)
+#define FHM_FILL_LEVEL (1836L)
+#define FHM_FILL_LEVEL_CELLS (1837L)
+#define FHM_MAC_MICRO_DROP (1838L)
+#define FHM_MAC_MICRO_DROP_CNT (1839L)
+#define FHM_MAX_FILL_LEVEL (1840L)
+#define FHM_MAX_FILL_LEVEL_CELLS (1841L)
+#define FHM_PKT_DROP (1842L)
+#define FHM_PKT_DROP_CNT (1843L)
+#define FHM_PKT_DROP_BYTES (1844L)
+#define FHM_PKT_DROP_BYTES_CNT (1845L)
+/* FLM */
+#define FLM_BUF_CTRL (1855L)
+#define FLM_BUF_CTRL_INF_AVAIL (1856L)
+#define FLM_BUF_CTRL_LRN_FREE (1857L)
+#define FLM_BUF_CTRL_STA_AVAIL (1858L)
+#define FLM_CONTROL (1859L)
+#define FLM_CONTROL_CRCRD (1860L)
+#define FLM_CONTROL_CRCWR (1861L)
+#define FLM_CONTROL_EAB (1862L)
+#define FLM_CONTROL_ENABLE (1863L)
+#define FLM_CONTROL_INIT (1864L)
+#define FLM_CONTROL_LDS (1865L)
+#define FLM_CONTROL_LFS (1866L)
+#define FLM_CONTROL_LIS (1867L)
+#define FLM_CONTROL_PDS (1868L)
+#define FLM_CONTROL_PIS (1869L)
+#define FLM_CONTROL_RBL (1870L)
+#define FLM_CONTROL_RDS (1871L)
+#define FLM_CONTROL_RIS (1872L)
+#define FLM_CONTROL_SPLIT_SDRAM_USAGE (1873L)
+#define FLM_CONTROL_UDS (1874L)
+#define FLM_CONTROL_UIS (1875L)
+#define FLM_CONTROL_WPD (1876L)
+#define FLM_INF_DATA (1877L)
+#define FLM_INF_DATA_BYTES (1878L)
+#define FLM_INF_DATA_BYT_A (1879L)
+#define FLM_INF_DATA_BYT_B (1880L)
+#define FLM_INF_DATA_CAUSE (1881L)
+#define FLM_INF_DATA_EOR (1882L)
+#define FLM_INF_DATA_ID (1883L)
+#define FLM_INF_DATA_PACKETS (1884L)
+#define FLM_INF_DATA_PCK_A (1885L)
+#define FLM_INF_DATA_PCK_B (1886L)
+#define FLM_INF_DATA_RTX_A (1887L)
+#define FLM_INF_DATA_RTX_B (1888L)
+#define FLM_INF_DATA_TCP_A (1889L)
+#define FLM_INF_DATA_TCP_B (1890L)
+#define FLM_INF_DATA_TS (1891L)
+#define FLM_LOAD_APS (1892L)
+#define FLM_LOAD_APS_APS (1893L)
+#define FLM_LOAD_BIN (1894L)
+#define FLM_LOAD_BIN_BIN (1895L)
+#define FLM_LOAD_LPS (1896L)
+#define FLM_LOAD_LPS_LPS (1897L)
+#define FLM_LOAD_PPS (1898L)
+#define FLM_LOAD_PPS_PPS (1899L)
+#define FLM_LRN_CTRL (1900L)
+#define FLM_LRN_CTRL_FREE (1901L)
+#define FLM_LRN_DATA (1902L)
+#define FLM_LRN_DATA_ADJ (1903L)
+#define FLM_LRN_DATA_COLOR (1904L)
+#define FLM_LRN_DATA_DSCP (1905L)
+#define FLM_LRN_DATA_ENT (1906L)
+#define FLM_LRN_DATA_EOR (1907L)
+#define FLM_LRN_DATA_FILL (1908L)
+#define FLM_LRN_DATA_FT (1909L)
+#define FLM_LRN_DATA_FT_MBR (1910L)
+#define FLM_LRN_DATA_FT_MISS (1911L)
+#define FLM_LRN_DATA_GFI (1912L)
+#define FLM_LRN_DATA_ID (1913L)
+#define FLM_LRN_DATA_KID (1914L)
+#define FLM_LRN_DATA_MBR_ID1 (1915L)
+#define FLM_LRN_DATA_MBR_ID2 (1916L)
+#define FLM_LRN_DATA_MBR_ID3 (1917L)
+#define FLM_LRN_DATA_MBR_ID4 (1918L)
+#define FLM_LRN_DATA_NAT_EN (1919L)
+#define FLM_LRN_DATA_NAT_IP (1920L)
+#define FLM_LRN_DATA_NAT_PORT (1921L)
+#define FLM_LRN_DATA_OP (1922L)
+#define FLM_LRN_DATA_PRIO (1923L)
+#define FLM_LRN_DATA_PROT (1924L)
+#define FLM_LRN_DATA_QFI (1925L)
+#define FLM_LRN_DATA_QW0 (1926L)
+#define FLM_LRN_DATA_QW4 (1927L)
+#define FLM_LRN_DATA_RATE (1928L)
+#define FLM_LRN_DATA_RQI (1929L)
+#define FLM_LRN_DATA_SIZE (1930L)
+#define FLM_LRN_DATA_STAT_PROF (1931L)
+#define FLM_LRN_DATA_SW8 (1932L)
+#define FLM_LRN_DATA_SW9 (1933L)
+#define FLM_LRN_DATA_TAU (1934L)
+#define FLM_LRN_DATA_TEID (1935L)
+#define FLM_LRN_DATA_TTL (1936L)
+#define FLM_LRN_DATA_VOL_IDX (1937L)
+#define FLM_PRIO (1938L)
+#define FLM_PRIO_FT0 (1939L)
+#define FLM_PRIO_FT1 (1940L)
+#define FLM_PRIO_FT2 (1941L)
+#define FLM_PRIO_FT3 (1942L)
+#define FLM_PRIO_LIMIT0 (1943L)
+#define FLM_PRIO_LIMIT1 (1944L)
+#define FLM_PRIO_LIMIT2 (1945L)
+#define FLM_PRIO_LIMIT3 (1946L)
+#define FLM_PST_CTRL (1947L)
+#define FLM_PST_CTRL_ADR (1948L)
+#define FLM_PST_CTRL_CNT (1949L)
+#define FLM_PST_DATA (1950L)
+#define FLM_PST_DATA_BP (1951L)
+#define FLM_PST_DATA_PP (1952L)
+#define FLM_PST_DATA_TP (1953L)
+#define FLM_RCP_CTRL (1954L)
+#define FLM_RCP_CTRL_ADR (1955L)
+#define FLM_RCP_CTRL_CNT (1956L)
+#define FLM_RCP_DATA (1957L)
+#define FLM_RCP_DATA_A (1958L)
+#define FLM_RCP_DATA_AUTO_IPV4_MASK (1959L)
+#define FLM_RCP_DATA_B (1960L)
+#define FLM_RCP_DATA_BYT_DYN (1961L)
+#define FLM_RCP_DATA_BYT_OFS (1962L)
+#define FLM_RCP_DATA_IPN (1963L)
+#define FLM_RCP_DATA_ITF (1964L)
+#define FLM_RCP_DATA_KID (1965L)
+#define FLM_RCP_DATA_LOOKUP (1966L)
+#define FLM_RCP_DATA_MASK (1967L)
+#define FLM_RCP_DATA_OPN (1968L)
+#define FLM_RCP_DATA_QW0_DYN (1969L)
+#define FLM_RCP_DATA_QW0_OFS (1970L)
+#define FLM_RCP_DATA_QW0_SEL (1971L)
+#define FLM_RCP_DATA_QW4_DYN (1972L)
+#define FLM_RCP_DATA_QW4_OFS (1973L)
+#define FLM_RCP_DATA_SW8_DYN (1974L)
+#define FLM_RCP_DATA_SW8_OFS (1975L)
+#define FLM_RCP_DATA_SW8_SEL (1976L)
+#define FLM_RCP_DATA_SW9_DYN (1977L)
+#define FLM_RCP_DATA_SW9_OFS (1978L)
+#define FLM_RCP_DATA_TXPLM (1979L)
+#define FLM_SCRUB (1980L)
+#define FLM_SCRUB_I (1981L)
+#define FLM_STATUS (1982L)
+#define FLM_STATUS_CALIBDONE (1983L)
+#define FLM_STATUS_CRCERR (1984L)
+#define FLM_STATUS_CRITICAL (1985L)
+#define FLM_STATUS_EFT_BP (1986L)
+#define FLM_STATUS_EFT_EVICT_BP (1987L)
+#define FLM_STATUS_IDLE (1988L)
+#define FLM_STATUS_INITDONE (1989L)
+#define FLM_STATUS_PANIC (1990L)
+#define FLM_STAT_AUL_DONE (1991L)
+#define FLM_STAT_AUL_DONE_CNT (1992L)
+#define FLM_STAT_AUL_FAIL (1993L)
+#define FLM_STAT_AUL_FAIL_CNT (1994L)
+#define FLM_STAT_AUL_IGNORE (1995L)
+#define FLM_STAT_AUL_IGNORE_CNT (1996L)
+#define FLM_STAT_CSH_HIT (1997L)
+#define FLM_STAT_CSH_HIT_CNT (1998L)
+#define FLM_STAT_CSH_MISS (1999L)
+#define FLM_STAT_CSH_MISS_CNT (2000L)
+#define FLM_STAT_CSH_UNH (2001L)
+#define FLM_STAT_CSH_UNH_CNT (2002L)
+#define FLM_STAT_CUC_MOVE (2003L)
+#define FLM_STAT_CUC_MOVE_CNT (2004L)
+#define FLM_STAT_CUC_START (2005L)
+#define FLM_STAT_CUC_START_CNT (2006L)
+#define FLM_STAT_FLOWS (2007L)
+#define FLM_STAT_FLOWS_CNT (2008L)
+#define FLM_STAT_INF_DONE (2009L)
+#define FLM_STAT_INF_DONE_CNT (2010L)
+#define FLM_STAT_INF_SKIP (2011L)
+#define FLM_STAT_INF_SKIP_CNT (2012L)
+#define FLM_STAT_LRN_DONE (2013L)
+#define FLM_STAT_LRN_DONE_CNT (2014L)
+#define FLM_STAT_LRN_FAIL (2015L)
+#define FLM_STAT_LRN_FAIL_CNT (2016L)
+#define FLM_STAT_LRN_IGNORE (2017L)
+#define FLM_STAT_LRN_IGNORE_CNT (2018L)
+#define FLM_STAT_PCK_DIS (2019L)
+#define FLM_STAT_PCK_DIS_CNT (2020L)
+#define FLM_STAT_PCK_HIT (2021L)
+#define FLM_STAT_PCK_HIT_CNT (2022L)
+#define FLM_STAT_PCK_MISS (2023L)
+#define FLM_STAT_PCK_MISS_CNT (2024L)
+#define FLM_STAT_PCK_UNH (2025L)
+#define FLM_STAT_PCK_UNH_CNT (2026L)
+#define FLM_STAT_PRB_DONE (2027L)
+#define FLM_STAT_PRB_DONE_CNT (2028L)
+#define FLM_STAT_PRB_IGNORE (2029L)
+#define FLM_STAT_PRB_IGNORE_CNT (2030L)
+#define FLM_STAT_REL_DONE (2031L)
+#define FLM_STAT_REL_DONE_CNT (2032L)
+#define FLM_STAT_REL_IGNORE (2033L)
+#define FLM_STAT_REL_IGNORE_CNT (2034L)
+#define FLM_STAT_STA_DONE (2035L)
+#define FLM_STAT_STA_DONE_CNT (2036L)
+#define FLM_STAT_TUL_DONE (2037L)
+#define FLM_STAT_TUL_DONE_CNT (2038L)
+#define FLM_STAT_UNL_DONE (2039L)
+#define FLM_STAT_UNL_DONE_CNT (2040L)
+#define FLM_STAT_UNL_IGNORE (2041L)
+#define FLM_STAT_UNL_IGNORE_CNT (2042L)
+#define FLM_STA_DATA (2043L)
+#define FLM_STA_DATA_EOR (2044L)
+#define FLM_STA_DATA_ID (2045L)
+#define FLM_STA_DATA_LDS (2046L)
+#define FLM_STA_DATA_LFS (2047L)
+#define FLM_STA_DATA_LIS (2048L)
+#define FLM_STA_DATA_PDS (2049L)
+#define FLM_STA_DATA_PIS (2050L)
+#define FLM_STA_DATA_RDS (2051L)
+#define FLM_STA_DATA_RIS (2052L)
+#define FLM_STA_DATA_UDS (2053L)
+#define FLM_STA_DATA_UIS (2054L)
+#define FLM_TIMEOUT (2055L)
+#define FLM_TIMEOUT_T (2056L)
+#define FLM_TRSWIN (2057L)
+#define FLM_TRSWIN_S (2058L)
+#define FLM_TRTWIN (2059L)
+#define FLM_TRTWIN_T (2060L)
+/* GFG */
+#define GFG_BURSTSIZE0 (2061L)
+#define GFG_BURSTSIZE0_VAL (2062L)
+#define GFG_BURSTSIZE1 (2063L)
+#define GFG_BURSTSIZE1_VAL (2064L)
+#define GFG_BURSTSIZE2 (2065L)
+#define GFG_BURSTSIZE2_VAL (2066L)
+#define GFG_BURSTSIZE3 (2067L)
+#define GFG_BURSTSIZE3_VAL (2068L)
+#define GFG_BURSTSIZE4 (2069L)
+#define GFG_BURSTSIZE4_VAL (2070L)
+#define GFG_BURSTSIZE5 (2071L)
+#define GFG_BURSTSIZE5_VAL (2072L)
+#define GFG_BURSTSIZE6 (2073L)
+#define GFG_BURSTSIZE6_VAL (2074L)
+#define GFG_BURSTSIZE7 (2075L)
+#define GFG_BURSTSIZE7_VAL (2076L)
+#define GFG_CTRL0 (2077L)
+#define GFG_CTRL0_ENABLE (2078L)
+#define GFG_CTRL0_MODE (2079L)
+#define GFG_CTRL0_PRBS_EN (2080L)
+#define GFG_CTRL0_SIZE (2081L)
+#define GFG_CTRL1 (2082L)
+#define GFG_CTRL1_ENABLE (2083L)
+#define GFG_CTRL1_MODE (2084L)
+#define GFG_CTRL1_PRBS_EN (2085L)
+#define GFG_CTRL1_SIZE (2086L)
+#define GFG_CTRL2 (2087L)
+#define GFG_CTRL2_ENABLE (2088L)
+#define GFG_CTRL2_MODE (2089L)
+#define GFG_CTRL2_PRBS_EN (2090L)
+#define GFG_CTRL2_SIZE (2091L)
+#define GFG_CTRL3 (2092L)
+#define GFG_CTRL3_ENABLE (2093L)
+#define GFG_CTRL3_MODE (2094L)
+#define GFG_CTRL3_PRBS_EN (2095L)
+#define GFG_CTRL3_SIZE (2096L)
+#define GFG_CTRL4 (2097L)
+#define GFG_CTRL4_ENABLE (2098L)
+#define GFG_CTRL4_MODE (2099L)
+#define GFG_CTRL4_PRBS_EN (2100L)
+#define GFG_CTRL4_SIZE (2101L)
+#define GFG_CTRL5 (2102L)
+#define GFG_CTRL5_ENABLE (2103L)
+#define GFG_CTRL5_MODE (2104L)
+#define GFG_CTRL5_PRBS_EN (2105L)
+#define GFG_CTRL5_SIZE (2106L)
+#define GFG_CTRL6 (2107L)
+#define GFG_CTRL6_ENABLE (2108L)
+#define GFG_CTRL6_MODE (2109L)
+#define GFG_CTRL6_PRBS_EN (2110L)
+#define GFG_CTRL6_SIZE (2111L)
+#define GFG_CTRL7 (2112L)
+#define GFG_CTRL7_ENABLE (2113L)
+#define GFG_CTRL7_MODE (2114L)
+#define GFG_CTRL7_PRBS_EN (2115L)
+#define GFG_CTRL7_SIZE (2116L)
+#define GFG_RUN0 (2117L)
+#define GFG_RUN0_RUN (2118L)
+#define GFG_RUN1 (2119L)
+#define GFG_RUN1_RUN (2120L)
+#define GFG_RUN2 (2121L)
+#define GFG_RUN2_RUN (2122L)
+#define GFG_RUN3 (2123L)
+#define GFG_RUN3_RUN (2124L)
+#define GFG_RUN4 (2125L)
+#define GFG_RUN4_RUN (2126L)
+#define GFG_RUN5 (2127L)
+#define GFG_RUN5_RUN (2128L)
+#define GFG_RUN6 (2129L)
+#define GFG_RUN6_RUN (2130L)
+#define GFG_RUN7 (2131L)
+#define GFG_RUN7_RUN (2132L)
+#define GFG_SIZEMASK0 (2133L)
+#define GFG_SIZEMASK0_VAL (2134L)
+#define GFG_SIZEMASK1 (2135L)
+#define GFG_SIZEMASK1_VAL (2136L)
+#define GFG_SIZEMASK2 (2137L)
+#define GFG_SIZEMASK2_VAL (2138L)
+#define GFG_SIZEMASK3 (2139L)
+#define GFG_SIZEMASK3_VAL (2140L)
+#define GFG_SIZEMASK4 (2141L)
+#define GFG_SIZEMASK4_VAL (2142L)
+#define GFG_SIZEMASK5 (2143L)
+#define GFG_SIZEMASK5_VAL (2144L)
+#define GFG_SIZEMASK6 (2145L)
+#define GFG_SIZEMASK6_VAL (2146L)
+#define GFG_SIZEMASK7 (2147L)
+#define GFG_SIZEMASK7_VAL (2148L)
+#define GFG_STREAMID0 (2149L)
+#define GFG_STREAMID0_VAL (2150L)
+#define GFG_STREAMID1 (2151L)
+#define GFG_STREAMID1_VAL (2152L)
+#define GFG_STREAMID2 (2153L)
+#define GFG_STREAMID2_VAL (2154L)
+#define GFG_STREAMID3 (2155L)
+#define GFG_STREAMID3_VAL (2156L)
+#define GFG_STREAMID4 (2157L)
+#define GFG_STREAMID4_VAL (2158L)
+#define GFG_STREAMID5 (2159L)
+#define GFG_STREAMID5_VAL (2160L)
+#define GFG_STREAMID6 (2161L)
+#define GFG_STREAMID6_VAL (2162L)
+#define GFG_STREAMID7 (2163L)
+#define GFG_STREAMID7_VAL (2164L)
+/* GMF */
+#define GMF_CTRL (2165L)
+#define GMF_CTRL_ENABLE (2166L)
+#define GMF_CTRL_FCS_ALWAYS (2167L)
+#define GMF_CTRL_IFG_AUTO_ADJUST_ENABLE (2168L)
+#define GMF_CTRL_IFG_ENABLE (2169L)
+#define GMF_CTRL_IFG_TX_NOW_ALWAYS (2170L)
+#define GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE (2171L)
+#define GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK (2172L)
+#define GMF_CTRL_IFG_TX_ON_TS_ALWAYS (2173L)
+#define GMF_CTRL_TS_INJECT_ALWAYS (2174L)
+#define GMF_CTRL_TS_INJECT_DUAL_STEP (2175L)
+#define GMF_DEBUG_LANE_MARKER (2176L)
+#define GMF_DEBUG_LANE_MARKER_COMPENSATION (2177L)
+#define GMF_IFG_MAX_ADJUST_SLACK (2178L)
+#define GMF_IFG_MAX_ADJUST_SLACK_SLACK (2179L)
+#define GMF_IFG_SET_CLOCK_DELTA (2180L)
+#define GMF_IFG_SET_CLOCK_DELTA_DELTA (2181L)
+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST (2182L)
+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA (2183L)
+#define GMF_IFG_TX_NOW_ON_TS (2184L)
+#define GMF_IFG_TX_NOW_ON_TS_TS (2185L)
+#define GMF_SPEED (2186L)
+#define GMF_SPEED_IFG_SPEED (2187L)
+#define GMF_STAT (2188L)
+#define GMF_STAT_CTRL_EMPTY (2189L)
+#define GMF_STAT_DATA_CTRL_EMPTY (2190L)
+#define GMF_STAT_SB_EMPTY (2191L)
+#define GMF_STAT_CTRL (2192L)
+#define GMF_STAT_CTRL_FILL_LEVEL (2193L)
+#define GMF_STAT_DATA0 (2194L)
+#define GMF_STAT_DATA0_EMPTY (2195L)
+#define GMF_STAT_DATA1 (2196L)
+#define GMF_STAT_DATA1_EMPTY (2197L)
+#define GMF_STAT_DATA_BUFFER (2198L)
+#define GMF_STAT_DATA_BUFFER_FREE (2199L)
+#define GMF_STAT_DATA_BUFFER_USED (2200L)
+#define GMF_STAT_MAX_DELAYED_PKT (2201L)
+#define GMF_STAT_MAX_DELAYED_PKT_NS (2202L)
+#define GMF_STAT_NEXT_PKT (2203L)
+#define GMF_STAT_NEXT_PKT_NS (2204L)
+#define GMF_STAT_STICKY (2205L)
+#define GMF_STAT_STICKY_DATA_UNDERFLOWED (2206L)
+#define GMF_STAT_STICKY_IFG_ADJUSTED (2207L)
+#define GMF_TS_INJECT (2208L)
+#define GMF_TS_INJECT_OFFSET (2209L)
+#define GMF_TS_INJECT_POS (2210L)
+/* GPIO_PHY */
+#define GPIO_PHY_CFG (2211L)
+#define GPIO_PHY_CFG_E_PORT0_RXLOS (2212L)
+#define GPIO_PHY_CFG_E_PORT1_RXLOS (2213L)
+#define GPIO_PHY_CFG_PORT0_INT_B (2214L)
+#define GPIO_PHY_CFG_PORT0_LPMODE (2215L)
+#define GPIO_PHY_CFG_PORT0_MODPRS_B (2216L)
+#define GPIO_PHY_CFG_PORT0_PLL_INTR (2217L)
+#define GPIO_PHY_CFG_PORT0_RESET_B (2218L)
+#define GPIO_PHY_CFG_PORT1_INT_B (2219L)
+#define GPIO_PHY_CFG_PORT1_LPMODE (2220L)
+#define GPIO_PHY_CFG_PORT1_MODPRS_B (2221L)
+#define GPIO_PHY_CFG_PORT1_PLL_INTR (2222L)
+#define GPIO_PHY_CFG_PORT1_RESET_B (2223L)
+#define GPIO_PHY_GPIO (2224L)
+#define GPIO_PHY_GPIO_E_PORT0_RXLOS (2225L)
+#define GPIO_PHY_GPIO_E_PORT1_RXLOS (2226L)
+#define GPIO_PHY_GPIO_PORT0_INT_B (2227L)
+#define GPIO_PHY_GPIO_PORT0_LPMODE (2228L)
+#define GPIO_PHY_GPIO_PORT0_MODPRS_B (2229L)
+#define GPIO_PHY_GPIO_PORT0_PLL_INTR (2230L)
+#define GPIO_PHY_GPIO_PORT0_RESET_B (2231L)
+#define GPIO_PHY_GPIO_PORT1_INT_B (2232L)
+#define GPIO_PHY_GPIO_PORT1_LPMODE (2233L)
+#define GPIO_PHY_GPIO_PORT1_MODPRS_B (2234L)
+#define GPIO_PHY_GPIO_PORT1_PLL_INTR (2235L)
+#define GPIO_PHY_GPIO_PORT1_RESET_B (2236L)
+/* GPIO_PHY_PORTS */
+#define GPIO_PHY_PORTS_CFG (2237L)
+#define GPIO_PHY_PORTS_CFG_E_PORT0_RXLOS (2238L)
+#define GPIO_PHY_PORTS_CFG_E_PORT0_TXDISABLE (2239L)
+#define GPIO_PHY_PORTS_CFG_E_PORT0_TXFAULT (2240L)
+#define GPIO_PHY_PORTS_CFG_E_PORT1_RXLOS (2241L)
+#define GPIO_PHY_PORTS_CFG_E_PORT1_TXDISABLE (2242L)
+#define GPIO_PHY_PORTS_CFG_E_PORT1_TXFAULT (2243L)
+#define GPIO_PHY_PORTS_CFG_E_PORT2_RXLOS (2244L)
+#define GPIO_PHY_PORTS_CFG_E_PORT2_TXDISABLE (2245L)
+#define GPIO_PHY_PORTS_CFG_E_PORT2_TXFAULT (2246L)
+#define GPIO_PHY_PORTS_CFG_E_PORT3_RXLOS (2247L)
+#define GPIO_PHY_PORTS_CFG_E_PORT3_TXDISABLE (2248L)
+#define GPIO_PHY_PORTS_CFG_E_PORT3_TXFAULT (2249L)
+#define GPIO_PHY_PORTS_CFG_E_PORT4_RXLOS (2250L)
+#define GPIO_PHY_PORTS_CFG_E_PORT4_TXDISABLE (2251L)
+#define GPIO_PHY_PORTS_CFG_E_PORT4_TXFAULT (2252L)
+#define GPIO_PHY_PORTS_CFG_E_PORT5_RXLOS (2253L)
+#define GPIO_PHY_PORTS_CFG_E_PORT5_TXDISABLE (2254L)
+#define GPIO_PHY_PORTS_CFG_E_PORT5_TXFAULT (2255L)
+#define GPIO_PHY_PORTS_CFG_E_PORT6_RXLOS (2256L)
+#define GPIO_PHY_PORTS_CFG_E_PORT6_TXDISABLE (2257L)
+#define GPIO_PHY_PORTS_CFG_E_PORT6_TXFAULT (2258L)
+#define GPIO_PHY_PORTS_CFG_E_PORT7_RXLOS (2259L)
+#define GPIO_PHY_PORTS_CFG_E_PORT7_TXDISABLE (2260L)
+#define GPIO_PHY_PORTS_CFG_E_PORT7_TXFAULT (2261L)
+#define GPIO_PHY_PORTS_GPIO (2262L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT0_RXLOS (2263L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXDISABLE (2264L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXFAULT (2265L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT1_RXLOS (2266L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXDISABLE (2267L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXFAULT (2268L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT2_RXLOS (2269L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXDISABLE (2270L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXFAULT (2271L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT3_RXLOS (2272L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXDISABLE (2273L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXFAULT (2274L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT4_RXLOS (2275L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXDISABLE (2276L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXFAULT (2277L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT5_RXLOS (2278L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXDISABLE (2279L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXFAULT (2280L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT6_RXLOS (2281L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXDISABLE (2282L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXFAULT (2283L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT7_RXLOS (2284L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXDISABLE (2285L)
+#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXFAULT (2286L)
+/* GPIO_SFPP */
+#define GPIO_SFPP_CFG (2287L)
+#define GPIO_SFPP_CFG_ABS (2288L)
+#define GPIO_SFPP_CFG_RS (2289L)
+#define GPIO_SFPP_CFG_RXLOS (2290L)
+#define GPIO_SFPP_CFG_TXDISABLE (2291L)
+#define GPIO_SFPP_CFG_TXFAULT (2292L)
+#define GPIO_SFPP_GPIO (2293L)
+#define GPIO_SFPP_GPIO_ABS (2294L)
+#define GPIO_SFPP_GPIO_RS (2295L)
+#define GPIO_SFPP_GPIO_RXLOS (2296L)
+#define GPIO_SFPP_GPIO_TXDISABLE (2297L)
+#define GPIO_SFPP_GPIO_TXFAULT (2298L)
+/* HFU */
+#define HFU_RCP_CTRL (2381L)
+#define HFU_RCP_CTRL_ADR (2382L)
+#define HFU_RCP_CTRL_CNT (2383L)
+#define HFU_RCP_DATA (2384L)
+#define HFU_RCP_DATA_CSINF (2385L)
+#define HFU_RCP_DATA_IL3OFS (2386L)
+#define HFU_RCP_DATA_IL4OFS (2387L)
+#define HFU_RCP_DATA_L3FRAG (2388L)
+#define HFU_RCP_DATA_L3PRT (2389L)
+#define HFU_RCP_DATA_L4PRT (2390L)
+#define HFU_RCP_DATA_LEN_A_ADD_DYN (2391L)
+#define HFU_RCP_DATA_LEN_A_ADD_OFS (2392L)
+#define HFU_RCP_DATA_LEN_A_OL4LEN (2393L)
+#define HFU_RCP_DATA_LEN_A_POS_DYN (2394L)
+#define HFU_RCP_DATA_LEN_A_POS_OFS (2395L)
+#define HFU_RCP_DATA_LEN_A_SUB_DYN (2396L)
+#define HFU_RCP_DATA_LEN_A_WR (2397L)
+#define HFU_RCP_DATA_LEN_B_ADD_DYN (2398L)
+#define HFU_RCP_DATA_LEN_B_ADD_OFS (2399L)
+#define HFU_RCP_DATA_LEN_B_POS_DYN (2400L)
+#define HFU_RCP_DATA_LEN_B_POS_OFS (2401L)
+#define HFU_RCP_DATA_LEN_B_SUB_DYN (2402L)
+#define HFU_RCP_DATA_LEN_B_WR (2403L)
+#define HFU_RCP_DATA_LEN_C_ADD_DYN (2404L)
+#define HFU_RCP_DATA_LEN_C_ADD_OFS (2405L)
+#define HFU_RCP_DATA_LEN_C_POS_DYN (2406L)
+#define HFU_RCP_DATA_LEN_C_POS_OFS (2407L)
+#define HFU_RCP_DATA_LEN_C_SUB_DYN (2408L)
+#define HFU_RCP_DATA_LEN_C_WR (2409L)
+#define HFU_RCP_DATA_OL3OFS (2410L)
+#define HFU_RCP_DATA_OL4OFS (2411L)
+#define HFU_RCP_DATA_TTL_POS_DYN (2412L)
+#define HFU_RCP_DATA_TTL_POS_OFS (2413L)
+#define HFU_RCP_DATA_TTL_WR (2414L)
+#define HFU_RCP_DATA_TUNNEL (2415L)
+/* HIF */
+#define HIF_BUILD_TIME (2416L)
+#define HIF_BUILD_TIME_TIME (2417L)
+#define HIF_CONFIG (2418L)
+#define HIF_CONFIG_EXT_TAG (2419L)
+#define HIF_CONFIG_MAX_READ (2420L)
+#define HIF_CONFIG_MAX_TLP (2421L)
+#define HIF_CONTROL (2422L)
+#define HIF_CONTROL_BLESSED (2423L)
+#define HIF_CONTROL_WRAW (2424L)
+#define HIF_PROD_ID_EX (2425L)
+#define HIF_PROD_ID_EX_LAYOUT (2426L)
+#define HIF_PROD_ID_EX_LAYOUT_VERSION (2427L)
+#define HIF_PROD_ID_EX_RESERVED (2428L)
+#define HIF_PROD_ID_EXT (2429L)
+#define HIF_PROD_ID_EXT_LAYOUT (2430L)
+#define HIF_PROD_ID_EXT_LAYOUT_VERSION (2431L)
+#define HIF_PROD_ID_EXT_RESERVED (2432L)
+#define HIF_PROD_ID_LSB (2433L)
+#define HIF_PROD_ID_LSB_GROUP_ID (2434L)
+#define HIF_PROD_ID_LSB_REV_ID (2435L)
+#define HIF_PROD_ID_LSB_VER_ID (2436L)
+#define HIF_PROD_ID_MSB (2437L)
+#define HIF_PROD_ID_MSB_BUILD_NO (2438L)
+#define HIF_PROD_ID_MSB_PATCH_NO (2439L)
+#define HIF_PROD_ID_MSB_TYPE_ID (2440L)
+#define HIF_SAMPLE_TIME (2441L)
+#define HIF_SAMPLE_TIME_SAMPLE_TIME (2442L)
+#define HIF_STATUS (2443L)
+#define HIF_STATUS_RD_ERR (2444L)
+#define HIF_STATUS_TAGS_IN_USE (2445L)
+#define HIF_STATUS_WR_ERR (2446L)
+#define HIF_STAT_CTRL (2447L)
+#define HIF_STAT_CTRL_STAT_ENA (2448L)
+#define HIF_STAT_CTRL_STAT_REQ (2449L)
+#define HIF_STAT_REFCLK (2450L)
+#define HIF_STAT_REFCLK_REFCLK250 (2451L)
+#define HIF_STAT_RX (2452L)
+#define HIF_STAT_RX_COUNTER (2453L)
+#define HIF_STAT_TX (2454L)
+#define HIF_STAT_TX_COUNTER (2455L)
+#define HIF_TEST0 (2456L)
+#define HIF_TEST0_DATA (2457L)
+#define HIF_TEST1 (2458L)
+#define HIF_TEST1_DATA (2459L)
+#define HIF_TEST2 (2460L)
+#define HIF_TEST2_DATA (2461L)
+#define HIF_TEST3 (2462L)
+#define HIF_TEST3_DATA (2463L)
+#define HIF_UUID0 (2464L)
+#define HIF_UUID0_UUID0 (2465L)
+#define HIF_UUID1 (2466L)
+#define HIF_UUID1_UUID1 (2467L)
+#define HIF_UUID2 (2468L)
+#define HIF_UUID2_UUID2 (2469L)
+#define HIF_UUID3 (2470L)
+#define HIF_UUID3_UUID3 (2471L)
+/* HSH */
+#define HSH_RCP_CTRL (2472L)
+#define HSH_RCP_CTRL_ADR (2473L)
+#define HSH_RCP_CTRL_CNT (2474L)
+#define HSH_RCP_DATA (2475L)
+#define HSH_RCP_DATA_AUTO_IPV4_MASK (2476L)
+#define HSH_RCP_DATA_HSH_TYPE (2477L)
+#define HSH_RCP_DATA_HSH_VALID (2478L)
+#define HSH_RCP_DATA_K (2479L)
+#define HSH_RCP_DATA_LOAD_DIST_TYPE (2480L)
+#define HSH_RCP_DATA_MAC_PORT_MASK (2481L)
+#define HSH_RCP_DATA_P_MASK (2482L)
+#define HSH_RCP_DATA_QW0_OFS (2483L)
+#define HSH_RCP_DATA_QW0_PE (2484L)
+#define HSH_RCP_DATA_QW4_OFS (2485L)
+#define HSH_RCP_DATA_QW4_PE (2486L)
+#define HSH_RCP_DATA_SEED (2487L)
+#define HSH_RCP_DATA_SORT (2488L)
+#define HSH_RCP_DATA_TNL_P (2489L)
+#define HSH_RCP_DATA_TOEPLITZ (2490L)
+#define HSH_RCP_DATA_W8_OFS (2491L)
+#define HSH_RCP_DATA_W8_PE (2492L)
+#define HSH_RCP_DATA_W8_SORT (2493L)
+#define HSH_RCP_DATA_W9_OFS (2494L)
+#define HSH_RCP_DATA_W9_P (2495L)
+#define HSH_RCP_DATA_W9_PE (2496L)
+#define HSH_RCP_DATA_W9_SORT (2497L)
+#define HSH_RCP_DATA_WORD_MASK (2498L)
+/* HST */
+#define HST_RCP_CTRL (2499L)
+#define HST_RCP_CTRL_ADR (2500L)
+#define HST_RCP_CTRL_CNT (2501L)
+#define HST_RCP_DATA (2502L)
+#define HST_RCP_DATA_END_DYN (2503L)
+#define HST_RCP_DATA_END_OFS (2504L)
+#define HST_RCP_DATA_MODIF0_CMD (2505L)
+#define HST_RCP_DATA_MODIF0_DYN (2506L)
+#define HST_RCP_DATA_MODIF0_OFS (2507L)
+#define HST_RCP_DATA_MODIF0_VALUE (2508L)
+#define HST_RCP_DATA_MODIF1_CMD (2509L)
+#define HST_RCP_DATA_MODIF1_DYN (2510L)
+#define HST_RCP_DATA_MODIF1_OFS (2511L)
+#define HST_RCP_DATA_MODIF1_VALUE (2512L)
+#define HST_RCP_DATA_MODIF2_CMD (2513L)
+#define HST_RCP_DATA_MODIF2_DYN (2514L)
+#define HST_RCP_DATA_MODIF2_OFS (2515L)
+#define HST_RCP_DATA_MODIF2_VALUE (2516L)
+#define HST_RCP_DATA_START_DYN (2517L)
+#define HST_RCP_DATA_START_OFS (2518L)
+#define HST_RCP_DATA_STRIP_MODE (2519L)
+/* ICORE_10G */
+#define ICORE_10G_INDIR_CTRL (2549L)
+#define ICORE_10G_INDIR_CTRL_RD_ENABLE (2550L)
+#define ICORE_10G_INDIR_CTRL_RD_READY (2551L)
+#define ICORE_10G_INDIR_CTRL_SUB_ADDR (2552L)
+#define ICORE_10G_INDIR_DATA (2553L)
+#define ICORE_10G_INDIR_DATA_DATA (2554L)
+#define ICORE_10G_MISC_CTRL (2555L)
+#define ICORE_10G_MISC_CTRL_LINE_LOOP (2556L)
+#define ICORE_10G_MISC_CTRL_LINK_LATENCY (2557L)
+#define ICORE_10G_MISC_CTRL_RES_MAC_RX (2558L)
+#define ICORE_10G_MISC_CTRL_RES_MAC_TX (2559L)
+#define ICORE_10G_MISC_CTRL_SERIAL_LOOP (2560L)
+#define ICORE_10G_MISC_CTRL_SET_LOCK2DATA (2561L)
+#define ICORE_10G_MISC_CTRL_SET_LOCK2REF (2562L)
+#define ICORE_10G_PHY_STATUS (2563L)
+#define ICORE_10G_PHY_STATUS_BLOCK_LOCK (2564L)
+#define ICORE_10G_PHY_STATUS_HI_BER (2565L)
+#define ICORE_10G_PHY_STATUS_HI_BER_CHANGED (2566L)
+#define ICORE_10G_PHY_STATUS_LINK_STATE (2567L)
+#define ICORE_10G_PHY_STATUS_LINK_STATE_CHANGED (2568L)
+#define ICORE_10G_PHY_STATUS_RXCLK_LOCKED (2569L)
+#define ICORE_10G_PHY_STATUS_RXCLK_LOCKED2DATA (2570L)
+#define ICORE_10G_PHY_STATUS_RX_CAL_BUSY (2571L)
+#define ICORE_10G_PHY_STATUS_TXCLK_LOCKED (2572L)
+#define ICORE_10G_PHY_STATUS_TX_CAL_BUSY (2573L)
+#define ICORE_10G_TFG_ADDR (2574L)
+#define ICORE_10G_TFG_ADDR_ADR (2575L)
+#define ICORE_10G_TFG_ADDR_RDENA (2576L)
+#define ICORE_10G_TFG_ADDR_RD_DONE (2577L)
+#define ICORE_10G_TFG_CTRL (2578L)
+#define ICORE_10G_TFG_CTRL_ID_ENA (2579L)
+#define ICORE_10G_TFG_CTRL_ID_POS (2580L)
+#define ICORE_10G_TFG_CTRL_RESTART (2581L)
+#define ICORE_10G_TFG_CTRL_TG_ACT (2582L)
+#define ICORE_10G_TFG_CTRL_TG_ENA (2583L)
+#define ICORE_10G_TFG_CTRL_TIME_MODE (2584L)
+#define ICORE_10G_TFG_CTRL_WRAP (2585L)
+#define ICORE_10G_TFG_DATA (2586L)
+#define ICORE_10G_TFG_DATA_ID (2587L)
+#define ICORE_10G_TFG_DATA_LENGTH (2588L)
+#define ICORE_10G_TFG_FRAME_HDR_0 (2589L)
+#define ICORE_10G_TFG_FRAME_HDR_0_HDR (2590L)
+#define ICORE_10G_TFG_FRAME_HDR_1 (2591L)
+#define ICORE_10G_TFG_FRAME_HDR_1_HDR (2592L)
+#define ICORE_10G_TFG_FRAME_HDR_2 (2593L)
+#define ICORE_10G_TFG_FRAME_HDR_2_HDR (2594L)
+#define ICORE_10G_TFG_FRAME_HDR_3 (2595L)
+#define ICORE_10G_TFG_FRAME_HDR_3_HDR (2596L)
+#define ICORE_10G_TFG_REPETITION (2597L)
+#define ICORE_10G_TFG_REPETITION_CNT (2598L)
+/* IFR */
+#define IFR_RCP_CTRL (2642L)
+#define IFR_RCP_CTRL_ADR (2643L)
+#define IFR_RCP_CTRL_CNT (2644L)
+#define IFR_RCP_DATA (2645L)
+#define IFR_RCP_DATA_EN (2646L)
+#define IFR_RCP_DATA_MTU (2647L)
+/* IIC */
+#define IIC_ADR (2648L)
+#define IIC_ADR_SLV_ADR (2649L)
+#define IIC_CR (2650L)
+#define IIC_CR_EN (2651L)
+#define IIC_CR_GC_EN (2652L)
+#define IIC_CR_MSMS (2653L)
+#define IIC_CR_RST (2654L)
+#define IIC_CR_RSTA (2655L)
+#define IIC_CR_TX (2656L)
+#define IIC_CR_TXAK (2657L)
+#define IIC_CR_TXFIFO_RESET (2658L)
+#define IIC_DGIE (2659L)
+#define IIC_DGIE_GIE (2660L)
+#define IIC_GPO (2661L)
+#define IIC_GPO_GPO_VAL (2662L)
+#define IIC_IER (2663L)
+#define IIC_IER_INT0 (2664L)
+#define IIC_IER_INT1 (2665L)
+#define IIC_IER_INT2 (2666L)
+#define IIC_IER_INT3 (2667L)
+#define IIC_IER_INT4 (2668L)
+#define IIC_IER_INT5 (2669L)
+#define IIC_IER_INT6 (2670L)
+#define IIC_IER_INT7 (2671L)
+#define IIC_ISR (2672L)
+#define IIC_ISR_INT0 (2673L)
+#define IIC_ISR_INT1 (2674L)
+#define IIC_ISR_INT2 (2675L)
+#define IIC_ISR_INT3 (2676L)
+#define IIC_ISR_INT4 (2677L)
+#define IIC_ISR_INT5 (2678L)
+#define IIC_ISR_INT6 (2679L)
+#define IIC_ISR_INT7 (2680L)
+#define IIC_RX_FIFO (2681L)
+#define IIC_RX_FIFO_RXDATA (2682L)
+#define IIC_RX_FIFO_OCY (2683L)
+#define IIC_RX_FIFO_OCY_OCY_VAL (2684L)
+#define IIC_RX_FIFO_PIRQ (2685L)
+#define IIC_RX_FIFO_PIRQ_CMP_VAL (2686L)
+#define IIC_SOFTR (2687L)
+#define IIC_SOFTR_RKEY (2688L)
+#define IIC_SR (2689L)
+#define IIC_SR_AAS (2690L)
+#define IIC_SR_ABGC (2691L)
+#define IIC_SR_BB (2692L)
+#define IIC_SR_RXFIFO_EMPTY (2693L)
+#define IIC_SR_RXFIFO_FULL (2694L)
+#define IIC_SR_SRW (2695L)
+#define IIC_SR_TXFIFO_EMPTY (2696L)
+#define IIC_SR_TXFIFO_FULL (2697L)
+#define IIC_TBUF (2698L)
+#define IIC_TBUF_TBUF_VAL (2699L)
+#define IIC_TEN_ADR (2700L)
+#define IIC_TEN_ADR_MSB_SLV_ADR (2701L)
+#define IIC_THDDAT (2702L)
+#define IIC_THDDAT_THDDAT_VAL (2703L)
+#define IIC_THDSTA (2704L)
+#define IIC_THDSTA_THDSTA_VAL (2705L)
+#define IIC_THIGH (2706L)
+#define IIC_THIGH_THIGH_VAL (2707L)
+#define IIC_TLOW (2708L)
+#define IIC_TLOW_TLOW_VAL (2709L)
+#define IIC_TSUDAT (2710L)
+#define IIC_TSUDAT_TSUDAT_VAL (2711L)
+#define IIC_TSUSTA (2712L)
+#define IIC_TSUSTA_TSUSTA_VAL (2713L)
+#define IIC_TSUSTO (2714L)
+#define IIC_TSUSTO_TSUSTO_VAL (2715L)
+#define IIC_TX_FIFO (2716L)
+#define IIC_TX_FIFO_START (2717L)
+#define IIC_TX_FIFO_STOP (2718L)
+#define IIC_TX_FIFO_TXDATA (2719L)
+#define IIC_TX_FIFO_OCY (2720L)
+#define IIC_TX_FIFO_OCY_OCY_VAL (2721L)
+/* INS */
+#define INS_RCP_CTRL (2722L)
+#define INS_RCP_CTRL_ADR (2723L)
+#define INS_RCP_CTRL_CNT (2724L)
+#define INS_RCP_DATA (2725L)
+#define INS_RCP_DATA_DYN (2726L)
+#define INS_RCP_DATA_LEN (2727L)
+#define INS_RCP_DATA_OFS (2728L)
+/* IOA */
+#define IOA_RECIPE_CTRL (2778L)
+#define IOA_RECIPE_CTRL_ADR (2779L)
+#define IOA_RECIPE_CTRL_CNT (2780L)
+#define IOA_RECIPE_DATA (2781L)
+#define IOA_RECIPE_DATA_QUEUE_ID (2782L)
+#define IOA_RECIPE_DATA_QUEUE_OVERRIDE_EN (2783L)
+#define IOA_RECIPE_DATA_TUNNEL_POP (2784L)
+#define IOA_RECIPE_DATA_VLAN_DEI (2785L)
+#define IOA_RECIPE_DATA_VLAN_PCP (2786L)
+#define IOA_RECIPE_DATA_VLAN_POP (2787L)
+#define IOA_RECIPE_DATA_VLAN_PUSH (2788L)
+#define IOA_RECIPE_DATA_VLAN_TPID_SEL (2789L)
+#define IOA_RECIPE_DATA_VLAN_VID (2790L)
+#define IOA_ROA_EPP_CTRL (2791L)
+#define IOA_ROA_EPP_CTRL_ADR (2792L)
+#define IOA_ROA_EPP_CTRL_CNT (2793L)
+#define IOA_ROA_EPP_DATA (2794L)
+#define IOA_ROA_EPP_DATA_PUSH_TUNNEL (2795L)
+#define IOA_ROA_EPP_DATA_TX_PORT (2796L)
+#define IOA_VLAN_TPID_SPECIAL (2797L)
+#define IOA_VLAN_TPID_SPECIAL_CUSTTPID0 (2798L)
+#define IOA_VLAN_TPID_SPECIAL_CUSTTPID1 (2799L)
+/* IPF */
+#define IPF_CTRL (2800L)
+#define IPF_CTRL_ALL_UNM (2801L)
+#define IPF_CTRL_ALL_UNM_INNER (2802L)
+#define IPF_CTRL_DEL_UNM (2803L)
+#define IPF_CTRL_ENABLE (2804L)
+#define IPF_CTRL_FST_UNM (2805L)
+#define IPF_CTRL_PASSIVE (2806L)
+#define IPF_CTRL_PERSIST (2807L)
+#define IPF_DEBUG (2808L)
+#define IPF_DEBUG_FTF_N (2809L)
+#define IPF_DEBUG_LIMIT_N (2810L)
+#define IPF_EXPIRE (2811L)
+#define IPF_EXPIRE_PERSIST (2812L)
+#define IPF_EXPIRE_T (2813L)
+#define IPF_FTF_DEBUG (2814L)
+#define IPF_FTF_DEBUG_N (2815L)
+#define IPF_RCP_CTRL (2816L)
+#define IPF_RCP_CTRL_ADR (2817L)
+#define IPF_RCP_CTRL_CNT (2818L)
+#define IPF_RCP_DATA (2819L)
+#define IPF_RCP_DATA_ALL_UNM (2820L)
+#define IPF_RCP_DATA_COL_INH (2821L)
+#define IPF_RCP_DATA_DEL_UNM (2822L)
+#define IPF_RCP_DATA_DISC_INH (2823L)
+#define IPF_RCP_DATA_DUP_INH (2824L)
+#define IPF_RCP_DATA_ENABLE (2825L)
+#define IPF_RCP_DATA_FST_UNM (2826L)
+#define IPF_RCP_DATA_GROUP_ID (2827L)
+#define IPF_RCP_DATA_HASH_CENC (2828L)
+#define IPF_RCP_DATA_HSH_INH (2829L)
+#define IPF_RCP_DATA_PORT_GROUP_ID (2830L)
+#define IPF_RCP_DATA_QUEUE_INH (2831L)
+#define IPF_RCP_DATA_UNMQ_HI (2832L)
+#define IPF_RCP_DATA_UNMQ_LO (2833L)
+#define IPF_RCP_DATA_UNM_FLAG_CENC (2834L)
+#define IPF_SIZE_DEBUG (2835L)
+#define IPF_SIZE_DEBUG_N (2836L)
+#define IPF_STAT_MAX1 (2837L)
+#define IPF_STAT_MAX1_N (2838L)
+#define IPF_STAT_MAX2 (2839L)
+#define IPF_STAT_MAX2_N (2840L)
+#define IPF_STAT_MAX3 (2841L)
+#define IPF_STAT_MAX3_N (2842L)
+#define IPF_STAT_MAX4 (2843L)
+#define IPF_STAT_MAX4_N (2844L)
+#define IPF_TIMEOUT (2845L)
+#define IPF_TIMEOUT_T (2846L)
+#define IPF_UNMQ_CTRL (2847L)
+#define IPF_UNMQ_CTRL_ADR (2848L)
+#define IPF_UNMQ_CTRL_CNT (2849L)
+#define IPF_UNMQ_DATA (2850L)
+#define IPF_UNMQ_DATA_CENC (2851L)
+#define IPF_UNMQ_DATA_EN (2852L)
+#define IPF_UNMQ_DATA_ID (2853L)
+#define IPF_UNM_FEED (2854L)
+#define IPF_UNM_FEED_ADDR (2855L)
+#define IPF_UNM_FEED_CNT (2856L)
+#define IPF_UNM_FEED_FEED (2857L)
+#define IPF_UNM_FEED_FEED_VALID (2858L)
+#define IPF_UNM_FEED_RES1 (2859L)
+#define IPF_UNM_FEED_RES2 (2860L)
+#define IPF_UNM_FEED_RES3 (2861L)
+/* KM */
+#define KM_CAM_CTRL (2862L)
+#define KM_CAM_CTRL_ADR (2863L)
+#define KM_CAM_CTRL_CNT (2864L)
+#define KM_CAM_DATA (2865L)
+#define KM_CAM_DATA_FT0 (2866L)
+#define KM_CAM_DATA_FT1 (2867L)
+#define KM_CAM_DATA_FT2 (2868L)
+#define KM_CAM_DATA_FT3 (2869L)
+#define KM_CAM_DATA_FT4 (2870L)
+#define KM_CAM_DATA_FT5 (2871L)
+#define KM_CAM_DATA_W0 (2872L)
+#define KM_CAM_DATA_W1 (2873L)
+#define KM_CAM_DATA_W2 (2874L)
+#define KM_CAM_DATA_W3 (2875L)
+#define KM_CAM_DATA_W4 (2876L)
+#define KM_CAM_DATA_W5 (2877L)
+#define KM_RCP_CTRL (2878L)
+#define KM_RCP_CTRL_ADR (2879L)
+#define KM_RCP_CTRL_CNT (2880L)
+#define KM_RCP_DATA (2881L)
+#define KM_RCP_DATA_BANK_A (2882L)
+#define KM_RCP_DATA_BANK_B (2883L)
+#define KM_RCP_DATA_DUAL (2884L)
+#define KM_RCP_DATA_DW0_B_DYN (2885L)
+#define KM_RCP_DATA_DW0_B_OFS (2886L)
+#define KM_RCP_DATA_DW10_DYN (2887L)
+#define KM_RCP_DATA_DW10_OFS (2888L)
+#define KM_RCP_DATA_DW10_SEL_A (2889L)
+#define KM_RCP_DATA_DW10_SEL_B (2890L)
+#define KM_RCP_DATA_DW2_B_DYN (2891L)
+#define KM_RCP_DATA_DW2_B_OFS (2892L)
+#define KM_RCP_DATA_DW8_B_DYN (2893L)
+#define KM_RCP_DATA_DW8_B_OFS (2894L)
+#define KM_RCP_DATA_DW8_DYN (2895L)
+#define KM_RCP_DATA_DW8_OFS (2896L)
+#define KM_RCP_DATA_DW8_SEL_A (2897L)
+#define KM_RCP_DATA_DW8_SEL_B (2898L)
+#define KM_RCP_DATA_EL_A (2899L)
+#define KM_RCP_DATA_EL_B (2900L)
+#define KM_RCP_DATA_FLOW_SET (2901L)
+#define KM_RCP_DATA_FTM_A (2902L)
+#define KM_RCP_DATA_FTM_B (2903L)
+#define KM_RCP_DATA_INFO_A (2904L)
+#define KM_RCP_DATA_INFO_B (2905L)
+#define KM_RCP_DATA_KEYWAY_A (2906L)
+#define KM_RCP_DATA_KEYWAY_B (2907L)
+#define KM_RCP_DATA_KL_A (2908L)
+#define KM_RCP_DATA_KL_B (2909L)
+#define KM_RCP_DATA_MASK_A (2910L)
+#define KM_RCP_DATA_MASK_B (2911L)
+#define KM_RCP_DATA_PAIRED (2912L)
+#define KM_RCP_DATA_QW0_B_DYN (2913L)
+#define KM_RCP_DATA_QW0_B_OFS (2914L)
+#define KM_RCP_DATA_QW0_DYN (2915L)
+#define KM_RCP_DATA_QW0_OFS (2916L)
+#define KM_RCP_DATA_QW0_SEL_A (2917L)
+#define KM_RCP_DATA_QW0_SEL_B (2918L)
+#define KM_RCP_DATA_QW4_B_DYN (2919L)
+#define KM_RCP_DATA_QW4_B_OFS (2920L)
+#define KM_RCP_DATA_QW4_DYN (2921L)
+#define KM_RCP_DATA_QW4_OFS (2922L)
+#define KM_RCP_DATA_QW4_SEL_A (2923L)
+#define KM_RCP_DATA_QW4_SEL_B (2924L)
+#define KM_RCP_DATA_SW4_B_DYN (2925L)
+#define KM_RCP_DATA_SW4_B_OFS (2926L)
+#define KM_RCP_DATA_SW5_B_DYN (2927L)
+#define KM_RCP_DATA_SW5_B_OFS (2928L)
+#define KM_RCP_DATA_SW8_B_DYN (2929L)
+#define KM_RCP_DATA_SW8_B_OFS (2930L)
+#define KM_RCP_DATA_SW8_DYN (2931L)
+#define KM_RCP_DATA_SW8_OFS (2932L)
+#define KM_RCP_DATA_SW8_SEL_A (2933L)
+#define KM_RCP_DATA_SW8_SEL_B (2934L)
+#define KM_RCP_DATA_SW9_B_DYN (2935L)
+#define KM_RCP_DATA_SW9_B_OFS (2936L)
+#define KM_RCP_DATA_SW9_DYN (2937L)
+#define KM_RCP_DATA_SW9_OFS (2938L)
+#define KM_RCP_DATA_SW9_SEL_A (2939L)
+#define KM_RCP_DATA_SW9_SEL_B (2940L)
+#define KM_RCP_DATA_SWX_CCH (2941L)
+#define KM_RCP_DATA_SWX_OVS_SB (2942L)
+#define KM_RCP_DATA_SWX_SEL_A (2943L)
+#define KM_RCP_DATA_SWX_SEL_B (2944L)
+#define KM_RCP_DATA_SYNERGY_MODE (2945L)
+#define KM_STATUS (2946L)
+#define KM_STATUS_TCQ_RDY (2947L)
+#define KM_TCAM_CTRL (2948L)
+#define KM_TCAM_CTRL_ADR (2949L)
+#define KM_TCAM_CTRL_CNT (2950L)
+#define KM_TCAM_DATA (2951L)
+#define KM_TCAM_DATA_T (2952L)
+#define KM_TCI_CTRL (2953L)
+#define KM_TCI_CTRL_ADR (2954L)
+#define KM_TCI_CTRL_CNT (2955L)
+#define KM_TCI_DATA (2956L)
+#define KM_TCI_DATA_COLOR (2957L)
+#define KM_TCI_DATA_FT (2958L)
+#define KM_TCQ_CTRL (2959L)
+#define KM_TCQ_CTRL_ADR (2960L)
+#define KM_TCQ_CTRL_CNT (2961L)
+#define KM_TCQ_DATA (2962L)
+#define KM_TCQ_DATA_BANK_MASK (2963L)
+#define KM_TCQ_DATA_QUAL (2964L)
+/* LAO */
+/* MAC */
+#define MAC_CONF_SERDES_BITFRAG (2965L)
+#define MAC_CONF_SERDES_BITFRAG_BITFRAG (2966L)
+#define MAC_CONF_SERDES_DELAY (2967L)
+#define MAC_CONF_SERDES_DELAY_DELAY (2968L)
+#define MAC_CONF_SERDES_REORDER (2969L)
+#define MAC_CONF_SERDES_REORDER_REORDER (2970L)
+#define MAC_FAULTY_BLK (2971L)
+#define MAC_FAULTY_BLK_DATA (2972L)
+#define MAC_HOST_STAT_BYTE_FILL (2973L)
+#define MAC_HOST_STAT_BYTE_FILL_CNT (2974L)
+#define MAC_INT (2975L)
+#define MAC_INT_EN (2976L)
+#define MAC_INT_MAX_PACE (2977L)
+#define MAC_LINK_SUMMARY (2978L)
+#define MAC_LINK_SUMMARY_ABS (2979L)
+#define MAC_LINK_SUMMARY_GBOX_INTERR (2980L)
+#define MAC_LINK_SUMMARY_GLB_ALARMN (2981L)
+#define MAC_LINK_SUMMARY_LH_ABS (2982L)
+#define MAC_LINK_SUMMARY_LH_GLB_ALARMN (2983L)
+#define MAC_LINK_SUMMARY_LH_LOCAL_FAULT (2984L)
+#define MAC_LINK_SUMMARY_LH_REMOTE_FAULT (2985L)
+#define MAC_LINK_SUMMARY_LH_RX_LOS (2986L)
+#define MAC_LINK_SUMMARY_LINK_DOWN_CNT (2987L)
+#define MAC_LINK_SUMMARY_LL_PHY_LINK_STATE (2988L)
+#define MAC_LINK_SUMMARY_LOCAL_FAULT (2989L)
+#define MAC_LINK_SUMMARY_NT_PHY_LINK_STATE (2990L)
+#define MAC_LINK_SUMMARY_REMOTE_FAULT (2991L)
+#define MAC_LINK_SUMMARY_RX_LOS (2992L)
+#define MAC_MAC_STAT_BYTE (2993L)
+#define MAC_MAC_STAT_BYTE_CNT (2994L)
+#define MAC_MAC_STAT_CRC (2995L)
+#define MAC_MAC_STAT_CRC_CNT (2996L)
+#define MAC_MAC_STAT_CV (2997L)
+#define MAC_MAC_STAT_CV_CNT (2998L)
+#define MAC_MAC_STAT_FRAME (2999L)
+#define MAC_MAC_STAT_FRAME_CNT (3000L)
+#define MAC_MAC_STAT_MICRO_DROP (3001L)
+#define MAC_MAC_STAT_MICRO_DROP_CNT (3002L)
+#define MAC_MAC_STAT_RATE_DROP (3003L)
+#define MAC_MAC_STAT_RATE_DROP_CNT (3004L)
+#define MAC_MAC_STAT_TRUNC (3005L)
+#define MAC_MAC_STAT_TRUNC_CNT (3006L)
+#define MAC_MDS_CEN_VAL (3007L)
+#define MAC_MDS_CEN_VAL_VAL (3008L)
+#define MAC_MDS_CONF (3009L)
+#define MAC_MDS_CONF_CENTER_REC_ENA (3010L)
+#define MAC_MDS_CONF_CLR_STAT (3011L)
+#define MAC_MDS_CONF_ENA_TS_MOD (3012L)
+#define MAC_MDS_CONF_REC_ENA (3013L)
+#define MAC_MDS_CONF_TIME_MODE (3014L)
+#define MAC_MDS_DATA (3015L)
+#define MAC_MDS_DATA_DATA (3016L)
+#define MAC_MDS_FRAMES (3017L)
+#define MAC_MDS_FRAMES_CNT (3018L)
+#define MAC_MDS_MAX (3019L)
+#define MAC_MDS_MAX_MAX (3020L)
+#define MAC_MDS_MIN (3021L)
+#define MAC_MDS_MIN_MIN (3022L)
+#define MAC_MDS_STAT (3023L)
+#define MAC_MDS_STAT_CLR_BUSY (3024L)
+#define MAC_MDS_STAT_HIT_MAX (3025L)
+#define MAC_MDS_STAT_HIT_MIN (3026L)
+#define MAC_MDS_VAL_REC (3027L)
+#define MAC_MDS_VAL_REC_VALUE (3028L)
+#define MAC_MDS_VAL_REC_FRAME (3029L)
+#define MAC_MDS_VAL_REC_FRAME_VALUE (3030L)
+#define MAC_NT_PORT_CTRL (3031L)
+#define MAC_NT_PORT_CTRL_LED_MODE (3032L)
+#define MAC_RAM_MDS_ADDR (3033L)
+#define MAC_RAM_MDS_ADDR_ADR (3034L)
+#define MAC_RAM_MDS_ADDR_CLR_RAM (3035L)
+#define MAC_RAM_MDS_ADDR_RD_DONE (3036L)
+#define MAC_RAM_MDS_ADDR_RD_ENA (3037L)
+#define MAC_RAW_ADDR (3038L)
+#define MAC_RAW_ADDR_ADR (3039L)
+#define MAC_RAW_ADDR_RDENA (3040L)
+#define MAC_RAW_ADDR_RD_DONE (3041L)
+#define MAC_RAW_CTRL (3042L)
+#define MAC_RAW_CTRL_OVERWR_LM (3043L)
+#define MAC_RAW_CTRL_RESTART (3044L)
+#define MAC_RAW_CTRL_TG_ACT (3045L)
+#define MAC_RAW_CTRL_TG_ENA (3046L)
+#define MAC_RAW_CTRL_WRAP (3047L)
+#define MAC_RAW_DATA (3048L)
+#define MAC_RAW_DATA_RAW_DATA (3049L)
+#define MAC_RAW_REPETITION (3050L)
+#define MAC_RAW_REPETITION_CNT (3051L)
+#define MAC_RX_CONFIG (3052L)
+#define MAC_RX_CONFIG_DESCRAMB (3053L)
+#define MAC_RX_CONFIG_HOST_CLR_CNT (3054L)
+#define MAC_RX_CONFIG_MAC_CLR_CNT (3055L)
+#define MAC_RX_CONFIG_MIN_RX_FRAME (3056L)
+#define MAC_RX_CONFIG_NT_DEBOUNCE_LATENCY (3057L)
+#define MAC_RX_CONFIG_NT_FORCE_LINK_DOWN (3058L)
+#define MAC_RX_CONFIG_NT_LINKUP_LATENCY (3059L)
+#define MAC_RX_CONFIG_RST_BLK_ERR (3060L)
+#define MAC_RX_CONFIG_RX_MAC_EN (3061L)
+#define MAC_RX_CONFIG_TS_EOP (3062L)
+#define MAC_RX_CONFIG_TXRX_LOOP (3063L)
+#define MAC_RX_CONFIG2 (3064L)
+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_INT (3065L)
+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_LINK (3066L)
+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_RST (3067L)
+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_INT (3068L)
+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_LINK (3069L)
+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_RST (3070L)
+#define MAC_RX_STATUS (3071L)
+#define MAC_RX_STATUS_CORE_MODE (3072L)
+#define MAC_RX_STATUS_LOCAL_FAULT (3073L)
+#define MAC_RX_STATUS_REMOTE_FAULT (3074L)
+#define MAC_RX_STATUS_RXTX_OVERFLOW (3075L)
+#define MAC_RX_STATUS_VERSION (3076L)
+#define MAC_TFG_ADDR (3077L)
+#define MAC_TFG_ADDR_ADR (3078L)
+#define MAC_TFG_ADDR_RDENA (3079L)
+#define MAC_TFG_ADDR_RD_DONE (3080L)
+#define MAC_TFG_CTRL (3081L)
+#define MAC_TFG_CTRL_ID_ENA (3082L)
+#define MAC_TFG_CTRL_ID_POS (3083L)
+#define MAC_TFG_CTRL_RESTART (3084L)
+#define MAC_TFG_CTRL_TG_ACT (3085L)
+#define MAC_TFG_CTRL_TG_ENA (3086L)
+#define MAC_TFG_CTRL_TIME_MODE (3087L)
+#define MAC_TFG_CTRL_WRAP (3088L)
+#define MAC_TFG_DATA (3089L)
+#define MAC_TFG_DATA_GAP (3090L)
+#define MAC_TFG_DATA_ID (3091L)
+#define MAC_TFG_DATA_LENGTH (3092L)
+#define MAC_TFG_FRAME_HDR (3093L)
+#define MAC_TFG_FRAME_HDR_HDR (3094L)
+#define MAC_TFG_REPETITION (3095L)
+#define MAC_TFG_REPETITION_CNT (3096L)
+#define MAC_TX_CONFIG (3097L)
+#define MAC_TX_CONFIG_CLR_STICKY (3098L)
+#define MAC_TX_CONFIG_CRC_ERR_INS (3099L)
+#define MAC_TX_CONFIG_HOST_TX_ENA (3100L)
+#define MAC_TX_CONFIG_MAC_LOOP (3101L)
+#define MAC_TX_CONFIG_PCS_BIP_ERR (3102L)
+#define MAC_TX_CONFIG_PCS_DIS_BIP_INS (3103L)
+#define MAC_TX_CONFIG_PCS_IDLE (3104L)
+#define MAC_TX_CONFIG_PCS_IDLE_DIS (3105L)
+#define MAC_TX_CONFIG_PCS_LOCAL_FAULT (3106L)
+#define MAC_TX_CONFIG_PCS_LOCAL_FAULT_DIS (3107L)
+#define MAC_TX_CONFIG_PCS_REMOTE_FAULT (3108L)
+#define MAC_TX_CONFIG_PCS_REMOTE_FAULT_DIS (3109L)
+#define MAC_TX_CONFIG_PCS_SCRAMB_ENA (3110L)
+#define MAC_TX_CONFIG_PCS_SCRAMB_ERR (3111L)
+#define MAC_TX_CONFIG_TIME_OFFSET_TX (3112L)
+#define MAC_TX_CONFIG_TS_EOP (3113L)
+#define MAC_TX_STATUS (3114L)
+#define MAC_TX_STATUS_PCS_ERR (3115L)
+#define MAC_TX_STATUS_TX_MAC_ST (3116L)
+#define MAC_TX_STATUS_UNDER_FLOW (3117L)
+#define MAC_UPD_RX_COUNTERS (3118L)
+#define MAC_UPD_RX_COUNTERS_TRIGGER (3119L)
+/* MAC10 */
+#define MAC10_CFG_0 (3135L)
+#define MAC10_CFG_0_PAD_ENA (3136L)
+#define MAC10_CFG_0_RX_ENA (3137L)
+#define MAC10_CFG_0_RX_PAUSE_ENA (3138L)
+#define MAC10_CFG_0_STR_ENA (3139L)
+#define MAC10_CFG_0_TX_ENA (3140L)
+#define MAC10_CFG_0_TX_PAUSE_ENA (3141L)
+#define MAC10_MA (3142L)
+#define MAC10_MA_MAC10_ADR_0 (3143L)
+#define MAC10_MA_MAC_ADR_0 (3144L)
+#define MAC10_MA_LO (3145L)
+#define MAC10_MA_LO_MA_LO (3146L)
+#define MAC10_MA_MAX_SIZE (3147L)
+#define MAC10_MA_MAX_SIZE_MAC10_ADR_1 (3148L)
+#define MAC10_MA_MAX_SIZE_MAC_ADR_1 (3149L)
+#define MAC10_MA_MAX_SIZE_MTU (3150L)
+#define MAC10_MA_UP (3151L)
+#define MAC10_MA_UP_MA_UP (3152L)
+#define MAC10_STICKY_XAUI (3153L)
+#define MAC10_STICKY_XAUI_STICKY_XAUI (3154L)
+/* MAC100 */
+#define MAC100_CONF_SERDES_BITFRAG (3155L)
+#define MAC100_CONF_SERDES_BITFRAG_BITFRAG (3156L)
+#define MAC100_CONF_SERDES_DELAY (3157L)
+#define MAC100_CONF_SERDES_DELAY_DELAY (3158L)
+#define MAC100_CONF_SERDES_REORDER (3159L)
+#define MAC100_CONF_SERDES_REORDER_REORDER (3160L)
+#define MAC100_FAULTY_BLK (3161L)
+#define MAC100_FAULTY_BLK_DATA (3162L)
+#define MAC100_HOST_STAT_BYTE (3163L)
+#define MAC100_HOST_STAT_BYTE_CNT (3164L)
+#define MAC100_HOST_STAT_BYTE_FILL (3165L)
+#define MAC100_HOST_STAT_BYTE_FILL_CNT (3166L)
+#define MAC100_HOST_STAT_CRC (3167L)
+#define MAC100_HOST_STAT_CRC_CNT (3168L)
+#define MAC100_HOST_STAT_CV (3169L)
+#define MAC100_HOST_STAT_CV_CNT (3170L)
+#define MAC100_HOST_STAT_DROP (3171L)
+#define MAC100_HOST_STAT_DROP_CNT (3172L)
+#define MAC100_HOST_STAT_DROP_BYTE (3173L)
+#define MAC100_HOST_STAT_DROP_BYTE_CNT (3174L)
+#define MAC100_HOST_STAT_FRAME (3175L)
+#define MAC100_HOST_STAT_FRAME_CNT (3176L)
+#define MAC100_HOST_STAT_FRAME_FILL (3177L)
+#define MAC100_HOST_STAT_FRAME_FILL_CNT (3178L)
+#define MAC100_INT (3179L)
+#define MAC100_INT_EN (3180L)
+#define MAC100_INT_MAX_PACE (3181L)
+#define MAC100_LINK_SUMMARY (3182L)
+#define MAC100_LINK_SUMMARY_ABS (3183L)
+#define MAC100_LINK_SUMMARY_GBOX_INTERR (3184L)
+#define MAC100_LINK_SUMMARY_GLB_ALARMN (3185L)
+#define MAC100_LINK_SUMMARY_LH_ABS (3186L)
+#define MAC100_LINK_SUMMARY_LH_GLB_ALARMN (3187L)
+#define MAC100_LINK_SUMMARY_LH_LOCAL_FAULT (3188L)
+#define MAC100_LINK_SUMMARY_LH_REMOTE_FAULT (3189L)
+#define MAC100_LINK_SUMMARY_LH_RX_LOS (3190L)
+#define MAC100_LINK_SUMMARY_LINK_DOWN_CNT (3191L)
+#define MAC100_LINK_SUMMARY_LL_PHY_LINK_STATE (3192L)
+#define MAC100_LINK_SUMMARY_LOCAL_FAULT (3193L)
+#define MAC100_LINK_SUMMARY_NT_PHY_LINK_STATE (3194L)
+#define MAC100_LINK_SUMMARY_REMOTE_FAULT (3195L)
+#define MAC100_LINK_SUMMARY_RX_LOS (3196L)
+#define MAC100_MAC_STAT_BYTE (3197L)
+#define MAC100_MAC_STAT_BYTE_CNT (3198L)
+#define MAC100_MAC_STAT_CRC (3199L)
+#define MAC100_MAC_STAT_CRC_CNT (3200L)
+#define MAC100_MAC_STAT_CV (3201L)
+#define MAC100_MAC_STAT_CV_CNT (3202L)
+#define MAC100_MAC_STAT_FC (3203L)
+#define MAC100_MAC_STAT_FC_CNT (3204L)
+#define MAC100_MAC_STAT_FRAME (3205L)
+#define MAC100_MAC_STAT_FRAME_CNT (3206L)
+#define MAC100_MAC_STAT_MICRO_DROP (3207L)
+#define MAC100_MAC_STAT_MICRO_DROP_CNT (3208L)
+#define MAC100_MAC_STAT_PAUSE (3209L)
+#define MAC100_MAC_STAT_PAUSE_CNT (3210L)
+#define MAC100_MAC_STAT_RATE_DROP (3211L)
+#define MAC100_MAC_STAT_RATE_DROP_CNT (3212L)
+#define MAC100_MAC_STAT_TRUNC (3213L)
+#define MAC100_MAC_STAT_TRUNC_CNT (3214L)
+#define MAC100_MDS_CEN_VAL (3215L)
+#define MAC100_MDS_CEN_VAL_VAL (3216L)
+#define MAC100_MDS_CONF (3217L)
+#define MAC100_MDS_CONF_CENTER_REC_ENA (3218L)
+#define MAC100_MDS_CONF_CLR_STAT (3219L)
+#define MAC100_MDS_CONF_ENA_TS_MOD (3220L)
+#define MAC100_MDS_CONF_REC_ENA (3221L)
+#define MAC100_MDS_CONF_TIME_MODE (3222L)
+#define MAC100_MDS_DATA (3223L)
+#define MAC100_MDS_DATA_DATA (3224L)
+#define MAC100_MDS_FRAMES (3225L)
+#define MAC100_MDS_FRAMES_CNT (3226L)
+#define MAC100_MDS_MAX (3227L)
+#define MAC100_MDS_MAX_MAX (3228L)
+#define MAC100_MDS_MIN (3229L)
+#define MAC100_MDS_MIN_MIN (3230L)
+#define MAC100_MDS_STAT (3231L)
+#define MAC100_MDS_STAT_CLR_BUSY (3232L)
+#define MAC100_MDS_STAT_HIT_MAX (3233L)
+#define MAC100_MDS_STAT_HIT_MIN (3234L)
+#define MAC100_MDS_VAL_REC (3235L)
+#define MAC100_MDS_VAL_REC_VALUE (3236L)
+#define MAC100_MDS_VAL_REC_FRAME (3237L)
+#define MAC100_MDS_VAL_REC_FRAME_VALUE (3238L)
+#define MAC100_NT_PORT_CTRL (3239L)
+#define MAC100_NT_PORT_CTRL_LED_MODE (3240L)
+#define MAC100_RAM_MDS_ADDR (3241L)
+#define MAC100_RAM_MDS_ADDR_ADR (3242L)
+#define MAC100_RAM_MDS_ADDR_CLR_RAM (3243L)
+#define MAC100_RAM_MDS_ADDR_RD_DONE (3244L)
+#define MAC100_RAM_MDS_ADDR_RD_ENA (3245L)
+#define MAC100_RAW_ADDR (3246L)
+#define MAC100_RAW_ADDR_ADR (3247L)
+#define MAC100_RAW_ADDR_RDENA (3248L)
+#define MAC100_RAW_ADDR_RD_DONE (3249L)
+#define MAC100_RAW_CTRL (3250L)
+#define MAC100_RAW_CTRL_OVERWR_LM (3251L)
+#define MAC100_RAW_CTRL_RESTART (3252L)
+#define MAC100_RAW_CTRL_TG_ACT (3253L)
+#define MAC100_RAW_CTRL_TG_ENA (3254L)
+#define MAC100_RAW_CTRL_WRAP (3255L)
+#define MAC100_RAW_DATA (3256L)
+#define MAC100_RAW_DATA_RAW_DATA (3257L)
+#define MAC100_RAW_REPETITION (3258L)
+#define MAC100_RAW_REPETITION_CNT (3259L)
+#define MAC100_RX_CONFIG (3260L)
+#define MAC100_RX_CONFIG_DESCRAMB (3261L)
+#define MAC100_RX_CONFIG_HADP_RUN_MODE (3262L)
+#define MAC100_RX_CONFIG_HOST_CLR_CNT (3263L)
+#define MAC100_RX_CONFIG_MAC_CLR_CNT (3264L)
+#define MAC100_RX_CONFIG_MIN_RX_FRAME (3265L)
+#define MAC100_RX_CONFIG_NT_DEBOUNCE_LATENCY (3266L)
+#define MAC100_RX_CONFIG_NT_FORCE_LINK_DOWN (3267L)
+#define MAC100_RX_CONFIG_NT_LINKUP_LATENCY (3268L)
+#define MAC100_RX_CONFIG_RST_BLK_ERR (3269L)
+#define MAC100_RX_CONFIG_RX_MAC_EN (3270L)
+#define MAC100_RX_CONFIG_TS_EOP (3271L)
+#define MAC100_RX_CONFIG_TXRX_LOOP (3272L)
+#define MAC100_RX_CONFIG2 (3273L)
+#define MAC100_RX_CONFIG2_NT_MOD_ABS_MASK_INT (3274L)
+#define MAC100_RX_CONFIG2_NT_MOD_ABS_MASK_LINK (3275L)
+#define MAC100_RX_CONFIG2_NT_MOD_ABS_MASK_RST (3276L)
+#define MAC100_RX_CONFIG2_NT_RXLOS_MASK_INT (3277L)
+#define MAC100_RX_CONFIG2_NT_RXLOS_MASK_LINK (3278L)
+#define MAC100_RX_CONFIG2_NT_RXLOS_MASK_RST (3279L)
+#define MAC100_RX_STATUS (3280L)
+#define MAC100_RX_STATUS_CORE_MODE (3281L)
+#define MAC100_RX_STATUS_LOCAL_FAULT (3282L)
+#define MAC100_RX_STATUS_REMOTE_FAULT (3283L)
+#define MAC100_RX_STATUS_RXTX_OVERFLOW (3284L)
+#define MAC100_RX_STATUS_VERSION (3285L)
+#define MAC100_TFG_ADDR (3286L)
+#define MAC100_TFG_ADDR_ADR (3287L)
+#define MAC100_TFG_ADDR_RDENA (3288L)
+#define MAC100_TFG_ADDR_RD_DONE (3289L)
+#define MAC100_TFG_CTRL (3290L)
+#define MAC100_TFG_CTRL_ID_ENA (3291L)
+#define MAC100_TFG_CTRL_ID_POS (3292L)
+#define MAC100_TFG_CTRL_RESTART (3293L)
+#define MAC100_TFG_CTRL_TG_ACT (3294L)
+#define MAC100_TFG_CTRL_TG_ENA (3295L)
+#define MAC100_TFG_CTRL_TIME_MODE (3296L)
+#define MAC100_TFG_CTRL_WRAP (3297L)
+#define MAC100_TFG_DATA (3298L)
+#define MAC100_TFG_DATA_GAP (3299L)
+#define MAC100_TFG_DATA_ID (3300L)
+#define MAC100_TFG_DATA_LENGTH (3301L)
+#define MAC100_TFG_FRAME_HDR (3302L)
+#define MAC100_TFG_FRAME_HDR_HDR (3303L)
+#define MAC100_TFG_REPETITION (3304L)
+#define MAC100_TFG_REPETITION_CNT (3305L)
+#define MAC100_TX_CONFIG (3306L)
+#define MAC100_TX_CONFIG_CLR_STICKY (3307L)
+#define MAC100_TX_CONFIG_CRC_ERR_INS (3308L)
+#define MAC100_TX_CONFIG_HADP_LOOP (3309L)
+#define MAC100_TX_CONFIG_HOST_TX_ENA (3310L)
+#define MAC100_TX_CONFIG_MAC_LOOP (3311L)
+#define MAC100_TX_CONFIG_PCS_BIP_ERR (3312L)
+#define MAC100_TX_CONFIG_PCS_DIS_BIP_INS (3313L)
+#define MAC100_TX_CONFIG_PCS_IDLE (3314L)
+#define MAC100_TX_CONFIG_PCS_IDLE_DIS (3315L)
+#define MAC100_TX_CONFIG_PCS_LOCAL_FAULT (3316L)
+#define MAC100_TX_CONFIG_PCS_LOCAL_FAULT_DIS (3317L)
+#define MAC100_TX_CONFIG_PCS_REMOTE_FAULT (3318L)
+#define MAC100_TX_CONFIG_PCS_REMOTE_FAULT_DIS (3319L)
+#define MAC100_TX_CONFIG_PCS_SCRAMB_ENA (3320L)
+#define MAC100_TX_CONFIG_PCS_SCRAMB_ERR (3321L)
+#define MAC100_TX_CONFIG_TIME_OFFSET_TX (3322L)
+#define MAC100_TX_CONFIG_TS_EOP (3323L)
+#define MAC100_TX_STATUS (3324L)
+#define MAC100_TX_STATUS_PCS_ERR (3325L)
+#define MAC100_TX_STATUS_TX_HADP_ST (3326L)
+#define MAC100_TX_STATUS_TX_MAC_ST (3327L)
+#define MAC100_TX_STATUS_UNDER_FLOW (3328L)
+#define MAC100_UPD_RX_COUNTERS (3329L)
+#define MAC100_UPD_RX_COUNTERS_TRIGGER (3330L)
+/* MAC10G */
+#define MAC10G_CFG (3331L)
+#define MAC10G_CFG_MIN_RX_FRAME (3332L)
+#define MAC10G_CFG_RX_ENA (3333L)
+#define MAC10G_CFG_RX_EOP_TS (3334L)
+#define MAC10G_CFG_RX_PAUSE_ENA (3335L)
+#define MAC10G_CFG_STR_ENA (3336L)
+#define MAC10G_CFG_TX_ENA (3337L)
+#define MAC10G_CFG_TX_PAUSE_ENA (3338L)
+#define MAC10G_MA_LO (3339L)
+#define MAC10G_MA_LO_MA_LO (3340L)
+#define MAC10G_MA_UP (3341L)
+#define MAC10G_MA_UP_MA_UP (3342L)
+/* MAC1G */
+#define MAC1G_CFG (3343L)
+#define MAC1G_CFG_MIN_RX_FRAME (3344L)
+#define MAC1G_CFG_RX_ENA (3345L)
+#define MAC1G_CFG_RX_EOP_TS (3346L)
+#define MAC1G_CFG_RX_PAUSE_ENA (3347L)
+#define MAC1G_CFG_SPEED (3348L)
+#define MAC1G_CFG_STR_ENA (3349L)
+#define MAC1G_CFG_TX_ENA (3350L)
+#define MAC1G_CFG_TX_PAUSE_ENA (3351L)
+#define MAC1G_MA_LO (3352L)
+#define MAC1G_MA_LO_MA_LO (3353L)
+#define MAC1G_MA_UP (3354L)
+#define MAC1G_MA_UP_MA_UP (3355L)
+/* MAC_PCS */
+#define MAC_PCS_BAD_CODE (3366L)
+#define MAC_PCS_BAD_CODE_CODE_ERR (3367L)
+#define MAC_PCS_BIP_ERR (3368L)
+#define MAC_PCS_BIP_ERR_BIP_ERR (3369L)
+#define MAC_PCS_BLOCK_LOCK (3370L)
+#define MAC_PCS_BLOCK_LOCK_LOCK (3371L)
+#define MAC_PCS_BLOCK_LOCK_CHG (3372L)
+#define MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG (3373L)
+#define MAC_PCS_CLKRX_FRQ (3374L)
+#define MAC_PCS_CLKRX_FRQ_RX_FREQ (3375L)
+#define MAC_PCS_CLKTX_FRQ (3376L)
+#define MAC_PCS_CLKTX_FRQ_TX_FREQ (3377L)
+#define MAC_PCS_DEBOUNCE_CTRL (3378L)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY (3379L)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN (3380L)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY (3381L)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL (3382L)
+#define MAC_PCS_DRP_CONFIG (3383L)
+#define MAC_PCS_DRP_CONFIG_DRP_ADR (3384L)
+#define MAC_PCS_DRP_CONFIG_DRP_DI (3385L)
+#define MAC_PCS_DRP_CONFIG_DRP_EN (3386L)
+#define MAC_PCS_DRP_CONFIG_DRP_MOD_ADR (3387L)
+#define MAC_PCS_DRP_CONFIG_DRP_WREN (3388L)
+#define MAC_PCS_DRP_CTRL (3389L)
+#define MAC_PCS_DRP_CTRL_ADR (3390L)
+#define MAC_PCS_DRP_CTRL_DATA (3391L)
+#define MAC_PCS_DRP_CTRL_DBG_BUSY (3392L)
+#define MAC_PCS_DRP_CTRL_DONE (3393L)
+#define MAC_PCS_DRP_CTRL_MOD_ADR (3394L)
+#define MAC_PCS_DRP_CTRL_WREN (3395L)
+#define MAC_PCS_DRP_DATA (3396L)
+#define MAC_PCS_DRP_DATA_DRP_DO (3397L)
+#define MAC_PCS_DRP_DATA_DRP_RDY (3398L)
+#define MAC_PCS_FEC_CTRL (3399L)
+#define MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN (3400L)
+#define MAC_PCS_FEC_CW_CNT (3401L)
+#define MAC_PCS_FEC_CW_CNT_CW_CNT (3402L)
+#define MAC_PCS_FEC_ERR_CNT_0 (3403L)
+#define MAC_PCS_FEC_ERR_CNT_0_ERR_CNT (3404L)
+#define MAC_PCS_FEC_ERR_CNT_1 (3405L)
+#define MAC_PCS_FEC_ERR_CNT_1_ERR_CNT (3406L)
+#define MAC_PCS_FEC_ERR_CNT_2 (3407L)
+#define MAC_PCS_FEC_ERR_CNT_2_ERR_CNT (3408L)
+#define MAC_PCS_FEC_ERR_CNT_3 (3409L)
+#define MAC_PCS_FEC_ERR_CNT_3_ERR_CNT (3410L)
+#define MAC_PCS_FEC_LANE_DLY_0 (3411L)
+#define MAC_PCS_FEC_LANE_DLY_0_DLY (3412L)
+#define MAC_PCS_FEC_LANE_DLY_1 (3413L)
+#define MAC_PCS_FEC_LANE_DLY_1_DLY (3414L)
+#define MAC_PCS_FEC_LANE_DLY_2 (3415L)
+#define MAC_PCS_FEC_LANE_DLY_2_DLY (3416L)
+#define MAC_PCS_FEC_LANE_DLY_3 (3417L)
+#define MAC_PCS_FEC_LANE_DLY_3_DLY (3418L)
+#define MAC_PCS_FEC_LANE_MAP (3419L)
+#define MAC_PCS_FEC_LANE_MAP_MAPPING (3420L)
+#define MAC_PCS_FEC_STAT (3421L)
+#define MAC_PCS_FEC_STAT_AM_LOCK (3422L)
+#define MAC_PCS_FEC_STAT_AM_LOCK_0 (3423L)
+#define MAC_PCS_FEC_STAT_AM_LOCK_1 (3424L)
+#define MAC_PCS_FEC_STAT_AM_LOCK_2 (3425L)
+#define MAC_PCS_FEC_STAT_AM_LOCK_3 (3426L)
+#define MAC_PCS_FEC_STAT_BLOCK_LOCK (3427L)
+#define MAC_PCS_FEC_STAT_BYPASS (3428L)
+#define MAC_PCS_FEC_STAT_FEC_LANE_ALGN (3429L)
+#define MAC_PCS_FEC_STAT_HI_SER (3430L)
+#define MAC_PCS_FEC_STAT_PCS_LANE_ALGN (3431L)
+#define MAC_PCS_FEC_STAT_VALID (3432L)
+#define MAC_PCS_FEC_UCW_CNT (3433L)
+#define MAC_PCS_FEC_UCW_CNT_UCW_CNT (3434L)
+#define MAC_PCS_FRAMING_ERR (3435L)
+#define MAC_PCS_FRAMING_ERR_FRAMING_ERR (3436L)
+#define MAC_PCS_GTY_CTL (3437L)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_0 (3438L)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_1 (3439L)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_2 (3440L)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_3 (3441L)
+#define MAC_PCS_GTY_CTL_RX (3442L)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_0 (3443L)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_1 (3444L)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_2 (3445L)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_3 (3446L)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_0 (3447L)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_1 (3448L)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_2 (3449L)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_3 (3450L)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_0 (3451L)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_1 (3452L)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_2 (3453L)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_3 (3454L)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_0 (3455L)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_1 (3456L)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_2 (3457L)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_3 (3458L)
+#define MAC_PCS_GTY_CTL_RX_RATE_0 (3459L)
+#define MAC_PCS_GTY_CTL_RX_RATE_1 (3460L)
+#define MAC_PCS_GTY_CTL_RX_RATE_2 (3461L)
+#define MAC_PCS_GTY_CTL_RX_RATE_3 (3462L)
+#define MAC_PCS_GTY_CTL_TX (3463L)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_0 (3464L)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_1 (3465L)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_2 (3466L)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_3 (3467L)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_0 (3468L)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_1 (3469L)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_2 (3470L)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_3 (3471L)
+#define MAC_PCS_GTY_DIFF_CTL (3472L)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0 (3473L)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1 (3474L)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2 (3475L)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3 (3476L)
+#define MAC_PCS_GTY_LOOP (3477L)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_0 (3478L)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_1 (3479L)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_2 (3480L)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_3 (3481L)
+#define MAC_PCS_GTY_POST_CURSOR (3482L)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0 (3483L)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1 (3484L)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2 (3485L)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3 (3486L)
+#define MAC_PCS_GTY_PRBS_SEL (3487L)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0 (3488L)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1 (3489L)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2 (3490L)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3 (3491L)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0 (3492L)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1 (3493L)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2 (3494L)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3 (3495L)
+#define MAC_PCS_GTY_PRE_CURSOR (3496L)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0 (3497L)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1 (3498L)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2 (3499L)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3 (3500L)
+#define MAC_PCS_GTY_RX_BUF_STAT (3501L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0 (3502L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1 (3503L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2 (3504L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3 (3505L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0 (3506L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1 (3507L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2 (3508L)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3 (3509L)
+#define MAC_PCS_GTY_SCAN_CTL (3510L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0 (3511L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1 (3512L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2 (3513L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3 (3514L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0 (3515L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1 (3516L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2 (3517L)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3 (3518L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0 (3519L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1 (3520L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2 (3521L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3 (3522L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0 (3523L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1 (3524L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2 (3525L)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3 (3526L)
+#define MAC_PCS_GTY_SCAN_STAT (3527L)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0 (3528L)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1 (3529L)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2 (3530L)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3 (3531L)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0 (3532L)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1 (3533L)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2 (3534L)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3 (3535L)
+#define MAC_PCS_GTY_STAT (3536L)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_0 (3537L)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_1 (3538L)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_2 (3539L)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_3 (3540L)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_0 (3541L)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_1 (3542L)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_2 (3543L)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_3 (3544L)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_0 (3545L)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_1 (3546L)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_2 (3547L)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_3 (3548L)
+#define MAC_PCS_LANE_ALIGNER_FILL (3549L)
+#define MAC_PCS_LANE_ALIGNER_FILL_FILL (3550L)
+#define MAC_PCS_LINK_SUMMARY (3551L)
+#define MAC_PCS_LINK_SUMMARY_ABS (3552L)
+#define MAC_PCS_LINK_SUMMARY_LH_ABS (3553L)
+#define MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT (3554L)
+#define MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT (3555L)
+#define MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT (3556L)
+#define MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE (3557L)
+#define MAC_PCS_LINK_SUMMARY_LOCAL_FAULT (3558L)
+#define MAC_PCS_LINK_SUMMARY_NIM_INTERR (3559L)
+#define MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE (3560L)
+#define MAC_PCS_LINK_SUMMARY_REMOTE_FAULT (3561L)
+#define MAC_PCS_LINK_SUMMARY_RESERVED (3562L)
+#define MAC_PCS_MAC_PCS_CONFIG (3563L)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST (3564L)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE (3565L)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC (3566L)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST (3567L)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN (3568L)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST (3569L)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE (3570L)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE (3571L)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST (3572L)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE (3573L)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI (3574L)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN (3575L)
+#define MAC_PCS_MAX_PKT_LEN (3576L)
+#define MAC_PCS_MAX_PKT_LEN_MAX_LEN (3577L)
+#define MAC_PCS_MF_ERR (3578L)
+#define MAC_PCS_MF_ERR_MF_ERR (3579L)
+#define MAC_PCS_MF_LEN_ERR (3580L)
+#define MAC_PCS_MF_LEN_ERR_MF_LEN_ERR (3581L)
+#define MAC_PCS_MF_REPEAT_ERR (3582L)
+#define MAC_PCS_MF_REPEAT_ERR_MF_REPEAT_ERR (3583L)
+#define MAC_PCS_PHYMAC_MISC (3584L)
+#define MAC_PCS_PHYMAC_MISC_TS_EOP (3585L)
+#define MAC_PCS_PHYMAC_MISC_TX_MUX_STATE (3586L)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_HOST (3587L)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP (3588L)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_TFG (3589L)
+#define MAC_PCS_PHY_STAT (3590L)
+#define MAC_PCS_PHY_STAT_ALARM (3591L)
+#define MAC_PCS_PHY_STAT_MOD_PRS (3592L)
+#define MAC_PCS_PHY_STAT_RX_LOS (3593L)
+#define MAC_PCS_STAT_PCS_RX (3594L)
+#define MAC_PCS_STAT_PCS_RX_ALIGNED (3595L)
+#define MAC_PCS_STAT_PCS_RX_ALIGNED_ERR (3596L)
+#define MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS (3597L)
+#define MAC_PCS_STAT_PCS_RX_HI_BER (3598L)
+#define MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT (3599L)
+#define MAC_PCS_STAT_PCS_RX_LOCAL_FAULT (3600L)
+#define MAC_PCS_STAT_PCS_RX_MISALIGNED (3601L)
+#define MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT (3602L)
+#define MAC_PCS_STAT_PCS_RX_REMOTE_FAULT (3603L)
+#define MAC_PCS_STAT_PCS_RX_STATUS (3604L)
+#define MAC_PCS_STAT_PCS_RX_LATCH (3605L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED (3606L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR (3607L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS (3608L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_HI_BER (3609L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT (3610L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT (3611L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED (3612L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT (3613L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT (3614L)
+#define MAC_PCS_STAT_PCS_RX_LATCH_STATUS (3615L)
+#define MAC_PCS_STAT_PCS_TX (3616L)
+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT (3617L)
+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED (3618L)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR (3619L)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED (3620L)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR (3621L)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED (3622L)
+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT (3623L)
+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED (3624L)
+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT (3625L)
+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED (3626L)
+#define MAC_PCS_SYNCED (3627L)
+#define MAC_PCS_SYNCED_SYNC (3628L)
+#define MAC_PCS_SYNCED_ERR (3629L)
+#define MAC_PCS_SYNCED_ERR_SYNC_ERROR (3630L)
+#define MAC_PCS_TEST_ERR (3631L)
+#define MAC_PCS_TEST_ERR_CODE_ERR (3632L)
+#define MAC_PCS_TIMESTAMP_COMP (3633L)
+#define MAC_PCS_TIMESTAMP_COMP_RX_DLY (3634L)
+#define MAC_PCS_TIMESTAMP_COMP_TX_DLY (3635L)
+#define MAC_PCS_VL_DEMUXED (3636L)
+#define MAC_PCS_VL_DEMUXED_LOCK (3637L)
+#define MAC_PCS_VL_DEMUXED_CHG (3638L)
+#define MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG (3639L)
+#define MAC_PCS_VL_NUMBER (3640L)
+#define MAC_PCS_VL_NUMBER_VL_NUMBER (3641L)
+/* MAC_PCS_XXV */
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0 (3642L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ASMDIR (3643L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_BYPASS (3644L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ENABLE (3645L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_PAUSE (3646L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_RESTART (3647L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1 (3648L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ASMDIR (3649L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_BYPASS (3650L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ENABLE (3651L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_PAUSE (3652L)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_RESTART (3653L)
+#define MAC_PCS_XXV_ANEG_1G_STA_0 (3654L)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_COMPLETE (3655L)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ANEG_ABLE (3656L)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ASM (3657L)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_PAUSE (3658L)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_RF (3659L)
+#define MAC_PCS_XXV_ANEG_1G_STA_1 (3660L)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_COMPLETE (3661L)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ANEG_ABLE (3662L)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ASM (3663L)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_PAUSE (3664L)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_RF (3665L)
+#define MAC_PCS_XXV_ANEG_ABILITY_0 (3666L)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR (3667L)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR1 (3668L)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR_S (3669L)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR (3670L)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR1 (3671L)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR_S (3672L)
+#define MAC_PCS_XXV_ANEG_ABILITY_1 (3673L)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR (3674L)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR1 (3675L)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR_S (3676L)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR (3677L)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR1 (3678L)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR_S (3679L)
+#define MAC_PCS_XXV_ANEG_ABILITY_2 (3680L)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR (3681L)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR1 (3682L)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR_S (3683L)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR (3684L)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR1 (3685L)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR_S (3686L)
+#define MAC_PCS_XXV_ANEG_ABILITY_3 (3687L)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR (3688L)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR1 (3689L)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR_S (3690L)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR (3691L)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR1 (3692L)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR_S (3693L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0 (3694L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_ASMDIR (3695L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_BYPASS (3696L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_ENABLE (3697L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST (3698L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST_10G (3699L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_ABILITY (3700L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_REQUEST (3701L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_HIDE_FEC74 (3702L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_NONCE_SEED (3703L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_PAUSE (3704L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_PSEUDO (3705L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_REMOTE_FAULT (3706L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_RESTART (3707L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_RS_FEC_REQUEST (3708L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_FEC_OVERWRITE (3709L)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_SPEED_OVERWRITE (3710L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1 (3711L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_ASMDIR (3712L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_BYPASS (3713L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_ENABLE (3714L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST (3715L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST_10G (3716L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_ABILITY (3717L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_REQUEST (3718L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_HIDE_FEC74 (3719L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_NONCE_SEED (3720L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_PAUSE (3721L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_PSEUDO (3722L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_REMOTE_FAULT (3723L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_RESTART (3724L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_RS_FEC_REQUEST (3725L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_FEC_OVERWRITE (3726L)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_SPEED_OVERWRITE (3727L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2 (3728L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_ASMDIR (3729L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_BYPASS (3730L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_ENABLE (3731L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST (3732L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST_10G (3733L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_ABILITY (3734L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_REQUEST (3735L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_HIDE_FEC74 (3736L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_NONCE_SEED (3737L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_PAUSE (3738L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_PSEUDO (3739L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_REMOTE_FAULT (3740L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_RESTART (3741L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_RS_FEC_REQUEST (3742L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_FEC_OVERWRITE (3743L)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_SPEED_OVERWRITE (3744L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3 (3745L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_ASMDIR (3746L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_BYPASS (3747L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_ENABLE (3748L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST (3749L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST_10G (3750L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_ABILITY (3751L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_REQUEST (3752L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_HIDE_FEC74 (3753L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_NONCE_SEED (3754L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_PAUSE (3755L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_PSEUDO (3756L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_REMOTE_FAULT (3757L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_RESTART (3758L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_RS_FEC_REQUEST (3759L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_FEC_OVERWRITE (3760L)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_SPEED_OVERWRITE (3761L)
+#define MAC_PCS_XXV_ANEG_DEBUG_0 (3762L)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_END (3763L)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_STARTED (3764L)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_CDR_HOLD (3765L)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_END (3766L)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_STARTED (3767L)
+#define MAC_PCS_XXV_ANEG_DEBUG_1 (3768L)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_END (3769L)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_STARTED (3770L)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_CDR_HOLD (3771L)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_END (3772L)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_STARTED (3773L)
+#define MAC_PCS_XXV_ANEG_DEBUG_2 (3774L)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_END (3775L)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_STARTED (3776L)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_CDR_HOLD (3777L)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_END (3778L)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_STARTED (3779L)
+#define MAC_PCS_XXV_ANEG_DEBUG_3 (3780L)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_END (3781L)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_STARTED (3782L)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_CDR_HOLD (3783L)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_END (3784L)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_STARTED (3785L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0 (3786L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR (3787L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR1 (3788L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR_S (3789L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1 (3790L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR (3791L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR1 (3792L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR_S (3793L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2 (3794L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR (3795L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR1 (3796L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR_S (3797L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3 (3798L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR (3799L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR1 (3800L)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR_S (3801L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0 (3802L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR (3803L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR_S (3804L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1 (3805L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR (3806L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR_S (3807L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2 (3808L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR (3809L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR_S (3810L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3 (3811L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR (3812L)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR_S (3813L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0 (3814L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_ABILITY (3815L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_REQUEST (3816L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_ABILITY (3817L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_REQUEST (3818L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_25GBASE_CR1 (3819L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_EX_ABILITY_VALID (3820L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1 (3821L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_ABILITY (3822L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_REQUEST (3823L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_ABILITY (3824L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_REQUEST (3825L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_25GBASE_CR1 (3826L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_EX_ABILITY_VALID (3827L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2 (3828L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_ABILITY (3829L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_REQUEST (3830L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_ABILITY (3831L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_REQUEST (3832L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_25GBASE_CR1 (3833L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_EX_ABILITY_VALID (3834L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3 (3835L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_ABILITY (3836L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_REQUEST (3837L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_ABILITY (3838L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_REQUEST (3839L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_25GBASE_CR1 (3840L)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_EX_ABILITY_VALID (3841L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0 (3842L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ABILITY_VALID (3843L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ANEG_ABLE (3844L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ASM (3845L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_FEC74_REQ (3846L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_PAUSE (3847L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RF (3848L)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RS_FEC_REQ (3849L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1 (3850L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ABILITY_VALID (3851L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ANEG_ABLE (3852L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ASM (3853L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_FEC74_REQ (3854L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_PAUSE (3855L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RF (3856L)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RS_FEC_REQ (3857L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2 (3858L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ABILITY_VALID (3859L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ANEG_ABLE (3860L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ASM (3861L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_FEC74_REQ (3862L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_PAUSE (3863L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RF (3864L)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RS_FEC_REQ (3865L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3 (3866L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ABILITY_VALID (3867L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ANEG_ABLE (3868L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ASM (3869L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_FEC74_REQ (3870L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_PAUSE (3871L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RF (3872L)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RS_FEC_REQ (3873L)
+#define MAC_PCS_XXV_ANEG_STA_0 (3874L)
+#define MAC_PCS_XXV_ANEG_STA_0_COMPLETE (3875L)
+#define MAC_PCS_XXV_ANEG_STA_0_FEC74_EN (3876L)
+#define MAC_PCS_XXV_ANEG_STA_0_PAR_D_FAULT (3877L)
+#define MAC_PCS_XXV_ANEG_STA_0_RS_FEC_EN (3878L)
+#define MAC_PCS_XXV_ANEG_STA_0_RX_PAUSE_EN (3879L)
+#define MAC_PCS_XXV_ANEG_STA_0_TX_PAUSE_EN (3880L)
+#define MAC_PCS_XXV_ANEG_STA_1 (3881L)
+#define MAC_PCS_XXV_ANEG_STA_1_COMPLETE (3882L)
+#define MAC_PCS_XXV_ANEG_STA_1_FEC74_EN (3883L)
+#define MAC_PCS_XXV_ANEG_STA_1_PAR_D_FAULT (3884L)
+#define MAC_PCS_XXV_ANEG_STA_1_RS_FEC_EN (3885L)
+#define MAC_PCS_XXV_ANEG_STA_1_RX_PAUSE_EN (3886L)
+#define MAC_PCS_XXV_ANEG_STA_1_TX_PAUSE_EN (3887L)
+#define MAC_PCS_XXV_ANEG_STA_2 (3888L)
+#define MAC_PCS_XXV_ANEG_STA_2_COMPLETE (3889L)
+#define MAC_PCS_XXV_ANEG_STA_2_FEC74_EN (3890L)
+#define MAC_PCS_XXV_ANEG_STA_2_PAR_D_FAULT (3891L)
+#define MAC_PCS_XXV_ANEG_STA_2_RS_FEC_EN (3892L)
+#define MAC_PCS_XXV_ANEG_STA_2_RX_PAUSE_EN (3893L)
+#define MAC_PCS_XXV_ANEG_STA_2_TX_PAUSE_EN (3894L)
+#define MAC_PCS_XXV_ANEG_STA_3 (3895L)
+#define MAC_PCS_XXV_ANEG_STA_3_COMPLETE (3896L)
+#define MAC_PCS_XXV_ANEG_STA_3_FEC74_EN (3897L)
+#define MAC_PCS_XXV_ANEG_STA_3_PAR_D_FAULT (3898L)
+#define MAC_PCS_XXV_ANEG_STA_3_RS_FEC_EN (3899L)
+#define MAC_PCS_XXV_ANEG_STA_3_RX_PAUSE_EN (3900L)
+#define MAC_PCS_XXV_ANEG_STA_3_TX_PAUSE_EN (3901L)
+#define MAC_PCS_XXV_CLK_REF_ACTIVITY (3902L)
+#define MAC_PCS_XXV_CLK_REF_ACTIVITY_COUNT (3903L)
+#define MAC_PCS_XXV_CORE_CONF_0 (3904L)
+#define MAC_PCS_XXV_CORE_CONF_0_ENHANCED_TS (3905L)
+#define MAC_PCS_XXV_CORE_CONF_0_INLINE_MODE (3906L)
+#define MAC_PCS_XXV_CORE_CONF_0_LINE_LOOPBACK (3907L)
+#define MAC_PCS_XXV_CORE_CONF_0_RX_ENABLE (3908L)
+#define MAC_PCS_XXV_CORE_CONF_0_RX_FORCE_RESYNC (3909L)
+#define MAC_PCS_XXV_CORE_CONF_0_TS_AT_EOP (3910L)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_ENABLE (3911L)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_IGN_FCS (3912L)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_INS_FCS (3913L)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_IDLE (3914L)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_LFI (3915L)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_RFI (3916L)
+#define MAC_PCS_XXV_CORE_CONF_1 (3917L)
+#define MAC_PCS_XXV_CORE_CONF_1_ENHANCED_TS (3918L)
+#define MAC_PCS_XXV_CORE_CONF_1_INLINE_MODE (3919L)
+#define MAC_PCS_XXV_CORE_CONF_1_LINE_LOOPBACK (3920L)
+#define MAC_PCS_XXV_CORE_CONF_1_RX_ENABLE (3921L)
+#define MAC_PCS_XXV_CORE_CONF_1_RX_FORCE_RESYNC (3922L)
+#define MAC_PCS_XXV_CORE_CONF_1_TS_AT_EOP (3923L)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_ENABLE (3924L)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_IGN_FCS (3925L)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_INS_FCS (3926L)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_IDLE (3927L)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_LFI (3928L)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_RFI (3929L)
+#define MAC_PCS_XXV_CORE_CONF_2 (3930L)
+#define MAC_PCS_XXV_CORE_CONF_2_ENHANCED_TS (3931L)
+#define MAC_PCS_XXV_CORE_CONF_2_INLINE_MODE (3932L)
+#define MAC_PCS_XXV_CORE_CONF_2_LINE_LOOPBACK (3933L)
+#define MAC_PCS_XXV_CORE_CONF_2_RX_ENABLE (3934L)
+#define MAC_PCS_XXV_CORE_CONF_2_RX_FORCE_RESYNC (3935L)
+#define MAC_PCS_XXV_CORE_CONF_2_TS_AT_EOP (3936L)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_ENABLE (3937L)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_IGN_FCS (3938L)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_INS_FCS (3939L)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_IDLE (3940L)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_LFI (3941L)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_RFI (3942L)
+#define MAC_PCS_XXV_CORE_CONF_3 (3943L)
+#define MAC_PCS_XXV_CORE_CONF_3_ENHANCED_TS (3944L)
+#define MAC_PCS_XXV_CORE_CONF_3_INLINE_MODE (3945L)
+#define MAC_PCS_XXV_CORE_CONF_3_LINE_LOOPBACK (3946L)
+#define MAC_PCS_XXV_CORE_CONF_3_RX_ENABLE (3947L)
+#define MAC_PCS_XXV_CORE_CONF_3_RX_FORCE_RESYNC (3948L)
+#define MAC_PCS_XXV_CORE_CONF_3_TS_AT_EOP (3949L)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_ENABLE (3950L)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_IGN_FCS (3951L)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_INS_FCS (3952L)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_IDLE (3953L)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_LFI (3954L)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_RFI (3955L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0 (3956L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_DEBOUNCE_LATENCY (3957L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_FORCE_LINK_DOWN (3958L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_LINKUP_LATENCY (3959L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_PORT_CTRL (3960L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1 (3961L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_DEBOUNCE_LATENCY (3962L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_FORCE_LINK_DOWN (3963L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_LINKUP_LATENCY (3964L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_PORT_CTRL (3965L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2 (3966L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_DEBOUNCE_LATENCY (3967L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_FORCE_LINK_DOWN (3968L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_LINKUP_LATENCY (3969L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_PORT_CTRL (3970L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3 (3971L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_DEBOUNCE_LATENCY (3972L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_FORCE_LINK_DOWN (3973L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_LINKUP_LATENCY (3974L)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_PORT_CTRL (3975L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_0 (3976L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_0_FEC74_CCW_CNT (3977L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_1 (3978L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_1_FEC74_CCW_CNT (3979L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_2 (3980L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_2_FEC74_CCW_CNT (3981L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_3 (3982L)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_3_FEC74_CCW_CNT (3983L)
+#define MAC_PCS_XXV_FEC74_CONFIG_0 (3984L)
+#define MAC_PCS_XXV_FEC74_CONFIG_0_FEC74_ERRORS_TO_PCS (3985L)
+#define MAC_PCS_XXV_FEC74_CONFIG_0_RX_FEC74_ENABLE (3986L)
+#define MAC_PCS_XXV_FEC74_CONFIG_0_TX_FEC74_ENABLE (3987L)
+#define MAC_PCS_XXV_FEC74_CONFIG_1 (3988L)
+#define MAC_PCS_XXV_FEC74_CONFIG_1_FEC74_ERRORS_TO_PCS (3989L)
+#define MAC_PCS_XXV_FEC74_CONFIG_1_RX_FEC74_ENABLE (3990L)
+#define MAC_PCS_XXV_FEC74_CONFIG_1_TX_FEC74_ENABLE (3991L)
+#define MAC_PCS_XXV_FEC74_CONFIG_2 (3992L)
+#define MAC_PCS_XXV_FEC74_CONFIG_2_FEC74_ERRORS_TO_PCS (3993L)
+#define MAC_PCS_XXV_FEC74_CONFIG_2_RX_FEC74_ENABLE (3994L)
+#define MAC_PCS_XXV_FEC74_CONFIG_2_TX_FEC74_ENABLE (3995L)
+#define MAC_PCS_XXV_FEC74_CONFIG_3 (3996L)
+#define MAC_PCS_XXV_FEC74_CONFIG_3_FEC74_ERRORS_TO_PCS (3997L)
+#define MAC_PCS_XXV_FEC74_CONFIG_3_RX_FEC74_ENABLE (3998L)
+#define MAC_PCS_XXV_FEC74_CONFIG_3_TX_FEC74_ENABLE (3999L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_0 (4000L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_0_FEC74_UCW_CNT (4001L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_1 (4002L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_1_FEC74_UCW_CNT (4003L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_2 (4004L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_2_FEC74_UCW_CNT (4005L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_3 (4006L)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_3_FEC74_UCW_CNT (4007L)
+#define MAC_PCS_XXV_GTY_CTL_RX_0 (4008L)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_CDR_HOLD (4009L)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_EQUA_RST (4010L)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_LPM_EN (4011L)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_POLARITY (4012L)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_RATE (4013L)
+#define MAC_PCS_XXV_GTY_CTL_RX_1 (4014L)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_CDR_HOLD (4015L)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_EQUA_RST (4016L)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_LPM_EN (4017L)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_POLARITY (4018L)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_RATE (4019L)
+#define MAC_PCS_XXV_GTY_CTL_RX_2 (4020L)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_CDR_HOLD (4021L)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_EQUA_RST (4022L)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_LPM_EN (4023L)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_POLARITY (4024L)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_RATE (4025L)
+#define MAC_PCS_XXV_GTY_CTL_RX_3 (4026L)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_CDR_HOLD (4027L)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_EQUA_RST (4028L)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_LPM_EN (4029L)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_POLARITY (4030L)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_RATE (4031L)
+#define MAC_PCS_XXV_GTY_CTL_TX_0 (4032L)
+#define MAC_PCS_XXV_GTY_CTL_TX_0_INHIBIT (4033L)
+#define MAC_PCS_XXV_GTY_CTL_TX_0_POLARITY (4034L)
+#define MAC_PCS_XXV_GTY_CTL_TX_1 (4035L)
+#define MAC_PCS_XXV_GTY_CTL_TX_1_INHIBIT (4036L)
+#define MAC_PCS_XXV_GTY_CTL_TX_1_POLARITY (4037L)
+#define MAC_PCS_XXV_GTY_CTL_TX_2 (4038L)
+#define MAC_PCS_XXV_GTY_CTL_TX_2_INHIBIT (4039L)
+#define MAC_PCS_XXV_GTY_CTL_TX_2_POLARITY (4040L)
+#define MAC_PCS_XXV_GTY_CTL_TX_3 (4041L)
+#define MAC_PCS_XXV_GTY_CTL_TX_3_INHIBIT (4042L)
+#define MAC_PCS_XXV_GTY_CTL_TX_3_POLARITY (4043L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_0 (4044L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL (4045L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL_ADJUSTED (4046L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_1 (4047L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL (4048L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL_ADJUSTED (4049L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_2 (4050L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL (4051L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL_ADJUSTED (4052L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_3 (4053L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL (4054L)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL_ADJUSTED (4055L)
+#define MAC_PCS_XXV_GTY_LOOP_0 (4056L)
+#define MAC_PCS_XXV_GTY_LOOP_0_GT_LOOP (4057L)
+#define MAC_PCS_XXV_GTY_LOOP_1 (4058L)
+#define MAC_PCS_XXV_GTY_LOOP_1_GT_LOOP (4059L)
+#define MAC_PCS_XXV_GTY_LOOP_2 (4060L)
+#define MAC_PCS_XXV_GTY_LOOP_2_GT_LOOP (4061L)
+#define MAC_PCS_XXV_GTY_LOOP_3 (4062L)
+#define MAC_PCS_XXV_GTY_LOOP_3_GT_LOOP (4063L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_0 (4064L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_0_TX_MAIN_CTL (4065L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_1 (4066L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_1_TX_MAIN_CTL (4067L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_2 (4068L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_2_TX_MAIN_CTL (4069L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_3 (4070L)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_3_TX_MAIN_CTL (4071L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_0 (4072L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR (4073L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR_ADJUSTED (4074L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_1 (4075L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR (4076L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR_ADJUSTED (4077L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_2 (4078L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR (4079L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR_ADJUSTED (4080L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_3 (4081L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR (4082L)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR_ADJUSTED (4083L)
+#define MAC_PCS_XXV_GTY_PRBS_0 (4084L)
+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR (4085L)
+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR_INS (4086L)
+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_RST (4087L)
+#define MAC_PCS_XXV_GTY_PRBS_0_RX_PRBS_SEL (4088L)
+#define MAC_PCS_XXV_GTY_PRBS_0_TX_PRBS_SEL (4089L)
+#define MAC_PCS_XXV_GTY_PRBS_1 (4090L)
+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR (4091L)
+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR_INS (4092L)
+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_RST (4093L)
+#define MAC_PCS_XXV_GTY_PRBS_1_RX_PRBS_SEL (4094L)
+#define MAC_PCS_XXV_GTY_PRBS_1_TX_PRBS_SEL (4095L)
+#define MAC_PCS_XXV_GTY_PRBS_2 (4096L)
+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR (4097L)
+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR_INS (4098L)
+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_RST (4099L)
+#define MAC_PCS_XXV_GTY_PRBS_2_RX_PRBS_SEL (4100L)
+#define MAC_PCS_XXV_GTY_PRBS_2_TX_PRBS_SEL (4101L)
+#define MAC_PCS_XXV_GTY_PRBS_3 (4102L)
+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR (4103L)
+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR_INS (4104L)
+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_RST (4105L)
+#define MAC_PCS_XXV_GTY_PRBS_3_RX_PRBS_SEL (4106L)
+#define MAC_PCS_XXV_GTY_PRBS_3_TX_PRBS_SEL (4107L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_0 (4108L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_0_COUNT (4109L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_1 (4110L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_1_COUNT (4111L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_2 (4112L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_2_COUNT (4113L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_3 (4114L)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_3_COUNT (4115L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0 (4116L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR (4117L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR_ADJUSTED (4118L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1 (4119L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR (4120L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR_ADJUSTED (4121L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2 (4122L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR (4123L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR_ADJUSTED (4124L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3 (4125L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR (4126L)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR_ADJUSTED (4127L)
+#define MAC_PCS_XXV_GTY_STATUS_0 (4128L)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_POWERGOOD (4129L)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_RXBUFSTATUS (4130L)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_STARTOFSEQ (4131L)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_TXBUFSTATUS (4132L)
+#define MAC_PCS_XXV_GTY_STATUS_1 (4133L)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_POWERGOOD (4134L)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_RXBUFSTATUS (4135L)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_STARTOFSEQ (4136L)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_TXBUFSTATUS (4137L)
+#define MAC_PCS_XXV_GTY_STATUS_2 (4138L)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_POWERGOOD (4139L)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_RXBUFSTATUS (4140L)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_STARTOFSEQ (4141L)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_TXBUFSTATUS (4142L)
+#define MAC_PCS_XXV_GTY_STATUS_3 (4143L)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_POWERGOOD (4144L)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_RXBUFSTATUS (4145L)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_STARTOFSEQ (4146L)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_TXBUFSTATUS (4147L)
+#define MAC_PCS_XXV_LATENCY_0 (4148L)
+#define MAC_PCS_XXV_LATENCY_0_RX_LATENCY_MEAS (4149L)
+#define MAC_PCS_XXV_LATENCY_1 (4150L)
+#define MAC_PCS_XXV_LATENCY_1_RX_LATENCY_MEAS (4151L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0 (4152L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_MAIN (4153L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_POST (4154L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_PRE (4155L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_MAIN (4156L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_POST (4157L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_PRE (4158L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INIT (4159L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_PRESET (4160L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1 (4161L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_MAIN (4162L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_POST (4163L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_PRE (4164L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_MAIN (4165L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_POST (4166L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_PRE (4167L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INIT (4168L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_PRESET (4169L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2 (4170L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_MAIN (4171L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_POST (4172L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_PRE (4173L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_MAIN (4174L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_POST (4175L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_PRE (4176L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INIT (4177L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_PRESET (4178L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3 (4179L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_MAIN (4180L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_POST (4181L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_PRE (4182L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_MAIN (4183L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_POST (4184L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_PRE (4185L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INIT (4186L)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_PRESET (4187L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0 (4188L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_MAIN_STA (4189L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_POST_STA (4190L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_PRE_STA (4191L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1 (4192L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_MAIN_STA (4193L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_POST_STA (4194L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_PRE_STA (4195L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2 (4196L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_MAIN_STA (4197L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_POST_STA (4198L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_PRE_STA (4199L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3 (4200L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_MAIN_STA (4201L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_POST_STA (4202L)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_PRE_STA (4203L)
+#define MAC_PCS_XXV_LINK_SPEED_0 (4204L)
+#define MAC_PCS_XXV_LINK_SPEED_0_10G (4205L)
+#define MAC_PCS_XXV_LINK_SPEED_0_SPEED (4206L)
+#define MAC_PCS_XXV_LINK_SPEED_0_TOGGLE (4207L)
+#define MAC_PCS_XXV_LINK_SPEED_1 (4208L)
+#define MAC_PCS_XXV_LINK_SPEED_1_10G (4209L)
+#define MAC_PCS_XXV_LINK_SPEED_1_SPEED (4210L)
+#define MAC_PCS_XXV_LINK_SPEED_1_TOGGLE (4211L)
+#define MAC_PCS_XXV_LINK_SPEED_2 (4212L)
+#define MAC_PCS_XXV_LINK_SPEED_2_10G (4213L)
+#define MAC_PCS_XXV_LINK_SPEED_2_SPEED (4214L)
+#define MAC_PCS_XXV_LINK_SPEED_2_TOGGLE (4215L)
+#define MAC_PCS_XXV_LINK_SPEED_3 (4216L)
+#define MAC_PCS_XXV_LINK_SPEED_3_10G (4217L)
+#define MAC_PCS_XXV_LINK_SPEED_3_SPEED (4218L)
+#define MAC_PCS_XXV_LINK_SPEED_3_TOGGLE (4219L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0 (4220L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_ABS (4221L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_COMPLETE (4222L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_CONSORTIUM_MISMATCH (4223L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_INTERNAL_LOCAL_FAULT (4224L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_ABS (4225L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_INTERNAL_LOCAL_FAULT (4226L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_LOCAL_FAULT (4227L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT (4228L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_REMOTE_FAULT (4229L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_FEC74_LOCK_ERROR (4230L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE (4231L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_PCS_VALID_CTRL_CODE (4232L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_RSFEC_HI_SER (4233L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_LOCAL_FAULT (4234L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_UNDERRUN (4235L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LINK_DOWN_CNT (4236L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_PHY_LINK_STATE (4237L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK (4238L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_FEC74_LOCK (4239L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_RSFEC_LANE_ALIGNMENT (4240L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_TX_RSFEC_LANE_ALIGNMENT (4241L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LT_DONE (4242L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_NIM_INTERR (4243L)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_NT_PHY_LINK_STATE (4244L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1 (4245L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_ABS (4246L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_COMPLETE (4247L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_CONSORTIUM_MISMATCH (4248L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_INTERNAL_LOCAL_FAULT (4249L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_ABS (4250L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_INTERNAL_LOCAL_FAULT (4251L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_LOCAL_FAULT (4252L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT (4253L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_REMOTE_FAULT (4254L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_FEC74_LOCK_ERROR (4255L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE (4256L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_PCS_VALID_CTRL_CODE (4257L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_RSFEC_HI_SER (4258L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_LOCAL_FAULT (4259L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_UNDERRUN (4260L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LINK_DOWN_CNT (4261L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_PHY_LINK_STATE (4262L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK (4263L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_FEC74_LOCK (4264L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_RSFEC_LANE_ALIGNMENT (4265L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_TX_RSFEC_LANE_ALIGNMENT (4266L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LT_DONE (4267L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_NIM_INTERR (4268L)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_NT_PHY_LINK_STATE (4269L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2 (4270L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_ABS (4271L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_COMPLETE (4272L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_CONSORTIUM_MISMATCH (4273L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_INTERNAL_LOCAL_FAULT (4274L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_ABS (4275L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_INTERNAL_LOCAL_FAULT (4276L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_LOCAL_FAULT (4277L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RECEIVED_LOCAL_FAULT (4278L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_REMOTE_FAULT (4279L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_FEC74_LOCK_ERROR (4280L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_HIGH_BIT_ERROR_RATE (4281L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_PCS_VALID_CTRL_CODE (4282L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_RSFEC_HI_SER (4283L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_LOCAL_FAULT (4284L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_UNDERRUN (4285L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LINK_DOWN_CNT (4286L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_PHY_LINK_STATE (4287L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_BLOCK_LOCK (4288L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_FEC74_LOCK (4289L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_RSFEC_LANE_ALIGNMENT (4290L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_TX_RSFEC_LANE_ALIGNMENT (4291L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LT_DONE (4292L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_NIM_INTERR (4293L)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_NT_PHY_LINK_STATE (4294L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3 (4295L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_ABS (4296L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_COMPLETE (4297L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_CONSORTIUM_MISMATCH (4298L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_INTERNAL_LOCAL_FAULT (4299L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_ABS (4300L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_INTERNAL_LOCAL_FAULT (4301L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_LOCAL_FAULT (4302L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RECEIVED_LOCAL_FAULT (4303L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_REMOTE_FAULT (4304L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_FEC74_LOCK_ERROR (4305L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_HIGH_BIT_ERROR_RATE (4306L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_PCS_VALID_CTRL_CODE (4307L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_RSFEC_HI_SER (4308L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_LOCAL_FAULT (4309L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_UNDERRUN (4310L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LINK_DOWN_CNT (4311L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_PHY_LINK_STATE (4312L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_BLOCK_LOCK (4313L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_FEC74_LOCK (4314L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_RSFEC_LANE_ALIGNMENT (4315L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_TX_RSFEC_LANE_ALIGNMENT (4316L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LT_DONE (4317L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_NIM_INTERR (4318L)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_NT_PHY_LINK_STATE (4319L)
+#define MAC_PCS_XXV_LT_CONF_0 (4320L)
+#define MAC_PCS_XXV_LT_CONF_0_ENABLE (4321L)
+#define MAC_PCS_XXV_LT_CONF_0_RESTART (4322L)
+#define MAC_PCS_XXV_LT_CONF_0_SEED (4323L)
+#define MAC_PCS_XXV_LT_CONF_1 (4324L)
+#define MAC_PCS_XXV_LT_CONF_1_ENABLE (4325L)
+#define MAC_PCS_XXV_LT_CONF_1_RESTART (4326L)
+#define MAC_PCS_XXV_LT_CONF_1_SEED (4327L)
+#define MAC_PCS_XXV_LT_CONF_2 (4328L)
+#define MAC_PCS_XXV_LT_CONF_2_ENABLE (4329L)
+#define MAC_PCS_XXV_LT_CONF_2_RESTART (4330L)
+#define MAC_PCS_XXV_LT_CONF_2_SEED (4331L)
+#define MAC_PCS_XXV_LT_CONF_3 (4332L)
+#define MAC_PCS_XXV_LT_CONF_3_ENABLE (4333L)
+#define MAC_PCS_XXV_LT_CONF_3_RESTART (4334L)
+#define MAC_PCS_XXV_LT_CONF_3_SEED (4335L)
+#define MAC_PCS_XXV_LT_STA_0 (4336L)
+#define MAC_PCS_XXV_LT_STA_0_DONE (4337L)
+#define MAC_PCS_XXV_LT_STA_0_FAIL (4338L)
+#define MAC_PCS_XXV_LT_STA_0_LOCK (4339L)
+#define MAC_PCS_XXV_LT_STA_0_TRAIN (4340L)
+#define MAC_PCS_XXV_LT_STA_1 (4341L)
+#define MAC_PCS_XXV_LT_STA_1_DONE (4342L)
+#define MAC_PCS_XXV_LT_STA_1_FAIL (4343L)
+#define MAC_PCS_XXV_LT_STA_1_LOCK (4344L)
+#define MAC_PCS_XXV_LT_STA_1_TRAIN (4345L)
+#define MAC_PCS_XXV_LT_STA_2 (4346L)
+#define MAC_PCS_XXV_LT_STA_2_DONE (4347L)
+#define MAC_PCS_XXV_LT_STA_2_FAIL (4348L)
+#define MAC_PCS_XXV_LT_STA_2_LOCK (4349L)
+#define MAC_PCS_XXV_LT_STA_2_TRAIN (4350L)
+#define MAC_PCS_XXV_LT_STA_3 (4351L)
+#define MAC_PCS_XXV_LT_STA_3_DONE (4352L)
+#define MAC_PCS_XXV_LT_STA_3_FAIL (4353L)
+#define MAC_PCS_XXV_LT_STA_3_LOCK (4354L)
+#define MAC_PCS_XXV_LT_STA_3_TRAIN (4355L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0 (4356L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_ATTRIB (4357L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_NEXT (4358L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_PREV (4359L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1 (4360L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_ATTRIB (4361L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_NEXT (4362L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_PREV (4363L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2 (4364L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_ATTRIB (4365L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_NEXT (4366L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_PREV (4367L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3 (4368L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_ATTRIB (4369L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_NEXT (4370L)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_PREV (4371L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0 (4372L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_ATTRIB (4373L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_NEXT (4374L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_PREV (4375L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_SEL (4376L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_TABLE_ADDR (4377L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_UPDATE (4378L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1 (4379L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_ATTRIB (4380L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_NEXT (4381L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_PREV (4382L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_SEL (4383L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_TABLE_ADDR (4384L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_UPDATE (4385L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2 (4386L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_ATTRIB (4387L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_NEXT (4388L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_PREV (4389L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_SEL (4390L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_TABLE_ADDR (4391L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_UPDATE (4392L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3 (4393L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_ATTRIB (4394L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_NEXT (4395L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_PREV (4396L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_SEL (4397L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_TABLE_ADDR (4398L)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_UPDATE (4399L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0 (4400L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0_RX_MAX_LENGTH (4401L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1 (4402L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1_RX_MAX_LENGTH (4403L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2 (4404L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2_RX_MAX_LENGTH (4405L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3 (4406L)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3_RX_MAX_LENGTH (4407L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0 (4408L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_MIN_RX_FRAME (4409L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_RX_MIN_LENGTH (4410L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1 (4411L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_MIN_RX_FRAME (4412L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_RX_MIN_LENGTH (4413L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2 (4414L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_MIN_RX_FRAME (4415L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_RX_MIN_LENGTH (4416L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3 (4417L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_MIN_RX_FRAME (4418L)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_RX_MIN_LENGTH (4419L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_0 (4420L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_0_MAX_LEN (4421L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_1 (4422L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_1_MAX_LEN (4423L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_2 (4424L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_2_MAX_LEN (4425L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_3 (4426L)
+#define MAC_PCS_XXV_MAX_PKT_LEN_3_MAX_LEN (4427L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0 (4428L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_MAIN (4429L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_POST (4430L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_PRE (4431L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ENABLE (4432L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_INIT (4433L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_PRESET (4434L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_RX_READY (4435L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1 (4436L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_MAIN (4437L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_POST (4438L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_PRE (4439L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ENABLE (4440L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_INIT (4441L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_PRESET (4442L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_RX_READY (4443L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2 (4444L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_MAIN (4445L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_POST (4446L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_PRE (4447L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ENABLE (4448L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_INIT (4449L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_PRESET (4450L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_RX_READY (4451L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3 (4452L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_MAIN (4453L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_POST (4454L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_PRE (4455L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ENABLE (4456L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_INIT (4457L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_PRESET (4458L)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_RX_READY (4459L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0 (4460L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_MAIN_STA (4461L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_POST_STA (4462L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_PRE_STA (4463L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1 (4464L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_MAIN_STA (4465L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_POST_STA (4466L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_PRE_STA (4467L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2 (4468L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_MAIN_STA (4469L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_POST_STA (4470L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_PRE_STA (4471L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3 (4472L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_MAIN_STA (4473L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_POST_STA (4474L)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_PRE_STA (4475L)
+#define MAC_PCS_XXV_RST_0 (4476L)
+#define MAC_PCS_XXV_RST_0_MAC_PCS (4477L)
+#define MAC_PCS_XXV_RST_1 (4478L)
+#define MAC_PCS_XXV_RST_1_MAC_PCS (4479L)
+#define MAC_PCS_XXV_RST_2 (4480L)
+#define MAC_PCS_XXV_RST_2_MAC_PCS (4481L)
+#define MAC_PCS_XXV_RST_3 (4482L)
+#define MAC_PCS_XXV_RST_3_MAC_PCS (4483L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0 (4484L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0_RS_FEC_CCW_CNT (4485L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1 (4486L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1_RS_FEC_CCW_CNT (4487L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2 (4488L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2_RS_FEC_CCW_CNT (4489L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3 (4490L)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3_RS_FEC_CCW_CNT (4491L)
+#define MAC_PCS_XXV_RS_FEC_CONF_0 (4492L)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_CONSORTIUM (4493L)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_CORRECTION (4494L)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_ENABLE (4495L)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_IEEE_ERROR_INDICATION (4496L)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_INDICATION (4497L)
+#define MAC_PCS_XXV_RS_FEC_CONF_1 (4498L)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_CONSORTIUM (4499L)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_CORRECTION (4500L)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_ENABLE (4501L)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_IEEE_ERROR_INDICATION (4502L)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_INDICATION (4503L)
+#define MAC_PCS_XXV_RS_FEC_CONF_2 (4504L)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_CONSORTIUM (4505L)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_CORRECTION (4506L)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_ENABLE (4507L)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_IEEE_ERROR_INDICATION (4508L)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_INDICATION (4509L)
+#define MAC_PCS_XXV_RS_FEC_CONF_3 (4510L)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_CONSORTIUM (4511L)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_CORRECTION (4512L)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_ENABLE (4513L)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_IEEE_ERROR_INDICATION (4514L)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_INDICATION (4515L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0 (4516L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0_RS_FEC_ERR_CNT (4517L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1 (4518L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1_RS_FEC_ERR_CNT (4519L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2 (4520L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2_RS_FEC_ERR_CNT (4521L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3 (4522L)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3_RS_FEC_ERR_CNT (4523L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0 (4524L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0_RS_FEC_UCW_CNT (4525L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1 (4526L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1_RS_FEC_UCW_CNT (4527L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2 (4528L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2_RS_FEC_UCW_CNT (4529L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3 (4530L)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3_RS_FEC_UCW_CNT (4531L)
+#define MAC_PCS_XXV_RX_BAD_FCS_0 (4532L)
+#define MAC_PCS_XXV_RX_BAD_FCS_0_COUNT (4533L)
+#define MAC_PCS_XXV_RX_BAD_FCS_1 (4534L)
+#define MAC_PCS_XXV_RX_BAD_FCS_1_COUNT (4535L)
+#define MAC_PCS_XXV_RX_BAD_FCS_2 (4536L)
+#define MAC_PCS_XXV_RX_BAD_FCS_2_COUNT (4537L)
+#define MAC_PCS_XXV_RX_BAD_FCS_3 (4538L)
+#define MAC_PCS_XXV_RX_BAD_FCS_3_COUNT (4539L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_0 (4540L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_0_COUNT (4541L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_1 (4542L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_1_COUNT (4543L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_2 (4544L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_2_COUNT (4545L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_3 (4546L)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_3_COUNT (4547L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_0 (4548L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_0_COUNT (4549L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_1 (4550L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_1_COUNT (4551L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_2 (4552L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_2_COUNT (4553L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_3 (4554L)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_3_COUNT (4555L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_0 (4556L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_0_COUNT (4557L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_1 (4558L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_1_COUNT (4559L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_2 (4560L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_2_COUNT (4561L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_3 (4562L)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_3_COUNT (4563L)
+#define MAC_PCS_XXV_RX_LATENCY_0 (4564L)
+#define MAC_PCS_XXV_RX_LATENCY_0_LATENCY (4565L)
+#define MAC_PCS_XXV_RX_LATENCY_1 (4566L)
+#define MAC_PCS_XXV_RX_LATENCY_1_LATENCY (4567L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_0 (4568L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_0_COUNT (4569L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_1 (4570L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_1_COUNT (4571L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_2 (4572L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_2_COUNT (4573L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_3 (4574L)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_3_COUNT (4575L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0 (4576L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0_COUNT (4577L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1 (4578L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1_COUNT (4579L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2 (4580L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2_COUNT (4581L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3 (4582L)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3_COUNT (4583L)
+#define MAC_PCS_XXV_SUB_RST_0 (4584L)
+#define MAC_PCS_XXV_SUB_RST_0_AN_LT (4585L)
+#define MAC_PCS_XXV_SUB_RST_0_QPLL (4586L)
+#define MAC_PCS_XXV_SUB_RST_0_RX_BUF (4587L)
+#define MAC_PCS_XXV_SUB_RST_0_RX_GT_DATA (4588L)
+#define MAC_PCS_XXV_SUB_RST_0_RX_MAC_PCS (4589L)
+#define MAC_PCS_XXV_SUB_RST_0_RX_PCS (4590L)
+#define MAC_PCS_XXV_SUB_RST_0_RX_PMA (4591L)
+#define MAC_PCS_XXV_SUB_RST_0_SPEED_CTRL (4592L)
+#define MAC_PCS_XXV_SUB_RST_0_TX_GT_DATA (4593L)
+#define MAC_PCS_XXV_SUB_RST_0_TX_MAC_PCS (4594L)
+#define MAC_PCS_XXV_SUB_RST_0_TX_PCS (4595L)
+#define MAC_PCS_XXV_SUB_RST_0_TX_PMA (4596L)
+#define MAC_PCS_XXV_SUB_RST_1 (4597L)
+#define MAC_PCS_XXV_SUB_RST_1_AN_LT (4598L)
+#define MAC_PCS_XXV_SUB_RST_1_QPLL (4599L)
+#define MAC_PCS_XXV_SUB_RST_1_RX_BUF (4600L)
+#define MAC_PCS_XXV_SUB_RST_1_RX_GT_DATA (4601L)
+#define MAC_PCS_XXV_SUB_RST_1_RX_MAC_PCS (4602L)
+#define MAC_PCS_XXV_SUB_RST_1_RX_PCS (4603L)
+#define MAC_PCS_XXV_SUB_RST_1_RX_PMA (4604L)
+#define MAC_PCS_XXV_SUB_RST_1_SPEED_CTRL (4605L)
+#define MAC_PCS_XXV_SUB_RST_1_TX_GT_DATA (4606L)
+#define MAC_PCS_XXV_SUB_RST_1_TX_MAC_PCS (4607L)
+#define MAC_PCS_XXV_SUB_RST_1_TX_PCS (4608L)
+#define MAC_PCS_XXV_SUB_RST_1_TX_PMA (4609L)
+#define MAC_PCS_XXV_SUB_RST_2 (4610L)
+#define MAC_PCS_XXV_SUB_RST_2_AN_LT (4611L)
+#define MAC_PCS_XXV_SUB_RST_2_QPLL (4612L)
+#define MAC_PCS_XXV_SUB_RST_2_RX_BUF (4613L)
+#define MAC_PCS_XXV_SUB_RST_2_RX_GT_DATA (4614L)
+#define MAC_PCS_XXV_SUB_RST_2_RX_MAC_PCS (4615L)
+#define MAC_PCS_XXV_SUB_RST_2_RX_PCS (4616L)
+#define MAC_PCS_XXV_SUB_RST_2_RX_PMA (4617L)
+#define MAC_PCS_XXV_SUB_RST_2_SPEED_CTRL (4618L)
+#define MAC_PCS_XXV_SUB_RST_2_TX_GT_DATA (4619L)
+#define MAC_PCS_XXV_SUB_RST_2_TX_MAC_PCS (4620L)
+#define MAC_PCS_XXV_SUB_RST_2_TX_PCS (4621L)
+#define MAC_PCS_XXV_SUB_RST_2_TX_PMA (4622L)
+#define MAC_PCS_XXV_SUB_RST_3 (4623L)
+#define MAC_PCS_XXV_SUB_RST_3_AN_LT (4624L)
+#define MAC_PCS_XXV_SUB_RST_3_QPLL (4625L)
+#define MAC_PCS_XXV_SUB_RST_3_RX_BUF (4626L)
+#define MAC_PCS_XXV_SUB_RST_3_RX_GT_DATA (4627L)
+#define MAC_PCS_XXV_SUB_RST_3_RX_MAC_PCS (4628L)
+#define MAC_PCS_XXV_SUB_RST_3_RX_PCS (4629L)
+#define MAC_PCS_XXV_SUB_RST_3_RX_PMA (4630L)
+#define MAC_PCS_XXV_SUB_RST_3_SPEED_CTRL (4631L)
+#define MAC_PCS_XXV_SUB_RST_3_TX_GT_DATA (4632L)
+#define MAC_PCS_XXV_SUB_RST_3_TX_MAC_PCS (4633L)
+#define MAC_PCS_XXV_SUB_RST_3_TX_PCS (4634L)
+#define MAC_PCS_XXV_SUB_RST_3_TX_PMA (4635L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0 (4636L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0_QPLL_LOCK (4637L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_RX_RST (4638L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_TX_RST (4639L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1 (4640L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1_QPLL_LOCK (4641L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_RX_RST (4642L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_TX_RST (4643L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2 (4644L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2_QPLL_LOCK (4645L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_RX_RST (4646L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_TX_RST (4647L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3 (4648L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3_QPLL_LOCK (4649L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_RX_RST (4650L)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_TX_RST (4651L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_0 (4652L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_0_RX_DLY (4653L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_0_TX_DLY (4654L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_1 (4655L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_1_RX_DLY (4656L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_1_TX_DLY (4657L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_2 (4658L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_2_RX_DLY (4659L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_2_TX_DLY (4660L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_3 (4661L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_3_RX_DLY (4662L)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_3_TX_DLY (4663L)
+#define MAC_PCS_XXV_TX_BAD_FCS_0 (4664L)
+#define MAC_PCS_XXV_TX_BAD_FCS_0_COUNT (4665L)
+#define MAC_PCS_XXV_TX_BAD_FCS_1 (4666L)
+#define MAC_PCS_XXV_TX_BAD_FCS_1_COUNT (4667L)
+#define MAC_PCS_XXV_TX_BAD_FCS_2 (4668L)
+#define MAC_PCS_XXV_TX_BAD_FCS_2_COUNT (4669L)
+#define MAC_PCS_XXV_TX_BAD_FCS_3 (4670L)
+#define MAC_PCS_XXV_TX_BAD_FCS_3_COUNT (4671L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_0 (4672L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_0_COUNT (4673L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_1 (4674L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_1_COUNT (4675L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_2 (4676L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_2_COUNT (4677L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_3 (4678L)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_3_COUNT (4679L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_0 (4680L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_0_COUNT (4681L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_1 (4682L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_1_COUNT (4683L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_2 (4684L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_2_COUNT (4685L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_3 (4686L)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_3_COUNT (4687L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_0 (4688L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_0_COUNT (4689L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_1 (4690L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_1_COUNT (4691L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_2 (4692L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_2_COUNT (4693L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_3 (4694L)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_3_COUNT (4695L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_0 (4696L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_0_COUNT (4697L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_1 (4698L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_1_COUNT (4699L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_2 (4700L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_2_COUNT (4701L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_3 (4702L)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_3_COUNT (4703L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0 (4704L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0_COUNT (4705L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1 (4706L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1_COUNT (4707L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2 (4708L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2_COUNT (4709L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3 (4710L)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3_COUNT (4711L)
+/* MAC_RX */
+#define MAC_RX_BAD_FCS (4712L)
+#define MAC_RX_BAD_FCS_COUNT (4713L)
+#define MAC_RX_BAD_PREAMBLE (4714L)
+#define MAC_RX_BAD_PREAMBLE_COUNT (4715L)
+#define MAC_RX_BAD_SFD (4716L)
+#define MAC_RX_BAD_SFD_COUNT (4717L)
+#define MAC_RX_BROADCAST (4718L)
+#define MAC_RX_BROADCAST_COUNT (4719L)
+#define MAC_RX_FRAGMENT (4720L)
+#define MAC_RX_FRAGMENT_COUNT (4721L)
+#define MAC_RX_INRANGEERR (4722L)
+#define MAC_RX_INRANGEERR_COUNT (4723L)
+#define MAC_RX_JABBER (4724L)
+#define MAC_RX_JABBER_COUNT (4725L)
+#define MAC_RX_MULTICAST (4726L)
+#define MAC_RX_MULTICAST_COUNT (4727L)
+#define MAC_RX_OVERSIZE (4728L)
+#define MAC_RX_OVERSIZE_COUNT (4729L)
+#define MAC_RX_PACKET_1024_1518_BYTES (4730L)
+#define MAC_RX_PACKET_1024_1518_BYTES_COUNT (4731L)
+#define MAC_RX_PACKET_128_255_BYTES (4732L)
+#define MAC_RX_PACKET_128_255_BYTES_COUNT (4733L)
+#define MAC_RX_PACKET_1519_1522_BYTES (4734L)
+#define MAC_RX_PACKET_1519_1522_BYTES_COUNT (4735L)
+#define MAC_RX_PACKET_1523_1548_BYTES (4736L)
+#define MAC_RX_PACKET_1523_1548_BYTES_COUNT (4737L)
+#define MAC_RX_PACKET_1549_2047_BYTES (4738L)
+#define MAC_RX_PACKET_1549_2047_BYTES_COUNT (4739L)
+#define MAC_RX_PACKET_2048_4095_BYTES (4740L)
+#define MAC_RX_PACKET_2048_4095_BYTES_COUNT (4741L)
+#define MAC_RX_PACKET_256_511_BYTES (4742L)
+#define MAC_RX_PACKET_256_511_BYTES_COUNT (4743L)
+#define MAC_RX_PACKET_4096_8191_BYTES (4744L)
+#define MAC_RX_PACKET_4096_8191_BYTES_COUNT (4745L)
+#define MAC_RX_PACKET_512_1023_BYTES (4746L)
+#define MAC_RX_PACKET_512_1023_BYTES_COUNT (4747L)
+#define MAC_RX_PACKET_64_BYTES (4748L)
+#define MAC_RX_PACKET_64_BYTES_COUNT (4749L)
+#define MAC_RX_PACKET_65_127_BYTES (4750L)
+#define MAC_RX_PACKET_65_127_BYTES_COUNT (4751L)
+#define MAC_RX_PACKET_8192_9215_BYTES (4752L)
+#define MAC_RX_PACKET_8192_9215_BYTES_COUNT (4753L)
+#define MAC_RX_PACKET_BAD_FCS (4754L)
+#define MAC_RX_PACKET_BAD_FCS_COUNT (4755L)
+#define MAC_RX_PACKET_LARGE (4756L)
+#define MAC_RX_PACKET_LARGE_COUNT (4757L)
+#define MAC_RX_PACKET_SMALL (4758L)
+#define MAC_RX_PACKET_SMALL_COUNT (4759L)
+#define MAC_RX_STOMPED_FCS (4760L)
+#define MAC_RX_STOMPED_FCS_COUNT (4761L)
+#define MAC_RX_TOOLONG (4762L)
+#define MAC_RX_TOOLONG_COUNT (4763L)
+#define MAC_RX_TOTAL_BYTES (4764L)
+#define MAC_RX_TOTAL_BYTES_COUNT (4765L)
+#define MAC_RX_TOTAL_GOOD_BYTES (4766L)
+#define MAC_RX_TOTAL_GOOD_BYTES_COUNT (4767L)
+#define MAC_RX_TOTAL_GOOD_PACKETS (4768L)
+#define MAC_RX_TOTAL_GOOD_PACKETS_COUNT (4769L)
+#define MAC_RX_TOTAL_PACKETS (4770L)
+#define MAC_RX_TOTAL_PACKETS_COUNT (4771L)
+#define MAC_RX_TRUNCATED (4772L)
+#define MAC_RX_TRUNCATED_COUNT (4773L)
+#define MAC_RX_UNDERSIZE (4774L)
+#define MAC_RX_UNDERSIZE_COUNT (4775L)
+#define MAC_RX_UNICAST (4776L)
+#define MAC_RX_UNICAST_COUNT (4777L)
+#define MAC_RX_VLAN (4778L)
+#define MAC_RX_VLAN_COUNT (4779L)
+/* MAC_TFG */
+#define MAC_TFG_TFG_ADDR (4780L)
+#define MAC_TFG_TFG_ADDR_ADR (4781L)
+#define MAC_TFG_TFG_ADDR_RDENA (4782L)
+#define MAC_TFG_TFG_ADDR_RD_DONE (4783L)
+#define MAC_TFG_TFG_CTRL (4784L)
+#define MAC_TFG_TFG_CTRL_ID_ENA (4785L)
+#define MAC_TFG_TFG_CTRL_ID_POS (4786L)
+#define MAC_TFG_TFG_CTRL_RESTART (4787L)
+#define MAC_TFG_TFG_CTRL_TG_ACT (4788L)
+#define MAC_TFG_TFG_CTRL_TG_ENA (4789L)
+#define MAC_TFG_TFG_CTRL_TIME_MODE (4790L)
+#define MAC_TFG_TFG_CTRL_WRAP (4791L)
+#define MAC_TFG_TFG_DATA (4792L)
+#define MAC_TFG_TFG_DATA_GAP (4793L)
+#define MAC_TFG_TFG_DATA_ID (4794L)
+#define MAC_TFG_TFG_DATA_LENGTH (4795L)
+#define MAC_TFG_TFG_FRAME_HDR (4796L)
+#define MAC_TFG_TFG_FRAME_HDR_HDR (4797L)
+#define MAC_TFG_TFG_REPETITION (4798L)
+#define MAC_TFG_TFG_REPETITION_CNT (4799L)
+/* MAC_TX */
+#define MAC_TX_BAD_FCS (4800L)
+#define MAC_TX_BAD_FCS_COUNT (4801L)
+#define MAC_TX_BROADCAST (4802L)
+#define MAC_TX_BROADCAST_COUNT (4803L)
+#define MAC_TX_FRAME_ERRORS (4804L)
+#define MAC_TX_FRAME_ERRORS_COUNT (4805L)
+#define MAC_TX_MULTICAST (4806L)
+#define MAC_TX_MULTICAST_COUNT (4807L)
+#define MAC_TX_PACKET_1024_1518_BYTES (4808L)
+#define MAC_TX_PACKET_1024_1518_BYTES_COUNT (4809L)
+#define MAC_TX_PACKET_128_255_BYTES (4810L)
+#define MAC_TX_PACKET_128_255_BYTES_COUNT (4811L)
+#define MAC_TX_PACKET_1519_1522_BYTES (4812L)
+#define MAC_TX_PACKET_1519_1522_BYTES_COUNT (4813L)
+#define MAC_TX_PACKET_1523_1548_BYTES (4814L)
+#define MAC_TX_PACKET_1523_1548_BYTES_COUNT (4815L)
+#define MAC_TX_PACKET_1549_2047_BYTES (4816L)
+#define MAC_TX_PACKET_1549_2047_BYTES_COUNT (4817L)
+#define MAC_TX_PACKET_2048_4095_BYTES (4818L)
+#define MAC_TX_PACKET_2048_4095_BYTES_COUNT (4819L)
+#define MAC_TX_PACKET_256_511_BYTES (4820L)
+#define MAC_TX_PACKET_256_511_BYTES_COUNT (4821L)
+#define MAC_TX_PACKET_4096_8191_BYTES (4822L)
+#define MAC_TX_PACKET_4096_8191_BYTES_COUNT (4823L)
+#define MAC_TX_PACKET_512_1023_BYTES (4824L)
+#define MAC_TX_PACKET_512_1023_BYTES_COUNT (4825L)
+#define MAC_TX_PACKET_64_BYTES (4826L)
+#define MAC_TX_PACKET_64_BYTES_COUNT (4827L)
+#define MAC_TX_PACKET_65_127_BYTES (4828L)
+#define MAC_TX_PACKET_65_127_BYTES_COUNT (4829L)
+#define MAC_TX_PACKET_8192_9215_BYTES (4830L)
+#define MAC_TX_PACKET_8192_9215_BYTES_COUNT (4831L)
+#define MAC_TX_PACKET_LARGE (4832L)
+#define MAC_TX_PACKET_LARGE_COUNT (4833L)
+#define MAC_TX_PACKET_SMALL (4834L)
+#define MAC_TX_PACKET_SMALL_COUNT (4835L)
+#define MAC_TX_TOTAL_BYTES (4836L)
+#define MAC_TX_TOTAL_BYTES_COUNT (4837L)
+#define MAC_TX_TOTAL_GOOD_BYTES (4838L)
+#define MAC_TX_TOTAL_GOOD_BYTES_COUNT (4839L)
+#define MAC_TX_TOTAL_GOOD_PACKETS (4840L)
+#define MAC_TX_TOTAL_GOOD_PACKETS_COUNT (4841L)
+#define MAC_TX_TOTAL_PACKETS (4842L)
+#define MAC_TX_TOTAL_PACKETS_COUNT (4843L)
+#define MAC_TX_UNICAST (4844L)
+#define MAC_TX_UNICAST_COUNT (4845L)
+#define MAC_TX_VLAN (4846L)
+#define MAC_TX_VLAN_COUNT (4847L)
+/* MCU */
+#define MCU_CSR (4848L)
+#define MCU_CSR_HALT (4849L)
+#define MCU_CSR_PAUSE (4850L)
+#define MCU_CSR_RESET (4851L)
+#define MCU_CSR_RESET_MCU (4852L)
+#define MCU_DRAM_CTRL (4853L)
+#define MCU_DRAM_CTRL_ADR (4854L)
+#define MCU_DRAM_CTRL_CNT (4855L)
+#define MCU_DRAM_RD_DATA (4856L)
+#define MCU_DRAM_RD_DATA_DATA (4857L)
+#define MCU_DRAM_WR_DATA (4858L)
+#define MCU_DRAM_WR_DATA_DATA (4859L)
+#define MCU_IRAM_CTRL (4860L)
+#define MCU_IRAM_CTRL_ADR (4861L)
+#define MCU_IRAM_CTRL_CNT (4862L)
+#define MCU_IRAM_DATA (4863L)
+#define MCU_IRAM_DATA_DATA (4864L)
+/* MDG */
+#define MDG_BSO_CTRL (4865L)
+#define MDG_BSO_CTRL_ADR (4866L)
+#define MDG_BSO_CTRL_CNT (4867L)
+#define MDG_BSO_DATA (4868L)
+#define MDG_BSO_DATA_OFFSET (4869L)
+#define MDG_CONTROL (4870L)
+#define MDG_CONTROL_AE (4871L)
+#define MDG_CONTROL_AS (4872L)
+#define MDG_CONTROL_CE (4873L)
+#define MDG_CONTROL_EN (4874L)
+#define MDG_DBG_EGS_FC0 (4875L)
+#define MDG_DBG_EGS_FC0_BLOCKED (4876L)
+#define MDG_DBG_EGS_FC1 (4877L)
+#define MDG_DBG_EGS_FC1_BLOCKED (4878L)
+#define MDG_DBG_EGS_FC2 (4879L)
+#define MDG_DBG_EGS_FC2_BLOCKED (4880L)
+#define MDG_DBG_EGS_FC3 (4881L)
+#define MDG_DBG_EGS_FC3_BLOCKED (4882L)
+#define MDG_DBG_HBM (4883L)
+#define MDG_DBG_HBM_ADR (4884L)
+#define MDG_DBG_HBM_MAIN (4885L)
+#define MDG_DBG_HBM_MAP (4886L)
+#define MDG_DBG_HBM_META (4887L)
+#define MDG_DBG_HBM_VALID (4888L)
+#define MDG_DBG_IGS_FC0 (4889L)
+#define MDG_DBG_IGS_FC0_BLOCKED (4890L)
+#define MDG_DBG_IGS_FC1 (4891L)
+#define MDG_DBG_IGS_FC1_BLOCKED (4892L)
+#define MDG_DBG_IGS_FC2 (4893L)
+#define MDG_DBG_IGS_FC2_BLOCKED (4894L)
+#define MDG_DBG_IGS_FC3 (4895L)
+#define MDG_DBG_IGS_FC3_BLOCKED (4896L)
+#define MDG_HBM_CTRL (4897L)
+#define MDG_HBM_CTRL_ADR (4898L)
+#define MDG_HBM_CTRL_CNT (4899L)
+#define MDG_HBM_DATA (4900L)
+#define MDG_HBM_DATA_MAIN (4901L)
+#define MDG_HBM_DATA_MAP (4902L)
+#define MDG_HBM_DATA_META (4903L)
+#define MDG_HBS_CTRL (4904L)
+#define MDG_HBS_CTRL_ADR (4905L)
+#define MDG_HBS_CTRL_CNT (4906L)
+#define MDG_HBS_DATA (4907L)
+#define MDG_HBS_DATA_SIZE (4908L)
+#define MDG_MAX_BYTES (4909L)
+#define MDG_MAX_BYTES_MAX (4910L)
+#define MDG_MAX_PACKETS (4911L)
+#define MDG_MAX_PACKETS_MAX (4912L)
+#define MDG_TIMEOUT (4913L)
+#define MDG_TIMEOUT_T (4914L)
+/* MSK */
+#define MSK_RCP_CTRL (4980L)
+#define MSK_RCP_CTRL_ADR (4981L)
+#define MSK_RCP_CTRL_CNT (4982L)
+#define MSK_RCP_DATA (4983L)
+#define MSK_RCP_DATA_MASK_DYN0 (4984L)
+#define MSK_RCP_DATA_MASK_DYN1 (4985L)
+#define MSK_RCP_DATA_MASK_DYN2 (4986L)
+#define MSK_RCP_DATA_MASK_DYN3 (4987L)
+#define MSK_RCP_DATA_MASK_EN0 (4988L)
+#define MSK_RCP_DATA_MASK_EN1 (4989L)
+#define MSK_RCP_DATA_MASK_EN2 (4990L)
+#define MSK_RCP_DATA_MASK_EN3 (4991L)
+#define MSK_RCP_DATA_MASK_LEN0 (4992L)
+#define MSK_RCP_DATA_MASK_LEN1 (4993L)
+#define MSK_RCP_DATA_MASK_LEN2 (4994L)
+#define MSK_RCP_DATA_MASK_LEN3 (4995L)
+#define MSK_RCP_DATA_MASK_OFS0 (4996L)
+#define MSK_RCP_DATA_MASK_OFS1 (4997L)
+#define MSK_RCP_DATA_MASK_OFS2 (4998L)
+#define MSK_RCP_DATA_MASK_OFS3 (4999L)
+/* NIF */
+#define NIF_CTRL (5000L)
+#define NIF_CTRL_GT_PWDN (5001L)
+#define NIF_CTRL_GT_SEL (5002L)
+#define NIF_CTRL_LOOPBACK (5003L)
+#define NIF_CTRL_PMA_INIT (5004L)
+#define NIF_CTRL_PRBS_ERR (5005L)
+#define NIF_CTRL_PRBS_RST (5006L)
+#define NIF_CTRL_PRBS_SEL (5007L)
+#define NIF_CTRL_QPLL_SEL (5008L)
+#define NIF_CTRL_RST (5009L)
+#define NIF_CTRL_TX_INHIBIT (5010L)
+#define NIF_DRP_IF (5011L)
+#define NIF_DRP_IF_ADR (5012L)
+#define NIF_DRP_IF_DATA (5013L)
+#define NIF_DRP_IF_DBG_BUSY (5014L)
+#define NIF_DRP_IF_DONE (5015L)
+#define NIF_DRP_IF_WREN (5016L)
+#define NIF_ERROR (5017L)
+#define NIF_ERROR_HARD_ERR (5018L)
+#define NIF_ERROR_SOFT_ERR (5019L)
+#define NIF_ERROR_SOFT_ERR_CNT (5020L)
+#define NIF_GTH_TX_TUNING (5021L)
+#define NIF_GTH_TX_TUNING_DIFF_CTRL (5022L)
+#define NIF_GTH_TX_TUNING_POST_CURSOR (5023L)
+#define NIF_GTH_TX_TUNING_PRE_CURSOR (5024L)
+#define NIF_HARD_ERROR_CNT (5025L)
+#define NIF_HARD_ERROR_CNT_UNCORRECTABLE_ERRORS (5026L)
+#define NIF_STATUS (5027L)
+#define NIF_STATUS_CH_UP (5028L)
+#define NIF_STATUS_EP0_0_UP (5029L)
+#define NIF_STATUS_EP0_1_UP (5030L)
+#define NIF_STATUS_EP0_2_UP (5031L)
+#define NIF_STATUS_EP0_3_UP (5032L)
+#define NIF_STATUS_EP1_0_UP (5033L)
+#define NIF_STATUS_EP1_1_UP (5034L)
+#define NIF_STATUS_EP1_2_UP (5035L)
+#define NIF_STATUS_EP1_3_UP (5036L)
+#define NIF_STATUS_EP1_4_UP (5037L)
+#define NIF_STATUS_EP1_5_UP (5038L)
+#define NIF_STATUS_EP3_0_UP (5039L)
+#define NIF_STATUS_EP3_1_UP (5040L)
+#define NIF_STATUS_EP3_2_UP (5041L)
+#define NIF_STATUS_EP3_3_UP (5042L)
+#define NIF_STATUS_MMCM_ULCK (5043L)
+#define NIF_STATUS_PLL_LCK (5044L)
+#define NIF_STATUS_QPLLOUT_LCK (5045L)
+#define NIF_STATUS_QPLLOUT_REF_LOST (5046L)
+#define NIF_STATUS_QPLL_LCK (5047L)
+#define NIF_STATUS_RXRST_DONE (5048L)
+#define NIF_STATUS_TXRST_DONE (5049L)
+#define NIF_STATUS_STICK (5050L)
+#define NIF_STATUS_STICK_CH_DOWN (5051L)
+#define NIF_STATUS_STICK_LN_DOWN (5052L)
+#define NIF_STATUS_STICK_MMCM_ULCK (5053L)
+#define NIF_STATUS_STICK_PLL_ULCK (5054L)
+#define NIF_USER_REG (5055L)
+#define NIF_USER_REG_PRIMARY (5056L)
+#define NIF_USER_REG_RST (5057L)
+#define NIF_USER_REG_SECONDARY (5058L)
+#define NIF_USER_REG_STAT (5059L)
+#define NIF_USER_REG_STAT_LL (5060L)
+/* PCIE3 */
+#define PCIE3_BUILD_SEED (5228L)
+#define PCIE3_BUILD_SEED_BUILD_SEED (5229L)
+#define PCIE3_BUILD_TIME (5230L)
+#define PCIE3_BUILD_TIME_TIME (5231L)
+#define PCIE3_CONFIG (5232L)
+#define PCIE3_CONFIG_EXT_TAG (5233L)
+#define PCIE3_CONFIG_MAX_READ (5234L)
+#define PCIE3_CONFIG_MAX_TLP (5235L)
+#define PCIE3_CONTROL (5236L)
+#define PCIE3_CONTROL_RD_ATTR (5237L)
+#define PCIE3_CONTROL_WRAW (5238L)
+#define PCIE3_CONTROL_WR_ATTR (5239L)
+#define PCIE3_CORESPEED (5240L)
+#define PCIE3_CORESPEED_CORESPEED (5241L)
+#define PCIE3_CORESPEED_DDR3SPEED (5242L)
+#define PCIE3_DRP_COMMON (5243L)
+#define PCIE3_DRP_COMMON_DRP_ADDR (5244L)
+#define PCIE3_DRP_COMMON_DRP_RDY (5245L)
+#define PCIE3_DRP_COMMON_GTH_SEL (5246L)
+#define PCIE3_DRP_COMMON_WR (5247L)
+#define PCIE3_DRP_DATE (5248L)
+#define PCIE3_DRP_DATE_DRP_DATA (5249L)
+#define PCIE3_EP_TO_RP_ERR (5250L)
+#define PCIE3_EP_TO_RP_ERR_ERR_COR (5251L)
+#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (5252L)
+#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (5253L)
+#define PCIE3_INT_CLR (5254L)
+#define PCIE3_INT_CLR_AVR (5255L)
+#define PCIE3_INT_CLR_FHM (5256L)
+#define PCIE3_INT_CLR_INT_0 (5257L)
+#define PCIE3_INT_CLR_INT_1 (5258L)
+#define PCIE3_INT_CLR_INT_10 (5259L)
+#define PCIE3_INT_CLR_INT_11 (5260L)
+#define PCIE3_INT_CLR_INT_12 (5261L)
+#define PCIE3_INT_CLR_INT_13 (5262L)
+#define PCIE3_INT_CLR_INT_14 (5263L)
+#define PCIE3_INT_CLR_INT_15 (5264L)
+#define PCIE3_INT_CLR_INT_16 (5265L)
+#define PCIE3_INT_CLR_INT_17 (5266L)
+#define PCIE3_INT_CLR_INT_18 (5267L)
+#define PCIE3_INT_CLR_INT_19 (5268L)
+#define PCIE3_INT_CLR_INT_2 (5269L)
+#define PCIE3_INT_CLR_INT_20 (5270L)
+#define PCIE3_INT_CLR_INT_21 (5271L)
+#define PCIE3_INT_CLR_INT_22 (5272L)
+#define PCIE3_INT_CLR_INT_23 (5273L)
+#define PCIE3_INT_CLR_INT_24 (5274L)
+#define PCIE3_INT_CLR_INT_25 (5275L)
+#define PCIE3_INT_CLR_INT_26 (5276L)
+#define PCIE3_INT_CLR_INT_27 (5277L)
+#define PCIE3_INT_CLR_INT_28 (5278L)
+#define PCIE3_INT_CLR_INT_29 (5279L)
+#define PCIE3_INT_CLR_INT_3 (5280L)
+#define PCIE3_INT_CLR_INT_30 (5281L)
+#define PCIE3_INT_CLR_INT_31 (5282L)
+#define PCIE3_INT_CLR_INT_4 (5283L)
+#define PCIE3_INT_CLR_INT_5 (5284L)
+#define PCIE3_INT_CLR_INT_6 (5285L)
+#define PCIE3_INT_CLR_INT_7 (5286L)
+#define PCIE3_INT_CLR_INT_8 (5287L)
+#define PCIE3_INT_CLR_INT_9 (5288L)
+#define PCIE3_INT_CLR_PORT (5289L)
+#define PCIE3_INT_CLR_PPS (5290L)
+#define PCIE3_INT_CLR_QSPI (5291L)
+#define PCIE3_INT_CLR_SPIM (5292L)
+#define PCIE3_INT_CLR_SPIS (5293L)
+#define PCIE3_INT_CLR_STA (5294L)
+#define PCIE3_INT_CLR_TIMER (5295L)
+#define PCIE3_INT_FORC (5296L)
+#define PCIE3_INT_FORC_AVR (5297L)
+#define PCIE3_INT_FORC_FHM (5298L)
+#define PCIE3_INT_FORC_INT_0 (5299L)
+#define PCIE3_INT_FORC_INT_1 (5300L)
+#define PCIE3_INT_FORC_INT_10 (5301L)
+#define PCIE3_INT_FORC_INT_11 (5302L)
+#define PCIE3_INT_FORC_INT_12 (5303L)
+#define PCIE3_INT_FORC_INT_13 (5304L)
+#define PCIE3_INT_FORC_INT_14 (5305L)
+#define PCIE3_INT_FORC_INT_15 (5306L)
+#define PCIE3_INT_FORC_INT_16 (5307L)
+#define PCIE3_INT_FORC_INT_17 (5308L)
+#define PCIE3_INT_FORC_INT_18 (5309L)
+#define PCIE3_INT_FORC_INT_19 (5310L)
+#define PCIE3_INT_FORC_INT_2 (5311L)
+#define PCIE3_INT_FORC_INT_20 (5312L)
+#define PCIE3_INT_FORC_INT_21 (5313L)
+#define PCIE3_INT_FORC_INT_22 (5314L)
+#define PCIE3_INT_FORC_INT_23 (5315L)
+#define PCIE3_INT_FORC_INT_24 (5316L)
+#define PCIE3_INT_FORC_INT_25 (5317L)
+#define PCIE3_INT_FORC_INT_26 (5318L)
+#define PCIE3_INT_FORC_INT_27 (5319L)
+#define PCIE3_INT_FORC_INT_28 (5320L)
+#define PCIE3_INT_FORC_INT_29 (5321L)
+#define PCIE3_INT_FORC_INT_3 (5322L)
+#define PCIE3_INT_FORC_INT_30 (5323L)
+#define PCIE3_INT_FORC_INT_31 (5324L)
+#define PCIE3_INT_FORC_INT_4 (5325L)
+#define PCIE3_INT_FORC_INT_5 (5326L)
+#define PCIE3_INT_FORC_INT_6 (5327L)
+#define PCIE3_INT_FORC_INT_7 (5328L)
+#define PCIE3_INT_FORC_INT_8 (5329L)
+#define PCIE3_INT_FORC_INT_9 (5330L)
+#define PCIE3_INT_FORC_PORT (5331L)
+#define PCIE3_INT_FORC_PPS (5332L)
+#define PCIE3_INT_FORC_QSPI (5333L)
+#define PCIE3_INT_FORC_SPIM (5334L)
+#define PCIE3_INT_FORC_SPIS (5335L)
+#define PCIE3_INT_FORC_STA (5336L)
+#define PCIE3_INT_FORC_TIMER (5337L)
+#define PCIE3_INT_MASK (5338L)
+#define PCIE3_INT_MASK_AVR (5339L)
+#define PCIE3_INT_MASK_FHM (5340L)
+#define PCIE3_INT_MASK_IIC0 (5341L)
+#define PCIE3_INT_MASK_IIC1 (5342L)
+#define PCIE3_INT_MASK_IIC2 (5343L)
+#define PCIE3_INT_MASK_IIC3 (5344L)
+#define PCIE3_INT_MASK_IIC4 (5345L)
+#define PCIE3_INT_MASK_IIC5 (5346L)
+#define PCIE3_INT_MASK_INT_0 (5347L)
+#define PCIE3_INT_MASK_INT_1 (5348L)
+#define PCIE3_INT_MASK_INT_10 (5349L)
+#define PCIE3_INT_MASK_INT_11 (5350L)
+#define PCIE3_INT_MASK_INT_12 (5351L)
+#define PCIE3_INT_MASK_INT_13 (5352L)
+#define PCIE3_INT_MASK_INT_14 (5353L)
+#define PCIE3_INT_MASK_INT_15 (5354L)
+#define PCIE3_INT_MASK_INT_16 (5355L)
+#define PCIE3_INT_MASK_INT_17 (5356L)
+#define PCIE3_INT_MASK_INT_18 (5357L)
+#define PCIE3_INT_MASK_INT_19 (5358L)
+#define PCIE3_INT_MASK_INT_2 (5359L)
+#define PCIE3_INT_MASK_INT_20 (5360L)
+#define PCIE3_INT_MASK_INT_21 (5361L)
+#define PCIE3_INT_MASK_INT_22 (5362L)
+#define PCIE3_INT_MASK_INT_23 (5363L)
+#define PCIE3_INT_MASK_INT_24 (5364L)
+#define PCIE3_INT_MASK_INT_25 (5365L)
+#define PCIE3_INT_MASK_INT_26 (5366L)
+#define PCIE3_INT_MASK_INT_27 (5367L)
+#define PCIE3_INT_MASK_INT_28 (5368L)
+#define PCIE3_INT_MASK_INT_29 (5369L)
+#define PCIE3_INT_MASK_INT_3 (5370L)
+#define PCIE3_INT_MASK_INT_30 (5371L)
+#define PCIE3_INT_MASK_INT_31 (5372L)
+#define PCIE3_INT_MASK_INT_4 (5373L)
+#define PCIE3_INT_MASK_INT_5 (5374L)
+#define PCIE3_INT_MASK_INT_6 (5375L)
+#define PCIE3_INT_MASK_INT_7 (5376L)
+#define PCIE3_INT_MASK_INT_8 (5377L)
+#define PCIE3_INT_MASK_INT_9 (5378L)
+#define PCIE3_INT_MASK_PORT (5379L)
+#define PCIE3_INT_MASK_PPS (5380L)
+#define PCIE3_INT_MASK_QSPI (5381L)
+#define PCIE3_INT_MASK_SPIM (5382L)
+#define PCIE3_INT_MASK_SPIS (5383L)
+#define PCIE3_INT_MASK_STA (5384L)
+#define PCIE3_INT_MASK_TIMER (5385L)
+#define PCIE3_LAT_CTRL (5386L)
+#define PCIE3_LAT_CTRL_CLEAR_RAM (5387L)
+#define PCIE3_LAT_CTRL_ENABLE (5388L)
+#define PCIE3_LAT_CTRL_PRESCAL (5389L)
+#define PCIE3_LAT_CTRL_RAM_VLD (5390L)
+#define PCIE3_LAT_CTRL_READ_RAM (5391L)
+#define PCIE3_LAT_CTRL_STATUS (5392L)
+#define PCIE3_LAT_MAX (5393L)
+#define PCIE3_LAT_MAX_MAX (5394L)
+#define PCIE3_LAT_RAMADR (5395L)
+#define PCIE3_LAT_RAMADR_ADR (5396L)
+#define PCIE3_LAT_RAMDATA (5397L)
+#define PCIE3_LAT_RAMDATA_DATA (5398L)
+#define PCIE3_LINK_STATUS (5399L)
+#define PCIE3_LINK_STATUS_CLEAR (5400L)
+#define PCIE3_LINK_STATUS_RETRAIN_CNT (5401L)
+#define PCIE3_MARKADR_LSB (5402L)
+#define PCIE3_MARKADR_LSB_ADR (5403L)
+#define PCIE3_MARKADR_MSB (5404L)
+#define PCIE3_MARKADR_MSB_ADR (5405L)
+#define PCIE3_PB_INTERVAL (5406L)
+#define PCIE3_PB_INTERVAL_INTERVAL (5407L)
+#define PCIE3_PB_MAX_RD (5408L)
+#define PCIE3_PB_MAX_RD_PB (5409L)
+#define PCIE3_PB_MAX_WR (5410L)
+#define PCIE3_PB_MAX_WR_PB (5411L)
+#define PCIE3_PCIE_CTRL (5412L)
+#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (5413L)
+#define PCIE3_PCI_ENDPOINT (5414L)
+#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (5415L)
+#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (5416L)
+#define PCIE3_PCI_ENDPOINT_GET_MSG (5417L)
+#define PCIE3_PCI_ENDPOINT_IF_ID (5418L)
+#define PCIE3_PCI_ENDPOINT_SEND_MSG (5419L)
+#define PCIE3_PCI_TEST0 (5420L)
+#define PCIE3_PCI_TEST0_DATA (5421L)
+#define PCIE3_PCI_TEST1 (5422L)
+#define PCIE3_PCI_TEST1_DATA (5423L)
+#define PCIE3_PCI_TEST2 (5424L)
+#define PCIE3_PCI_TEST2_DATA (5425L)
+#define PCIE3_PCI_TEST3 (5426L)
+#define PCIE3_PCI_TEST3_DATA (5427L)
+#define PCIE3_PROD_ID_EX (5428L)
+#define PCIE3_PROD_ID_EX_LAYOUT (5429L)
+#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (5430L)
+#define PCIE3_PROD_ID_EX_RESERVED (5431L)
+#define PCIE3_PROD_ID_LSB (5432L)
+#define PCIE3_PROD_ID_LSB_GROUP_ID (5433L)
+#define PCIE3_PROD_ID_LSB_REV_ID (5434L)
+#define PCIE3_PROD_ID_LSB_VER_ID (5435L)
+#define PCIE3_PROD_ID_MSB (5436L)
+#define PCIE3_PROD_ID_MSB_BUILD_NO (5437L)
+#define PCIE3_PROD_ID_MSB_PATCH_NO (5438L)
+#define PCIE3_PROD_ID_MSB_TYPE_ID (5439L)
+#define PCIE3_RESET_CTRL (5440L)
+#define PCIE3_RESET_CTRL_MASK (5441L)
+#define PCIE3_RP_TO_EP_ERR (5442L)
+#define PCIE3_RP_TO_EP_ERR_ERR_COR (5443L)
+#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (5444L)
+#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (5445L)
+#define PCIE3_SAMPLE_TIME (5446L)
+#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (5447L)
+#define PCIE3_STATUS (5448L)
+#define PCIE3_STATUS_RD_ERR (5449L)
+#define PCIE3_STATUS_TAGS_IN_USE (5450L)
+#define PCIE3_STATUS_WR_ERR (5451L)
+#define PCIE3_STATUS0 (5452L)
+#define PCIE3_STATUS0_TAGS_IN_USE (5453L)
+#define PCIE3_STATUS0_UR_ADDR (5454L)
+#define PCIE3_STATUS0_UR_DWORD (5455L)
+#define PCIE3_STATUS0_UR_FBE (5456L)
+#define PCIE3_STATUS0_UR_FMT (5457L)
+#define PCIE3_STATUS0_UR_LBE (5458L)
+#define PCIE3_STATUS0_UR_REG (5459L)
+#define PCIE3_STAT_CTRL (5460L)
+#define PCIE3_STAT_CTRL_STAT_ENA (5461L)
+#define PCIE3_STAT_CTRL_STAT_REQ (5462L)
+#define PCIE3_STAT_REFCLK (5463L)
+#define PCIE3_STAT_REFCLK_REFCLK250 (5464L)
+#define PCIE3_STAT_RQ_RDY (5465L)
+#define PCIE3_STAT_RQ_RDY_COUNTER (5466L)
+#define PCIE3_STAT_RQ_VLD (5467L)
+#define PCIE3_STAT_RQ_VLD_COUNTER (5468L)
+#define PCIE3_STAT_RX (5469L)
+#define PCIE3_STAT_RX_COUNTER (5470L)
+#define PCIE3_STAT_TX (5471L)
+#define PCIE3_STAT_TX_COUNTER (5472L)
+#define PCIE3_TEST0 (5473L)
+#define PCIE3_TEST0_DATA (5474L)
+#define PCIE3_TEST1 (5475L)
+#define PCIE3_TEST1_DATA (5476L)
+#define PCIE3_TEST2_DATA (5477L)
+#define PCIE3_TEST3_DATA (5478L)
+#define PCIE3_UUID0 (5479L)
+#define PCIE3_UUID0_UUID0 (5480L)
+#define PCIE3_UUID1 (5481L)
+#define PCIE3_UUID1_UUID1 (5482L)
+#define PCIE3_UUID2 (5483L)
+#define PCIE3_UUID2_UUID2 (5484L)
+#define PCIE3_UUID3 (5485L)
+#define PCIE3_UUID3_UUID3 (5486L)
+/* PCI_RD_TG */
+#define PCI_RD_TG_TG_CTRL (5487L)
+#define PCI_RD_TG_TG_CTRL_TG_RD_RDY (5488L)
+#define PCI_RD_TG_TG_RDADDR (5489L)
+#define PCI_RD_TG_TG_RDADDR_RAM_ADDR (5490L)
+#define PCI_RD_TG_TG_RDDATA0 (5491L)
+#define PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW (5492L)
+#define PCI_RD_TG_TG_RDDATA1 (5493L)
+#define PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH (5494L)
+#define PCI_RD_TG_TG_RDDATA2 (5495L)
+#define PCI_RD_TG_TG_RDDATA2_REQ_HID (5496L)
+#define PCI_RD_TG_TG_RDDATA2_REQ_SIZE (5497L)
+#define PCI_RD_TG_TG_RDDATA2_WAIT (5498L)
+#define PCI_RD_TG_TG_RDDATA2_WRAP (5499L)
+#define PCI_RD_TG_TG_RD_RUN (5500L)
+#define PCI_RD_TG_TG_RD_RUN_RD_ITERATION (5501L)
+/* PCI_TA */
+#define PCI_TA_CONTROL (5502L)
+#define PCI_TA_CONTROL_ENABLE (5503L)
+#define PCI_TA_LENGTH_ERROR (5504L)
+#define PCI_TA_LENGTH_ERROR_AMOUNT (5505L)
+#define PCI_TA_PACKET_BAD (5506L)
+#define PCI_TA_PACKET_BAD_AMOUNT (5507L)
+#define PCI_TA_PACKET_GOOD (5508L)
+#define PCI_TA_PACKET_GOOD_AMOUNT (5509L)
+#define PCI_TA_PAYLOAD_ERROR (5510L)
+#define PCI_TA_PAYLOAD_ERROR_AMOUNT (5511L)
+/* PCI_WR_TG */
+#define PCI_WR_TG_TG_CTRL (5512L)
+#define PCI_WR_TG_TG_CTRL_TG_WR_RDY (5513L)
+#define PCI_WR_TG_TG_SEQ (5514L)
+#define PCI_WR_TG_TG_SEQ_SEQUENCE (5515L)
+#define PCI_WR_TG_TG_WRADDR (5516L)
+#define PCI_WR_TG_TG_WRADDR_RAM_ADDR (5517L)
+#define PCI_WR_TG_TG_WRDATA0 (5518L)
+#define PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW (5519L)
+#define PCI_WR_TG_TG_WRDATA1 (5520L)
+#define PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH (5521L)
+#define PCI_WR_TG_TG_WRDATA2 (5522L)
+#define PCI_WR_TG_TG_WRDATA2_INC_MODE (5523L)
+#define PCI_WR_TG_TG_WRDATA2_REQ_HID (5524L)
+#define PCI_WR_TG_TG_WRDATA2_REQ_SIZE (5525L)
+#define PCI_WR_TG_TG_WRDATA2_WAIT (5526L)
+#define PCI_WR_TG_TG_WRDATA2_WRAP (5527L)
+#define PCI_WR_TG_TG_WR_RUN (5528L)
+#define PCI_WR_TG_TG_WR_RUN_WR_ITERATION (5529L)
+/* PCM_NT100A01_01 */
+#define PCM_NT100A01_01_CTRL (5530L)
+#define PCM_NT100A01_01_CTRL_PTP_CLKSEL (5531L)
+#define PCM_NT100A01_01_CTRL_REC_MMCM_RST (5532L)
+#define PCM_NT100A01_01_CTRL_TS_CLKSEL (5533L)
+#define PCM_NT100A01_01_CTRL_TS_MMCM_RST (5534L)
+#define PCM_NT100A01_01_GPIO_I (5535L)
+#define PCM_NT100A01_01_GPIO_I_SI5328_C2B (5536L)
+#define PCM_NT100A01_01_GPIO_I_SI5328_CS_CA (5537L)
+#define PCM_NT100A01_01_GPIO_I_SI5328_INT_C1B (5538L)
+#define PCM_NT100A01_01_GPIO_I_SI5328_LOL (5539L)
+#define PCM_NT100A01_01_GPIO_O (5540L)
+#define PCM_NT100A01_01_GPIO_O_SI5328_CS_CA (5541L)
+#define PCM_NT100A01_01_GPIO_O_SI5328_RST_B (5542L)
+#define PCM_NT100A01_01_GPIO_T (5543L)
+#define PCM_NT100A01_01_GPIO_T_SI5328_CS_CA (5544L)
+#define PCM_NT100A01_01_LATCH (5545L)
+#define PCM_NT100A01_01_LATCH_REC_MMCM_LOCKED (5546L)
+#define PCM_NT100A01_01_LATCH_TCXO_MMCM_LOCKED (5547L)
+#define PCM_NT100A01_01_LATCH_TS_MMCM_LOCKED (5548L)
+#define PCM_NT100A01_01_STAT (5549L)
+#define PCM_NT100A01_01_STAT_REC_MMCM_LOCKED (5550L)
+#define PCM_NT100A01_01_STAT_TCXO_MMCM_LOCKED (5551L)
+#define PCM_NT100A01_01_STAT_TS_MMCM_LOCKED (5552L)
+/* PCM_NT50B01_01 */
+#define PCM_NT50B01_01_CTRL (5553L)
+#define PCM_NT50B01_01_CTRL_TS_CLKSEL (5554L)
+#define PCM_NT50B01_01_CTRL_TS_MMCM_RST (5555L)
+#define PCM_NT50B01_01_LATCH (5556L)
+#define PCM_NT50B01_01_LATCH_TS_MMCM_LOCKED (5557L)
+#define PCM_NT50B01_01_STAT (5558L)
+#define PCM_NT50B01_01_STAT_TS_MMCM_LOCKED (5559L)
+/* PCS */
+#define PCS_BER_COUNT (5560L)
+#define PCS_BER_COUNT_CNT (5561L)
+#define PCS_BIP_COUNT (5562L)
+#define PCS_BIP_COUNT_CNT (5563L)
+#define PCS_BLOCK_LOCK (5564L)
+#define PCS_BLOCK_LOCK_LOCK (5565L)
+#define PCS_BLOCK_LOCK_LATCH (5566L)
+#define PCS_BLOCK_LOCK_LATCH_LATCH_LOCK (5567L)
+#define PCS_BLOCK_LOCK_ST (5568L)
+#define PCS_BLOCK_LOCK_ST_LATCH_STATE (5569L)
+#define PCS_DDR3_STATUS (5570L)
+#define PCS_DDR3_STATUS_CALIB_DONE (5571L)
+#define PCS_DRP_CONFIG (5572L)
+#define PCS_DRP_CONFIG_DRP_ADR (5573L)
+#define PCS_DRP_CONFIG_DRP_DI (5574L)
+#define PCS_DRP_CONFIG_DRP_EN (5575L)
+#define PCS_DRP_CONFIG_DRP_WREN (5576L)
+#define PCS_DRP_DATA (5577L)
+#define PCS_DRP_DATA_DRP_DO (5578L)
+#define PCS_DRP_DATA_DRP_RDY (5579L)
+#define PCS_FSM_DONE (5580L)
+#define PCS_FSM_DONE_RX_RST_DONE (5581L)
+#define PCS_FSM_DONE_TX_RST_DONE (5582L)
+#define PCS_GTH_CONFIG (5583L)
+#define PCS_GTH_CONFIG_EYE_SCAN_RST (5584L)
+#define PCS_GTH_CONFIG_EYE_SCAN_TRIG (5585L)
+#define PCS_GTH_CONFIG_GT_LOOP (5586L)
+#define PCS_GTH_CONFIG_GT_LPM_EN (5587L)
+#define PCS_GTH_CONFIG_GT_MRST (5588L)
+#define PCS_GTH_CONFIG_GT_RX_RST (5589L)
+#define PCS_GTH_CONFIG_GT_SOFT_RST (5590L)
+#define PCS_GTH_CONFIG_GT_TX_RST (5591L)
+#define PCS_GTH_CONFIG_RX_MONITOR_SEL (5592L)
+#define PCS_GTH_CONFIG_RX_PCS_RST (5593L)
+#define PCS_GTH_CONFIG_RX_USER_RDY (5594L)
+#define PCS_GTH_CONFIG_TX_PCS_RST (5595L)
+#define PCS_GTH_CONFIG_TX_USER_RDYU (5596L)
+#define PCS_GTH_CONTROL (5597L)
+#define PCS_GTH_CONTROL_CPLL_LOCK (5598L)
+#define PCS_GTH_CONTROL_CPLL_REFCLK_LOST (5599L)
+#define PCS_GTH_CONTROL_RX_BUF_RST (5600L)
+#define PCS_GTH_TX_TUNING (5601L)
+#define PCS_GTH_TX_TUNING_DIFF_CTRL (5602L)
+#define PCS_GTH_TX_TUNING_POST_CURSOR (5603L)
+#define PCS_GTH_TX_TUNING_PRE_CURSOR (5604L)
+#define PCS_LANE_LOCK (5605L)
+#define PCS_LANE_LOCK_LOCK (5606L)
+#define PCS_LANE_LOCK_LATCH (5607L)
+#define PCS_LANE_LOCK_LATCH_LATCH_LOCK (5608L)
+#define PCS_LANE_LOCK_ST (5609L)
+#define PCS_LANE_LOCK_ST_LATCH_STATE (5610L)
+#define PCS_LANE_MAPPING (5611L)
+#define PCS_LANE_MAPPING_LANE (5612L)
+#define PCS_LANE_OFFSET (5613L)
+#define PCS_LANE_OFFSET_DIFF (5614L)
+#define PCS_PCS_CONFIG (5615L)
+#define PCS_PCS_CONFIG_BER_RST (5616L)
+#define PCS_PCS_CONFIG_BIP_RST (5617L)
+#define PCS_PCS_CONFIG_LANE_ADDR (5618L)
+#define PCS_PCS_CONFIG_LANE_BLOCK_CLR (5619L)
+#define PCS_PCS_CONFIG_TIME_OFFSET_RX (5620L)
+#define PCS_PCS_CONFIG_TXRX_LOOP (5621L)
+#define PCS_PCS_STATUS (5622L)
+#define PCS_PCS_STATUS_ALIGN (5623L)
+#define PCS_PCS_STATUS_DELAY_ERR (5624L)
+#define PCS_PCS_STATUS_FIFO_DELAY (5625L)
+#define PCS_PCS_STATUS_HI_BER (5626L)
+#define PCS_POLARITY (5627L)
+#define PCS_POLARITY_RX_POL (5628L)
+#define PCS_POLARITY_TX_POL (5629L)
+/* PCS100 */
+#define PCS100_BER_COUNT (5630L)
+#define PCS100_BER_COUNT_CNT (5631L)
+#define PCS100_BIP_COUNT (5632L)
+#define PCS100_BIP_COUNT_CNT (5633L)
+#define PCS100_BLOCK_LOCK (5634L)
+#define PCS100_BLOCK_LOCK_LOCK (5635L)
+#define PCS100_BLOCK_LOCK_LATCH (5636L)
+#define PCS100_BLOCK_LOCK_LATCH_LATCH_LOCK (5637L)
+#define PCS100_BLOCK_LOCK_ST (5638L)
+#define PCS100_BLOCK_LOCK_ST_LATCH_STATE (5639L)
+#define PCS100_DDR3_STATUS (5640L)
+#define PCS100_DDR3_STATUS_CALIB_DONE (5641L)
+#define PCS100_DRP_CONFIG (5642L)
+#define PCS100_DRP_CONFIG_DRP_ADR (5643L)
+#define PCS100_DRP_CONFIG_DRP_DI (5644L)
+#define PCS100_DRP_CONFIG_DRP_EN (5645L)
+#define PCS100_DRP_CONFIG_DRP_WREN (5646L)
+#define PCS100_DRP_DATA (5647L)
+#define PCS100_DRP_DATA_DRP_DO (5648L)
+#define PCS100_DRP_DATA_DRP_RDY (5649L)
+#define PCS100_FSM_DONE (5650L)
+#define PCS100_FSM_DONE_RX_RST_DONE (5651L)
+#define PCS100_FSM_DONE_TX_RST_DONE (5652L)
+#define PCS100_GTH_CONFIG (5653L)
+#define PCS100_GTH_CONFIG_EYE_SCAN_RST (5654L)
+#define PCS100_GTH_CONFIG_EYE_SCAN_TRIG (5655L)
+#define PCS100_GTH_CONFIG_GT_LOOP (5656L)
+#define PCS100_GTH_CONFIG_GT_MRST (5657L)
+#define PCS100_GTH_CONFIG_GT_RX_RST (5658L)
+#define PCS100_GTH_CONFIG_GT_SOFT_RST (5659L)
+#define PCS100_GTH_CONFIG_GT_TX_RST (5660L)
+#define PCS100_GTH_CONFIG_RX_MONITOR_SEL (5661L)
+#define PCS100_GTH_CONFIG_RX_PCS_RST (5662L)
+#define PCS100_GTH_CONFIG_RX_USER_RDY (5663L)
+#define PCS100_GTH_CONFIG_TX_PCS_RST (5664L)
+#define PCS100_GTH_CONFIG_TX_USER_RDYU (5665L)
+#define PCS100_GTH_CONTROL (5666L)
+#define PCS100_GTH_CONTROL_CPLL_LOCK (5667L)
+#define PCS100_GTH_CONTROL_CPLL_REFCLK_LOST (5668L)
+#define PCS100_GTH_CONTROL_QPLL_LOCK (5669L)
+#define PCS100_GTH_CONTROL_QPLL_REFCLK_LOST (5670L)
+#define PCS100_GTH_CONTROL_RX_BUF_RST (5671L)
+#define PCS100_GTH_TX_TUNING (5672L)
+#define PCS100_GTH_TX_TUNING_DIFF_CTRL (5673L)
+#define PCS100_GTH_TX_TUNING_POST_CURSOR (5674L)
+#define PCS100_GTH_TX_TUNING_PRE_CURSOR (5675L)
+#define PCS100_LANE_LOCK (5676L)
+#define PCS100_LANE_LOCK_LOCK (5677L)
+#define PCS100_LANE_LOCK_LATCH (5678L)
+#define PCS100_LANE_LOCK_LATCH_LATCH_LOCK (5679L)
+#define PCS100_LANE_LOCK_ST (5680L)
+#define PCS100_LANE_LOCK_ST_LATCH_STATE (5681L)
+#define PCS100_LANE_MAPPING (5682L)
+#define PCS100_LANE_MAPPING_LANE (5683L)
+#define PCS100_LANE_OFFSET (5684L)
+#define PCS100_LANE_OFFSET_DIFF (5685L)
+#define PCS100_PCS_CONFIG (5686L)
+#define PCS100_PCS_CONFIG_BER_RST (5687L)
+#define PCS100_PCS_CONFIG_BIP_RST (5688L)
+#define PCS100_PCS_CONFIG_LANE_ADDR (5689L)
+#define PCS100_PCS_CONFIG_LANE_BLOCK_CLR (5690L)
+#define PCS100_PCS_CONFIG_TIME_OFFSET_RX (5691L)
+#define PCS100_PCS_CONFIG_TXRX_LOOP (5692L)
+#define PCS100_PCS_STATUS (5693L)
+#define PCS100_PCS_STATUS_ALIGN (5694L)
+#define PCS100_PCS_STATUS_DELAY_ERR (5695L)
+#define PCS100_PCS_STATUS_FIFO_DELAY (5696L)
+#define PCS100_PCS_STATUS_HI_BER (5697L)
+/* PDB */
+#define PDB_CONFIG (5698L)
+#define PDB_CONFIG_PORT_OFS (5699L)
+#define PDB_CONFIG_TS_FORMAT (5700L)
+#define PDB_RCP_CTRL (5701L)
+#define PDB_RCP_CTRL_ADR (5702L)
+#define PDB_RCP_CTRL_CNT (5703L)
+#define PDB_RCP_DATA (5704L)
+#define PDB_RCP_DATA_ALIGN (5705L)
+#define PDB_RCP_DATA_CRC_OVERWRITE (5706L)
+#define PDB_RCP_DATA_DESCRIPTOR (5707L)
+#define PDB_RCP_DATA_DESC_LEN (5708L)
+#define PDB_RCP_DATA_DUPLICATE_BIT (5709L)
+#define PDB_RCP_DATA_DUPLICATE_EN (5710L)
+#define PDB_RCP_DATA_IP_PROT_TNL (5711L)
+#define PDB_RCP_DATA_OFS0_DYN (5712L)
+#define PDB_RCP_DATA_OFS0_REL (5713L)
+#define PDB_RCP_DATA_OFS1_DYN (5714L)
+#define PDB_RCP_DATA_OFS1_REL (5715L)
+#define PDB_RCP_DATA_OFS2_DYN (5716L)
+#define PDB_RCP_DATA_OFS2_REL (5717L)
+#define PDB_RCP_DATA_PCAP_KEEP_FCS (5718L)
+#define PDB_RCP_DATA_PPC_HSH (5719L)
+#define PDB_RCP_DATA_TX_IGNORE (5720L)
+#define PDB_RCP_DATA_TX_NOW (5721L)
+#define PDB_RCP_DATA_TX_PORT (5722L)
+/* PDI */
+#define PDI_CR (5723L)
+#define PDI_CR_EN (5724L)
+#define PDI_CR_PARITY (5725L)
+#define PDI_CR_RST (5726L)
+#define PDI_CR_RXRST (5727L)
+#define PDI_CR_STOP (5728L)
+#define PDI_CR_TXRST (5729L)
+#define PDI_DRR (5730L)
+#define PDI_DRR_DRR (5731L)
+#define PDI_DTR (5732L)
+#define PDI_DTR_DTR (5733L)
+#define PDI_PRE (5734L)
+#define PDI_PRE_PRE (5735L)
+#define PDI_SR (5736L)
+#define PDI_SR_DISABLE_BUSY (5737L)
+#define PDI_SR_DONE (5738L)
+#define PDI_SR_ENABLE_BUSY (5739L)
+#define PDI_SR_FRAME_ERR (5740L)
+#define PDI_SR_OVERRUN_ERR (5741L)
+#define PDI_SR_PARITY_ERR (5742L)
+#define PDI_SR_RXLVL (5743L)
+#define PDI_SR_RX_BUSY (5744L)
+#define PDI_SR_TXLVL (5745L)
+#define PDI_SR_TX_BUSY (5746L)
+#define PDI_SRR (5747L)
+#define PDI_SRR_RST (5748L)
+/* PHY10G */
+#define PHY10G_CORE_CONF (5749L)
+#define PHY10G_CORE_CONF_CLEAR_PCS_LINK_FAULTS (5750L)
+#define PHY10G_CORE_CONF_CLEAR_PCS_STATUS2 (5751L)
+#define PHY10G_CORE_CONF_CLEAR_PMA_PMD_LINK_FAULTS (5752L)
+#define PHY10G_CORE_CONF_CLEAR_TEST_PATT_ERR_COUNT (5753L)
+#define PHY10G_CORE_CONF_DATA_PATT_SEL (5754L)
+#define PHY10G_CORE_CONF_GLOBAL_TX_DISABLE (5755L)
+#define PHY10G_CORE_CONF_NT_FORCE_LINK_DOWN (5756L)
+#define PHY10G_CORE_CONF_NT_LINKUP_LATENCY (5757L)
+#define PHY10G_CORE_CONF_PCS_LOOPBACK (5758L)
+#define PHY10G_CORE_CONF_PCS_RESET (5759L)
+#define PHY10G_CORE_CONF_PMA_LOOPBACK (5760L)
+#define PHY10G_CORE_CONF_PMA_RESET (5761L)
+#define PHY10G_CORE_CONF_PMD_TX_DISABLE (5762L)
+#define PHY10G_CORE_CONF_PRBS31_RX_EN (5763L)
+#define PHY10G_CORE_CONF_PRBS31_TX_EN (5764L)
+#define PHY10G_CORE_CONF_RX_TEST_PATT_EN (5765L)
+#define PHY10G_CORE_CONF_SET_PCS_LINK_STATUS (5766L)
+#define PHY10G_CORE_CONF_SET_PMA_LINK_STATUS (5767L)
+#define PHY10G_CORE_CONF_TEST_PATT_SEL (5768L)
+#define PHY10G_CORE_CONF_TX_TEST_PATT_EN (5769L)
+#define PHY10G_CORE_STAT (5770L)
+#define PHY10G_CORE_STAT_NT_LINK_STATE (5771L)
+#define PHY10G_CORE_STAT_PCS_BER_COUNT (5772L)
+#define PHY10G_CORE_STAT_PCS_BLOCK_LOCK (5773L)
+#define PHY10G_CORE_STAT_PCS_ERR_BLOCK_COUNT (5774L)
+#define PHY10G_CORE_STAT_PCS_HIBER (5775L)
+#define PHY10G_CORE_STAT_PCS_RESET (5776L)
+#define PHY10G_CORE_STAT_PCS_RX_FAULT (5777L)
+#define PHY10G_CORE_STAT_PCS_RX_HIBER_LH (5778L)
+#define PHY10G_CORE_STAT_PCS_RX_LINK_STATUS (5779L)
+#define PHY10G_CORE_STAT_PCS_RX_LOCKED (5780L)
+#define PHY10G_CORE_STAT_PCS_RX_LOCKED_LL (5781L)
+#define PHY10G_CORE_STAT_PCS_TEST_PATT_ERR_COUNT (5782L)
+#define PHY10G_CORE_STAT_PCS_TX_FAULT (5783L)
+#define PHY10G_CORE_STAT_PMA_PMD_LINK_STAT (5784L)
+#define PHY10G_CORE_STAT_PMA_PMD_RX_FAULT (5785L)
+#define PHY10G_CORE_STAT_PMA_PMD_TX_FAULT (5786L)
+#define PHY10G_CORE_STAT_PMA_RESET (5787L)
+#define PHY10G_CORE_STAT_RX_SIG_DET (5788L)
+#define PHY10G_CORE_STAT_TENG_PCS_RX_LINK_STATUS (5789L)
+#define PHY10G_CTRL (5790L)
+#define PHY10G_CTRL_FORCE_LINK_DOWN (5791L)
+#define PHY10G_CTRL_HOST_LOOPBACK (5792L)
+#define PHY10G_CTRL_LINE_LOOPBACK (5793L)
+#define PHY10G_CTRL_LINKUP_LATENCY (5794L)
+#define PHY10G_CTRL_SOFT_RESET (5795L)
+#define PHY10G_GPIO (5796L)
+#define PHY10G_GPIO_ABS (5797L)
+#define PHY10G_GPIO_LED_MODE (5798L)
+#define PHY10G_GPIO_LED_MODE_NIM (5799L)
+#define PHY10G_GPIO_LED_MODE_PHY (5800L)
+#define PHY10G_GPIO_PWR_EN (5801L)
+#define PHY10G_GPIO_RX_LOS (5802L)
+#define PHY10G_GPIO_TX_FAULT (5803L)
+#define PHY10G_GT_CTRL (5804L)
+#define PHY10G_GT_CTRL_EYESCANRESET (5805L)
+#define PHY10G_GT_CTRL_EYESCANTRIGGER (5806L)
+#define PHY10G_GT_CTRL_RXCDRHOLD (5807L)
+#define PHY10G_GT_CTRL_RXDFELPMRESET (5808L)
+#define PHY10G_GT_CTRL_RXLPMEN (5809L)
+#define PHY10G_GT_CTRL_RXPMARESET (5810L)
+#define PHY10G_GT_CTRL_RXPRBSENABLE (5811L)
+#define PHY10G_GT_CTRL_RXRATE (5812L)
+#define PHY10G_GT_CTRL_TXDIFFCTRL (5813L)
+#define PHY10G_GT_CTRL_TXPCSRESET (5814L)
+#define PHY10G_GT_CTRL_TXPMARESET (5815L)
+#define PHY10G_GT_CTRL_TXPOSTCURSOR (5816L)
+#define PHY10G_GT_CTRL_TXPRBSENABLE (5817L)
+#define PHY10G_GT_CTRL_TXPRBSFORCEERR (5818L)
+#define PHY10G_GT_CTRL_TXPRECURSOR (5819L)
+#define PHY10G_GT_STAT (5820L)
+#define PHY10G_GT_STAT_DMONITOROUT (5821L)
+#define PHY10G_GT_STAT_EYESCANDATAERROR (5822L)
+#define PHY10G_GT_STAT_RXBUFSTATUS (5823L)
+#define PHY10G_GT_STAT_RXPMARESETDONE (5824L)
+#define PHY10G_GT_STAT_RXPRBSERR (5825L)
+#define PHY10G_GT_STAT_RXPRBSLOCKED (5826L)
+#define PHY10G_GT_STAT_RXRESETDONE (5827L)
+#define PHY10G_GT_STAT_TXBUFSTATUS (5828L)
+#define PHY10G_GT_STAT_TXRESETDONE (5829L)
+#define PHY10G_GT_STAT2 (5830L)
+#define PHY10G_GT_STAT2_DMONITOR (5831L)
+#define PHY10G_GT_STAT2_RXPRBSCNT (5832L)
+#define PHY10G_INT (5833L)
+#define PHY10G_INT_EN (5834L)
+#define PHY10G_INT_MAX_PACE (5835L)
+#define PHY10G_LINK_SUMMARY (5836L)
+#define PHY10G_LINK_SUMMARY_ABS (5837L)
+#define PHY10G_LINK_SUMMARY_CORE_STATUS (5838L)
+#define PHY10G_LINK_SUMMARY_LINK_DOWN_CNT (5839L)
+#define PHY10G_LINK_SUMMARY_NT_LINK_STATE (5840L)
+#define PHY10G_LINK_SUMMARY_RES (5841L)
+#define PHY10G_TS_COMP (5842L)
+#define PHY10G_TS_COMP_RX (5843L)
+/* PHY3S10G */
+#define PHY3S10G_ANEG_ADV_3S (5844L)
+#define PHY3S10G_ANEG_ADV_3S_DUPLEX (5845L)
+#define PHY3S10G_ANEG_ADV_3S_PAUSE (5846L)
+#define PHY3S10G_ANEG_ADV_3S_REMOTE_FAULT (5847L)
+#define PHY3S10G_CORE_CONF_10G (5848L)
+#define PHY3S10G_CORE_CONF_10G_CLEAR_PCS_LINK_FAULTS (5849L)
+#define PHY3S10G_CORE_CONF_10G_CLEAR_PCS_STATUS2 (5850L)
+#define PHY3S10G_CORE_CONF_10G_CLEAR_PMA_PMD_LINK_FAULTS (5851L)
+#define PHY3S10G_CORE_CONF_10G_PCS_LOOPBACK (5852L)
+#define PHY3S10G_CORE_CONF_10G_PCS_RESET (5853L)
+#define PHY3S10G_CORE_CONF_10G_PMA_LOOPBACK (5854L)
+#define PHY3S10G_CORE_CONF_10G_PMA_RESET (5855L)
+#define PHY3S10G_CORE_CONF_10G_SET_PCS_LINK_STATUS (5856L)
+#define PHY3S10G_CORE_CONF_10G_SET_PMA_LINK_STATUS (5857L)
+#define PHY3S10G_CORE_CONF_3S (5858L)
+#define PHY3S10G_CORE_CONF_3S_ANEG_BYPASS_EN (5859L)
+#define PHY3S10G_CORE_CONF_3S_ANEG_EN (5860L)
+#define PHY3S10G_CORE_CONF_3S_ANEG_RESTART (5861L)
+#define PHY3S10G_CORE_CONF_3S_BASEX_OR_SGMII (5862L)
+#define PHY3S10G_CORE_CONF_3S_LINK_TIMER_BASEX (5863L)
+#define PHY3S10G_CORE_CONF_3S_LOOPBACK_CTRL (5864L)
+#define PHY3S10G_CORE_CONF_3S_POWER_DOWN (5865L)
+#define PHY3S10G_CORE_CONF_3S_SPEED (5866L)
+#define PHY3S10G_CORE_CONF_3S_UNIDIRECT_EN (5867L)
+#define PHY3S10G_CORE_STAT_10G (5868L)
+#define PHY3S10G_CORE_STAT_10G_NT_LINK_STATE (5869L)
+#define PHY3S10G_CORE_STAT_10G_PCS_BER_COUNT (5870L)
+#define PHY3S10G_CORE_STAT_10G_PCS_BLOCK_LOCK (5871L)
+#define PHY3S10G_CORE_STAT_10G_PCS_ERR_BLOCK_COUNT (5872L)
+#define PHY3S10G_CORE_STAT_10G_PCS_HIBER (5873L)
+#define PHY3S10G_CORE_STAT_10G_PCS_RX_HIBER_LH (5874L)
+#define PHY3S10G_CORE_STAT_10G_PCS_RX_LINK_STATUS (5875L)
+#define PHY3S10G_CORE_STAT_10G_PCS_RX_LOCKED (5876L)
+#define PHY3S10G_CORE_STAT_10G_PCS_RX_LOCKED_LL (5877L)
+#define PHY3S10G_CORE_STAT_10G_PMA_PMD_LINK_STAT (5878L)
+#define PHY3S10G_CORE_STAT_10G_RX_SIG_DET (5879L)
+#define PHY3S10G_CORE_STAT_10G_TENG_PCS_RX_LINK_STATUS (5880L)
+#define PHY3S10G_CORE_STAT_3S (5881L)
+#define PHY3S10G_CORE_STAT_3S_ANEG_COMPLETE (5882L)
+#define PHY3S10G_CORE_STAT_3S_DUPLEX_MODE (5883L)
+#define PHY3S10G_CORE_STAT_3S_LINK_STATUS (5884L)
+#define PHY3S10G_CORE_STAT_3S_LINK_SYNC (5885L)
+#define PHY3S10G_CORE_STAT_3S_NT_LINK_STATE (5886L)
+#define PHY3S10G_CORE_STAT_3S_PAUSE (5887L)
+#define PHY3S10G_CORE_STAT_3S_PHY_LINK_STAT (5888L)
+#define PHY3S10G_CORE_STAT_3S_REM_FAULT_ENC (5889L)
+#define PHY3S10G_CORE_STAT_3S_RESERVED (5890L)
+#define PHY3S10G_CORE_STAT_3S_RUDI_C (5891L)
+#define PHY3S10G_CORE_STAT_3S_RUDI_I (5892L)
+#define PHY3S10G_CORE_STAT_3S_RUDI_INVALID (5893L)
+#define PHY3S10G_CORE_STAT_3S_RXDISPERR (5894L)
+#define PHY3S10G_CORE_STAT_3S_RXNOTINTABLE (5895L)
+#define PHY3S10G_CORE_STAT_3S_SPEED (5896L)
+#define PHY3S10G_CTRL (5897L)
+#define PHY3S10G_CTRL_FORCE_LINK_DOWN (5898L)
+#define PHY3S10G_CTRL_HOST_LOOPBACK_10G (5899L)
+#define PHY3S10G_CTRL_HOST_LOOPBACK_3S (5900L)
+#define PHY3S10G_CTRL_LINE_LOOPBACK_10G (5901L)
+#define PHY3S10G_CTRL_LINE_LOOPBACK_3S (5902L)
+#define PHY3S10G_CTRL_LINKUP_LATENCY (5903L)
+#define PHY3S10G_CTRL_PHY_CHANGE_FSM_DONE (5904L)
+#define PHY3S10G_CTRL_PHY_SEL (5905L)
+#define PHY3S10G_CTRL_SOFT_RESET (5906L)
+#define PHY3S10G_GPIO (5907L)
+#define PHY3S10G_GPIO_ABS (5908L)
+#define PHY3S10G_GPIO_LED_MODE (5909L)
+#define PHY3S10G_GPIO_RATE_SEL (5910L)
+#define PHY3S10G_GPIO_RX_LOS (5911L)
+#define PHY3S10G_GPIO_TX_DISABLE (5912L)
+#define PHY3S10G_GPIO_TX_FAULT (5913L)
+#define PHY3S10G_GT_CR (5914L)
+#define PHY3S10G_GT_CR_EYESCANRESET (5915L)
+#define PHY3S10G_GT_CR_EYESCANTRIGGER (5916L)
+#define PHY3S10G_GT_CR_LOOPBACK (5917L)
+#define PHY3S10G_GT_CR_RXCDRHOLD (5918L)
+#define PHY3S10G_GT_CR_RXDFELPMRESET (5919L)
+#define PHY3S10G_GT_CR_RXLPMEN (5920L)
+#define PHY3S10G_GT_CR_RXPMARESET (5921L)
+#define PHY3S10G_GT_CR_RXPRBSCNTRESET (5922L)
+#define PHY3S10G_GT_CR_RXPRBSSEL (5923L)
+#define PHY3S10G_GT_CR_TXDIFFCTRL (5924L)
+#define PHY3S10G_GT_CR_TXPMARESET (5925L)
+#define PHY3S10G_GT_CR_TXPOSTCURSOR (5926L)
+#define PHY3S10G_GT_CR_TXPRBSFORCEERR (5927L)
+#define PHY3S10G_GT_CR_TXPRBSSEL (5928L)
+#define PHY3S10G_GT_CR_TXPRECURSOR (5929L)
+#define PHY3S10G_GT_SR (5930L)
+#define PHY3S10G_GT_SR_EYESCANDATAERROR (5931L)
+#define PHY3S10G_GT_SR_RXBUFSTATUS (5932L)
+#define PHY3S10G_GT_SR_RXPMARESETDONE (5933L)
+#define PHY3S10G_GT_SR_RXPRBSERR (5934L)
+#define PHY3S10G_GT_SR_RXRESETDONE (5935L)
+#define PHY3S10G_GT_SR_TXBUFSTATUS (5936L)
+#define PHY3S10G_GT_SR_TXRESETDONE (5937L)
+#define PHY3S10G_INT (5938L)
+#define PHY3S10G_INT_EN (5939L)
+#define PHY3S10G_INT_MAX_PACE (5940L)
+#define PHY3S10G_LINK_SUMMARY (5941L)
+#define PHY3S10G_LINK_SUMMARY_ABS (5942L)
+#define PHY3S10G_LINK_SUMMARY_ANEG_BYPASS (5943L)
+#define PHY3S10G_LINK_SUMMARY_LINK_DOWN_CNT (5944L)
+#define PHY3S10G_LINK_SUMMARY_NT_LINK_STATE (5945L)
+#define PHY3S10G_TS_COMP (5946L)
+#define PHY3S10G_TS_COMP_RX (5947L)
+#define PHY3S10G_TS_COMP_RX_10G (5948L)
+#define PHY3S10G_TS_COMP_RX_3S (5949L)
+/* PM */
+#define PM_CTRL (5950L)
+#define PM_CTRL_SW_CLEAN_DONE (5951L)
+#define PM_DEBUG_RP (5952L)
+#define PM_DEBUG_RP_RP (5953L)
+#define PM_DEBUG_RP_SETUP (5954L)
+#define PM_DEBUG_RP_SETUP_HB (5955L)
+#define PM_DEBUG_RX_BLOCK (5956L)
+#define PM_DEBUG_RX_BLOCK_MASK (5957L)
+#define PM_HB_SIZE_RX_MEM_CTRL (5958L)
+#define PM_HB_SIZE_RX_MEM_CTRL_A (5959L)
+#define PM_HB_SIZE_RX_MEM_CTRL_CNT (5960L)
+#define PM_HB_SIZE_RX_MEM_DATA (5961L)
+#define PM_HB_SIZE_RX_MEM_DATA_SIZE (5962L)
+#define PM_HB_SIZE_RX_THRESHOLD (5963L)
+#define PM_HB_SIZE_RX_THRESHOLD_D (5964L)
+#define PM_HB_SIZE_TX_THRESHOLD (5965L)
+#define PM_HB_SIZE_TX_THRESHOLD_D (5966L)
+#define PM_PBI_MEM_CTRL (5967L)
+#define PM_PBI_MEM_CTRL_A (5968L)
+#define PM_PBI_MEM_CTRL_CNT (5969L)
+#define PM_PBI_MEM_DATA (5970L)
+#define PM_PBI_MEM_DATA_PHYADDR (5971L)
+#define PM_PBI_MEM_DATA_SIZE (5972L)
+#define PM_POINTER_BANKS (5973L)
+#define PM_POINTER_BANKS_D (5974L)
+#define PM_RXTX_FAST_MEM_CTRL (5975L)
+#define PM_RXTX_FAST_MEM_CTRL_A (5976L)
+#define PM_RXTX_FAST_MEM_CTRL_CNT (5977L)
+#define PM_RXTX_FAST_MEM_DATA (5978L)
+#define PM_RXTX_FAST_MEM_DATA_BANK (5979L)
+#define PM_RXTX_FAST_MEM_DATA_ENTRY (5980L)
+#define PM_RXTX_FAST_MEM_DATA_HOST_BUFFER (5981L)
+#define PM_RXTX_FAST_MEM_DATA_RX_TX (5982L)
+#define PM_RXTX_FAST_MEM_DATA_VLD (5983L)
+#define PM_RXTX_SLOW_MEM_CTRL (5984L)
+#define PM_RXTX_SLOW_MEM_CTRL_A (5985L)
+#define PM_RXTX_SLOW_MEM_CTRL_CNT (5986L)
+#define PM_RXTX_SLOW_MEM_DATA (5987L)
+#define PM_RXTX_SLOW_MEM_DATA_BANK (5988L)
+#define PM_RXTX_SLOW_MEM_DATA_ENTRY (5989L)
+#define PM_RXTX_SLOW_MEM_DATA_HOST_BUFFER (5990L)
+#define PM_RXTX_SLOW_MEM_DATA_RX_TX (5991L)
+#define PM_RXTX_SLOW_MEM_DATA_VLD (5992L)
+#define PM_RXWP_MEM_CTRL (5993L)
+#define PM_RXWP_MEM_CTRL_A (5994L)
+#define PM_RXWP_MEM_CTRL_CNT (5995L)
+#define PM_RXWP_MEM_DATA (5996L)
+#define PM_RXWP_MEM_DATA_BANK (5997L)
+#define PM_RXWP_MEM_DATA_ENTRY (5998L)
+#define PM_RXWP_MEM_DATA_HOST_BUFFER (5999L)
+#define PM_RXWP_MEM_DATA_VLD (6000L)
+#define PM_RX_BLOCKED_STATUS (6001L)
+#define PM_RX_BLOCKED_STATUS_D (6002L)
+#define PM_RX_BLOCKED_STATUS_HI (6003L)
+#define PM_RX_BLOCKED_STATUS_HI_D (6004L)
+#define PM_RX_OVERFLOW_STATUS (6005L)
+#define PM_RX_OVERFLOW_STATUS_D (6006L)
+#define PM_RX_READER (6007L)
+#define PM_RX_READER_MASK (6008L)
+#define PM_RX_TX_FAST_POINTER_BLOCK_INTERVAL (6009L)
+#define PM_RX_TX_FAST_POINTER_BLOCK_INTERVAL_D (6010L)
+#define PM_RX_TX_SLOW_POINTER_BLOCK_INTERVAL (6011L)
+#define PM_RX_TX_SLOW_POINTER_BLOCK_INTERVAL_D (6012L)
+#define PM_RX_WRITE_POINTER_BLOCK_INTERVAL (6013L)
+#define PM_RX_WRITE_POINTER_BLOCK_INTERVAL_D (6014L)
+#define PM_TXRP_MEM_CTRL (6015L)
+#define PM_TXRP_MEM_CTRL_A (6016L)
+#define PM_TXRP_MEM_CTRL_CNT (6017L)
+#define PM_TXRP_MEM_DATA (6018L)
+#define PM_TXRP_MEM_DATA_BANK (6019L)
+#define PM_TXRP_MEM_DATA_ENTRY (6020L)
+#define PM_TXRP_MEM_DATA_HOST_BUFFER (6021L)
+#define PM_TXRP_MEM_DATA_VLD (6022L)
+#define PM_TX_READ_POINTER_BLOCK_INTERVAL (6023L)
+#define PM_TX_READ_POINTER_BLOCK_INTERVAL_D (6024L)
+/* PRM_NT100A01_01 */
+#define PRM_NT100A01_01_POWER (6025L)
+#define PRM_NT100A01_01_POWER_PU_NSEB (6026L)
+#define PRM_NT100A01_01_POWER_PU_PHY (6027L)
+#define PRM_NT100A01_01_RST (6028L)
+#define PRM_NT100A01_01_RST_PERIPH (6029L)
+#define PRM_NT100A01_01_RST_PLATFORM (6030L)
+/* PRM_NT50B01_01 */
+#define PRM_NT50B01_01_POWER (6031L)
+#define PRM_NT50B01_01_POWER_PU_NSEB (6032L)
+#define PRM_NT50B01_01_POWER_PU_PHY (6033L)
+#define PRM_NT50B01_01_RST (6034L)
+#define PRM_NT50B01_01_RST_PERIPH (6035L)
+#define PRM_NT50B01_01_RST_PLATFORM (6036L)
+/* PTP1588 */
+#define PTP1588_CONF (6037L)
+#define PTP1588_CONF_MII_RX_TX_LOOP (6038L)
+#define PTP1588_CONF_MII_TX_RX_LOOP (6039L)
+#define PTP1588_CONF_PHY_RST (6040L)
+#define PTP1588_CONF_PHY_RST1 (6041L)
+#define PTP1588_CONF_PHY_RST2 (6042L)
+#define PTP1588_CONF_PTP_CTRL_LOCAL (6043L)
+#define PTP1588_CONF_PTP_RX_CTRL (6044L)
+#define PTP1588_CONF_PTP_TX_CTRL (6045L)
+#define PTP1588_CONF_PTP_TX_CTRL_OS (6046L)
+#define PTP1588_CONF_RX_IGNORE_DEST_ADDR (6047L)
+#define PTP1588_CONF_TG_CMD (6048L)
+#define PTP1588_CONF_TG_MODE (6049L)
+#define PTP1588_CONF_TSM_MI_ACK (6050L)
+#define PTP1588_CONF_TSM_MI_BUSY (6051L)
+#define PTP1588_CONF_TSM_MI_ENA (6052L)
+#define PTP1588_CONF_TSM_MI_REQ (6053L)
+#define PTP1588_CONF_TX_IFG (6054L)
+#define PTP1588_CONF_TX_IGNORE_DEST_ADDR (6055L)
+#define PTP1588_CTRL (6056L)
+#define PTP1588_CTRL_CLK_ENABLE (6057L)
+#define PTP1588_CTRL_MII_RX_TX_LOOP (6058L)
+#define PTP1588_CTRL_MII_TX_RX_LOOP (6059L)
+#define PTP1588_CTRL_PRESENT (6060L)
+#define PTP1588_CTRL_RESET_N (6061L)
+#define PTP1588_CTRL_TS_MI_ACK (6062L)
+#define PTP1588_CTRL_TS_MI_BUSY (6063L)
+#define PTP1588_CTRL_TS_MI_ENA (6064L)
+#define PTP1588_CTRL_TS_MI_REQ (6065L)
+#define PTP1588_CTRL_TX_IFG (6066L)
+#define PTP1588_GP_DATA (6067L)
+#define PTP1588_GP_DATA_GPIO (6068L)
+#define PTP1588_GP_DATA_PWRDOWN_INTN (6069L)
+#define PTP1588_GP_DATA_TIMESYNC_CON (6070L)
+#define PTP1588_GP_DATA_LH (6071L)
+#define PTP1588_GP_DATA_LH_GPIO (6072L)
+#define PTP1588_GP_DATA_LH_PWRDOWN_INTN (6073L)
+#define PTP1588_GP_DATA_LH_TIMESYNC_CON (6074L)
+#define PTP1588_GP_DATA_LL (6075L)
+#define PTP1588_GP_DATA_LL_GPIO (6076L)
+#define PTP1588_GP_DATA_LL_PWRDOWN_INTN (6077L)
+#define PTP1588_GP_DATA_LL_TIMESYNC_CON (6078L)
+#define PTP1588_GP_OE (6079L)
+#define PTP1588_GP_OE_GPIO (6080L)
+#define PTP1588_GP_OE_PWRDOWN_INTN (6081L)
+#define PTP1588_GP_OE_TIMESYNC_CON (6082L)
+#define PTP1588_MAC_HOST_ADDR (6083L)
+#define PTP1588_MAC_HOST_ADDR_ADDR (6084L)
+#define PTP1588_MAC_HOST_ADDR_MDIO_ACCESS (6085L)
+#define PTP1588_MAC_HOST_ADDR_OPCODE (6086L)
+#define PTP1588_MAC_HOST_ADDR_RDY (6087L)
+#define PTP1588_MAC_HOST_DATA_LSB (6088L)
+#define PTP1588_MAC_HOST_DATA_LSB_DATA (6089L)
+#define PTP1588_MAC_HOST_DATA_MSB (6090L)
+#define PTP1588_MAC_HOST_DATA_MSB_DATA (6091L)
+#define PTP1588_MAC_INBAND_STAT (6092L)
+#define PTP1588_MAC_INBAND_STAT_DUPLEX (6093L)
+#define PTP1588_MAC_INBAND_STAT_LINK (6094L)
+#define PTP1588_MAC_INBAND_STAT_SPEED (6095L)
+#define PTP1588_MAC_MI_CONF (6096L)
+#define PTP1588_MAC_MI_CONF_ACCESS_TYPE (6097L)
+#define PTP1588_MAC_MI_CONF_ADDRESS (6098L)
+#define PTP1588_MAC_MI_CONF_RDY (6099L)
+#define PTP1588_MAC_MI_DATA (6100L)
+#define PTP1588_MAC_MI_DATA_DATA (6101L)
+#define PTP1588_RX_HOST_ADR_LSB (6102L)
+#define PTP1588_RX_HOST_ADR_LSB_LSB (6103L)
+#define PTP1588_RX_HOST_ADR_MSB (6104L)
+#define PTP1588_RX_HOST_ADR_MSB_MSB (6105L)
+#define PTP1588_RX_HOST_CONF (6106L)
+#define PTP1588_RX_HOST_CONF_ENA (6107L)
+#define PTP1588_RX_HOST_CONF_RDPTR (6108L)
+#define PTP1588_RX_HOST_CONF_REDUCED (6109L)
+#define PTP1588_RX_HOST_CTRL (6110L)
+#define PTP1588_RX_HOST_CTRL_ENA (6111L)
+#define PTP1588_RX_HOST_CTRL_RDPTR (6112L)
+#define PTP1588_RX_HOST_CTRL_REDUCED (6113L)
+#define PTP1588_STAT (6114L)
+#define PTP1588_STAT_DATA (6115L)
+#define PTP1588_STAT_CONF (6116L)
+#define PTP1588_STAT_CONF_INDEX (6117L)
+#define PTP1588_STAT_CONF_LOCK (6118L)
+#define PTP1588_STAT_CTRL (6119L)
+#define PTP1588_STAT_CTRL_INDEX (6120L)
+#define PTP1588_STAT_CTRL_LOCK (6121L)
+#define PTP1588_TX_FIRST_DAT (6122L)
+#define PTP1588_TX_FIRST_DAT_DAT (6123L)
+#define PTP1588_TX_LAST1_DAT (6124L)
+#define PTP1588_TX_LAST1_DAT_DAT (6125L)
+#define PTP1588_TX_LAST2_DAT (6126L)
+#define PTP1588_TX_LAST2_DAT_DAT (6127L)
+#define PTP1588_TX_LAST3_DAT (6128L)
+#define PTP1588_TX_LAST3_DAT_DAT (6129L)
+#define PTP1588_TX_LAST4_DAT (6130L)
+#define PTP1588_TX_LAST4_DAT_DAT (6131L)
+#define PTP1588_TX_MID_DAT (6132L)
+#define PTP1588_TX_MID_DAT_DAT (6133L)
+#define PTP1588_TX_PACKET_STATE (6134L)
+#define PTP1588_TX_PACKET_STATE_MSG_TYPE (6135L)
+#define PTP1588_TX_PACKET_STATE_PCK_TYPE (6136L)
+#define PTP1588_TX_PACKET_STATE_SEQ_ID (6137L)
+#define PTP1588_TX_PACKET_STATE_TEST_MARGIN (6138L)
+#define PTP1588_TX_PACKET_STATE_VALID (6139L)
+#define PTP1588_TX_STATUS (6140L)
+#define PTP1588_TX_STATUS_DB_ERR (6141L)
+#define PTP1588_TX_STATUS_DB_FULL (6142L)
+#define PTP1588_TX_STATUS_FIFO_STATUS (6143L)
+#define PTP1588_TX_STATUS_RDY (6144L)
+#define PTP1588_TX_STATUS_TG_ENA (6145L)
+#define PTP1588_TX_STATUS_TG_MODE (6146L)
+#define PTP1588_TX_TIMESTAMP_NS (6147L)
+#define PTP1588_TX_TIMESTAMP_NS_TIMESTAMP (6148L)
+#define PTP1588_TX_TIMESTAMP_SEC (6149L)
+#define PTP1588_TX_TIMESTAMP_SEC_TIMESTAMP (6150L)
+/* QM */
+#define QM_BLOCK_SIZE (6151L)
+#define QM_BLOCK_SIZE_CELLS (6152L)
+#define QM_CTRL (6153L)
+#define QM_CTRL_ACTIVE_QUEUES (6154L)
+#define QM_CTRL_ACTIVE_QUEUES_QPI_BYPASS (6155L)
+#define QM_CTRL_ENABLE (6156L)
+#define QM_CTRL_PRIORITY_SCHEME (6157L)
+#define QM_DEBUG_BLOCK_SIZE (6158L)
+#define QM_DEBUG_BLOCK_SIZE_CELLS (6159L)
+#define QM_DEBUG_CRC (6160L)
+#define QM_DEBUG_CRC_FORCE_ERROR (6161L)
+#define QM_DEBUG_SDRAM_SIZE (6162L)
+#define QM_DEBUG_SDRAM_SIZE_MASK (6163L)
+#define QM_GROUP_LIMIT_MEM_CTRL (6164L)
+#define QM_GROUP_LIMIT_MEM_CTRL_A (6165L)
+#define QM_GROUP_LIMIT_MEM_CTRL_CNT (6166L)
+#define QM_GROUP_LIMIT_MEM_DATA (6167L)
+#define QM_GROUP_LIMIT_MEM_DATA_LIMIT (6168L)
+#define QM_GROUP_MAPPING_MEM_CTRL (6169L)
+#define QM_GROUP_MAPPING_MEM_CTRL_A (6170L)
+#define QM_GROUP_MAPPING_MEM_CTRL_CNT (6171L)
+#define QM_GROUP_MAPPING_MEM_DATA (6172L)
+#define QM_GROUP_MAPPING_MEM_DATA_GROUP0 (6173L)
+#define QM_GROUP_MAPPING_MEM_DATA_GROUP1 (6174L)
+#define QM_GROUP_MAPPING_MEM_DATA_GROUP2 (6175L)
+#define QM_PRIO_LEVELS_MEM_CTRL (6176L)
+#define QM_PRIO_LEVELS_MEM_CTRL_A (6177L)
+#define QM_PRIO_LEVELS_MEM_CTRL_CNT (6178L)
+#define QM_PRIO_LEVELS_MEM_DATA (6179L)
+#define QM_PRIO_LEVELS_MEM_DATA_PRIO (6180L)
+#define QM_QUEUE_LIMIT_MEM_CTRL (6181L)
+#define QM_QUEUE_LIMIT_MEM_CTRL_A (6182L)
+#define QM_QUEUE_LIMIT_MEM_CTRL_CNT (6183L)
+#define QM_QUEUE_LIMIT_MEM_DATA (6184L)
+#define QM_QUEUE_LIMIT_MEM_DATA_LIMIT (6185L)
+#define QM_STATUS_BLOCKED (6186L)
+#define QM_STATUS_BLOCKED_D (6187L)
+#define QM_STATUS_BLOCKED_HI (6188L)
+#define QM_STATUS_BLOCKED_HI_D (6189L)
+#define QM_STATUS_BLOCKING (6190L)
+#define QM_STATUS_BLOCKING_D (6191L)
+#define QM_STATUS_BLOCKING_HI (6192L)
+#define QM_STATUS_BLOCKING_HI_D (6193L)
+#define QM_STATUS_CRC_ERROR (6194L)
+#define QM_STATUS_CRC_ERROR_CNT (6195L)
+#define QM_STATUS_EMPTY (6196L)
+#define QM_STATUS_EMPTY_D (6197L)
+#define QM_STATUS_EMPTY_HI (6198L)
+#define QM_STATUS_EMPTY_HI_D (6199L)
+#define QM_STATUS_FLUSH_DROP (6200L)
+#define QM_STATUS_FLUSH_DROP_CNT (6201L)
+#define QM_STATUS_SDRAM_BLOCK_MAX_USAGE (6202L)
+#define QM_STATUS_SDRAM_BLOCK_MAX_USAGE_D (6203L)
+#define QM_STATUS_SDRAM_BLOCK_USAGE (6204L)
+#define QM_STATUS_SDRAM_BLOCK_USAGE_D (6205L)
+#define QM_STATUS_SDRAM_CELL_MAX_USAGE (6206L)
+#define QM_STATUS_SDRAM_CELL_MAX_USAGE_D (6207L)
+#define QM_STATUS_SDRAM_CELL_USAGE (6208L)
+#define QM_STATUS_SDRAM_CELL_USAGE_D (6209L)
+/* QSL */
+#define QSL_LTX_CTRL (6210L)
+#define QSL_LTX_CTRL_ADR (6211L)
+#define QSL_LTX_CTRL_CNT (6212L)
+#define QSL_LTX_DATA (6213L)
+#define QSL_LTX_DATA_LR (6214L)
+#define QSL_LTX_DATA_TSA (6215L)
+#define QSL_LTX_DATA_TX_PORT (6216L)
+#define QSL_QEN_CTRL (6217L)
+#define QSL_QEN_CTRL_ADR (6218L)
+#define QSL_QEN_CTRL_CNT (6219L)
+#define QSL_QEN_DATA (6220L)
+#define QSL_QEN_DATA_EN (6221L)
+#define QSL_QST_CTRL (6222L)
+#define QSL_QST_CTRL_ADR (6223L)
+#define QSL_QST_CTRL_CNT (6224L)
+#define QSL_QST_DATA (6225L)
+#define QSL_QST_DATA_EN (6226L)
+#define QSL_QST_DATA_LRE (6227L)
+#define QSL_QST_DATA_QEN (6228L)
+#define QSL_QST_DATA_QUEUE (6229L)
+#define QSL_QST_DATA_TCI (6230L)
+#define QSL_QST_DATA_TX_PORT (6231L)
+#define QSL_QST_DATA_VEN (6232L)
+#define QSL_RCP_CTRL (6233L)
+#define QSL_RCP_CTRL_ADR (6234L)
+#define QSL_RCP_CTRL_CNT (6235L)
+#define QSL_RCP_DATA (6236L)
+#define QSL_RCP_DATA_CAO (6237L)
+#define QSL_RCP_DATA_DISCARD (6238L)
+#define QSL_RCP_DATA_DROP (6239L)
+#define QSL_RCP_DATA_LR (6240L)
+#define QSL_RCP_DATA_TBL_HI (6241L)
+#define QSL_RCP_DATA_TBL_IDX (6242L)
+#define QSL_RCP_DATA_TBL_LO (6243L)
+#define QSL_RCP_DATA_TBL_MSK (6244L)
+#define QSL_RCP_DATA_TSA (6245L)
+#define QSL_RCP_DATA_VLI (6246L)
+#define QSL_UNMQ_CTRL (6247L)
+#define QSL_UNMQ_CTRL_ADR (6248L)
+#define QSL_UNMQ_CTRL_CNT (6249L)
+#define QSL_UNMQ_DATA (6250L)
+#define QSL_UNMQ_DATA_DEST_QUEUE (6251L)
+#define QSL_UNMQ_DATA_EN (6252L)
+/* QSPI */
+#define QSPI_CR (6253L)
+#define QSPI_CR_CPHA (6254L)
+#define QSPI_CR_CPOL (6255L)
+#define QSPI_CR_LOOP (6256L)
+#define QSPI_CR_LSBF (6257L)
+#define QSPI_CR_MSSAE (6258L)
+#define QSPI_CR_MST (6259L)
+#define QSPI_CR_MTI (6260L)
+#define QSPI_CR_RXFIFO_RST (6261L)
+#define QSPI_CR_SPE (6262L)
+#define QSPI_CR_TXFIFO_RST (6263L)
+#define QSPI_DGIE (6264L)
+#define QSPI_DGIE_GIE (6265L)
+#define QSPI_DRR (6266L)
+#define QSPI_DRR_DATA_VAL (6267L)
+#define QSPI_DTR (6268L)
+#define QSPI_DTR_DATA_VAL (6269L)
+#define QSPI_IER (6270L)
+#define QSPI_IER_CMD_ERR (6271L)
+#define QSPI_IER_CPOL_CPHA_ERR (6272L)
+#define QSPI_IER_DRR_FULL (6273L)
+#define QSPI_IER_DRR_NEMPTY (6274L)
+#define QSPI_IER_DRR_OR (6275L)
+#define QSPI_IER_DTR_EMPTY (6276L)
+#define QSPI_IER_DTR_UR (6277L)
+#define QSPI_IER_LOOP_ERR (6278L)
+#define QSPI_IER_MODF (6279L)
+#define QSPI_IER_MSB_ERR (6280L)
+#define QSPI_IER_SLV_ERR (6281L)
+#define QSPI_IER_SLV_MODF (6282L)
+#define QSPI_IER_SLV_MS (6283L)
+#define QSPI_IER_TXFIFO_HEMPTY (6284L)
+#define QSPI_ISR (6285L)
+#define QSPI_ISR_CMD_ERR (6286L)
+#define QSPI_ISR_CPOL_CPHA_ERR (6287L)
+#define QSPI_ISR_DRR_FULL (6288L)
+#define QSPI_ISR_DRR_NEMPTY (6289L)
+#define QSPI_ISR_DRR_OR (6290L)
+#define QSPI_ISR_DTR_EMPTY (6291L)
+#define QSPI_ISR_DTR_UR (6292L)
+#define QSPI_ISR_LOOP_ERR (6293L)
+#define QSPI_ISR_MODF (6294L)
+#define QSPI_ISR_MSB_ERR (6295L)
+#define QSPI_ISR_SLV_ERR (6296L)
+#define QSPI_ISR_SLV_MODF (6297L)
+#define QSPI_ISR_SLV_MS (6298L)
+#define QSPI_ISR_TXFIFO_HEMPTY (6299L)
+#define QSPI_RX_FIFO_OCY (6300L)
+#define QSPI_RX_FIFO_OCY_OCY_VAL (6301L)
+#define QSPI_SR (6302L)
+#define QSPI_SR_CMD_ERR (6303L)
+#define QSPI_SR_CPOL_CPHA_ERR (6304L)
+#define QSPI_SR_LOOP_ERR (6305L)
+#define QSPI_SR_MODF (6306L)
+#define QSPI_SR_MSB_ERR (6307L)
+#define QSPI_SR_RXEMPTY (6308L)
+#define QSPI_SR_RXFULL (6309L)
+#define QSPI_SR_SLVMS (6310L)
+#define QSPI_SR_SLV_ERR (6311L)
+#define QSPI_SR_TXEMPTY (6312L)
+#define QSPI_SR_TXFULL (6313L)
+#define QSPI_SRR (6314L)
+#define QSPI_SRR_RST (6315L)
+#define QSPI_SSR (6316L)
+#define QSPI_SSR_SEL_SLV (6317L)
+#define QSPI_TX_FIFO_OCY (6318L)
+#define QSPI_TX_FIFO_OCY_OCY_VAL (6319L)
+/* R2DRP */
+#define R2DRP_CTRL (6320L)
+#define R2DRP_CTRL_ADR (6321L)
+#define R2DRP_CTRL_DATA (6322L)
+#define R2DRP_CTRL_DBG_BUSY (6323L)
+#define R2DRP_CTRL_DONE (6324L)
+#define R2DRP_CTRL_RES (6325L)
+#define R2DRP_CTRL_WREN (6326L)
+/* RAC */
+#define RAC_DBG_CTRL (6327L)
+#define RAC_DBG_CTRL_C (6328L)
+#define RAC_DBG_DATA (6329L)
+#define RAC_DBG_DATA_D (6330L)
+#define RAC_DUMMY0 (6331L)
+#define RAC_DUMMY1 (6332L)
+#define RAC_DUMMY2 (6333L)
+#define RAC_NDM_REGISTER (6334L)
+#define RAC_NDM_REGISTER_NDM (6335L)
+#define RAC_NMB_DATA (6336L)
+#define RAC_NMB_DATA_NMB_DATA (6337L)
+#define RAC_NMB_RD_ADR (6338L)
+#define RAC_NMB_RD_ADR_ADR (6339L)
+#define RAC_NMB_RD_ADR_RES (6340L)
+#define RAC_NMB_STATUS (6341L)
+#define RAC_NMB_STATUS_BUS_TIMEOUT (6342L)
+#define RAC_NMB_STATUS_NMB_READY (6343L)
+#define RAC_NMB_WR_ADR (6344L)
+#define RAC_NMB_WR_ADR_ADR (6345L)
+#define RAC_NMB_WR_ADR_RES (6346L)
+#define RAC_RAB_BUF_FREE (6347L)
+#define RAC_RAB_BUF_FREE_IB_FREE (6348L)
+#define RAC_RAB_BUF_FREE_IB_OVF (6349L)
+#define RAC_RAB_BUF_FREE_OB_FREE (6350L)
+#define RAC_RAB_BUF_FREE_OB_OVF (6351L)
+#define RAC_RAB_BUF_FREE_TIMEOUT (6352L)
+#define RAC_RAB_BUF_USED (6353L)
+#define RAC_RAB_BUF_USED_FLUSH (6354L)
+#define RAC_RAB_BUF_USED_IB_USED (6355L)
+#define RAC_RAB_BUF_USED_OB_USED (6356L)
+#define RAC_RAB_DMA_IB_HI (6357L)
+#define RAC_RAB_DMA_IB_HI_PHYADDR (6358L)
+#define RAC_RAB_DMA_IB_LO (6359L)
+#define RAC_RAB_DMA_IB_LO_PHYADDR (6360L)
+#define RAC_RAB_DMA_IB_RD (6361L)
+#define RAC_RAB_DMA_IB_RD_PTR (6362L)
+#define RAC_RAB_DMA_IB_WR (6363L)
+#define RAC_RAB_DMA_IB_WR_PTR (6364L)
+#define RAC_RAB_DMA_OB_HI (6365L)
+#define RAC_RAB_DMA_OB_HI_PHYADDR (6366L)
+#define RAC_RAB_DMA_OB_LO (6367L)
+#define RAC_RAB_DMA_OB_LO_PHYADDR (6368L)
+#define RAC_RAB_DMA_OB_WR (6369L)
+#define RAC_RAB_DMA_OB_WR_PTR (6370L)
+#define RAC_RAB_IB_DATA (6371L)
+#define RAC_RAB_IB_DATA_D (6372L)
+#define RAC_RAB_INIT (6373L)
+#define RAC_RAB_INIT_RAB (6374L)
+#define RAC_RAB_OB_DATA (6375L)
+#define RAC_RAB_OB_DATA_D (6376L)
+/* RBH */
+#define RBH_CTRL (6377L)
+#define RBH_CTRL_ENABLE_METADATA_HB (6378L)
+#define RBH_CTRL_ENABLE_PM (6379L)
+#define RBH_CTRL_ENABLE_QHM (6380L)
+#define RBH_CTRL_HB_MAX (6381L)
+#define RBH_CTRL_HB_SEGMENT_SIZE (6382L)
+#define RBH_CTRL_RESERVED (6383L)
+#define RBH_CTRL_RESET_CREDITS_QHM (6384L)
+#define RBH_DEB_REG1 (6385L)
+#define RBH_DEB_REG1_VALUE (6386L)
+#define RBH_DEB_REG2 (6387L)
+#define RBH_DEB_REG2_VALUE (6388L)
+#define RBH_DEB_REG3 (6389L)
+#define RBH_DEB_REG3_VALUE (6390L)
+#define RBH_FLUSH_ADR_HI (6391L)
+#define RBH_FLUSH_ADR_HI_VALUE (6392L)
+#define RBH_FLUSH_ADR_LO (6393L)
+#define RBH_FLUSH_ADR_LO_VALUE (6394L)
+#define RBH_HOST_BUF_SIZE_MEM_CTRL (6395L)
+#define RBH_HOST_BUF_SIZE_MEM_CTRL_A (6396L)
+#define RBH_HOST_BUF_SIZE_MEM_CTRL_CNT (6397L)
+#define RBH_HOST_BUF_SIZE_MEM_DATA (6398L)
+#define RBH_HOST_BUF_SIZE_MEM_DATA_HB_SEGMENT_CNT (6399L)
+#define RBH_STATUS (6400L)
+#define RBH_STATUS_BUFFER_EMPTY (6401L)
+#define RBH_STATUS_DWA_DATAFIFO_EMPTY (6402L)
+#define RBH_STATUS_PWA_DATAFIFO_EMPTY (6403L)
+#define RBH_WP_SET_MEM_CTRL (6404L)
+#define RBH_WP_SET_MEM_CTRL_A (6405L)
+#define RBH_WP_SET_MEM_CTRL_CNT (6406L)
+#define RBH_WP_SET_MEM_DATA (6407L)
+#define RBH_WP_SET_MEM_DATA_WP (6408L)
+/* RFD */
+#define RFD_CTRL (6409L)
+#define RFD_CTRL_CFP (6410L)
+#define RFD_CTRL_ISL (6411L)
+#define RFD_CTRL_PWMCW (6412L)
+#define RFD_MAX_FRAME_SIZE (6413L)
+#define RFD_MAX_FRAME_SIZE_MAX (6414L)
+#define RFD_TNL_VLAN (6415L)
+#define RFD_TNL_VLAN_TPID0 (6416L)
+#define RFD_TNL_VLAN_TPID1 (6417L)
+#define RFD_VLAN (6418L)
+#define RFD_VLAN_TPID0 (6419L)
+#define RFD_VLAN_TPID1 (6420L)
+#define RFD_VXLAN (6421L)
+#define RFD_VXLAN_DP0 (6422L)
+#define RFD_VXLAN_DP1 (6423L)
+/* RMC */
+#define RMC_CTRL (6424L)
+#define RMC_CTRL_BLOCK_KEEPA (6425L)
+#define RMC_CTRL_BLOCK_MAC_PORT (6426L)
+#define RMC_CTRL_BLOCK_RPP_SLICE (6427L)
+#define RMC_CTRL_BLOCK_STATT (6428L)
+#define RMC_CTRL_LAG_PHY_ODD_EVEN (6429L)
+#define RMC_DBG (6430L)
+#define RMC_DBG_MERGE (6431L)
+#define RMC_MAC_IF (6432L)
+#define RMC_MAC_IF_ERR (6433L)
+#define RMC_STATUS (6434L)
+#define RMC_STATUS_DESCR_FIFO_OF (6435L)
+#define RMC_STATUS_SF_RAM_OF (6436L)
+/* RNTC */
+#define RNTC_CTRL (6437L)
+#define RNTC_CTRL_RNTC_ENA (6438L)
+#define RNTC_STAT (6439L)
+#define RNTC_STAT_EMPTY (6440L)
+#define RNTC_TX_DATA (6441L)
+#define RNTC_TX_DATA_D (6442L)
+/* ROA */
+#define ROA_CONFIG (6443L)
+#define ROA_CONFIG_FWD_CELLBUILDER_PCKS (6444L)
+#define ROA_CONFIG_FWD_NON_NORMAL_PCKS (6445L)
+#define ROA_CONFIG_FWD_NORMAL_PCKS (6446L)
+#define ROA_CONFIG_FWD_RECIRCULATE (6447L)
+#define ROA_CONFIG_FWD_TXPORT0 (6448L)
+#define ROA_CONFIG_FWD_TXPORT1 (6449L)
+#define ROA_IGS (6450L)
+#define ROA_IGS_BYTE (6451L)
+#define ROA_IGS_BYTE_DROP (6452L)
+#define ROA_IGS_PKT (6453L)
+#define ROA_IGS_PKT_DROP (6454L)
+#define ROA_LAGCFG_CTRL (6455L)
+#define ROA_LAGCFG_CTRL_ADR (6456L)
+#define ROA_LAGCFG_CTRL_CNT (6457L)
+#define ROA_LAGCFG_DATA (6458L)
+#define ROA_LAGCFG_DATA_TXPHY_PORT (6459L)
+#define ROA_RCC (6460L)
+#define ROA_RCC_BYTE (6461L)
+#define ROA_RCC_BYTE_DROP (6462L)
+#define ROA_RCC_PKT (6463L)
+#define ROA_RCC_PKT_DROP (6464L)
+#define ROA_TUNCFG_CTRL (6465L)
+#define ROA_TUNCFG_CTRL_ADR (6466L)
+#define ROA_TUNCFG_CTRL_CNT (6467L)
+#define ROA_TUNCFG_DATA (6468L)
+#define ROA_TUNCFG_DATA_PUSH_TUNNEL (6469L)
+#define ROA_TUNCFG_DATA_RECIRCULATE (6470L)
+#define ROA_TUNCFG_DATA_RECIRC_BYPASS (6471L)
+#define ROA_TUNCFG_DATA_RECIRC_PORT (6472L)
+#define ROA_TUNCFG_DATA_TUN_IPCS_PRECALC (6473L)
+#define ROA_TUNCFG_DATA_TUN_IPCS_UPD (6474L)
+#define ROA_TUNCFG_DATA_TUN_IPTL_PRECALC (6475L)
+#define ROA_TUNCFG_DATA_TUN_IPTL_UPD (6476L)
+#define ROA_TUNCFG_DATA_TUN_IP_TYPE (6477L)
+#define ROA_TUNCFG_DATA_TUN_LEN (6478L)
+#define ROA_TUNCFG_DATA_TUN_TYPE (6479L)
+#define ROA_TUNCFG_DATA_TUN_VLAN (6480L)
+#define ROA_TUNCFG_DATA_TUN_VXLAN_UDP_LEN_UPD (6481L)
+#define ROA_TUNCFG_DATA_TX_LAG_IX (6482L)
+#define ROA_TUNHDR_CTRL (6483L)
+#define ROA_TUNHDR_CTRL_ADR (6484L)
+#define ROA_TUNHDR_CTRL_CNT (6485L)
+#define ROA_TUNHDR_DATA (6486L)
+#define ROA_TUNHDR_DATA_TUNNEL_HDR (6487L)
+/* RPL */
+#define RPL_EXT_CTRL (6488L)
+#define RPL_EXT_CTRL_ADR (6489L)
+#define RPL_EXT_CTRL_CNT (6490L)
+#define RPL_EXT_DATA (6491L)
+#define RPL_EXT_DATA_RPL_PTR (6492L)
+#define RPL_RCP_CTRL (6493L)
+#define RPL_RCP_CTRL_ADR (6494L)
+#define RPL_RCP_CTRL_CNT (6495L)
+#define RPL_RCP_DATA (6496L)
+#define RPL_RCP_DATA_DYN (6497L)
+#define RPL_RCP_DATA_EXT_PRIO (6498L)
+#define RPL_RCP_DATA_LEN (6499L)
+#define RPL_RCP_DATA_OFS (6500L)
+#define RPL_RCP_DATA_RPL_PTR (6501L)
+#define RPL_RPL_CTRL (6502L)
+#define RPL_RPL_CTRL_ADR (6503L)
+#define RPL_RPL_CTRL_CNT (6504L)
+#define RPL_RPL_DATA (6505L)
+#define RPL_RPL_DATA_VALUE (6506L)
+/* RPP_LR */
+#define RPP_LR_IFR_RCP_CTRL (6507L)
+#define RPP_LR_IFR_RCP_CTRL_ADR (6508L)
+#define RPP_LR_IFR_RCP_CTRL_CNT (6509L)
+#define RPP_LR_IFR_RCP_DATA (6510L)
+#define RPP_LR_IFR_RCP_DATA_EN (6511L)
+#define RPP_LR_IFR_RCP_DATA_MTU (6512L)
+#define RPP_LR_RCP_CTRL (6513L)
+#define RPP_LR_RCP_CTRL_ADR (6514L)
+#define RPP_LR_RCP_CTRL_CNT (6515L)
+#define RPP_LR_RCP_DATA (6516L)
+#define RPP_LR_RCP_DATA_EXP (6517L)
+/* RST7000 */
+#define RST7000_RST (6518L)
+#define RST7000_RST_SYS (6519L)
+/* RST7001 */
+#define RST7001_RST (6520L)
+#define RST7001_RST_SYS (6521L)
+/* RST9500 */
+#define RST9500_CTRL (6598L)
+#define RST9500_CTRL_PTP_MMCM_CLKSEL (6599L)
+#define RST9500_CTRL_TS_CLKSEL (6600L)
+#define RST9500_CTRL_TS_CLKSEL_OVERRIDE (6601L)
+#define RST9500_RST (6602L)
+#define RST9500_RST_DDR3 (6603L)
+#define RST9500_RST_DDR3_IDLY_MMCM (6604L)
+#define RST9500_RST_PERIPH (6605L)
+#define RST9500_RST_PHY10G_QPLL (6606L)
+#define RST9500_RST_PHY3S10G (6607L)
+#define RST9500_RST_PHY3S_MMCM (6608L)
+#define RST9500_RST_PTP (6609L)
+#define RST9500_RST_PTP_MMCM (6610L)
+#define RST9500_RST_RPP (6611L)
+#define RST9500_RST_SDC (6612L)
+#define RST9500_RST_SI5326 (6613L)
+#define RST9500_RST_SYS (6614L)
+#define RST9500_RST_TS (6615L)
+#define RST9500_RST_TS_MMCM (6616L)
+#define RST9500_RST_STAT (6617L)
+#define RST9500_RST_STAT_PCS_RESET_BY_SERDES (6618L)
+#define RST9500_STAT (6619L)
+#define RST9500_STAT_DDR3_IDLY_MMCM_LOCKED (6620L)
+#define RST9500_STAT_DDR3_MMCM_LOCKED (6621L)
+#define RST9500_STAT_DDR3_PLL_LOCKED (6622L)
+#define RST9500_STAT_PHY10G_QPLL_LOCK_0_1 (6623L)
+#define RST9500_STAT_PHY10G_QPLL_LOCK_2_3 (6624L)
+#define RST9500_STAT_PHY3S_MMCM_LOCKED (6625L)
+#define RST9500_STAT_PTP_MMCM_LOCKED (6626L)
+#define RST9500_STAT_SYNCE_MAIN_CLK_LOS (6627L)
+#define RST9500_STAT_SYS_MMCM_LOCKED (6628L)
+#define RST9500_STAT_TS_MMCM_LOCKED (6629L)
+#define RST9500_STICKY (6630L)
+#define RST9500_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6631L)
+#define RST9500_STICKY_DDR3_MMCM_UNLOCKED (6632L)
+#define RST9500_STICKY_DDR3_PLL_UNLOCKED (6633L)
+#define RST9500_STICKY_PHY10G_QPLL_UNLOCK_0_1 (6634L)
+#define RST9500_STICKY_PHY10G_QPLL_UNLOCK_2_3 (6635L)
+#define RST9500_STICKY_PHY3S_MMCM_UNLOCKED (6636L)
+#define RST9500_STICKY_PTP_MMCM_UNLOCKED (6637L)
+#define RST9500_STICKY_TS_MMCM_UNLOCKED (6638L)
+/* RST9501 */
+#define RST9501_CTRL (6639L)
+#define RST9501_CTRL_PTP_MMCM_CLKSEL (6640L)
+#define RST9501_CTRL_TS_CLKSEL (6641L)
+#define RST9501_CTRL_TS_CLKSEL_OVERRIDE (6642L)
+#define RST9501_RST (6643L)
+#define RST9501_RST_DDR3 (6644L)
+#define RST9501_RST_DDR3_IDLY_MMCM (6645L)
+#define RST9501_RST_PERIPH (6646L)
+#define RST9501_RST_PHY10G_QPLL (6647L)
+#define RST9501_RST_PHY3S10G (6648L)
+#define RST9501_RST_PHY3S_MMCM (6649L)
+#define RST9501_RST_PTP (6650L)
+#define RST9501_RST_PTP_MMCM (6651L)
+#define RST9501_RST_RPP (6652L)
+#define RST9501_RST_SDC (6653L)
+#define RST9501_RST_SI5326 (6654L)
+#define RST9501_RST_SYS (6655L)
+#define RST9501_RST_TS (6656L)
+#define RST9501_RST_TS_MMCM (6657L)
+#define RST9501_RST_STAT (6658L)
+#define RST9501_RST_STAT_PCS_RESET_BY_SERDES (6659L)
+#define RST9501_STAT (6660L)
+#define RST9501_STAT_DDR3_IDLY_MMCM_LOCKED (6661L)
+#define RST9501_STAT_DDR3_MMCM_LOCKED (6662L)
+#define RST9501_STAT_DDR3_PLL_LOCKED (6663L)
+#define RST9501_STAT_PHY10G_QPLL_LOCK_0_1 (6664L)
+#define RST9501_STAT_PHY10G_QPLL_LOCK_2_3 (6665L)
+#define RST9501_STAT_PHY3S_MMCM_LOCKED (6666L)
+#define RST9501_STAT_PTP_MMCM_LOCKED (6667L)
+#define RST9501_STAT_SYNCE_MAIN_CLK_LOS (6668L)
+#define RST9501_STAT_SYS_MMCM_LOCKED (6669L)
+#define RST9501_STAT_TS_MMCM_LOCKED (6670L)
+#define RST9501_STICKY (6671L)
+#define RST9501_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6672L)
+#define RST9501_STICKY_DDR3_MMCM_UNLOCKED (6673L)
+#define RST9501_STICKY_DDR3_PLL_UNLOCKED (6674L)
+#define RST9501_STICKY_PHY10G_QPLL_UNLOCK_0_1 (6675L)
+#define RST9501_STICKY_PHY10G_QPLL_UNLOCK_2_3 (6676L)
+#define RST9501_STICKY_PHY3S_MMCM_UNLOCKED (6677L)
+#define RST9501_STICKY_PTP_MMCM_UNLOCKED (6678L)
+#define RST9501_STICKY_TS_MMCM_UNLOCKED (6679L)
+/* RST9502 */
+#define RST9502_CTRL (6680L)
+#define RST9502_CTRL_PTP_MMCM_CLKSEL (6681L)
+#define RST9502_CTRL_TS_CLKSEL (6682L)
+#define RST9502_CTRL_TS_CLKSEL_OVERRIDE (6683L)
+#define RST9502_RST (6684L)
+#define RST9502_RST_DDR3 (6685L)
+#define RST9502_RST_DDR3_IDLY_MMCM (6686L)
+#define RST9502_RST_NSEB (6687L)
+#define RST9502_RST_PERIPH (6688L)
+#define RST9502_RST_PHY10G_QPLL (6689L)
+#define RST9502_RST_PHY3S10G (6690L)
+#define RST9502_RST_PHY3S_MMCM (6691L)
+#define RST9502_RST_PTP (6692L)
+#define RST9502_RST_PTP_MMCM (6693L)
+#define RST9502_RST_RPP (6694L)
+#define RST9502_RST_SDC (6695L)
+#define RST9502_RST_SI5326 (6696L)
+#define RST9502_RST_SYS (6697L)
+#define RST9502_RST_TS (6698L)
+#define RST9502_RST_TS_MMCM (6699L)
+#define RST9502_RST_STAT (6700L)
+#define RST9502_RST_STAT_PCS_RESET_BY_SERDES (6701L)
+#define RST9502_STAT (6702L)
+#define RST9502_STAT_DDR3_IDLY_MMCM_LOCKED (6703L)
+#define RST9502_STAT_DDR3_MMCM_LOCKED (6704L)
+#define RST9502_STAT_DDR3_PLL_LOCKED (6705L)
+#define RST9502_STAT_PHY10G_QPLL_LOCK_0_1 (6706L)
+#define RST9502_STAT_PHY10G_QPLL_LOCK_2_3 (6707L)
+#define RST9502_STAT_PHY3S_MMCM_LOCKED (6708L)
+#define RST9502_STAT_PTP_MMCM_LOCKED (6709L)
+#define RST9502_STAT_SYNCE_MAIN_CLK_LOS (6710L)
+#define RST9502_STAT_SYS_MMCM_LOCKED (6711L)
+#define RST9502_STAT_TS_MMCM_LOCKED (6712L)
+#define RST9502_STICKY (6713L)
+#define RST9502_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6714L)
+#define RST9502_STICKY_DDR3_MMCM_UNLOCKED (6715L)
+#define RST9502_STICKY_DDR3_PLL_UNLOCKED (6716L)
+#define RST9502_STICKY_PHY10G_QPLL_UNLOCK_0_1 (6717L)
+#define RST9502_STICKY_PHY10G_QPLL_UNLOCK_2_3 (6718L)
+#define RST9502_STICKY_PHY3S_MMCM_UNLOCKED (6719L)
+#define RST9502_STICKY_PTP_MMCM_UNLOCKED (6720L)
+#define RST9502_STICKY_TS_MMCM_UNLOCKED (6721L)
+/* RST9503 */
+#define RST9503_CTRL (6722L)
+#define RST9503_CTRL_PTP_MMCM_CLKSEL (6723L)
+#define RST9503_CTRL_TS_CLKSEL (6724L)
+#define RST9503_CTRL_TS_CLKSEL_OVERRIDE (6725L)
+#define RST9503_PORT_CLK_SEL (6726L)
+#define RST9503_PORT_CLK_SEL_PORT0 (6727L)
+#define RST9503_PORT_CLK_SEL_PORT1 (6728L)
+#define RST9503_RST (6729L)
+#define RST9503_RST_DDR3 (6730L)
+#define RST9503_RST_DDR3_IDLY_MMCM (6731L)
+#define RST9503_RST_MAC_RX (6732L)
+#define RST9503_RST_MAC_RX_MMCM (6733L)
+#define RST9503_RST_MAC_TX (6734L)
+#define RST9503_RST_NSEB (6735L)
+#define RST9503_RST_PCS_RX (6736L)
+#define RST9503_RST_PERIPH (6737L)
+#define RST9503_RST_PHY40G (6738L)
+#define RST9503_RST_PTP (6739L)
+#define RST9503_RST_PTP_MMCM (6740L)
+#define RST9503_RST_RPP (6741L)
+#define RST9503_RST_SDC (6742L)
+#define RST9503_RST_SERDES_RX (6743L)
+#define RST9503_RST_SERDES_TX (6744L)
+#define RST9503_RST_SI5326 (6745L)
+#define RST9503_RST_SYS (6746L)
+#define RST9503_RST_TS (6747L)
+#define RST9503_RST_TS_MMCM (6748L)
+#define RST9503_RST_STAT (6749L)
+#define RST9503_RST_STAT_PCS_RESET_BY_SERDES (6750L)
+#define RST9503_STAT (6751L)
+#define RST9503_STAT_DDR3_IDLY_MMCM_LOCKED (6752L)
+#define RST9503_STAT_DDR3_MMCM_LOCKED (6753L)
+#define RST9503_STAT_DDR3_PLL_LOCKED (6754L)
+#define RST9503_STAT_MAC_RX_MMCM_LOCKED (6755L)
+#define RST9503_STAT_PTP_MMCM_LOCKED (6756L)
+#define RST9503_STAT_SYNCE_MAIN_CLK_LOS (6757L)
+#define RST9503_STAT_SYS_MMCM_LOCKED (6758L)
+#define RST9503_STAT_TS_MMCM_LOCKED (6759L)
+#define RST9503_STICKY (6760L)
+#define RST9503_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6761L)
+#define RST9503_STICKY_DDR3_MMCM_UNLOCKED (6762L)
+#define RST9503_STICKY_DDR3_PLL_UNLOCKED (6763L)
+#define RST9503_STICKY_MAC_RX_MMCM_UNLOCKED (6764L)
+#define RST9503_STICKY_PTP_MMCM_UNLOCKED (6765L)
+#define RST9503_STICKY_TS_MMCM_UNLOCKED (6766L)
+/* RST9504 */
+#define RST9504_CTRL (6767L)
+#define RST9504_CTRL_PTP_MMCM_CLKSEL (6768L)
+#define RST9504_CTRL_TS_CLKSEL (6769L)
+#define RST9504_CTRL_TS_CLKSEL_OVERRIDE (6770L)
+#define RST9504_RST (6771L)
+#define RST9504_RST_DDR3 (6772L)
+#define RST9504_RST_DDR3_IDLY_MMCM (6773L)
+#define RST9504_RST_MAC_RX (6774L)
+#define RST9504_RST_MAC_RX_MMCM (6775L)
+#define RST9504_RST_MAC_TX (6776L)
+#define RST9504_RST_NSEB (6777L)
+#define RST9504_RST_PCS_RX (6778L)
+#define RST9504_RST_PERIPH (6779L)
+#define RST9504_RST_PHY100G (6780L)
+#define RST9504_RST_PTP (6781L)
+#define RST9504_RST_PTP_MMCM (6782L)
+#define RST9504_RST_RPP (6783L)
+#define RST9504_RST_SDC (6784L)
+#define RST9504_RST_SERDES_RX (6785L)
+#define RST9504_RST_SERDES_TX (6786L)
+#define RST9504_RST_SI5326 (6787L)
+#define RST9504_RST_SYS (6788L)
+#define RST9504_RST_TS (6789L)
+#define RST9504_RST_TS_MMCM (6790L)
+#define RST9504_RST_STAT (6791L)
+#define RST9504_RST_STAT_PCS_RESET_BY_SERDES (6792L)
+#define RST9504_STAT (6793L)
+#define RST9504_STAT_DDR3_IDLY_MMCM_LOCKED (6794L)
+#define RST9504_STAT_DDR3_MMCM_LOCKED (6795L)
+#define RST9504_STAT_DDR3_PLL_LOCKED (6796L)
+#define RST9504_STAT_MAC_RX_MMCM_LOCKED (6797L)
+#define RST9504_STAT_PTP_MMCM_LOCKED (6798L)
+#define RST9504_STAT_SYNCE_MAIN_CLK_LOS (6799L)
+#define RST9504_STAT_SYS_MMCM_LOCKED (6800L)
+#define RST9504_STAT_TS_MMCM_LOCKED (6801L)
+#define RST9504_STICKY (6802L)
+#define RST9504_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6803L)
+#define RST9504_STICKY_DDR3_MMCM_UNLOCKED (6804L)
+#define RST9504_STICKY_DDR3_PLL_UNLOCKED (6805L)
+#define RST9504_STICKY_MAC_RX_MMCM_UNLOCKED (6806L)
+#define RST9504_STICKY_PTP_MMCM_UNLOCKED (6807L)
+#define RST9504_STICKY_TS_MMCM_UNLOCKED (6808L)
+/* RST9505 */
+#define RST9505_CTRL (6809L)
+#define RST9505_CTRL_PTP_MMCM_CLKSEL (6810L)
+#define RST9505_CTRL_TS_CLKSEL (6811L)
+#define RST9505_CTRL_TS_CLKSEL_OVERRIDE (6812L)
+#define RST9505_RST (6813L)
+#define RST9505_RST_DDR3 (6814L)
+#define RST9505_RST_DDR3_IDLY_MMCM (6815L)
+#define RST9505_RST_MAC_RX (6816L)
+#define RST9505_RST_MAC_RX_MMCM (6817L)
+#define RST9505_RST_MAC_TX (6818L)
+#define RST9505_RST_NSEB (6819L)
+#define RST9505_RST_PCS_RX (6820L)
+#define RST9505_RST_PERIPH (6821L)
+#define RST9505_RST_PHY100G (6822L)
+#define RST9505_RST_PTP (6823L)
+#define RST9505_RST_PTP_MMCM (6824L)
+#define RST9505_RST_RPP (6825L)
+#define RST9505_RST_SDC (6826L)
+#define RST9505_RST_SERDES_RX (6827L)
+#define RST9505_RST_SERDES_TX (6828L)
+#define RST9505_RST_SI5326 (6829L)
+#define RST9505_RST_SYS (6830L)
+#define RST9505_RST_TS (6831L)
+#define RST9505_RST_TS_MMCM (6832L)
+#define RST9505_RST_STAT (6833L)
+#define RST9505_RST_STAT_PCS_RESET_BY_SERDES (6834L)
+#define RST9505_STAT (6835L)
+#define RST9505_STAT_DDR3_IDLY_MMCM_LOCKED (6836L)
+#define RST9505_STAT_DDR3_MMCM_LOCKED (6837L)
+#define RST9505_STAT_DDR3_PLL_LOCKED (6838L)
+#define RST9505_STAT_MAC_RX_MMCM_LOCKED (6839L)
+#define RST9505_STAT_PTP_MMCM_LOCKED (6840L)
+#define RST9505_STAT_SYNCE_MAIN_CLK_LOS (6841L)
+#define RST9505_STAT_SYS_MMCM_LOCKED (6842L)
+#define RST9505_STAT_TS_MMCM_LOCKED (6843L)
+#define RST9505_STICKY (6844L)
+#define RST9505_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6845L)
+#define RST9505_STICKY_DDR3_MMCM_UNLOCKED (6846L)
+#define RST9505_STICKY_DDR3_PLL_UNLOCKED (6847L)
+#define RST9505_STICKY_MAC_RX_MMCM_UNLOCKED (6848L)
+#define RST9505_STICKY_PTP_MMCM_UNLOCKED (6849L)
+#define RST9505_STICKY_TS_MMCM_UNLOCKED (6850L)
+/* RST9506 */
+/* RST9507 */
+/* RST9508 */
+#define RST9508_CTRL (6851L)
+#define RST9508_CTRL_PTP_MMCM_CLKSEL (6852L)
+#define RST9508_CTRL_TS_CLKSEL (6853L)
+#define RST9508_CTRL_TS_CLKSEL_OVERRIDE (6854L)
+#define RST9508_CTRL_TS_CLKSEL_REF (6855L)
+#define RST9508_POWER (6856L)
+#define RST9508_POWER_PU_NSEB (6857L)
+#define RST9508_POWER_PU_PHY (6858L)
+#define RST9508_RST (6859L)
+#define RST9508_RST_CORE_MMCM (6860L)
+#define RST9508_RST_DDR4 (6861L)
+#define RST9508_RST_MAC_RX (6862L)
+#define RST9508_RST_PERIPH (6863L)
+#define RST9508_RST_PHY (6864L)
+#define RST9508_RST_PTP (6865L)
+#define RST9508_RST_PTP_MMCM (6866L)
+#define RST9508_RST_RPP (6867L)
+#define RST9508_RST_SDC (6868L)
+#define RST9508_RST_SYS (6869L)
+#define RST9508_RST_SYS_MMCM (6870L)
+#define RST9508_RST_TMC (6871L)
+#define RST9508_RST_TS (6872L)
+#define RST9508_RST_TSM_REF_MMCM (6873L)
+#define RST9508_RST_TS_MMCM (6874L)
+#define RST9508_STAT (6875L)
+#define RST9508_STAT_CORE_MMCM_LOCKED (6876L)
+#define RST9508_STAT_DDR4_MMCM_LOCKED (6877L)
+#define RST9508_STAT_DDR4_PLL_LOCKED (6878L)
+#define RST9508_STAT_PCI_SYS_MMCM_LOCKED (6879L)
+#define RST9508_STAT_PTP_MMCM_LOCKED (6880L)
+#define RST9508_STAT_SYS_MMCM_LOCKED (6881L)
+#define RST9508_STAT_TSM_REF_MMCM_LOCKED (6882L)
+#define RST9508_STAT_TS_MMCM_LOCKED (6883L)
+#define RST9508_STICKY (6884L)
+#define RST9508_STICKY_CORE_MMCM_UNLOCKED (6885L)
+#define RST9508_STICKY_DDR4_MMCM_UNLOCKED (6886L)
+#define RST9508_STICKY_DDR4_PLL_UNLOCKED (6887L)
+#define RST9508_STICKY_PCI_SYS_MMCM_UNLOCKED (6888L)
+#define RST9508_STICKY_PTP_MMCM_UNLOCKED (6889L)
+#define RST9508_STICKY_SYS_MMCM_UNLOCKED (6890L)
+#define RST9508_STICKY_TSM_REF_MMCM_UNLOCKED (6891L)
+#define RST9508_STICKY_TS_MMCM_UNLOCKED (6892L)
+/* RST9509 */
+/* RST9510 */
+/* RST9512 */
+#define RST9512_CTRL (6893L)
+#define RST9512_CTRL_PTP_MMCM_CLKSEL (6894L)
+#define RST9512_CTRL_TS_CLKSEL (6895L)
+#define RST9512_CTRL_TS_CLKSEL_OVERRIDE (6896L)
+#define RST9512_CTRL_TS_CLKSEL_REF (6897L)
+#define RST9512_POWER (6898L)
+#define RST9512_POWER_PU_NSEB (6899L)
+#define RST9512_POWER_PU_PHY (6900L)
+#define RST9512_RST (6901L)
+#define RST9512_RST_CORE_MMCM (6902L)
+#define RST9512_RST_DDR4 (6903L)
+#define RST9512_RST_MAC_RX (6904L)
+#define RST9512_RST_MAC_TX (6905L)
+#define RST9512_RST_PCS_RX (6906L)
+#define RST9512_RST_PERIPH (6907L)
+#define RST9512_RST_PHY (6908L)
+#define RST9512_RST_PTP (6909L)
+#define RST9512_RST_PTP_MMCM (6910L)
+#define RST9512_RST_RPP (6911L)
+#define RST9512_RST_SDC (6912L)
+#define RST9512_RST_SERDES_RX (6913L)
+#define RST9512_RST_SERDES_RX_DATAPATH (6914L)
+#define RST9512_RST_SERDES_TX (6915L)
+#define RST9512_RST_SYS (6916L)
+#define RST9512_RST_SYS_MMCM (6917L)
+#define RST9512_RST_TS (6918L)
+#define RST9512_RST_TSM_REF_MMCM (6919L)
+#define RST9512_RST_TS_MMCM (6920L)
+#define RST9512_STAT (6921L)
+#define RST9512_STAT_CORE_MMCM_LOCKED (6922L)
+#define RST9512_STAT_DDR4_MMCM_LOCKED (6923L)
+#define RST9512_STAT_DDR4_PLL_LOCKED (6924L)
+#define RST9512_STAT_PCI_SYS_MMCM_LOCKED (6925L)
+#define RST9512_STAT_PTP_MMCM_LOCKED (6926L)
+#define RST9512_STAT_SYS_MMCM_LOCKED (6927L)
+#define RST9512_STAT_TSM_REF_MMCM_LOCKED (6928L)
+#define RST9512_STAT_TS_MMCM_LOCKED (6929L)
+#define RST9512_STICKY (6930L)
+#define RST9512_STICKY_CORE_MMCM_UNLOCKED (6931L)
+#define RST9512_STICKY_DDR4_MMCM_UNLOCKED (6932L)
+#define RST9512_STICKY_DDR4_PLL_UNLOCKED (6933L)
+#define RST9512_STICKY_PCI_SYS_MMCM_UNLOCKED (6934L)
+#define RST9512_STICKY_PTP_MMCM_UNLOCKED (6935L)
+#define RST9512_STICKY_SYS_MMCM_UNLOCKED (6936L)
+#define RST9512_STICKY_TSM_REF_MMCM_UNLOCKED (6937L)
+#define RST9512_STICKY_TS_MMCM_UNLOCKED (6938L)
+/* RST9513 */
+/* RST9515 */
+#define RST9515_CTRL (6939L)
+#define RST9515_CTRL_PTP_MMCM_CLKSEL (6940L)
+#define RST9515_CTRL_TS_CLKSEL (6941L)
+#define RST9515_CTRL_TS_CLKSEL_OVERRIDE (6942L)
+#define RST9515_CTRL_TS_CLKSEL_REF (6943L)
+#define RST9515_POWER (6944L)
+#define RST9515_POWER_PU_NSEB (6945L)
+#define RST9515_POWER_PU_PHY (6946L)
+#define RST9515_RST (6947L)
+#define RST9515_RST_CORE_MMCM (6948L)
+#define RST9515_RST_DDR4 (6949L)
+#define RST9515_RST_MAC_RX (6950L)
+#define RST9515_RST_PERIPH (6951L)
+#define RST9515_RST_PHY (6952L)
+#define RST9515_RST_PTP (6953L)
+#define RST9515_RST_PTP_MMCM (6954L)
+#define RST9515_RST_RPP (6955L)
+#define RST9515_RST_SDC (6956L)
+#define RST9515_RST_SYS (6957L)
+#define RST9515_RST_SYS_MMCM (6958L)
+#define RST9515_RST_TMC (6959L)
+#define RST9515_RST_TS (6960L)
+#define RST9515_RST_TSM_REF_MMCM (6961L)
+#define RST9515_RST_TS_MMCM (6962L)
+#define RST9515_STAT (6963L)
+#define RST9515_STAT_CORE_MMCM_LOCKED (6964L)
+#define RST9515_STAT_DDR4_MMCM_LOCKED (6965L)
+#define RST9515_STAT_DDR4_PLL_LOCKED (6966L)
+#define RST9515_STAT_PCI_SYS_MMCM_LOCKED (6967L)
+#define RST9515_STAT_PTP_MMCM_LOCKED (6968L)
+#define RST9515_STAT_SYS_MMCM_LOCKED (6969L)
+#define RST9515_STAT_TSM_REF_MMCM_LOCKED (6970L)
+#define RST9515_STAT_TS_MMCM_LOCKED (6971L)
+#define RST9515_STICKY (6972L)
+#define RST9515_STICKY_CORE_MMCM_UNLOCKED (6973L)
+#define RST9515_STICKY_DDR4_MMCM_UNLOCKED (6974L)
+#define RST9515_STICKY_DDR4_PLL_UNLOCKED (6975L)
+#define RST9515_STICKY_PCI_SYS_MMCM_UNLOCKED (6976L)
+#define RST9515_STICKY_PTP_MMCM_UNLOCKED (6977L)
+#define RST9515_STICKY_SYS_MMCM_UNLOCKED (6978L)
+#define RST9515_STICKY_TSM_REF_MMCM_UNLOCKED (6979L)
+#define RST9515_STICKY_TS_MMCM_UNLOCKED (6980L)
+/* RST9516 */
+#define RST9516_CTRL (6981L)
+#define RST9516_CTRL_PTP_MMCM_CLKSEL (6982L)
+#define RST9516_CTRL_TS_CLKSEL (6983L)
+#define RST9516_CTRL_TS_CLKSEL_OVERRIDE (6984L)
+#define RST9516_CTRL_TS_CLKSEL_REF (6985L)
+#define RST9516_POWER (6986L)
+#define RST9516_POWER_PU_NSEB (6987L)
+#define RST9516_POWER_PU_PHY (6988L)
+#define RST9516_RST (6989L)
+#define RST9516_RST_CORE_MMCM (6990L)
+#define RST9516_RST_DDR4 (6991L)
+#define RST9516_RST_MAC_RX (6992L)
+#define RST9516_RST_PCS_RX (6993L)
+#define RST9516_RST_PERIPH (6994L)
+#define RST9516_RST_PHY (6995L)
+#define RST9516_RST_PTP (6996L)
+#define RST9516_RST_PTP_MMCM (6997L)
+#define RST9516_RST_RPP (6998L)
+#define RST9516_RST_SDC (6999L)
+#define RST9516_RST_SERDES_RX (7000L)
+#define RST9516_RST_SERDES_TX (7001L)
+#define RST9516_RST_SYS (7002L)
+#define RST9516_RST_SYS_MMCM (7003L)
+#define RST9516_RST_TMC (7004L)
+#define RST9516_RST_TS (7005L)
+#define RST9516_RST_TSM_REF_MMCM (7006L)
+#define RST9516_RST_TS_MMCM (7007L)
+#define RST9516_STAT (7008L)
+#define RST9516_STAT_CORE_MMCM_LOCKED (7009L)
+#define RST9516_STAT_DDR4_MMCM_LOCKED (7010L)
+#define RST9516_STAT_DDR4_PLL_LOCKED (7011L)
+#define RST9516_STAT_PCI_SYS_MMCM_LOCKED (7012L)
+#define RST9516_STAT_PTP_MMCM_LOCKED (7013L)
+#define RST9516_STAT_SYS_MMCM_LOCKED (7014L)
+#define RST9516_STAT_TSM_REF_MMCM_LOCKED (7015L)
+#define RST9516_STAT_TS_MMCM_LOCKED (7016L)
+#define RST9516_STICKY (7017L)
+#define RST9516_STICKY_CORE_MMCM_UNLOCKED (7018L)
+#define RST9516_STICKY_DDR4_MMCM_UNLOCKED (7019L)
+#define RST9516_STICKY_DDR4_PLL_UNLOCKED (7020L)
+#define RST9516_STICKY_PCI_SYS_MMCM_UNLOCKED (7021L)
+#define RST9516_STICKY_PTP_MMCM_UNLOCKED (7022L)
+#define RST9516_STICKY_SYS_MMCM_UNLOCKED (7023L)
+#define RST9516_STICKY_TSM_REF_MMCM_UNLOCKED (7024L)
+#define RST9516_STICKY_TS_MMCM_UNLOCKED (7025L)
+/* RST9517 */
+#define RST9517_CTRL (7026L)
+#define RST9517_CTRL_PTP_MMCM_CLKSEL (7027L)
+#define RST9517_CTRL_TS_CLKSEL (7028L)
+#define RST9517_CTRL_TS_CLKSEL_OVERRIDE (7029L)
+#define RST9517_RST (7030L)
+#define RST9517_RST_DDR3 (7031L)
+#define RST9517_RST_DDR3_IDLY_MMCM (7032L)
+#define RST9517_RST_NSEB (7033L)
+#define RST9517_RST_PERIPH (7034L)
+#define RST9517_RST_PHY10G_QPLL (7035L)
+#define RST9517_RST_PHY3S10G (7036L)
+#define RST9517_RST_PHY3S_MMCM (7037L)
+#define RST9517_RST_PTP (7038L)
+#define RST9517_RST_PTP_MMCM (7039L)
+#define RST9517_RST_RPP (7040L)
+#define RST9517_RST_SDC (7041L)
+#define RST9517_RST_SI5326 (7042L)
+#define RST9517_RST_SYS (7043L)
+#define RST9517_RST_TS (7044L)
+#define RST9517_RST_TS_MMCM (7045L)
+#define RST9517_RST_STAT (7046L)
+#define RST9517_RST_STAT_PCS_RESET_BY_SERDES (7047L)
+#define RST9517_STAT (7048L)
+#define RST9517_STAT_DDR3_IDLY_MMCM_LOCKED (7049L)
+#define RST9517_STAT_DDR3_MMCM_LOCKED (7050L)
+#define RST9517_STAT_DDR3_PLL_LOCKED (7051L)
+#define RST9517_STAT_PHY10G_QPLL_LOCK_0_1 (7052L)
+#define RST9517_STAT_PHY10G_QPLL_LOCK_2_3 (7053L)
+#define RST9517_STAT_PHY3S_MMCM_LOCKED (7054L)
+#define RST9517_STAT_PTP_MMCM_LOCKED (7055L)
+#define RST9517_STAT_SYNCE_MAIN_CLK_LOS (7056L)
+#define RST9517_STAT_SYS_MMCM_LOCKED (7057L)
+#define RST9517_STAT_TS_MMCM_LOCKED (7058L)
+#define RST9517_STICKY (7059L)
+#define RST9517_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7060L)
+#define RST9517_STICKY_DDR3_MMCM_UNLOCKED (7061L)
+#define RST9517_STICKY_DDR3_PLL_UNLOCKED (7062L)
+#define RST9517_STICKY_PHY10G_QPLL_UNLOCK_0_1 (7063L)
+#define RST9517_STICKY_PHY10G_QPLL_UNLOCK_2_3 (7064L)
+#define RST9517_STICKY_PHY3S_MMCM_UNLOCKED (7065L)
+#define RST9517_STICKY_PTP_MMCM_UNLOCKED (7066L)
+#define RST9517_STICKY_TS_MMCM_UNLOCKED (7067L)
+/* RST9519 */
+#define RST9519_CTRL (7068L)
+#define RST9519_CTRL_PTP_MMCM_CLKSEL (7069L)
+#define RST9519_CTRL_TS_CLKSEL (7070L)
+#define RST9519_CTRL_TS_CLKSEL_OVERRIDE (7071L)
+#define RST9519_RST (7072L)
+#define RST9519_RST_DDR3 (7073L)
+#define RST9519_RST_DDR3_IDLY_MMCM (7074L)
+#define RST9519_RST_PERIPH (7075L)
+#define RST9519_RST_PHY10G (7076L)
+#define RST9519_RST_PHY10G_QPLL (7077L)
+#define RST9519_RST_PTP (7078L)
+#define RST9519_RST_PTP_MMCM (7079L)
+#define RST9519_RST_RPP (7080L)
+#define RST9519_RST_SDC (7081L)
+#define RST9519_RST_SI5326 (7082L)
+#define RST9519_RST_SYS (7083L)
+#define RST9519_RST_TS (7084L)
+#define RST9519_RST_TS_MMCM (7085L)
+#define RST9519_RST_STAT (7086L)
+#define RST9519_RST_STAT_PCS_RESET_BY_SERDES (7087L)
+#define RST9519_STAT (7088L)
+#define RST9519_STAT_DDR3_IDLY_MMCM_LOCKED (7089L)
+#define RST9519_STAT_DDR3_MMCM_LOCKED (7090L)
+#define RST9519_STAT_DDR3_PLL_LOCKED (7091L)
+#define RST9519_STAT_PHY10G_QPLL_LOCK (7092L)
+#define RST9519_STAT_PTP_MMCM_LOCKED (7093L)
+#define RST9519_STAT_SYNCE_MAIN_CLK_LOS (7094L)
+#define RST9519_STAT_SYS_MMCM_LOCKED (7095L)
+#define RST9519_STAT_TS_MMCM_LOCKED (7096L)
+#define RST9519_STICKY (7097L)
+#define RST9519_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7098L)
+#define RST9519_STICKY_DDR3_MMCM_UNLOCKED (7099L)
+#define RST9519_STICKY_DDR3_PLL_UNLOCKED (7100L)
+#define RST9519_STICKY_PHY10G_QPLL_UNLOCK (7101L)
+#define RST9519_STICKY_PTP_MMCM_UNLOCKED (7102L)
+#define RST9519_STICKY_TS_MMCM_UNLOCKED (7103L)
+/* RST9520 */
+/* RST9521 */
+#define RST9521_CTRL (7104L)
+#define RST9521_CTRL_PTP_MMCM_CLKSEL (7105L)
+#define RST9521_CTRL_TS_CLKSEL (7106L)
+#define RST9521_CTRL_TS_CLKSEL_OVERRIDE (7107L)
+#define RST9521_POWER (7108L)
+#define RST9521_POWER_PU_NSEB (7109L)
+#define RST9521_POWER_PU_PHY (7110L)
+#define RST9521_RST (7111L)
+#define RST9521_RST_CORE_MMCM (7112L)
+#define RST9521_RST_DDR4 (7113L)
+#define RST9521_RST_MAC_RX (7114L)
+#define RST9521_RST_PERIPH (7115L)
+#define RST9521_RST_PHY (7116L)
+#define RST9521_RST_PTP (7117L)
+#define RST9521_RST_PTP_MMCM (7118L)
+#define RST9521_RST_RPP (7119L)
+#define RST9521_RST_SDC (7120L)
+#define RST9521_RST_SYS (7121L)
+#define RST9521_RST_SYS_MMCM (7122L)
+#define RST9521_RST_TMC (7123L)
+#define RST9521_RST_TS (7124L)
+#define RST9521_RST_TSM_REF_MMCM (7125L)
+#define RST9521_RST_TS_MMCM (7126L)
+#define RST9521_STAT (7127L)
+#define RST9521_STAT_CORE_MMCM_LOCKED (7128L)
+#define RST9521_STAT_DDR4_MMCM_LOCKED (7129L)
+#define RST9521_STAT_DDR4_PLL_LOCKED (7130L)
+#define RST9521_STAT_PTP_MMCM_LOCKED (7131L)
+#define RST9521_STAT_SYS_MMCM_LOCKED (7132L)
+#define RST9521_STAT_TS_MMCM_LOCKED (7133L)
+#define RST9521_STICKY (7134L)
+#define RST9521_STICKY_CORE_MMCM_UNLOCKED (7135L)
+#define RST9521_STICKY_DDR4_MMCM_UNLOCKED (7136L)
+#define RST9521_STICKY_DDR4_PLL_UNLOCKED (7137L)
+#define RST9521_STICKY_PTP_MMCM_UNLOCKED (7138L)
+#define RST9521_STICKY_SYS_MMCM_UNLOCKED (7139L)
+#define RST9521_STICKY_TS_MMCM_UNLOCKED (7140L)
+/* RST9522 */
+#define RST9522_CTRL (7141L)
+#define RST9522_CTRL_PTP_MMCM_CLKSEL (7142L)
+#define RST9522_CTRL_TS_CLKSEL (7143L)
+#define RST9522_CTRL_TS_CLKSEL_OVERRIDE (7144L)
+#define RST9522_CTRL_TS_CLKSEL_REF (7145L)
+#define RST9522_POWER (7146L)
+#define RST9522_POWER_PU_NSEB (7147L)
+#define RST9522_POWER_PU_PHY (7148L)
+#define RST9522_RST (7149L)
+#define RST9522_RST_CORE_MMCM (7150L)
+#define RST9522_RST_DDR4 (7151L)
+#define RST9522_RST_PERIPH (7152L)
+#define RST9522_RST_PHY10G (7153L)
+#define RST9522_RST_PHY10G_QPLL (7154L)
+#define RST9522_RST_PTP (7155L)
+#define RST9522_RST_PTP_MMCM (7156L)
+#define RST9522_RST_RPP (7157L)
+#define RST9522_RST_SDC (7158L)
+#define RST9522_RST_SYS (7159L)
+#define RST9522_RST_SYS_MMCM (7160L)
+#define RST9522_RST_TS (7161L)
+#define RST9522_RST_TSM_REF_MMCM (7162L)
+#define RST9522_RST_TS_MMCM (7163L)
+#define RST9522_STAT (7164L)
+#define RST9522_STAT_CORE_MMCM_LOCKED (7165L)
+#define RST9522_STAT_DDR4_MMCM_LOCKED (7166L)
+#define RST9522_STAT_DDR4_PLL_LOCKED (7167L)
+#define RST9522_STAT_PCI_SYS_MMCM_LOCKED (7168L)
+#define RST9522_STAT_PHY10G_QPLL_LOCKED (7169L)
+#define RST9522_STAT_PTP_MMCM_LOCKED (7170L)
+#define RST9522_STAT_SYS_MMCM_LOCKED (7171L)
+#define RST9522_STAT_TSM_REF_MMCM_LOCKED (7172L)
+#define RST9522_STAT_TS_MMCM_LOCKED (7173L)
+#define RST9522_STICKY (7174L)
+#define RST9522_STICKY_CORE_MMCM_UNLOCKED (7175L)
+#define RST9522_STICKY_DDR4_MMCM_UNLOCKED (7176L)
+#define RST9522_STICKY_DDR4_PLL_UNLOCKED (7177L)
+#define RST9522_STICKY_PCI_SYS_MMCM_UNLOCKED (7178L)
+#define RST9522_STICKY_PHY10G_QPLL_UNLOCKED (7179L)
+#define RST9522_STICKY_PTP_MMCM_UNLOCKED (7180L)
+#define RST9522_STICKY_SYS_MMCM_UNLOCKED (7181L)
+#define RST9522_STICKY_TSM_REF_MMCM_UNLOCKED (7182L)
+#define RST9522_STICKY_TS_MMCM_UNLOCKED (7183L)
+/* RST9523 */
+/* RST9524 */
+#define RST9524_CTRL (7184L)
+#define RST9524_CTRL_PTP_MMCM_CLKSEL (7185L)
+#define RST9524_CTRL_TS_CLKSEL (7186L)
+#define RST9524_CTRL_TS_CLKSEL_OVERRIDE (7187L)
+#define RST9524_POWER (7188L)
+#define RST9524_POWER_PU_NSEB (7189L)
+#define RST9524_POWER_PU_PHY (7190L)
+#define RST9524_RST (7191L)
+#define RST9524_RST_CORE_MMCM (7192L)
+#define RST9524_RST_DDR4 (7193L)
+#define RST9524_RST_MAC_RX (7194L)
+#define RST9524_RST_PERIPH (7195L)
+#define RST9524_RST_PHY (7196L)
+#define RST9524_RST_PTP (7197L)
+#define RST9524_RST_PTP_MMCM (7198L)
+#define RST9524_RST_RPP (7199L)
+#define RST9524_RST_SDC (7200L)
+#define RST9524_RST_SYS (7201L)
+#define RST9524_RST_SYS_MMCM (7202L)
+#define RST9524_RST_TMC (7203L)
+#define RST9524_RST_TS (7204L)
+#define RST9524_RST_TS_MMCM (7205L)
+#define RST9524_STAT (7206L)
+#define RST9524_STAT_CORE_MMCM_LOCKED (7207L)
+#define RST9524_STAT_DDR4_MMCM_LOCKED (7208L)
+#define RST9524_STAT_DDR4_PLL_LOCKED (7209L)
+#define RST9524_STAT_PTP_MMCM_LOCKED (7210L)
+#define RST9524_STAT_SYS_MMCM_LOCKED (7211L)
+#define RST9524_STAT_TS_MMCM_LOCKED (7212L)
+#define RST9524_STICKY (7213L)
+#define RST9524_STICKY_CORE_MMCM_UNLOCKED (7214L)
+#define RST9524_STICKY_DDR4_MMCM_UNLOCKED (7215L)
+#define RST9524_STICKY_DDR4_PLL_UNLOCKED (7216L)
+#define RST9524_STICKY_PTP_MMCM_UNLOCKED (7217L)
+#define RST9524_STICKY_SYS_MMCM_UNLOCKED (7218L)
+#define RST9524_STICKY_TS_MMCM_UNLOCKED (7219L)
+/* RST9525 */
+#define RST9525_CTRL (7220L)
+#define RST9525_CTRL_PTP_MMCM_CLKSEL (7221L)
+#define RST9525_CTRL_TS_CLKSEL (7222L)
+#define RST9525_CTRL_TS_CLKSEL_OVERRIDE (7223L)
+#define RST9525_CTRL_TS_CLKSEL_REF (7224L)
+#define RST9525_POWER (7225L)
+#define RST9525_POWER_PU_NSEB (7226L)
+#define RST9525_POWER_PU_PHY (7227L)
+#define RST9525_RST (7228L)
+#define RST9525_RST_CORE_MMCM (7229L)
+#define RST9525_RST_DDR4 (7230L)
+#define RST9525_RST_MAC_RX (7231L)
+#define RST9525_RST_MAC_TX (7232L)
+#define RST9525_RST_PCS_RX (7233L)
+#define RST9525_RST_PERIPH (7234L)
+#define RST9525_RST_PHY (7235L)
+#define RST9525_RST_PTP (7236L)
+#define RST9525_RST_PTP_MMCM (7237L)
+#define RST9525_RST_RPP (7238L)
+#define RST9525_RST_SDC (7239L)
+#define RST9525_RST_SERDES_RX (7240L)
+#define RST9525_RST_SERDES_RX_DATAPATH (7241L)
+#define RST9525_RST_SERDES_TX (7242L)
+#define RST9525_RST_SYS (7243L)
+#define RST9525_RST_SYS_MMCM (7244L)
+#define RST9525_RST_TS (7245L)
+#define RST9525_RST_TSM_REF_MMCM (7246L)
+#define RST9525_RST_TS_MMCM (7247L)
+#define RST9525_STAT (7248L)
+#define RST9525_STAT_CORE_MMCM_LOCKED (7249L)
+#define RST9525_STAT_DDR4_MMCM_LOCKED (7250L)
+#define RST9525_STAT_DDR4_PLL_LOCKED (7251L)
+#define RST9525_STAT_PCI_SYS_MMCM_LOCKED (7252L)
+#define RST9525_STAT_PTP_MMCM_LOCKED (7253L)
+#define RST9525_STAT_SYS_MMCM_LOCKED (7254L)
+#define RST9525_STAT_TSM_REF_MMCM_LOCKED (7255L)
+#define RST9525_STAT_TS_MMCM_LOCKED (7256L)
+#define RST9525_STICKY (7257L)
+#define RST9525_STICKY_CORE_MMCM_UNLOCKED (7258L)
+#define RST9525_STICKY_DDR4_MMCM_UNLOCKED (7259L)
+#define RST9525_STICKY_DDR4_PLL_UNLOCKED (7260L)
+#define RST9525_STICKY_PCI_SYS_MMCM_UNLOCKED (7261L)
+#define RST9525_STICKY_PTP_MMCM_UNLOCKED (7262L)
+#define RST9525_STICKY_SYS_MMCM_UNLOCKED (7263L)
+#define RST9525_STICKY_TSM_REF_MMCM_UNLOCKED (7264L)
+#define RST9525_STICKY_TS_MMCM_UNLOCKED (7265L)
+/* RST9526 */
+#define RST9526_CTRL (7266L)
+#define RST9526_CTRL_PTP_MMCM_CLKSEL (7267L)
+#define RST9526_CTRL_TS_CLKSEL (7268L)
+#define RST9526_CTRL_TS_CLKSEL_OVERRIDE (7269L)
+#define RST9526_POWER (7270L)
+#define RST9526_POWER_PU_NSEB (7271L)
+#define RST9526_POWER_PU_PHY (7272L)
+#define RST9526_RST (7273L)
+#define RST9526_RST_CORE_MMCM (7274L)
+#define RST9526_RST_DDR4 (7275L)
+#define RST9526_RST_MAC_RX (7276L)
+#define RST9526_RST_MAC_TX (7277L)
+#define RST9526_RST_PCS_RX (7278L)
+#define RST9526_RST_PERIPH (7279L)
+#define RST9526_RST_PHY (7280L)
+#define RST9526_RST_PTP (7281L)
+#define RST9526_RST_PTP_MMCM (7282L)
+#define RST9526_RST_RPP (7283L)
+#define RST9526_RST_SDC (7284L)
+#define RST9526_RST_SERDES_RX (7285L)
+#define RST9526_RST_SERDES_RX_DATAPATH (7286L)
+#define RST9526_RST_SERDES_TX (7287L)
+#define RST9526_RST_SYS (7288L)
+#define RST9526_RST_SYS_MMCM (7289L)
+#define RST9526_RST_TMC (7290L)
+#define RST9526_RST_TS (7291L)
+#define RST9526_RST_TS_MMCM (7292L)
+#define RST9526_STAT (7293L)
+#define RST9526_STAT_CORE_MMCM_LOCKED (7294L)
+#define RST9526_STAT_DDR4_MMCM_LOCKED (7295L)
+#define RST9526_STAT_DDR4_PLL_LOCKED (7296L)
+#define RST9526_STAT_PTP_MMCM_LOCKED (7297L)
+#define RST9526_STAT_SYS_MMCM_LOCKED (7298L)
+#define RST9526_STAT_TS_MMCM_LOCKED (7299L)
+#define RST9526_STICKY (7300L)
+#define RST9526_STICKY_CORE_MMCM_UNLOCKED (7301L)
+#define RST9526_STICKY_DDR4_MMCM_UNLOCKED (7302L)
+#define RST9526_STICKY_DDR4_PLL_UNLOCKED (7303L)
+#define RST9526_STICKY_PTP_MMCM_UNLOCKED (7304L)
+#define RST9526_STICKY_SYS_MMCM_UNLOCKED (7305L)
+#define RST9526_STICKY_TS_MMCM_UNLOCKED (7306L)
+/* RST9527 */
+#define RST9527_CTRL (7307L)
+#define RST9527_CTRL_PTP_MMCM_CLKSEL (7308L)
+#define RST9527_CTRL_TS_CLKSEL (7309L)
+#define RST9527_CTRL_TS_CLKSEL_OVERRIDE (7310L)
+#define RST9527_POWER (7311L)
+#define RST9527_POWER_PU_NSEB (7312L)
+#define RST9527_POWER_PU_PHY (7313L)
+#define RST9527_RST (7314L)
+#define RST9527_RST_CORE_MMCM (7315L)
+#define RST9527_RST_DDR4 (7316L)
+#define RST9527_RST_MAC_RX (7317L)
+#define RST9527_RST_MAC_TX (7318L)
+#define RST9527_RST_PCS_RX (7319L)
+#define RST9527_RST_PERIPH (7320L)
+#define RST9527_RST_PHY (7321L)
+#define RST9527_RST_PTP (7322L)
+#define RST9527_RST_PTP_MMCM (7323L)
+#define RST9527_RST_RPP (7324L)
+#define RST9527_RST_SDC (7325L)
+#define RST9527_RST_SERDES_RX (7326L)
+#define RST9527_RST_SERDES_RX_DATAPATH (7327L)
+#define RST9527_RST_SERDES_TX (7328L)
+#define RST9527_RST_SYS (7329L)
+#define RST9527_RST_SYS_MMCM (7330L)
+#define RST9527_RST_TMC (7331L)
+#define RST9527_RST_TS (7332L)
+#define RST9527_RST_TS_MMCM (7333L)
+#define RST9527_STAT (7334L)
+#define RST9527_STAT_CORE_MMCM_LOCKED (7335L)
+#define RST9527_STAT_DDR4_MMCM_LOCKED (7336L)
+#define RST9527_STAT_DDR4_PLL_LOCKED (7337L)
+#define RST9527_STAT_PTP_MMCM_LOCKED (7338L)
+#define RST9527_STAT_SYS_MMCM_LOCKED (7339L)
+#define RST9527_STAT_TS_MMCM_LOCKED (7340L)
+#define RST9527_STICKY (7341L)
+#define RST9527_STICKY_CORE_MMCM_UNLOCKED (7342L)
+#define RST9527_STICKY_DDR4_MMCM_UNLOCKED (7343L)
+#define RST9527_STICKY_DDR4_PLL_UNLOCKED (7344L)
+#define RST9527_STICKY_PTP_MMCM_UNLOCKED (7345L)
+#define RST9527_STICKY_SYS_MMCM_UNLOCKED (7346L)
+#define RST9527_STICKY_TS_MMCM_UNLOCKED (7347L)
+/* RST9528 */
+/* RST9529 */
+#define RST9529_CTRL (7348L)
+#define RST9529_CTRL_PTP_MMCM_CLKSEL (7349L)
+#define RST9529_CTRL_TS_CLKSEL (7350L)
+#define RST9529_CTRL_TS_CLKSEL_OVERRIDE (7351L)
+#define RST9529_CTRL_TS_CLKSEL_REF (7352L)
+#define RST9529_POWER (7353L)
+#define RST9529_POWER_PU_NSEB (7354L)
+#define RST9529_POWER_PU_PHY (7355L)
+#define RST9529_RST (7356L)
+#define RST9529_RST_CORE_MMCM (7357L)
+#define RST9529_RST_DDR4 (7358L)
+#define RST9529_RST_PERIPH (7359L)
+#define RST9529_RST_PHY (7360L)
+#define RST9529_RST_PTP (7361L)
+#define RST9529_RST_PTP_MMCM (7362L)
+#define RST9529_RST_RPP (7363L)
+#define RST9529_RST_SDC (7364L)
+#define RST9529_RST_SYS (7365L)
+#define RST9529_RST_SYS_MMCM (7366L)
+#define RST9529_RST_TS (7367L)
+#define RST9529_RST_TSM_REF_MMCM (7368L)
+#define RST9529_RST_TS_MMCM (7369L)
+#define RST9529_STAT (7370L)
+#define RST9529_STAT_CORE_MMCM_LOCKED (7371L)
+#define RST9529_STAT_DDR4_MMCM_LOCKED (7372L)
+#define RST9529_STAT_DDR4_PLL_LOCKED (7373L)
+#define RST9529_STAT_PCI_SYS_MMCM_LOCKED (7374L)
+#define RST9529_STAT_PTP_MMCM_LOCKED (7375L)
+#define RST9529_STAT_SYS_MMCM_LOCKED (7376L)
+#define RST9529_STAT_TSM_REF_MMCM_LOCKED (7377L)
+#define RST9529_STAT_TS_MMCM_LOCKED (7378L)
+#define RST9529_STICKY (7379L)
+#define RST9529_STICKY_CORE_MMCM_UNLOCKED (7380L)
+#define RST9529_STICKY_DDR4_MMCM_UNLOCKED (7381L)
+#define RST9529_STICKY_DDR4_PLL_UNLOCKED (7382L)
+#define RST9529_STICKY_PCI_SYS_MMCM_UNLOCKED (7383L)
+#define RST9529_STICKY_PTP_MMCM_UNLOCKED (7384L)
+#define RST9529_STICKY_SYS_MMCM_UNLOCKED (7385L)
+#define RST9529_STICKY_TSM_REF_MMCM_UNLOCKED (7386L)
+#define RST9529_STICKY_TS_MMCM_UNLOCKED (7387L)
+/* RST9530 */
+#define RST9530_CTRL (7388L)
+#define RST9530_CTRL_PTP_MMCM_CLKSEL (7389L)
+#define RST9530_CTRL_TS_CLKSEL (7390L)
+#define RST9530_CTRL_TS_CLKSEL_OVERRIDE (7391L)
+#define RST9530_CTRL_TS_CLKSEL_REF (7392L)
+#define RST9530_POWER (7393L)
+#define RST9530_POWER_PU_NSEB (7394L)
+#define RST9530_POWER_PU_PHY (7395L)
+#define RST9530_RST (7396L)
+#define RST9530_RST_CORE_MMCM (7397L)
+#define RST9530_RST_DDR4 (7398L)
+#define RST9530_RST_NFV_OVS (7399L)
+#define RST9530_RST_PERIPH (7400L)
+#define RST9530_RST_PHY (7401L)
+#define RST9530_RST_PTP (7402L)
+#define RST9530_RST_PTP_MMCM (7403L)
+#define RST9530_RST_RPP (7404L)
+#define RST9530_RST_SDC (7405L)
+#define RST9530_RST_SYS (7406L)
+#define RST9530_RST_SYS_MMCM (7407L)
+#define RST9530_RST_TMC (7408L)
+#define RST9530_RST_TS (7409L)
+#define RST9530_RST_TSM_REF_MMCM (7410L)
+#define RST9530_RST_TS_MMCM (7411L)
+#define RST9530_STAT (7412L)
+#define RST9530_STAT_CORE_MMCM_LOCKED (7413L)
+#define RST9530_STAT_DDR4_MMCM_LOCKED (7414L)
+#define RST9530_STAT_DDR4_PLL_LOCKED (7415L)
+#define RST9530_STAT_PTP_MMCM_LOCKED (7416L)
+#define RST9530_STAT_SYS_MMCM_LOCKED (7417L)
+#define RST9530_STAT_TSM_REF_MMCM_LOCKED (7418L)
+#define RST9530_STAT_TS_MMCM_LOCKED (7419L)
+#define RST9530_STICKY (7420L)
+#define RST9530_STICKY_CORE_MMCM_UNLOCKED (7421L)
+#define RST9530_STICKY_DDR4_MMCM_UNLOCKED (7422L)
+#define RST9530_STICKY_DDR4_PLL_UNLOCKED (7423L)
+#define RST9530_STICKY_PCI_SYS_MMCM_UNLOCKED (7424L)
+#define RST9530_STICKY_PTP_MMCM_UNLOCKED (7425L)
+#define RST9530_STICKY_SYS_MMCM_UNLOCKED (7426L)
+#define RST9530_STICKY_TSM_REF_MMCM_UNLOCKED (7427L)
+#define RST9530_STICKY_TS_MMCM_UNLOCKED (7428L)
+/* RST9531 */
+#define RST9531_CTRL (7429L)
+#define RST9531_CTRL_PTP_MMCM_CLKSEL (7430L)
+#define RST9531_CTRL_TS_CLKSEL (7431L)
+#define RST9531_CTRL_TS_CLKSEL_OVERRIDE (7432L)
+#define RST9531_CTRL_TS_CLKSEL_REF (7433L)
+#define RST9531_POWER (7434L)
+#define RST9531_POWER_PU_NSEB (7435L)
+#define RST9531_POWER_PU_PHY (7436L)
+#define RST9531_RST (7437L)
+#define RST9531_RST_CORE_MMCM (7438L)
+#define RST9531_RST_DDR4 (7439L)
+#define RST9531_RST_PERIPH (7440L)
+#define RST9531_RST_PHY (7441L)
+#define RST9531_RST_PTP (7442L)
+#define RST9531_RST_PTP_MMCM (7443L)
+#define RST9531_RST_RPP (7444L)
+#define RST9531_RST_SDC (7445L)
+#define RST9531_RST_SYS (7446L)
+#define RST9531_RST_SYS_MMCM (7447L)
+#define RST9531_RST_TS (7448L)
+#define RST9531_RST_TSM_REF_MMCM (7449L)
+#define RST9531_RST_TS_MMCM (7450L)
+#define RST9531_STAT (7451L)
+#define RST9531_STAT_CORE_MMCM_LOCKED (7452L)
+#define RST9531_STAT_DDR4_MMCM_LOCKED (7453L)
+#define RST9531_STAT_DDR4_PLL_LOCKED (7454L)
+#define RST9531_STAT_PCI_SYS_MMCM_LOCKED (7455L)
+#define RST9531_STAT_PTP_MMCM_LOCKED (7456L)
+#define RST9531_STAT_SYS_MMCM_LOCKED (7457L)
+#define RST9531_STAT_TSM_REF_MMCM_LOCKED (7458L)
+#define RST9531_STAT_TS_MMCM_LOCKED (7459L)
+#define RST9531_STICKY (7460L)
+#define RST9531_STICKY_CORE_MMCM_UNLOCKED (7461L)
+#define RST9531_STICKY_DDR4_MMCM_UNLOCKED (7462L)
+#define RST9531_STICKY_DDR4_PLL_UNLOCKED (7463L)
+#define RST9531_STICKY_PCI_SYS_MMCM_UNLOCKED (7464L)
+#define RST9531_STICKY_PTP_MMCM_UNLOCKED (7465L)
+#define RST9531_STICKY_SYS_MMCM_UNLOCKED (7466L)
+#define RST9531_STICKY_TSM_REF_MMCM_UNLOCKED (7467L)
+#define RST9531_STICKY_TS_MMCM_UNLOCKED (7468L)
+/* RST9532 */
+#define RST9532_CTRL (7469L)
+#define RST9532_CTRL_PTP_MMCM_CLKSEL (7470L)
+#define RST9532_CTRL_TS_CLKSEL (7471L)
+#define RST9532_CTRL_TS_CLKSEL_OVERRIDE (7472L)
+#define RST9532_POWER (7473L)
+#define RST9532_POWER_PU_NSEB (7474L)
+#define RST9532_POWER_PU_PHY (7475L)
+#define RST9532_RST (7476L)
+#define RST9532_RST_CORE_MMCM (7477L)
+#define RST9532_RST_DDR4 (7478L)
+#define RST9532_RST_PERIPH (7479L)
+#define RST9532_RST_PHY (7480L)
+#define RST9532_RST_PTP (7481L)
+#define RST9532_RST_PTP_MMCM (7482L)
+#define RST9532_RST_RPP (7483L)
+#define RST9532_RST_SDC (7484L)
+#define RST9532_RST_SYS (7485L)
+#define RST9532_RST_SYS_MMCM (7486L)
+#define RST9532_RST_TMC (7487L)
+#define RST9532_RST_TS (7488L)
+#define RST9532_RST_TS_MMCM (7489L)
+#define RST9532_STAT (7490L)
+#define RST9532_STAT_CORE_MMCM_LOCKED (7491L)
+#define RST9532_STAT_DDR4_MMCM_LOCKED (7492L)
+#define RST9532_STAT_DDR4_PLL_LOCKED (7493L)
+#define RST9532_STAT_PTP_MMCM_LOCKED (7494L)
+#define RST9532_STAT_SYS_MMCM_LOCKED (7495L)
+#define RST9532_STAT_TS_MMCM_LOCKED (7496L)
+#define RST9532_STICKY (7497L)
+#define RST9532_STICKY_CORE_MMCM_UNLOCKED (7498L)
+#define RST9532_STICKY_DDR4_MMCM_UNLOCKED (7499L)
+#define RST9532_STICKY_DDR4_PLL_UNLOCKED (7500L)
+#define RST9532_STICKY_PTP_MMCM_UNLOCKED (7501L)
+#define RST9532_STICKY_SYS_MMCM_UNLOCKED (7502L)
+#define RST9532_STICKY_TS_MMCM_UNLOCKED (7503L)
+/* RST9533 */
+#define RST9533_CTRL (7504L)
+#define RST9533_CTRL_PTP_MMCM_CLKSEL (7505L)
+#define RST9533_CTRL_TS_CLKSEL (7506L)
+#define RST9533_CTRL_TS_CLKSEL_OVERRIDE (7507L)
+#define RST9533_POWER (7508L)
+#define RST9533_POWER_PU_NSEB (7509L)
+#define RST9533_POWER_PU_PHY (7510L)
+#define RST9533_RST (7511L)
+#define RST9533_RST_CORE_MMCM (7512L)
+#define RST9533_RST_DDR4 (7513L)
+#define RST9533_RST_PERIPH (7514L)
+#define RST9533_RST_PHY (7515L)
+#define RST9533_RST_PTP (7516L)
+#define RST9533_RST_PTP_MMCM (7517L)
+#define RST9533_RST_RPP (7518L)
+#define RST9533_RST_SDC (7519L)
+#define RST9533_RST_SYS (7520L)
+#define RST9533_RST_SYS_MMCM (7521L)
+#define RST9533_RST_TMC (7522L)
+#define RST9533_RST_TS (7523L)
+#define RST9533_RST_TS_MMCM (7524L)
+#define RST9533_STAT (7525L)
+#define RST9533_STAT_CORE_MMCM_LOCKED (7526L)
+#define RST9533_STAT_DDR4_MMCM_LOCKED (7527L)
+#define RST9533_STAT_DDR4_PLL_LOCKED (7528L)
+#define RST9533_STAT_PTP_MMCM_LOCKED (7529L)
+#define RST9533_STAT_SYS_MMCM_LOCKED (7530L)
+#define RST9533_STAT_TS_MMCM_LOCKED (7531L)
+#define RST9533_STICKY (7532L)
+#define RST9533_STICKY_CORE_MMCM_UNLOCKED (7533L)
+#define RST9533_STICKY_DDR4_MMCM_UNLOCKED (7534L)
+#define RST9533_STICKY_DDR4_PLL_UNLOCKED (7535L)
+#define RST9533_STICKY_PTP_MMCM_UNLOCKED (7536L)
+#define RST9533_STICKY_SYS_MMCM_UNLOCKED (7537L)
+#define RST9533_STICKY_TS_MMCM_UNLOCKED (7538L)
+/* RST9534 */
+#define RST9534_CTRL (7539L)
+#define RST9534_CTRL_PTP_MMCM_CLKSEL (7540L)
+#define RST9534_CTRL_TS_CLKSEL (7541L)
+#define RST9534_CTRL_TS_CLKSEL_OVERRIDE (7542L)
+#define RST9534_POWER (7543L)
+#define RST9534_POWER_PU_NSEB (7544L)
+#define RST9534_POWER_PU_PHY (7545L)
+#define RST9534_RST (7546L)
+#define RST9534_RST_CORE_MMCM (7547L)
+#define RST9534_RST_DDR4 (7548L)
+#define RST9534_RST_PERIPH (7549L)
+#define RST9534_RST_PHY (7550L)
+#define RST9534_RST_PTP (7551L)
+#define RST9534_RST_PTP_MMCM (7552L)
+#define RST9534_RST_RPP (7553L)
+#define RST9534_RST_SDC (7554L)
+#define RST9534_RST_SYS (7555L)
+#define RST9534_RST_SYS_MMCM (7556L)
+#define RST9534_RST_TMC (7557L)
+#define RST9534_RST_TS (7558L)
+#define RST9534_RST_TS_MMCM (7559L)
+#define RST9534_STAT (7560L)
+#define RST9534_STAT_CORE_MMCM_LOCKED (7561L)
+#define RST9534_STAT_DDR4_MMCM_LOCKED (7562L)
+#define RST9534_STAT_DDR4_PLL_LOCKED (7563L)
+#define RST9534_STAT_PTP_MMCM_LOCKED (7564L)
+#define RST9534_STAT_SYS_MMCM_LOCKED (7565L)
+#define RST9534_STAT_TS_MMCM_LOCKED (7566L)
+#define RST9534_STICKY (7567L)
+#define RST9534_STICKY_CORE_MMCM_UNLOCKED (7568L)
+#define RST9534_STICKY_DDR4_MMCM_UNLOCKED (7569L)
+#define RST9534_STICKY_DDR4_PLL_UNLOCKED (7570L)
+#define RST9534_STICKY_PTP_MMCM_UNLOCKED (7571L)
+#define RST9534_STICKY_SYS_MMCM_UNLOCKED (7572L)
+#define RST9534_STICKY_TS_MMCM_UNLOCKED (7573L)
+/* RST9535 */
+#define RST9535_CTRL (7574L)
+#define RST9535_CTRL_PTP_MMCM_CLKSEL (7575L)
+#define RST9535_CTRL_TS_CLKSEL (7576L)
+#define RST9535_CTRL_TS_CLKSEL_OVERRIDE (7577L)
+#define RST9535_POWER (7578L)
+#define RST9535_POWER_PU_NSEB (7579L)
+#define RST9535_POWER_PU_PHY (7580L)
+#define RST9535_RST (7581L)
+#define RST9535_RST_CORE_MMCM (7582L)
+#define RST9535_RST_DDR4 (7583L)
+#define RST9535_RST_MAC_RX (7584L)
+#define RST9535_RST_MAC_TX (7585L)
+#define RST9535_RST_PCS_RX (7586L)
+#define RST9535_RST_PERIPH (7587L)
+#define RST9535_RST_PHY (7588L)
+#define RST9535_RST_PTP (7589L)
+#define RST9535_RST_PTP_MMCM (7590L)
+#define RST9535_RST_RPP (7591L)
+#define RST9535_RST_SDC (7592L)
+#define RST9535_RST_SERDES_RX (7593L)
+#define RST9535_RST_SERDES_RX_DATAPATH (7594L)
+#define RST9535_RST_SERDES_TX (7595L)
+#define RST9535_RST_SYS (7596L)
+#define RST9535_RST_SYS_MMCM (7597L)
+#define RST9535_RST_TMC (7598L)
+#define RST9535_RST_TS (7599L)
+#define RST9535_RST_TS_MMCM (7600L)
+#define RST9535_STAT (7601L)
+#define RST9535_STAT_CORE_MMCM_LOCKED (7602L)
+#define RST9535_STAT_DDR4_MMCM_LOCKED (7603L)
+#define RST9535_STAT_DDR4_PLL_LOCKED (7604L)
+#define RST9535_STAT_PTP_MMCM_LOCKED (7605L)
+#define RST9535_STAT_SYS_MMCM_LOCKED (7606L)
+#define RST9535_STAT_TS_MMCM_LOCKED (7607L)
+#define RST9535_STICKY (7608L)
+#define RST9535_STICKY_CORE_MMCM_UNLOCKED (7609L)
+#define RST9535_STICKY_DDR4_MMCM_UNLOCKED (7610L)
+#define RST9535_STICKY_DDR4_PLL_UNLOCKED (7611L)
+#define RST9535_STICKY_PTP_MMCM_UNLOCKED (7612L)
+#define RST9535_STICKY_SYS_MMCM_UNLOCKED (7613L)
+#define RST9535_STICKY_TS_MMCM_UNLOCKED (7614L)
+/* RST9536 */
+#define RST9536_CTRL (7615L)
+#define RST9536_CTRL_PTP_MMCM_CLKSEL (7616L)
+#define RST9536_CTRL_TS_CLKSEL (7617L)
+#define RST9536_CTRL_TS_CLKSEL_OVERRIDE (7618L)
+#define RST9536_POWER (7619L)
+#define RST9536_POWER_PU_NSEB (7620L)
+#define RST9536_POWER_PU_PHY (7621L)
+#define RST9536_RST (7622L)
+#define RST9536_RST_CORE_MMCM (7623L)
+#define RST9536_RST_DDR4 (7624L)
+#define RST9536_RST_MAC_RX (7625L)
+#define RST9536_RST_PERIPH (7626L)
+#define RST9536_RST_PHY (7627L)
+#define RST9536_RST_PTP (7628L)
+#define RST9536_RST_PTP_MMCM (7629L)
+#define RST9536_RST_RPP (7630L)
+#define RST9536_RST_SDC (7631L)
+#define RST9536_RST_SYS (7632L)
+#define RST9536_RST_SYS_MMCM (7633L)
+#define RST9536_RST_TMC (7634L)
+#define RST9536_RST_TS (7635L)
+#define RST9536_RST_TS_MMCM (7636L)
+#define RST9536_STAT (7637L)
+#define RST9536_STAT_CORE_MMCM_LOCKED (7638L)
+#define RST9536_STAT_DDR4_MMCM_LOCKED (7639L)
+#define RST9536_STAT_DDR4_PLL_LOCKED (7640L)
+#define RST9536_STAT_PTP_MMCM_LOCKED (7641L)
+#define RST9536_STAT_SYS_MMCM_LOCKED (7642L)
+#define RST9536_STAT_TS_MMCM_LOCKED (7643L)
+#define RST9536_STICKY (7644L)
+#define RST9536_STICKY_CORE_MMCM_UNLOCKED (7645L)
+#define RST9536_STICKY_DDR4_MMCM_UNLOCKED (7646L)
+#define RST9536_STICKY_DDR4_PLL_UNLOCKED (7647L)
+#define RST9536_STICKY_PTP_MMCM_UNLOCKED (7648L)
+#define RST9536_STICKY_SYS_MMCM_UNLOCKED (7649L)
+#define RST9536_STICKY_TS_MMCM_UNLOCKED (7650L)
+/* RST9537 */
+#define RST9537_CTRL (7651L)
+#define RST9537_CTRL_PTP_MMCM_CLKSEL (7652L)
+#define RST9537_CTRL_TS_CLKSEL (7653L)
+#define RST9537_CTRL_TS_CLKSEL_OVERRIDE (7654L)
+#define RST9537_RST (7655L)
+#define RST9537_RST_DDR3 (7656L)
+#define RST9537_RST_DDR3_IDLY_MMCM (7657L)
+#define RST9537_RST_NSEB (7658L)
+#define RST9537_RST_PERIPH (7659L)
+#define RST9537_RST_PHY10G_QPLL (7660L)
+#define RST9537_RST_PHY3S10G (7661L)
+#define RST9537_RST_PHY3S_MMCM (7662L)
+#define RST9537_RST_PTP (7663L)
+#define RST9537_RST_PTP_MMCM (7664L)
+#define RST9537_RST_RPP (7665L)
+#define RST9537_RST_SDC (7666L)
+#define RST9537_RST_SI5326 (7667L)
+#define RST9537_RST_SYS (7668L)
+#define RST9537_RST_TS (7669L)
+#define RST9537_RST_TS_MMCM (7670L)
+#define RST9537_RST_STAT (7671L)
+#define RST9537_RST_STAT_PCS_RESET_BY_SERDES (7672L)
+#define RST9537_STAT (7673L)
+#define RST9537_STAT_DDR3_IDLY_MMCM_LOCKED (7674L)
+#define RST9537_STAT_DDR3_MMCM_LOCKED (7675L)
+#define RST9537_STAT_DDR3_PLL_LOCKED (7676L)
+#define RST9537_STAT_PHY10G_QPLL_LOCK_0_1 (7677L)
+#define RST9537_STAT_PHY10G_QPLL_LOCK_2_3 (7678L)
+#define RST9537_STAT_PHY3S_MMCM_LOCKED (7679L)
+#define RST9537_STAT_PTP_MMCM_LOCKED (7680L)
+#define RST9537_STAT_SYNCE_MAIN_CLK_LOS (7681L)
+#define RST9537_STAT_SYS_MMCM_LOCKED (7682L)
+#define RST9537_STAT_TS_MMCM_LOCKED (7683L)
+#define RST9537_STICKY (7684L)
+#define RST9537_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7685L)
+#define RST9537_STICKY_DDR3_MMCM_UNLOCKED (7686L)
+#define RST9537_STICKY_DDR3_PLL_UNLOCKED (7687L)
+#define RST9537_STICKY_PHY10G_QPLL_UNLOCK_0_1 (7688L)
+#define RST9537_STICKY_PHY10G_QPLL_UNLOCK_2_3 (7689L)
+#define RST9537_STICKY_PHY3S_MMCM_UNLOCKED (7690L)
+#define RST9537_STICKY_PTP_MMCM_UNLOCKED (7691L)
+#define RST9537_STICKY_TS_MMCM_UNLOCKED (7692L)
+/* RST9538 */
+#define RST9538_CTRL (7693L)
+#define RST9538_CTRL_PTP_MMCM_CLKSEL (7694L)
+#define RST9538_CTRL_TS_CLKSEL (7695L)
+#define RST9538_CTRL_TS_CLKSEL_OVERRIDE (7696L)
+#define RST9538_RST (7697L)
+#define RST9538_RST_DDR3 (7698L)
+#define RST9538_RST_DDR3_IDLY_MMCM (7699L)
+#define RST9538_RST_NSEB (7700L)
+#define RST9538_RST_PERIPH (7701L)
+#define RST9538_RST_PHY10G_QPLL (7702L)
+#define RST9538_RST_PHY3S10G (7703L)
+#define RST9538_RST_PHY3S_MMCM (7704L)
+#define RST9538_RST_PTP (7705L)
+#define RST9538_RST_PTP_MMCM (7706L)
+#define RST9538_RST_RPP (7707L)
+#define RST9538_RST_SDC (7708L)
+#define RST9538_RST_SI5326 (7709L)
+#define RST9538_RST_SYS (7710L)
+#define RST9538_RST_TS (7711L)
+#define RST9538_RST_TS_MMCM (7712L)
+#define RST9538_RST_STAT (7713L)
+#define RST9538_RST_STAT_PCS_RESET_BY_SERDES (7714L)
+#define RST9538_STAT (7715L)
+#define RST9538_STAT_DDR3_IDLY_MMCM_LOCKED (7716L)
+#define RST9538_STAT_DDR3_MMCM_LOCKED (7717L)
+#define RST9538_STAT_DDR3_PLL_LOCKED (7718L)
+#define RST9538_STAT_PHY10G_QPLL_LOCK_0_1 (7719L)
+#define RST9538_STAT_PHY10G_QPLL_LOCK_2_3 (7720L)
+#define RST9538_STAT_PHY3S_MMCM_LOCKED (7721L)
+#define RST9538_STAT_PTP_MMCM_LOCKED (7722L)
+#define RST9538_STAT_SYNCE_MAIN_CLK_LOS (7723L)
+#define RST9538_STAT_SYS_MMCM_LOCKED (7724L)
+#define RST9538_STAT_TS_MMCM_LOCKED (7725L)
+#define RST9538_STICKY (7726L)
+#define RST9538_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7727L)
+#define RST9538_STICKY_DDR3_MMCM_UNLOCKED (7728L)
+#define RST9538_STICKY_DDR3_PLL_UNLOCKED (7729L)
+#define RST9538_STICKY_PHY10G_QPLL_UNLOCK_0_1 (7730L)
+#define RST9538_STICKY_PHY10G_QPLL_UNLOCK_2_3 (7731L)
+#define RST9538_STICKY_PHY3S_MMCM_UNLOCKED (7732L)
+#define RST9538_STICKY_PTP_MMCM_UNLOCKED (7733L)
+#define RST9538_STICKY_TS_MMCM_UNLOCKED (7734L)
+/* RST9539 */
+#define RST9539_CTRL (7735L)
+#define RST9539_CTRL_PTP_MMCM_CLKSEL (7736L)
+#define RST9539_CTRL_TS_CLKSEL (7737L)
+#define RST9539_CTRL_TS_CLKSEL_OVERRIDE (7738L)
+#define RST9539_POWER (7739L)
+#define RST9539_POWER_PU_NSEB (7740L)
+#define RST9539_POWER_PU_PHY (7741L)
+#define RST9539_RST (7742L)
+#define RST9539_RST_CORE_MMCM (7743L)
+#define RST9539_RST_DDR4 (7744L)
+#define RST9539_RST_PERIPH (7745L)
+#define RST9539_RST_PHY (7746L)
+#define RST9539_RST_PTP (7747L)
+#define RST9539_RST_PTP_MMCM (7748L)
+#define RST9539_RST_RPP (7749L)
+#define RST9539_RST_SDC (7750L)
+#define RST9539_RST_SYS (7751L)
+#define RST9539_RST_SYS_MMCM (7752L)
+#define RST9539_RST_TMC (7753L)
+#define RST9539_RST_TS (7754L)
+#define RST9539_RST_TS_MMCM (7755L)
+#define RST9539_STAT (7756L)
+#define RST9539_STAT_CORE_MMCM_LOCKED (7757L)
+#define RST9539_STAT_DDR4_MMCM_LOCKED (7758L)
+#define RST9539_STAT_DDR4_PLL_LOCKED (7759L)
+#define RST9539_STAT_PTP_MMCM_LOCKED (7760L)
+#define RST9539_STAT_SYS_MMCM_LOCKED (7761L)
+#define RST9539_STAT_TS_MMCM_LOCKED (7762L)
+#define RST9539_STICKY (7763L)
+#define RST9539_STICKY_CORE_MMCM_UNLOCKED (7764L)
+#define RST9539_STICKY_DDR4_MMCM_UNLOCKED (7765L)
+#define RST9539_STICKY_DDR4_PLL_UNLOCKED (7766L)
+#define RST9539_STICKY_PTP_MMCM_UNLOCKED (7767L)
+#define RST9539_STICKY_SYS_MMCM_UNLOCKED (7768L)
+#define RST9539_STICKY_TS_MMCM_UNLOCKED (7769L)
+/* RST9540 */
+#define RST9540_CTRL (7770L)
+#define RST9540_CTRL_PTP_MMCM_CLKSEL (7771L)
+#define RST9540_CTRL_TS_CLKSEL (7772L)
+#define RST9540_CTRL_TS_CLKSEL_OVERRIDE (7773L)
+#define RST9540_POWER (7774L)
+#define RST9540_POWER_PU_NSEB (7775L)
+#define RST9540_POWER_PU_PHY (7776L)
+#define RST9540_RST (7777L)
+#define RST9540_RST_CORE_MMCM (7778L)
+#define RST9540_RST_DDR4 (7779L)
+#define RST9540_RST_MAC_RX (7780L)
+#define RST9540_RST_MAC_TX (7781L)
+#define RST9540_RST_PCS_RX (7782L)
+#define RST9540_RST_PERIPH (7783L)
+#define RST9540_RST_PHY (7784L)
+#define RST9540_RST_PTP (7785L)
+#define RST9540_RST_PTP_MMCM (7786L)
+#define RST9540_RST_RPP (7787L)
+#define RST9540_RST_SDC (7788L)
+#define RST9540_RST_SERDES_RX (7789L)
+#define RST9540_RST_SERDES_RX_DATAPATH (7790L)
+#define RST9540_RST_SERDES_TX (7791L)
+#define RST9540_RST_SYS (7792L)
+#define RST9540_RST_SYS_MMCM (7793L)
+#define RST9540_RST_TMC (7794L)
+#define RST9540_RST_TS (7795L)
+#define RST9540_RST_TS_MMCM (7796L)
+#define RST9540_STAT (7797L)
+#define RST9540_STAT_CORE_MMCM_LOCKED (7798L)
+#define RST9540_STAT_DDR4_MMCM_LOCKED (7799L)
+#define RST9540_STAT_DDR4_PLL_LOCKED (7800L)
+#define RST9540_STAT_PTP_MMCM_LOCKED (7801L)
+#define RST9540_STAT_SYS_MMCM_LOCKED (7802L)
+#define RST9540_STAT_TS_MMCM_LOCKED (7803L)
+#define RST9540_STICKY (7804L)
+#define RST9540_STICKY_CORE_MMCM_UNLOCKED (7805L)
+#define RST9540_STICKY_DDR4_MMCM_UNLOCKED (7806L)
+#define RST9540_STICKY_DDR4_PLL_UNLOCKED (7807L)
+#define RST9540_STICKY_PTP_MMCM_UNLOCKED (7808L)
+#define RST9540_STICKY_SYS_MMCM_UNLOCKED (7809L)
+#define RST9540_STICKY_TS_MMCM_UNLOCKED (7810L)
+/* RST9541 */
+#define RST9541_LATCH (7811L)
+#define RST9541_LATCH_DDR4_CALIB_COMPLETE (7812L)
+#define RST9541_LATCH_PHY_RDY (7813L)
+#define RST9541_POWER (7814L)
+#define RST9541_POWER_PU_PHY (7815L)
+#define RST9541_RST (7816L)
+#define RST9541_RST_DDR4 (7817L)
+#define RST9541_RST_PERIPH (7818L)
+#define RST9541_RST_PHY (7819L)
+#define RST9541_RST_POWER (7820L)
+#define RST9541_RST_SYS (7821L)
+#define RST9541_STAT (7822L)
+#define RST9541_STAT_DDR4_CALIB_COMPLETE (7823L)
+#define RST9541_STAT_PHY_RDY (7824L)
+/* RST9542 */
+#define RST9542_LATCH (7825L)
+#define RST9542_LATCH_DDR4_CALIB_COMPLETE (7826L)
+#define RST9542_LATCH_PHY_RDY (7827L)
+#define RST9542_POWER (7828L)
+#define RST9542_POWER_PU_PHY (7829L)
+#define RST9542_RST (7830L)
+#define RST9542_RST_DDR4 (7831L)
+#define RST9542_RST_PERIPH (7832L)
+#define RST9542_RST_PHY (7833L)
+#define RST9542_RST_SYS (7834L)
+#define RST9542_STAT (7835L)
+#define RST9542_STAT_DDR4_CALIB_COMPLETE (7836L)
+#define RST9542_STAT_PHY_RDY (7837L)
+/* RST9543 */
+#define RST9543_CTRL (7838L)
+#define RST9543_CTRL_PTP_MMCM_CLKSEL (7839L)
+#define RST9543_CTRL_TS_CLKSEL (7840L)
+#define RST9543_CTRL_TS_CLKSEL_OVERRIDE (7841L)
+#define RST9543_POWER (7842L)
+#define RST9543_POWER_PU_NSEB (7843L)
+#define RST9543_POWER_PU_PHY (7844L)
+#define RST9543_RST (7845L)
+#define RST9543_RST_CORE_MMCM (7846L)
+#define RST9543_RST_DDR4 (7847L)
+#define RST9543_RST_MAC_RX (7848L)
+#define RST9543_RST_PERIPH (7849L)
+#define RST9543_RST_PHY (7850L)
+#define RST9543_RST_PTP (7851L)
+#define RST9543_RST_PTP_MMCM (7852L)
+#define RST9543_RST_RPP (7853L)
+#define RST9543_RST_SDC (7854L)
+#define RST9543_RST_SYS (7855L)
+#define RST9543_RST_SYS_MMCM (7856L)
+#define RST9543_RST_TMC (7857L)
+#define RST9543_RST_TS (7858L)
+#define RST9543_RST_TS_MMCM (7859L)
+#define RST9543_STAT (7860L)
+#define RST9543_STAT_CORE_MMCM_LOCKED (7861L)
+#define RST9543_STAT_DDR4_MMCM_LOCKED (7862L)
+#define RST9543_STAT_DDR4_PLL_LOCKED (7863L)
+#define RST9543_STAT_PTP_MMCM_LOCKED (7864L)
+#define RST9543_STAT_SYS_MMCM_LOCKED (7865L)
+#define RST9543_STAT_TS_MMCM_LOCKED (7866L)
+#define RST9543_STICKY (7867L)
+#define RST9543_STICKY_CORE_MMCM_UNLOCKED (7868L)
+#define RST9543_STICKY_DDR4_MMCM_UNLOCKED (7869L)
+#define RST9543_STICKY_DDR4_PLL_UNLOCKED (7870L)
+#define RST9543_STICKY_PTP_MMCM_UNLOCKED (7871L)
+#define RST9543_STICKY_SYS_MMCM_UNLOCKED (7872L)
+#define RST9543_STICKY_TS_MMCM_UNLOCKED (7873L)
+/* RST9544 */
+#define RST9544_CTRL (7874L)
+#define RST9544_CTRL_PTP_MMCM_CLKSEL (7875L)
+#define RST9544_CTRL_TS_CLKSEL (7876L)
+#define RST9544_CTRL_TS_CLKSEL_OVERRIDE (7877L)
+#define RST9544_CTRL_TS_CLKSEL_REF (7878L)
+#define RST9544_POWER (7879L)
+#define RST9544_POWER_PU_NSEB (7880L)
+#define RST9544_POWER_PU_PHY (7881L)
+#define RST9544_RST (7882L)
+#define RST9544_RST_CORE_MMCM (7883L)
+#define RST9544_RST_DDR4 (7884L)
+#define RST9544_RST_NFV_OVS (7885L)
+#define RST9544_RST_PERIPH (7886L)
+#define RST9544_RST_PHY (7887L)
+#define RST9544_RST_PTP (7888L)
+#define RST9544_RST_PTP_MMCM (7889L)
+#define RST9544_RST_RPP (7890L)
+#define RST9544_RST_SDC (7891L)
+#define RST9544_RST_SYS (7892L)
+#define RST9544_RST_SYS_MMCM (7893L)
+#define RST9544_RST_TMC (7894L)
+#define RST9544_RST_TS (7895L)
+#define RST9544_RST_TSM_REF_MMCM (7896L)
+#define RST9544_RST_TS_MMCM (7897L)
+#define RST9544_STAT (7898L)
+#define RST9544_STAT_CORE_MMCM_LOCKED (7899L)
+#define RST9544_STAT_DDR4_MMCM_LOCKED (7900L)
+#define RST9544_STAT_DDR4_PLL_LOCKED (7901L)
+#define RST9544_STAT_PTP_MMCM_LOCKED (7902L)
+#define RST9544_STAT_SYS_MMCM_LOCKED (7903L)
+#define RST9544_STAT_TSM_REF_MMCM_LOCKED (7904L)
+#define RST9544_STAT_TS_MMCM_LOCKED (7905L)
+#define RST9544_STICKY (7906L)
+#define RST9544_STICKY_CORE_MMCM_UNLOCKED (7907L)
+#define RST9544_STICKY_DDR4_MMCM_UNLOCKED (7908L)
+#define RST9544_STICKY_DDR4_PLL_UNLOCKED (7909L)
+#define RST9544_STICKY_PCI_SYS_MMCM_UNLOCKED (7910L)
+#define RST9544_STICKY_PTP_MMCM_UNLOCKED (7911L)
+#define RST9544_STICKY_SYS_MMCM_UNLOCKED (7912L)
+#define RST9544_STICKY_TSM_REF_MMCM_UNLOCKED (7913L)
+#define RST9544_STICKY_TS_MMCM_UNLOCKED (7914L)
+/* RST9545 */
+#define RST9545_CTRL (7915L)
+#define RST9545_CTRL_PTP_MMCM_CLKSEL (7916L)
+#define RST9545_CTRL_TS_CLKSEL (7917L)
+#define RST9545_CTRL_TS_CLKSEL_OVERRIDE (7918L)
+#define RST9545_POWER (7919L)
+#define RST9545_POWER_PU_NSEB (7920L)
+#define RST9545_POWER_PU_PHY (7921L)
+#define RST9545_RST (7922L)
+#define RST9545_RST_CORE_MMCM (7923L)
+#define RST9545_RST_DDR4 (7924L)
+#define RST9545_RST_PERIPH (7925L)
+#define RST9545_RST_PHY (7926L)
+#define RST9545_RST_PTP (7927L)
+#define RST9545_RST_PTP_MMCM (7928L)
+#define RST9545_RST_RPP (7929L)
+#define RST9545_RST_SDC (7930L)
+#define RST9545_RST_SYS (7931L)
+#define RST9545_RST_SYS_MMCM (7932L)
+#define RST9545_RST_TMC (7933L)
+#define RST9545_RST_TS (7934L)
+#define RST9545_RST_TS_MMCM (7935L)
+#define RST9545_STAT (7936L)
+#define RST9545_STAT_CORE_MMCM_LOCKED (7937L)
+#define RST9545_STAT_DDR4_MMCM_LOCKED (7938L)
+#define RST9545_STAT_DDR4_PLL_LOCKED (7939L)
+#define RST9545_STAT_PTP_MMCM_LOCKED (7940L)
+#define RST9545_STAT_SYS_MMCM_LOCKED (7941L)
+#define RST9545_STAT_TS_MMCM_LOCKED (7942L)
+#define RST9545_STICKY (7943L)
+#define RST9545_STICKY_CORE_MMCM_UNLOCKED (7944L)
+#define RST9545_STICKY_DDR4_MMCM_UNLOCKED (7945L)
+#define RST9545_STICKY_DDR4_PLL_UNLOCKED (7946L)
+#define RST9545_STICKY_PTP_MMCM_UNLOCKED (7947L)
+#define RST9545_STICKY_SYS_MMCM_UNLOCKED (7948L)
+#define RST9545_STICKY_TS_MMCM_UNLOCKED (7949L)
+/* RST9546 */
+#define RST9546_CTRL (7950L)
+#define RST9546_CTRL_PTP_MMCM_CLKSEL (7951L)
+#define RST9546_CTRL_TS_CLKSEL (7952L)
+#define RST9546_CTRL_TS_CLKSEL_OVERRIDE (7953L)
+#define RST9546_POWER (7954L)
+#define RST9546_POWER_PU_NSEB (7955L)
+#define RST9546_POWER_PU_PHY (7956L)
+#define RST9546_RST (7957L)
+#define RST9546_RST_CORE_MMCM (7958L)
+#define RST9546_RST_DDR4 (7959L)
+#define RST9546_RST_MAC_RX (7960L)
+#define RST9546_RST_MAC_TX (7961L)
+#define RST9546_RST_PCS_RX (7962L)
+#define RST9546_RST_PERIPH (7963L)
+#define RST9546_RST_PHY (7964L)
+#define RST9546_RST_PTP (7965L)
+#define RST9546_RST_PTP_MMCM (7966L)
+#define RST9546_RST_RPP (7967L)
+#define RST9546_RST_SDC (7968L)
+#define RST9546_RST_SERDES_RX (7969L)
+#define RST9546_RST_SERDES_RX_DATAPATH (7970L)
+#define RST9546_RST_SERDES_TX (7971L)
+#define RST9546_RST_SYS (7972L)
+#define RST9546_RST_SYS_MMCM (7973L)
+#define RST9546_RST_TMC (7974L)
+#define RST9546_RST_TS (7975L)
+#define RST9546_RST_TS_MMCM (7976L)
+#define RST9546_STAT (7977L)
+#define RST9546_STAT_CORE_MMCM_LOCKED (7978L)
+#define RST9546_STAT_DDR4_MMCM_LOCKED (7979L)
+#define RST9546_STAT_DDR4_PLL_LOCKED (7980L)
+#define RST9546_STAT_PTP_MMCM_LOCKED (7981L)
+#define RST9546_STAT_SYS_MMCM_LOCKED (7982L)
+#define RST9546_STAT_TS_MMCM_LOCKED (7983L)
+#define RST9546_STICKY (7984L)
+#define RST9546_STICKY_CORE_MMCM_UNLOCKED (7985L)
+#define RST9546_STICKY_DDR4_MMCM_UNLOCKED (7986L)
+#define RST9546_STICKY_DDR4_PLL_UNLOCKED (7987L)
+#define RST9546_STICKY_PTP_MMCM_UNLOCKED (7988L)
+#define RST9546_STICKY_SYS_MMCM_UNLOCKED (7989L)
+#define RST9546_STICKY_TS_MMCM_UNLOCKED (7990L)
+/* RST9547 */
+#define RST9547_LATCH (7991L)
+#define RST9547_LATCH_DDR4_CALIB_COMPLETE (7992L)
+#define RST9547_LATCH_PHY_RDY (7993L)
+#define RST9547_POWER (7994L)
+#define RST9547_POWER_PU_PHY (7995L)
+#define RST9547_RST (7996L)
+#define RST9547_RST_DDR4 (7997L)
+#define RST9547_RST_PERIPH (7998L)
+#define RST9547_RST_PHY (7999L)
+#define RST9547_RST_SYS (8000L)
+#define RST9547_STAT (8001L)
+#define RST9547_STAT_DDR4_CALIB_COMPLETE (8002L)
+#define RST9547_STAT_PHY_RDY (8003L)
+/* RST9548 */
+#define RST9548_CTRL (8004L)
+#define RST9548_CTRL_PTP_MMCM_CLKSEL (8005L)
+#define RST9548_CTRL_TS_CLKSEL (8006L)
+#define RST9548_CTRL_TS_CLKSEL_OVERRIDE (8007L)
+#define RST9548_POWER (8008L)
+#define RST9548_POWER_PU_NSEB (8009L)
+#define RST9548_POWER_PU_PHY (8010L)
+#define RST9548_RST (8011L)
+#define RST9548_RST_CORE_MMCM (8012L)
+#define RST9548_RST_DDR4 (8013L)
+#define RST9548_RST_PERIPH (8014L)
+#define RST9548_RST_PHY (8015L)
+#define RST9548_RST_PTP (8016L)
+#define RST9548_RST_PTP_MMCM (8017L)
+#define RST9548_RST_RPP (8018L)
+#define RST9548_RST_SDC (8019L)
+#define RST9548_RST_SYS (8020L)
+#define RST9548_RST_SYS_MMCM (8021L)
+#define RST9548_RST_TMC (8022L)
+#define RST9548_RST_TS (8023L)
+#define RST9548_RST_TS_MMCM (8024L)
+#define RST9548_STAT (8025L)
+#define RST9548_STAT_CORE_MMCM_LOCKED (8026L)
+#define RST9548_STAT_DDR4_MMCM_LOCKED (8027L)
+#define RST9548_STAT_DDR4_PLL_LOCKED (8028L)
+#define RST9548_STAT_PTP_MMCM_LOCKED (8029L)
+#define RST9548_STAT_SYS_MMCM_LOCKED (8030L)
+#define RST9548_STAT_TS_MMCM_LOCKED (8031L)
+#define RST9548_STICKY (8032L)
+#define RST9548_STICKY_CORE_MMCM_UNLOCKED (8033L)
+#define RST9548_STICKY_DDR4_MMCM_UNLOCKED (8034L)
+#define RST9548_STICKY_DDR4_PLL_UNLOCKED (8035L)
+#define RST9548_STICKY_PTP_MMCM_UNLOCKED (8036L)
+#define RST9548_STICKY_SYS_MMCM_UNLOCKED (8037L)
+#define RST9548_STICKY_TS_MMCM_UNLOCKED (8038L)
+/* RST9549 */
+#define RST9549_CTRL (8039L)
+#define RST9549_CTRL_PTP_MMCM_CLKSEL (8040L)
+#define RST9549_CTRL_TS_CLKSEL (8041L)
+#define RST9549_CTRL_TS_CLKSEL_OVERRIDE (8042L)
+#define RST9549_POWER (8043L)
+#define RST9549_POWER_PU_NSEB (8044L)
+#define RST9549_POWER_PU_PHY (8045L)
+#define RST9549_RST (8046L)
+#define RST9549_RST_CORE_MMCM (8047L)
+#define RST9549_RST_DDR4 (8048L)
+#define RST9549_RST_PERIPH (8049L)
+#define RST9549_RST_PHY (8050L)
+#define RST9549_RST_PTP (8051L)
+#define RST9549_RST_PTP_MMCM (8052L)
+#define RST9549_RST_RPP (8053L)
+#define RST9549_RST_SDC (8054L)
+#define RST9549_RST_SYS (8055L)
+#define RST9549_RST_SYS_MMCM (8056L)
+#define RST9549_RST_TMC (8057L)
+#define RST9549_RST_TS (8058L)
+#define RST9549_RST_TS_MMCM (8059L)
+#define RST9549_STAT (8060L)
+#define RST9549_STAT_CORE_MMCM_LOCKED (8061L)
+#define RST9549_STAT_DDR4_MMCM_LOCKED (8062L)
+#define RST9549_STAT_DDR4_PLL_LOCKED (8063L)
+#define RST9549_STAT_PTP_MMCM_LOCKED (8064L)
+#define RST9549_STAT_SYS_MMCM_LOCKED (8065L)
+#define RST9549_STAT_TS_MMCM_LOCKED (8066L)
+#define RST9549_STICKY (8067L)
+#define RST9549_STICKY_CORE_MMCM_UNLOCKED (8068L)
+#define RST9549_STICKY_DDR4_MMCM_UNLOCKED (8069L)
+#define RST9549_STICKY_DDR4_PLL_UNLOCKED (8070L)
+#define RST9549_STICKY_PTP_MMCM_UNLOCKED (8071L)
+#define RST9549_STICKY_SYS_MMCM_UNLOCKED (8072L)
+#define RST9549_STICKY_TS_MMCM_UNLOCKED (8073L)
+/* RST9553 */
+#define RST9553_LATCH (8074L)
+#define RST9553_LATCH_DDR4_CALIB_COMPLETE (8075L)
+#define RST9553_LATCH_PHY_RDY (8076L)
+#define RST9553_RST (8077L)
+#define RST9553_RST_DDR4 (8078L)
+#define RST9553_RST_PHY (8079L)
+#define RST9553_RST_SYS (8080L)
+#define RST9553_STAT (8081L)
+#define RST9553_STAT_DDR4_CALIB_COMPLETE (8082L)
+#define RST9553_STAT_PHY_RDY (8083L)
+/* RST9555 */
+#define RST9555_CTRL (8094L)
+#define RST9555_CTRL_PTP_MMCM_CLKSEL (8095L)
+#define RST9555_CTRL_TS_CLKSEL (8096L)
+#define RST9555_CTRL_TS_CLKSEL_OVERRIDE (8097L)
+#define RST9555_POWER (8098L)
+#define RST9555_POWER_PU_NSEB (8099L)
+#define RST9555_POWER_PU_PHY (8100L)
+#define RST9555_RST (8101L)
+#define RST9555_RST_CORE_MMCM (8102L)
+#define RST9555_RST_DDR4 (8103L)
+#define RST9555_RST_PERIPH (8104L)
+#define RST9555_RST_PHY (8105L)
+#define RST9555_RST_PTP (8106L)
+#define RST9555_RST_PTP_MMCM (8107L)
+#define RST9555_RST_RPP (8108L)
+#define RST9555_RST_SDC (8109L)
+#define RST9555_RST_SYS (8110L)
+#define RST9555_RST_SYS_MMCM (8111L)
+#define RST9555_RST_TMC (8112L)
+#define RST9555_RST_TS (8113L)
+#define RST9555_RST_TS_MMCM (8114L)
+#define RST9555_STAT (8115L)
+#define RST9555_STAT_CORE_MMCM_LOCKED (8116L)
+#define RST9555_STAT_DDR4_MMCM_LOCKED (8117L)
+#define RST9555_STAT_DDR4_PLL_LOCKED (8118L)
+#define RST9555_STAT_PTP_MMCM_LOCKED (8119L)
+#define RST9555_STAT_SYS_MMCM_LOCKED (8120L)
+#define RST9555_STAT_TS_MMCM_LOCKED (8121L)
+#define RST9555_STICKY (8122L)
+#define RST9555_STICKY_CORE_MMCM_UNLOCKED (8123L)
+#define RST9555_STICKY_DDR4_MMCM_UNLOCKED (8124L)
+#define RST9555_STICKY_DDR4_PLL_UNLOCKED (8125L)
+#define RST9555_STICKY_PTP_MMCM_UNLOCKED (8126L)
+#define RST9555_STICKY_SYS_MMCM_UNLOCKED (8127L)
+#define RST9555_STICKY_TS_MMCM_UNLOCKED (8128L)
+/* RST9559 */
+#define RST9559_LATCH (8129L)
+#define RST9559_LATCH_DDR4_CALIB_COMPLETE (8130L)
+#define RST9559_LATCH_PHY_RDY (8131L)
+#define RST9559_RST (8132L)
+#define RST9559_RST_DDR4 (8133L)
+#define RST9559_RST_PHY (8134L)
+#define RST9559_RST_SYS (8135L)
+#define RST9559_STAT (8136L)
+#define RST9559_STAT_DDR4_CALIB_COMPLETE (8137L)
+#define RST9559_STAT_PHY_RDY (8138L)
+/* RST9563 */
+#define RST9563_CTRL (8159L)
+#define RST9563_CTRL_PTP_MMCM_CLKSEL (8160L)
+#define RST9563_CTRL_TS_CLKSEL (8161L)
+#define RST9563_CTRL_TS_CLKSEL_OVERRIDE (8162L)
+#define RST9563_POWER (8163L)
+#define RST9563_POWER_PU_NSEB (8164L)
+#define RST9563_POWER_PU_PHY (8165L)
+#define RST9563_RST (8166L)
+#define RST9563_RST_CORE_MMCM (8167L)
+#define RST9563_RST_DDR4 (8168L)
+#define RST9563_RST_MAC_RX (8169L)
+#define RST9563_RST_PERIPH (8170L)
+#define RST9563_RST_PHY (8171L)
+#define RST9563_RST_PTP (8172L)
+#define RST9563_RST_PTP_MMCM (8173L)
+#define RST9563_RST_RPP (8174L)
+#define RST9563_RST_SDC (8175L)
+#define RST9563_RST_SYS (8176L)
+#define RST9563_RST_SYS_MMCM (8177L)
+#define RST9563_RST_TMC (8178L)
+#define RST9563_RST_TS (8179L)
+#define RST9563_RST_TSM_REF_MMCM (8180L)
+#define RST9563_RST_TS_MMCM (8181L)
+#define RST9563_STAT (8182L)
+#define RST9563_STAT_CORE_MMCM_LOCKED (8183L)
+#define RST9563_STAT_DDR4_MMCM_LOCKED (8184L)
+#define RST9563_STAT_DDR4_PLL_LOCKED (8185L)
+#define RST9563_STAT_PTP_MMCM_LOCKED (8186L)
+#define RST9563_STAT_SYS_MMCM_LOCKED (8187L)
+#define RST9563_STAT_TS_MMCM_LOCKED (8188L)
+#define RST9563_STICKY (8189L)
+#define RST9563_STICKY_CORE_MMCM_UNLOCKED (8190L)
+#define RST9563_STICKY_DDR4_MMCM_UNLOCKED (8191L)
+#define RST9563_STICKY_DDR4_PLL_UNLOCKED (8192L)
+#define RST9563_STICKY_PTP_MMCM_UNLOCKED (8193L)
+#define RST9563_STICKY_SYS_MMCM_UNLOCKED (8194L)
+#define RST9563_STICKY_TS_MMCM_UNLOCKED (8195L)
+/* RTD */
+#define RTD_CTRL (8196L)
+#define RTD_CTRL_ENABLE_RTD (8197L)
+#define RTD_CTRL_ENABLE_TX_FLUSH (8198L)
+#define RTD_CTRL_ENABLE_TX_MACPHY (8199L)
+#define RTD_CTRL_RDPTR_UPDATE_TIMER (8200L)
+#define RTD_CTRL_RESERVED (8201L)
+#define RTD_CTRL_TX_SPEED (8202L)
+#define RTD_DEB_REG1 (8203L)
+#define RTD_DEB_REG1_VALUE (8204L)
+#define RTD_DEB_REG2 (8205L)
+#define RTD_DEB_REG2_VALUE (8206L)
+#define RTD_DEB_REG3 (8207L)
+#define RTD_DEB_REG3_VALUE (8208L)
+#define RTD_HOSTBUFFER_ADR_HI (8209L)
+#define RTD_HOSTBUFFER_ADR_HI_VALUE (8210L)
+#define RTD_HOSTBUFFER_ADR_LO (8211L)
+#define RTD_HOSTBUFFER_ADR_LO_VALUE (8212L)
+#define RTD_RDPTR_ADR_HI (8213L)
+#define RTD_RDPTR_ADR_HI_VALUE (8214L)
+#define RTD_RDPTR_ADR_LO (8215L)
+#define RTD_RDPTR_ADR_LO_VALUE (8216L)
+#define RTD_STATUS (8217L)
+#define RTD_STATUS_HB_EMPTY (8218L)
+#define RTD_STATUS_LHF_EMPTY (8219L)
+#define RTD_STATUS_UNPACKER_STATUS (8220L)
+#define RTD_WRPTR (8221L)
+#define RTD_WRPTR_VALUE (8222L)
+/* RTD_HMP */
+#define RTD_HMP_CTRL (8223L)
+#define RTD_HMP_CTRL_ENABLE_HMP_0 (8224L)
+#define RTD_HMP_CTRL_ENABLE_HMP_1 (8225L)
+#define RTD_HMP_CTRL_ENABLE_HMP_2 (8226L)
+#define RTD_HMP_CTRL_ENABLE_HMP_3 (8227L)
+#define RTD_HMP_CTRL_WRPTR_POLL_TIMER (8228L)
+#define RTD_HMP_DEB_REG1 (8229L)
+#define RTD_HMP_DEB_REG1_VALUE (8230L)
+#define RTD_HMP_DEB_REG2 (8231L)
+#define RTD_HMP_DEB_REG2_VALUE (8232L)
+#define RTD_HMP_DEB_REG3 (8233L)
+#define RTD_HMP_DEB_REG3_VALUE (8234L)
+#define RTD_HMP_STATUS (8235L)
+#define RTD_HMP_STATUS_HMP_ACTIVE (8236L)
+#define RTD_HMP_WRPTR_ADR_HI (8237L)
+#define RTD_HMP_WRPTR_ADR_HI_VALUE (8238L)
+#define RTD_HMP_WRPTR_ADR_LO (8239L)
+#define RTD_HMP_WRPTR_ADR_LO_VALUE (8240L)
+/* RTX */
+#define RTX_CTRL (8241L)
+#define RTX_CTRL_PORT (8242L)
+#define RTX_CTRL_SIZE (8243L)
+#define RTX_STATUS (8244L)
+#define RTX_STATUS_AF (8245L)
+#define RTX_STATUS_BUSY (8246L)
+#define RTX_TXF_CTRL (8247L)
+#define RTX_TXF_CTRL_CNT (8248L)
+#define RTX_TXF_DATA (8249L)
+#define RTX_TXF_DATA_PAYLOAD (8250L)
+#define RXAUI_DEBUG (8268L)
+#define RXAUI_DEBUG_MGT_CV_0 (8269L)
+#define RXAUI_DEBUG_MGT_CV_1 (8270L)
+#define RXAUI_DEBUG_MGT_CV_2 (8271L)
+#define RXAUI_DEBUG_MGT_CV_3 (8272L)
+#define RXAUI_DEBUG_MGT_CV_4 (8273L)
+#define RXAUI_DEBUG_MGT_CV_5 (8274L)
+#define RXAUI_DEBUG_MGT_CV_6 (8275L)
+#define RXAUI_DEBUG_MGT_CV_7 (8276L)
+#define RXAUI_DEBUG_MGT_RXLOCK_0 (8277L)
+#define RXAUI_DEBUG_MGT_RXLOCK_1 (8278L)
+#define RXAUI_DEBUG_MGT_RX_RESET (8279L)
+#define RXAUI_DEBUG_MGT_TX_RESET (8280L)
+#define RXAUI_DEBUG_MMCM1_LOCKED (8281L)
+#define RXAUI_DRP_AD (8282L)
+#define RXAUI_DRP_AD_ADDRESS (8283L)
+#define RXAUI_DRP_AD_DFEEYEDACMON (8284L)
+#define RXAUI_DRP_AD_GTX_NO (8285L)
+#define RXAUI_DRP_AD_READY (8286L)
+#define RXAUI_DRP_AD_RESERVED3 (8287L)
+#define RXAUI_DRP_AD_RESERVED4 (8288L)
+#define RXAUI_DRP_DA (8289L)
+#define RXAUI_DRP_DA_DATA (8290L)
+#define RXAUI_GTX_CONFIG (8291L)
+#define RXAUI_GTX_CONFIG_LOOPBACK (8292L)
+#define RXAUI_GTX_CONFIG_LOOPBACKMUX (8293L)
+#define RXAUI_GTX_CONFIG_PRBSCNTRESET (8294L)
+#define RXAUI_GTX_CONFIG_RESERVED6 (8295L)
+#define RXAUI_GTX_CONFIG_RESERVED7 (8296L)
+#define RXAUI_GTX_CONFIG_RXENPRBSTST (8297L)
+#define RXAUI_GTX_CONFIG_RXEQMIX (8298L)
+#define RXAUI_GTX_CONFIG_TXDIFFCTRL (8299L)
+#define RXAUI_GTX_CONFIG_TXENPRBSTST (8300L)
+#define RXAUI_GTX_CONFIG_TXPOSTEMPHAS (8301L)
+#define RXAUI_GTX_CONFIG_TXPRBSFORCEE (8302L)
+#define RXAUI_GTX_CONFIG_TXPREEMPHASI (8303L)
+#define RXAUI_GTX_STAT (8304L)
+#define RXAUI_GTX_STAT_RESERVED10 (8305L)
+#define RXAUI_GTX_STAT_RESERVED11 (8306L)
+#define RXAUI_GTX_STAT_RESERVED12 (8307L)
+#define RXAUI_GTX_STAT_RESERVED13 (8308L)
+#define RXAUI_GTX_STAT_RESERVED8 (8309L)
+#define RXAUI_GTX_STAT_RESERVED9 (8310L)
+#define RXAUI_GTX_STAT_RXBUFSTATUS0 (8311L)
+#define RXAUI_GTX_STAT_RXBUFSTATUS1 (8312L)
+#define RXAUI_GTX_STAT_RXBYTEISAL_0 (8313L)
+#define RXAUI_GTX_STAT_RXBYTEISAL_1 (8314L)
+#define RXAUI_GTX_STAT_RXBYTEREAL_0 (8315L)
+#define RXAUI_GTX_STAT_RXBYTEREAL_1 (8316L)
+#define RXAUI_GTX_STAT_RXCHANREAL_0 (8317L)
+#define RXAUI_GTX_STAT_RXCHANREAL_1 (8318L)
+#define RXAUI_GTX_STAT_RXCOMMADET_0 (8319L)
+#define RXAUI_GTX_STAT_RXCOMMADET_1 (8320L)
+#define RXAUI_GTX_STAT_RXPRBSERR_0 (8321L)
+#define RXAUI_GTX_STAT_RXPRBSERR_1 (8322L)
+/* SDC */
+#define SDC_CELL_CNT (8612L)
+#define SDC_CELL_CNT_CELL_CNT (8613L)
+#define SDC_CELL_CNT_PERIOD (8614L)
+#define SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD (8615L)
+#define SDC_CTRL (8616L)
+#define SDC_CTRL_INIT (8617L)
+#define SDC_CTRL_RESET_POINTERS (8618L)
+#define SDC_CTRL_RUN_TEST (8619L)
+#define SDC_CTRL_STOP_CLIENT (8620L)
+#define SDC_CTRL_TEST_EN (8621L)
+#define SDC_FILL_LVL (8622L)
+#define SDC_FILL_LVL_FILL_LVL (8623L)
+#define SDC_MAX_FILL_LVL (8624L)
+#define SDC_MAX_FILL_LVL_MAX_FILL_LVL (8625L)
+#define SDC_STAT (8626L)
+#define SDC_STAT_CALIB (8627L)
+#define SDC_STAT_CELL_CNT_STOPPED (8628L)
+#define SDC_STAT_ERR_FOUND (8629L)
+#define SDC_STAT_INIT_DONE (8630L)
+#define SDC_STAT_MMCM_LOCK (8631L)
+#define SDC_STAT_PLL_LOCK (8632L)
+#define SDC_STAT_RESETTING (8633L)
+/* SLC */
+#define SLC_RCP_CTRL (8681L)
+#define SLC_RCP_CTRL_ADR (8682L)
+#define SLC_RCP_CTRL_CNT (8683L)
+#define SLC_RCP_DATA (8684L)
+#define SLC_RCP_DATA_PCAP (8685L)
+#define SLC_RCP_DATA_TAIL_DYN (8686L)
+#define SLC_RCP_DATA_TAIL_OFS (8687L)
+#define SLC_RCP_DATA_TAIL_SLC_EN (8688L)
+/* SLC_LR */
+/* SMM */
+#define SMM_CTRL (8770L)
+#define SMM_CTRL_ENABLE (8771L)
+#define SMM_READY_STATUS (8772L)
+#define SMM_READY_STATUS_D (8773L)
+#define SMM_SEG_INVLD_STICKY_STATUS (8774L)
+#define SMM_SEG_INVLD_STICKY_STATUS_D (8775L)
+#define SMM_SEG_MEM_CTRL (8776L)
+#define SMM_SEG_MEM_CTRL_A (8777L)
+#define SMM_SEG_MEM_CTRL_CNT (8778L)
+#define SMM_SEG_MEM_DATA (8779L)
+#define SMM_SEG_MEM_DATA_PHYADDR (8780L)
+#define SMM_SEG_MEM_DATA_SIZE (8781L)
+#define SMM_START_SEG_MEM_CTRL (8782L)
+#define SMM_START_SEG_MEM_CTRL_A (8783L)
+#define SMM_START_SEG_MEM_CTRL_CNT (8784L)
+#define SMM_START_SEG_MEM_DATA (8785L)
+#define SMM_START_SEG_MEM_DATA_SEG (8786L)
+/* SPIM */
+#define SPIM_CFG (8793L)
+#define SPIM_CFG_PRE (8794L)
+#define SPIM_CMD (8795L)
+#define SPIM_CMD_ADDR (8796L)
+#define SPIM_CMD_CMD (8797L)
+#define SPIM_CMD_DATA (8798L)
+#define SPIM_CONF0 (8799L)
+#define SPIM_CONF0_BYTE_PACE (8800L)
+#define SPIM_CONF0_MIRROR_EN (8801L)
+#define SPIM_CONF0_MSB_FIRST (8802L)
+#define SPIM_CONF0_PRESCAL_CLK (8803L)
+#define SPIM_CONF0_RESTART (8804L)
+#define SPIM_CONF0_RST (8805L)
+#define SPIM_CONF0_SYNC_MON_EN (8806L)
+#define SPIM_CONF1 (8807L)
+#define SPIM_CONF1_MIRROR_PACE (8808L)
+#define SPIM_CONF1_MIRROR_SCAN (8809L)
+#define SPIM_CONF1_SYNCTIMEOUT (8810L)
+#define SPIM_CONF2 (8811L)
+#define SPIM_CONF2_MIRROR_PRESC (8812L)
+#define SPIM_CONF2_OPCODE_RD (8813L)
+#define SPIM_CONF2_OPCODE_WR (8814L)
+#define SPIM_CONF3 (8815L)
+#define SPIM_CONF3_MIRROR_RDADR (8816L)
+#define SPIM_CONF3_MIRROR_WRADR (8817L)
+#define SPIM_CR (8818L)
+#define SPIM_CR_EN (8819L)
+#define SPIM_CR_LOOP (8820L)
+#define SPIM_CR_RXRST (8821L)
+#define SPIM_CR_TXRST (8822L)
+#define SPIM_DRR (8823L)
+#define SPIM_DRR_DRR (8824L)
+#define SPIM_DTR (8825L)
+#define SPIM_DTR_DTR (8826L)
+#define SPIM_REPLY (8827L)
+#define SPIM_REPLY_RDDATA (8828L)
+#define SPIM_SR (8829L)
+#define SPIM_SR_DONE (8830L)
+#define SPIM_SR_RXEMPTY (8831L)
+#define SPIM_SR_RXFULL (8832L)
+#define SPIM_SR_RXLVL (8833L)
+#define SPIM_SR_TXEMPTY (8834L)
+#define SPIM_SR_TXFULL (8835L)
+#define SPIM_SR_TXLVL (8836L)
+#define SPIM_SRR (8837L)
+#define SPIM_SRR_RST (8838L)
+#define SPIM_STATUS (8839L)
+#define SPIM_STATUS_CMDPENDING (8840L)
+#define SPIM_STATUS_RESERVED (8841L)
+#define SPIM_STATUS_RESYNCDETECT (8842L)
+#define SPIM_STATUS_RESYNCING (8843L)
+/* SPIS */
+#define SPIS_CR (8844L)
+#define SPIS_CR_DEBUG (8845L)
+#define SPIS_CR_EN (8846L)
+#define SPIS_CR_LOOP (8847L)
+#define SPIS_CR_RXRST (8848L)
+#define SPIS_CR_TXRST (8849L)
+#define SPIS_DRR (8850L)
+#define SPIS_DRR_DRR (8851L)
+#define SPIS_DTR (8852L)
+#define SPIS_DTR_DTR (8853L)
+#define SPIS_RAM_CTRL (8854L)
+#define SPIS_RAM_CTRL_ADR (8855L)
+#define SPIS_RAM_CTRL_CNT (8856L)
+#define SPIS_RAM_DATA (8857L)
+#define SPIS_RAM_DATA_DATA (8858L)
+#define SPIS_SR (8859L)
+#define SPIS_SR_DONE (8860L)
+#define SPIS_SR_FRAME_ERR (8861L)
+#define SPIS_SR_READ_ERR (8862L)
+#define SPIS_SR_RXEMPTY (8863L)
+#define SPIS_SR_RXFULL (8864L)
+#define SPIS_SR_RXLVL (8865L)
+#define SPIS_SR_TXEMPTY (8866L)
+#define SPIS_SR_TXFULL (8867L)
+#define SPIS_SR_TXLVL (8868L)
+#define SPIS_SR_WRITE_ERR (8869L)
+#define SPIS_SRR (8870L)
+#define SPIS_SRR_RST (8871L)
+/* STA */
+#define STA_BYTE (8872L)
+#define STA_BYTE_CNT (8873L)
+#define STA_CFG (8874L)
+#define STA_CFG_CNT_CLEAR (8875L)
+#define STA_CFG_CNT_FRZ (8876L)
+#define STA_CFG_DMA_ENA (8877L)
+#define STA_CFG_TX_DISABLE (8878L)
+#define STA_CV_ERR (8879L)
+#define STA_CV_ERR_CNT (8880L)
+#define STA_FCS_ERR (8881L)
+#define STA_FCS_ERR_CNT (8882L)
+#define STA_HOST_ADR_LSB (8883L)
+#define STA_HOST_ADR_LSB_LSB (8884L)
+#define STA_HOST_ADR_MSB (8885L)
+#define STA_HOST_ADR_MSB_MSB (8886L)
+#define STA_PCKT (8887L)
+#define STA_PCKT_CNT (8888L)
+#define STA_STATUS (8889L)
+#define STA_STATUS_STAT_TOGGLE_MISSED (8890L)
+/* TBH */
+#define TBH_CTRL (9103L)
+#define TBH_CTRL_DISABLE_LR_LB (9104L)
+#define TBH_CTRL_ENABLE (9105L)
+#define TBH_CTRL_PORT (9106L)
+#define TBH_CTRL_PORT_AUS (9107L)
+#define TBH_CTRL_SEGMENT (9108L)
+#define TBH_CTRL_SEGMENT_SIZE (9109L)
+#define TBH_DBG_DLN_ERR (9110L)
+#define TBH_DBG_DLN_ERR_E (9111L)
+#define TBH_DBG_DLN_ERR_HB (9112L)
+#define TBH_DBG_ILLEGAL_RANGE (9113L)
+#define TBH_DBG_ILLEGAL_RANGE_E (9114L)
+#define TBH_DBG_ILLEGAL_RANGE_HB (9115L)
+#define TBH_DBG_MAX_PCI_QUIET (9116L)
+#define TBH_DBG_MAX_PCI_QUIET_CYCLES (9117L)
+#define TBH_DISABLE (9118L)
+#define TBH_DISABLE_DISABLE (9119L)
+#define TBH_DISABLE_HB (9120L)
+#define TBH_HB_DSC_MEM_CTRL (9121L)
+#define TBH_HB_DSC_MEM_CTRL_ADR (9122L)
+#define TBH_HB_DSC_MEM_CTRL_CNT (9123L)
+#define TBH_HB_DSC_MEM_DATA (9124L)
+#define TBH_HB_DSC_MEM_DATA_DT (9125L)
+#define TBH_HB_DSC_MEM_DATA_FCS (9126L)
+#define TBH_HB_DSC_MEM_DATA_FCS_CTL_POS (9127L)
+#define TBH_HB_DSC_MEM_DATA_FCS_CTL_USE (9128L)
+#define TBH_HB_DSC_MEM_DATA_IG_POS (9129L)
+#define TBH_HB_DSC_MEM_DATA_IG_USE (9130L)
+#define TBH_HB_DSC_MEM_DATA_OCS_CMD_POS (9131L)
+#define TBH_HB_DSC_MEM_DATA_OCS_CMD_USE (9132L)
+#define TBH_HB_DSC_MEM_DATA_OFS0_POS (9133L)
+#define TBH_HB_DSC_MEM_DATA_OFS0_USE (9134L)
+#define TBH_HB_DSC_MEM_DATA_OFS1_POS (9135L)
+#define TBH_HB_DSC_MEM_DATA_OFS1_USE (9136L)
+#define TBH_HB_DSC_MEM_DATA_OFS2_POS (9137L)
+#define TBH_HB_DSC_MEM_DATA_OFS2_USE (9138L)
+#define TBH_HB_DSC_MEM_DATA_PFD (9139L)
+#define TBH_HB_DSC_MEM_DATA_PORT (9140L)
+#define TBH_HB_DSC_MEM_DATA_PORT_MASK (9141L)
+#define TBH_HB_DSC_MEM_DATA_PORT_POS (9142L)
+#define TBH_HB_DSC_MEM_DATA_SET_CLOCK_POS (9143L)
+#define TBH_HB_DSC_MEM_DATA_SET_CLOCK_USE (9144L)
+#define TBH_HB_DSC_MEM_DATA_SW_TFD_TYPE_POS (9145L)
+#define TBH_HB_DSC_MEM_DATA_SW_TFD_TYPE_USE (9146L)
+#define TBH_HB_DSC_MEM_DATA_TS_APPEND (9147L)
+#define TBH_HB_DSC_MEM_DATA_TS_FMT (9148L)
+#define TBH_HB_DSC_MEM_DATA_TS_INJECT_POS (9149L)
+#define TBH_HB_DSC_MEM_DATA_TS_INJECT_USE (9150L)
+#define TBH_HB_DSC_MEM_DATA_TX_NOW_POS (9151L)
+#define TBH_HB_DSC_MEM_DATA_TX_NOW_USE (9152L)
+#define TBH_HB_DSC_MEM_DATA_TX_ON_TS (9153L)
+#define TBH_HB_DSC_MEM_DATA_WL_USE (9154L)
+#define TBH_HB_INFO_MEM_CTRL (9155L)
+#define TBH_HB_INFO_MEM_CTRL_A (9156L)
+#define TBH_HB_INFO_MEM_CTRL_CNT (9157L)
+#define TBH_HB_INFO_MEM_DATA (9158L)
+#define TBH_HB_INFO_MEM_DATA_SIZE (9159L)
+#define TBH_HB_PORTS_MEM_CTRL (9160L)
+#define TBH_HB_PORTS_MEM_CTRL_A (9161L)
+#define TBH_HB_PORTS_MEM_CTRL_CNT (9162L)
+#define TBH_HB_PORTS_MEM_DATA (9163L)
+#define TBH_HB_PORTS_MEM_DATA_MAPPING (9164L)
+#define TBH_PORT_MAPPING (9165L)
+#define TBH_PORT_MAPPING_P0 (9166L)
+#define TBH_PORT_MAPPING_P1 (9167L)
+#define TBH_PORT_MAPPING_P2 (9168L)
+#define TBH_PORT_MAPPING_P3 (9169L)
+#define TBH_PORT_MAPPING_P4 (9170L)
+#define TBH_PORT_MAPPING_P5 (9171L)
+#define TBH_PORT_MAPPING_P6 (9172L)
+#define TBH_PORT_MAPPING_P7 (9173L)
+#define TBH_SET_RD_POINTER (9174L)
+#define TBH_SET_RD_POINTER_HB (9175L)
+#define TBH_SET_RD_POINTER_OFFSET (9176L)
+#define TBH_STATUS (9177L)
+#define TBH_STATUS_STOPPED (9178L)
+/* TEMPMON */
+#define TEMPMON_ALARMS (9179L)
+#define TEMPMON_ALARMS_OT (9180L)
+#define TEMPMON_ALARMS_OT_OVERWR (9181L)
+#define TEMPMON_ALARMS_OT_OVERWRVAL (9182L)
+#define TEMPMON_ALARMS_TEMP (9183L)
+#define TEMPMON_STAT (9184L)
+#define TEMPMON_STAT_TEMP (9185L)
+/* TINT */
+#define TINT_CTRL (9186L)
+#define TINT_CTRL_INTERVAL (9187L)
+#define TINT_STATUS (9188L)
+#define TINT_STATUS_DELAYED (9189L)
+#define TINT_STATUS_SKIPPED (9190L)
+/* TMC */
+#define TMC_PORT_RPL (9191L)
+#define TMC_PORT_RPL_P0 (9192L)
+#define TMC_PORT_RPL_P1 (9193L)
+#define TMC_PORT_RPL_P2 (9194L)
+#define TMC_PORT_RPL_P3 (9195L)
+#define TMC_PORT_RPL_P4 (9196L)
+#define TMC_PORT_RPL_P5 (9197L)
+#define TMC_PORT_RPL_P6 (9198L)
+#define TMC_PORT_RPL_P7 (9199L)
+/* TSM */
+#define TSM_ADJ_FINE_N (9200L)
+#define TSM_ADJ_FINE_N_2DY (9201L)
+#define TSM_ADJ_FINE_N_2DY2DX (9202L)
+#define TSM_ADJ_FINE_P (9203L)
+#define TSM_ADJ_FINE_P_2DY (9204L)
+#define TSM_ADJ_FINE_P_2DY2DX (9205L)
+#define TSM_ADJ_LIMIT_HI (9206L)
+#define TSM_ADJ_LIMIT_HI_LIMIT (9207L)
+#define TSM_ADJ_LIMIT_LO (9208L)
+#define TSM_ADJ_LIMIT_LO_LIMIT (9209L)
+#define TSM_BASIC_2DY (9210L)
+#define TSM_BASIC_2DY_2DY (9211L)
+#define TSM_BASIC_2DY2DX (9212L)
+#define TSM_BASIC_2DY2DX_2DY2DX (9213L)
+#define TSM_CON0_CONFIG (9214L)
+#define TSM_CON0_CONFIG_BLIND (9215L)
+#define TSM_CON0_CONFIG_DC_SRC (9216L)
+#define TSM_CON0_CONFIG_PORT (9217L)
+#define TSM_CON0_CONFIG_PPSIN_2_5V (9218L)
+#define TSM_CON0_CONFIG_SAMPLE_EDGE (9219L)
+#define TSM_CON0_INTERFACE (9220L)
+#define TSM_CON0_INTERFACE_EX_TERM (9221L)
+#define TSM_CON0_INTERFACE_IN_REF_PWM (9222L)
+#define TSM_CON0_INTERFACE_PWM_ENA (9223L)
+#define TSM_CON0_INTERFACE_RESERVED (9224L)
+#define TSM_CON0_INTERFACE_VTERM_PWM (9225L)
+#define TSM_CON0_SAMPLE_HI (9226L)
+#define TSM_CON0_SAMPLE_HI_SEC (9227L)
+#define TSM_CON0_SAMPLE_LO (9228L)
+#define TSM_CON0_SAMPLE_LO_NS (9229L)
+#define TSM_CON1_CONFIG (9230L)
+#define TSM_CON1_CONFIG_BLIND (9231L)
+#define TSM_CON1_CONFIG_DC_SRC (9232L)
+#define TSM_CON1_CONFIG_PORT (9233L)
+#define TSM_CON1_CONFIG_PPSIN_2_5V (9234L)
+#define TSM_CON1_CONFIG_SAMPLE_EDGE (9235L)
+#define TSM_CON1_SAMPLE_HI (9236L)
+#define TSM_CON1_SAMPLE_HI_SEC (9237L)
+#define TSM_CON1_SAMPLE_LO (9238L)
+#define TSM_CON1_SAMPLE_LO_NS (9239L)
+#define TSM_CON2_CONFIG (9240L)
+#define TSM_CON2_CONFIG_BLIND (9241L)
+#define TSM_CON2_CONFIG_DC_SRC (9242L)
+#define TSM_CON2_CONFIG_PORT (9243L)
+#define TSM_CON2_CONFIG_PPSIN_2_5V (9244L)
+#define TSM_CON2_CONFIG_SAMPLE_EDGE (9245L)
+#define TSM_CON2_SAMPLE_HI (9246L)
+#define TSM_CON2_SAMPLE_HI_SEC (9247L)
+#define TSM_CON2_SAMPLE_LO (9248L)
+#define TSM_CON2_SAMPLE_LO_NS (9249L)
+#define TSM_CON3_CONFIG (9250L)
+#define TSM_CON3_CONFIG_BLIND (9251L)
+#define TSM_CON3_CONFIG_PORT (9252L)
+#define TSM_CON3_CONFIG_SAMPLE_EDGE (9253L)
+#define TSM_CON3_SAMPLE_HI (9254L)
+#define TSM_CON3_SAMPLE_HI_SEC (9255L)
+#define TSM_CON3_SAMPLE_LO (9256L)
+#define TSM_CON3_SAMPLE_LO_NS (9257L)
+#define TSM_CON4_CONFIG (9258L)
+#define TSM_CON4_CONFIG_BLIND (9259L)
+#define TSM_CON4_CONFIG_PORT (9260L)
+#define TSM_CON4_CONFIG_SAMPLE_EDGE (9261L)
+#define TSM_CON4_SAMPLE_HI (9262L)
+#define TSM_CON4_SAMPLE_HI_SEC (9263L)
+#define TSM_CON4_SAMPLE_LO (9264L)
+#define TSM_CON4_SAMPLE_LO_NS (9265L)
+#define TSM_CON5_CONFIG (9266L)
+#define TSM_CON5_CONFIG_BLIND (9267L)
+#define TSM_CON5_CONFIG_PORT (9268L)
+#define TSM_CON5_CONFIG_SAMPLE_EDGE (9269L)
+#define TSM_CON5_SAMPLE_HI (9270L)
+#define TSM_CON5_SAMPLE_HI_SEC (9271L)
+#define TSM_CON5_SAMPLE_LO (9272L)
+#define TSM_CON5_SAMPLE_LO_TIME (9273L)
+#define TSM_CON6_CONFIG (9274L)
+#define TSM_CON6_CONFIG_BLIND (9275L)
+#define TSM_CON6_CONFIG_PORT (9276L)
+#define TSM_CON6_CONFIG_SAMPLE_EDGE (9277L)
+#define TSM_CON6_SAMPLE_HI (9278L)
+#define TSM_CON6_SAMPLE_HI_SEC (9279L)
+#define TSM_CON6_SAMPLE_LO (9280L)
+#define TSM_CON6_SAMPLE_LO_NS (9281L)
+#define TSM_CON7_HOST_SAMPLE_HI (9282L)
+#define TSM_CON7_HOST_SAMPLE_HI_SEC (9283L)
+#define TSM_CON7_HOST_SAMPLE_LO (9284L)
+#define TSM_CON7_HOST_SAMPLE_LO_NS (9285L)
+#define TSM_CONFIG (9286L)
+#define TSM_CONFIG_NTTS_SRC (9287L)
+#define TSM_CONFIG_NTTS_SYNC (9288L)
+#define TSM_CONFIG_TIMESET_EDGE (9289L)
+#define TSM_CONFIG_TIMESET_SRC (9290L)
+#define TSM_CONFIG_TIMESET_UP (9291L)
+#define TSM_CONFIG_TS_FORMAT (9292L)
+#define TSM_CTRL (9293L)
+#define TSM_CTRL_DCEN_CON0 (9294L)
+#define TSM_CTRL_DCEN_CON1 (9295L)
+#define TSM_CTRL_DCEN_CON2 (9296L)
+#define TSM_CTRL_FORMAT (9297L)
+#define TSM_CTRL_HIGH_SAMPLE (9298L)
+#define TSM_CTRL_LED_CON0 (9299L)
+#define TSM_CTRL_LED_CON1 (9300L)
+#define TSM_CTRL_LED_CON2 (9301L)
+#define TSM_CTRL_PRIMARY_STAT (9302L)
+#define TSM_CTRL_OEN_CON0 (9303L)
+#define TSM_CTRL_OEN_CON1 (9304L)
+#define TSM_CTRL_OEN_CON2 (9305L)
+#define TSM_CTRL_PPSEN (9306L)
+#define TSM_CTRL_PPS_NEGEDGE (9307L)
+#define TSM_CTRL_PPS_TIME_UP (9308L)
+#define TSM_CTRL_PTP_TIME_UP (9309L)
+#define TSM_CTRL_RESERVED (9310L)
+#define TSM_CTRL_SEL_EXTSRC (9311L)
+#define TSM_CTRL_SYNEN (9312L)
+#define TSM_CTRL_TS_CON0 (9313L)
+#define TSM_CTRL_TS_CON1 (9314L)
+#define TSM_CTRL_TS_CON2 (9315L)
+#define TSM_EXT_STAT (9316L)
+#define TSM_EXT_STAT_STAT (9317L)
+#define TSM_EXT_TIME_HI (9318L)
+#define TSM_EXT_TIME_HI_TIME (9319L)
+#define TSM_EXT_TIME_LO (9320L)
+#define TSM_EXT_TIME_LO_TIME (9321L)
+#define TSM_INTERFACE (9322L)
+#define TSM_INTERFACE_EX_TERM (9323L)
+#define TSM_INTERFACE_IN_REF_PWM (9324L)
+#define TSM_INTERFACE_PWM_ENA (9325L)
+#define TSM_INTERFACE_RESERVED (9326L)
+#define TSM_INTERFACE_VTERM_PWM (9327L)
+#define TSM_INT_CONFIG (9328L)
+#define TSM_INT_CONFIG_AUTO_DISABLE (9329L)
+#define TSM_INT_CONFIG_MASK (9330L)
+#define TSM_INT_STAT (9331L)
+#define TSM_INT_STAT_CAUSE (9332L)
+#define TSM_INT_STAT_ENABLE (9333L)
+#define TSM_INT_TIME_HI (9334L)
+#define TSM_INT_TIME_HI_TIME (9335L)
+#define TSM_INT_TIME_LO (9336L)
+#define TSM_INT_TIME_LO_TIME (9337L)
+#define TSM_LED (9338L)
+#define TSM_LED_LED0_BG_COLOR (9339L)
+#define TSM_LED_LED0_COLOR (9340L)
+#define TSM_LED_LED0_MODE (9341L)
+#define TSM_LED_LED0_SRC (9342L)
+#define TSM_LED_LED1_BG_COLOR (9343L)
+#define TSM_LED_LED1_COLOR (9344L)
+#define TSM_LED_LED1_MODE (9345L)
+#define TSM_LED_LED1_SRC (9346L)
+#define TSM_LED_LED2_BG_COLOR (9347L)
+#define TSM_LED_LED2_COLOR (9348L)
+#define TSM_LED_LED2_MODE (9349L)
+#define TSM_LED_LED2_SRC (9350L)
+#define TSM_NTTS_CONFIG (9351L)
+#define TSM_NTTS_CONFIG_AUTO_HARDSET (9352L)
+#define TSM_NTTS_CONFIG_EXT_CLK_ADJ (9353L)
+#define TSM_NTTS_CONFIG_HIGH_SAMPLE (9354L)
+#define TSM_NTTS_CONFIG_TS_SRC_FORMAT (9355L)
+#define TSM_NTTS_CTRL (9356L)
+#define TSM_NTTS_CTRL_NTTS_CMD (9357L)
+#define TSM_NTTS_DATA_HI (9358L)
+#define TSM_NTTS_DATA_HI_DATA (9359L)
+#define TSM_NTTS_DATA_LO (9360L)
+#define TSM_NTTS_DATA_LO_DATA (9361L)
+#define TSM_NTTS_EXT_STAT (9362L)
+#define TSM_NTTS_EXT_STAT_PRIMARY_ID (9363L)
+#define TSM_NTTS_EXT_STAT_PRIMARY_REV (9364L)
+#define TSM_NTTS_EXT_STAT_PRIMARY_STAT (9365L)
+#define TSM_NTTS_LIMIT_HI (9366L)
+#define TSM_NTTS_LIMIT_HI_SEC (9367L)
+#define TSM_NTTS_LIMIT_LO (9368L)
+#define TSM_NTTS_LIMIT_LO_NS (9369L)
+#define TSM_NTTS_OFFSET (9370L)
+#define TSM_NTTS_OFFSET_NS (9371L)
+#define TSM_NTTS_SAMPLE_HI (9372L)
+#define TSM_NTTS_SAMPLE_HI_SEC (9373L)
+#define TSM_NTTS_SAMPLE_LO (9374L)
+#define TSM_NTTS_SAMPLE_LO_NS (9375L)
+#define TSM_NTTS_STAT (9376L)
+#define TSM_NTTS_STAT_NTTS_VALID (9377L)
+#define TSM_NTTS_STAT_SIGNAL_LOST (9378L)
+#define TSM_NTTS_STAT_SYNC_LOST (9379L)
+#define TSM_NTTS_TS_T0_HI (9380L)
+#define TSM_NTTS_TS_T0_HI_TIME (9381L)
+#define TSM_NTTS_TS_T0_LO (9382L)
+#define TSM_NTTS_TS_T0_LO_TIME (9383L)
+#define TSM_NTTS_TS_T0_OFFSET (9384L)
+#define TSM_NTTS_TS_T0_OFFSET_COUNT (9385L)
+#define TSM_OFFSET_HI (9386L)
+#define TSM_OFFSET_HI_OFFSET (9387L)
+#define TSM_OFFSET_LO (9388L)
+#define TSM_OFFSET_LO_OFFSET (9389L)
+#define TSM_PB_CTRL (9390L)
+#define TSM_PB_CTRL_INSTMEM_WR (9391L)
+#define TSM_PB_CTRL_RESET (9392L)
+#define TSM_PB_CTRL_RST (9393L)
+#define TSM_PB_INSTMEM (9394L)
+#define TSM_PB_INSTMEM_ADDR (9395L)
+#define TSM_PB_INSTMEM_DATA (9396L)
+#define TSM_PB_INSTMEM_MEM_ADDR (9397L)
+#define TSM_PB_INSTMEM_MEM_DATA (9398L)
+#define TSM_PI_CTRL_I (9399L)
+#define TSM_PI_CTRL_I_VAL (9400L)
+#define TSM_PI_CTRL_KI (9401L)
+#define TSM_PI_CTRL_KI_GAIN (9402L)
+#define TSM_PI_CTRL_KP (9403L)
+#define TSM_PI_CTRL_KP_GAIN (9404L)
+#define TSM_PI_CTRL_SHL (9405L)
+#define TSM_PI_CTRL_SHL_VAL (9406L)
+#define TSM_RSYNC_COUNT (9407L)
+#define TSM_RSYNC_COUNT_COUNT (9408L)
+#define TSM_STAT (9409L)
+#define TSM_STAT_EXT_SRC_OK (9410L)
+#define TSM_STAT_HARD_SYNC (9411L)
+#define TSM_STAT_INSYNC (9412L)
+#define TSM_STAT_LINK_ACTIVE (9413L)
+#define TSM_STAT_LINK_CON0 (9414L)
+#define TSM_STAT_LINK_CON1 (9415L)
+#define TSM_STAT_LINK_CON2 (9416L)
+#define TSM_STAT_LINK_CON3 (9417L)
+#define TSM_STAT_LINK_CON4 (9418L)
+#define TSM_STAT_LINK_CON5 (9419L)
+#define TSM_STAT_NTTS_INSYNC (9420L)
+#define TSM_STAT_PTP_MI_PRESENT (9421L)
+#define TSM_TIMER_CTRL (9422L)
+#define TSM_TIMER_CTRL_TIMER_EN_T0 (9423L)
+#define TSM_TIMER_CTRL_TIMER_EN_T1 (9424L)
+#define TSM_TIMER_CTRL_TRIGGER_SEL (9425L)
+#define TSM_TIMER_D_T0 (9426L)
+#define TSM_TIMER_D_T0_MAX_COUNT (9427L)
+#define TSM_TIMER_T0 (9428L)
+#define TSM_TIMER_T0_MAX_COUNT (9429L)
+#define TSM_TIMER_T1 (9430L)
+#define TSM_TIMER_T1_MAX_COUNT (9431L)
+#define TSM_TIMESTAMP_HI (9432L)
+#define TSM_TIMESTAMP_HI_TIME (9433L)
+#define TSM_TIMESTAMP_LO (9434L)
+#define TSM_TIMESTAMP_LO_TIME (9435L)
+#define TSM_TIME_HARDSET_HI (9436L)
+#define TSM_TIME_HARDSET_HI_TIME (9437L)
+#define TSM_TIME_HARDSET_LO (9438L)
+#define TSM_TIME_HARDSET_LO_TIME (9439L)
+#define TSM_TIME_HI (9440L)
+#define TSM_TIME_HI_SEC (9441L)
+#define TSM_TIME_HI_TIME (9442L)
+#define TSM_TIME_LO (9443L)
+#define TSM_TIME_LO_NS (9444L)
+#define TSM_TIME_RATE_ADJ (9445L)
+#define TSM_TIME_RATE_ADJ_FRACTION (9446L)
+#define TSM_TS_HI (9447L)
+#define TSM_TS_HI_TIME (9448L)
+#define TSM_TS_LO (9449L)
+#define TSM_TS_LO_TIME (9450L)
+#define TSM_TS_OFFSET (9451L)
+#define TSM_TS_OFFSET_NS (9452L)
+#define TSM_TS_STAT (9453L)
+#define TSM_TS_STAT_OVERRUN (9454L)
+#define TSM_TS_STAT_SAMPLES (9455L)
+#define TSM_TS_STAT_HI_OFFSET (9456L)
+#define TSM_TS_STAT_HI_OFFSET_NS (9457L)
+#define TSM_TS_STAT_LO_OFFSET (9458L)
+#define TSM_TS_STAT_LO_OFFSET_NS (9459L)
+#define TSM_TS_STAT_TAR_HI (9460L)
+#define TSM_TS_STAT_TAR_HI_SEC (9461L)
+#define TSM_TS_STAT_TAR_LO (9462L)
+#define TSM_TS_STAT_TAR_LO_NS (9463L)
+#define TSM_TS_STAT_X (9464L)
+#define TSM_TS_STAT_X_NS (9465L)
+#define TSM_TS_STAT_X2_HI (9466L)
+#define TSM_TS_STAT_X2_HI_NS (9467L)
+#define TSM_TS_STAT_X2_LO (9468L)
+#define TSM_TS_STAT_X2_LO_NS (9469L)
+#define TSM_UTC_OFFSET (9470L)
+#define TSM_UTC_OFFSET_SEC (9471L)
+
+#endif /* _NTHW_FPGA_REGISTERS_DEFS_ */