diff mbox series

[v2,01/10] net/octeon_ep: support cnf95n and cnf95o SoC

Message ID	20230405142537.1899973-2-sedara@marvell.com (mailing list archive)
State	Changes Requested, archived
Delegated to:	Jerin Jacob
Headers	From: Sathesh Edara <sedara@marvell.com> To: <sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>, "Radha Mohan Chintakuntla" <radhac@marvell.com>, Veerasenareddy Burru <vburru@marvell.com> CC: <dev@dpdk.org> Subject: [PATCH v2 01/10] net/octeon_ep: support cnf95n and cnf95o SoC Date: Wed, 5 Apr 2023 07:25:27 -0700 Message-ID: <20230405142537.1899973-2-sedara@marvell.com> In-Reply-To: <20230405142537.1899973-1-sedara@marvell.com> References: <20230404141855.1025625-2-sedara@marvell.com> <20230405142537.1899973-1-sedara@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Precedence: list Errors-To: dev-bounces@dpdk.org
Series	extend octeon ep driver functionality \| [v2,00/10] extend octeon ep driver functionality [v2,01/10] net/octeon_ep: support cnf95n and cnf95o SoC [v2,02/10] net/octeon_ep: support CNX10K series SoC [v2,03/10] net/octeon_ep: support error propagation [v2,04/10] net/octeon_ep: support IQ/OQ reset [v2,05/10] net/octeon_ep: support ISM [v2,06/10] net/octeon_ep: fix DMA incompletion [v2,07/10] net/octeon_ep: update queue size checks [v2,08/10] net/octeon_ep: support Mailbox between VF and PF [v2,09/10] net/octeon_ep: set watermark for output queues [v2,10/10] net/octeon_ep: set secondary process dev ops

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Sathesh B Edara April 5, 2023, 2:25 p.m. UTC

  This patch adds the required functionality in the Octeon endpoint
driver to support the cnf95n and cnf95o endpoint device.

Signed-off-by: Sathesh Edara <sedara@marvell.com>
---
 drivers/net/octeon_ep/otx2_ep_vf.h    |  2 ++
 drivers/net/octeon_ep/otx_ep_ethdev.c | 13 +++++++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/drivers/net/octeon_ep/otx2_ep_vf.h b/drivers/net/octeon_ep/otx2_ep_vf.h
index 757eeae9f0..8f00acd737 100644
--- a/drivers/net/octeon_ep/otx2_ep_vf.h
+++ b/drivers/net/octeon_ep/otx2_ep_vf.h
@@ -115,6 +115,8 @@ 
 
 #define PCI_DEVID_CN9K_EP_NET_VF		0xB203 /* OCTEON 9 EP mode */
 #define PCI_DEVID_CN98XX_EP_NET_VF		0xB103
+#define PCI_DEVID_CNF95N_EP_NET_VF		0xB403
+#define PCI_DEVID_CNF95O_EP_NET_VF		0xB603
 
 int
 otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);
diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c
index f43db1e398..24f62c3e49 100644
--- a/drivers/net/octeon_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c
@@ -105,6 +105,8 @@  otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
 		break;
 	case PCI_DEVID_CN9K_EP_NET_VF:
 	case PCI_DEVID_CN98XX_EP_NET_VF:
+	case PCI_DEVID_CNF95N_EP_NET_VF:
+	case PCI_DEVID_CNF95O_EP_NET_VF:
 		otx_epvf->chip_id = dev_id;
 		ret = otx2_ep_vf_setup_device(otx_epvf);
 		otx_epvf->fn_list.disable_io_queues(otx_epvf);
@@ -144,7 +146,9 @@  otx_epdev_init(struct otx_ep_device *otx_epvf)
 	if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF)
 		otx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;
 	else if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||
-		 otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF)
+		 otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||
+		 otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||
+		 otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)
 		otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
 	else if (otx_epvf->chip_id == PCI_DEVID_CNXK_EP_NET_VF)
 		otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
@@ -494,7 +498,10 @@  otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
 	otx_epvf->pdev = pdev;
 
 	otx_epdev_init(otx_epvf);
-	if (pdev->id.device_id == PCI_DEVID_CN9K_EP_NET_VF)
+	if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||
+	    otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||
+	    otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||
+	    otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)
 		otx_epvf->pkind = SDP_OTX2_PKIND_FS0;
 	else
 		otx_epvf->pkind = SDP_PKIND;
@@ -524,6 +531,8 @@  static const struct rte_pci_id pci_id_otx_ep_map[] = {
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_EP_NET_VF) },
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95N_EP_NET_VF) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95O_EP_NET_VF) },
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_EP_NET_VF) },
 	{ .vendor_id = 0, /* sentinel */ }
 };