diff mbox series

[1/2] net/igc/base: support Tx timestamp offload

Message ID 20221220034741.447037-2-simei.su@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series net/igc: support Tx timestamp offload |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation warning apply patch failure
ci/iol-testing warning apply patch failure

Commit Message

Simei Su Dec. 20, 2022, 3:47 a.m. UTC 
  Add definitions for Tx timestamp offload
"RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP".

Signed-off-by: Simei Su <simei.su@intel.com>
---
 drivers/net/igc/base/igc_defines.h | 9 +++++++++
 drivers/net/igc/base/igc_regs.h    | 8 ++++++++
 2 files changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/igc/base/igc_defines.h b/drivers/net/igc/base/igc_defines.h
index dd7330a..280570b 100644
--- a/drivers/net/igc/base/igc_defines.h
+++ b/drivers/net/igc/base/igc_defines.h
@@ -188,6 +188,15 @@ 
 #define IGC_RCTL_BSEX		0x02000000 /* Buffer size extension */
 #define IGC_RCTL_SECRC	0x04000000 /* Strip Ethernet CRC */
 
+#define IGC_DTXMXPKTSZ_TSN     0x19 /* 1600 bytes of max TX DMA packet size */
+#define IGC_TXPBSIZE_TSN       0x04145145 /* 5k bytes buffer for each queue */
+
+/* Transmit Scheduling */
+#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001
+#define IGC_TQAVCTRL_ENHANCED_QAV      0x00000008
+
+#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT  0x00000001
+
 /* Use byte values for the following shift parameters
  * Usage:
  *     psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) &
diff --git a/drivers/net/igc/base/igc_regs.h b/drivers/net/igc/base/igc_regs.h
index d424387..e423814 100644
--- a/drivers/net/igc/base/igc_regs.h
+++ b/drivers/net/igc/base/igc_regs.h
@@ -602,6 +602,14 @@ 
 #define IGC_RXMTRL	0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
 #define IGC_RXUDP	0x0B638 /* Time Sync Rx UDP Port - RW */
 
+#define IGC_QBVCYCLET	0x331C
+#define IGC_QBVCYCLET_S 0x3320
+#define IGC_STQT(_n)	(0x3324 + 0x4 * (_n))
+#define IGC_ENDQT(_n)	(0x3334 + 0x4 * (_n))
+#define IGC_TXQCTL(_n)	(0x3344 + 0x4 * (_n))
+#define IGC_BASET_L	0x3314
+#define IGC_BASET_H	0x3318
+
 /* Filtering Registers */
 #define IGC_SAQF(_n)	(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
 #define IGC_DAQF(_n)	(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */