[v5,2/2] eal: add power mgmt support on Arm
Checks
Commit Message
For Arm aarch, use WFE instruction to enable power monitor API, and use
SEV instruction to enable wake up API.
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: David Hunt <david.hunt@intel.com>
---
lib/eal/arm/include/rte_pause_64.h | 5 ++-
lib/eal/arm/rte_cpuflags.c | 5 +++
lib/eal/arm/rte_power_intrinsics.c | 72 ++++++++++++++++++++++++++++--
3 files changed, 78 insertions(+), 4 deletions(-)
Comments
On Wed, 14 Dec 2022 16:14:30 +0800
Feifei Wang <feifei.wang2@arm.com> wrote:
> +__check_val_size(const uint8_t sz)
> +{
> + switch (sz) {
> + case sizeof(uint8_t): /* fall-through */
> + case sizeof(uint16_t): /* fall-through */
> + case sizeof(uint32_t): /* fall-through */
> + case sizeof(uint64_t): /* fall-through */
> + return 0;
> + default:
> + /* unexpected size */
> + return -1;
> + }
> +}
> +#endif
One simplification would be to get rid of this function
and just check for unexpected size in the switch
statement in rte_power_monitor().
> + switch (pmc->size) {
> + case sizeof(uint8_t):
> + __RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value, __ATOMIC_RELAXED);
> + __RTE_ARM_WFE()
> + break;
> + case sizeof(uint16_t):
> + __RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value, __ATOMIC_RELAXED);
> + __RTE_ARM_WFE()
> + break;
> + case sizeof(uint32_t):
> + __RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value, __ATOMIC_RELAXED);
> + __RTE_ARM_WFE()
> + break;
> + case sizeof(uint64_t):
> + __RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value, __ATOMIC_RELAXED);
> + __RTE_ARM_WFE()
default:
return -1; /* unexpected size */
> + }
> -----邮件原件-----
> 发件人: Stephen Hemminger <stephen@networkplumber.org>
> 发送时间: Saturday, February 18, 2023 12:23 AM
> 收件人: Feifei Wang <Feifei.Wang2@arm.com>
> 抄送: Ruifeng Wang <Ruifeng.Wang@arm.com>; dev@dpdk.org; nd
> <nd@arm.com>; David Hunt <david.hunt@intel.com>
> 主题: Re: [PATCH v5 2/2] eal: add power mgmt support on Arm
>
> On Wed, 14 Dec 2022 16:14:30 +0800
> Feifei Wang <feifei.wang2@arm.com> wrote:
>
> > +__check_val_size(const uint8_t sz)
> > +{
> > + switch (sz) {
> > + case sizeof(uint8_t): /* fall-through */
> > + case sizeof(uint16_t): /* fall-through */
> > + case sizeof(uint32_t): /* fall-through */
> > + case sizeof(uint64_t): /* fall-through */
> > + return 0;
> > + default:
> > + /* unexpected size */
> > + return -1;
> > + }
> > +}
> > +#endif
>
> One simplification would be to get rid of this function and just check for
> unexpected size in the switch statement in rte_power_monitor().
Thanks for the comments.
__check_val_size API is following intel path. And agree with your comments,
for arm path, it is unnecessary.
Thus I will delete __check_val_size and simplify the code.
Best Regards
Feifei
>
> > + switch (pmc->size) {
> > + case sizeof(uint8_t):
> > + __RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > + __RTE_ARM_WFE()
> > + break;
> > + case sizeof(uint16_t):
> > + __RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > + __RTE_ARM_WFE()
> > + break;
> > + case sizeof(uint32_t):
> > + __RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > + __RTE_ARM_WFE()
> > + break;
> > + case sizeof(uint64_t):
> > + __RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > + __RTE_ARM_WFE()
>
> default:
> return -1; /* unexpected size */
> > + }
@@ -25,9 +25,12 @@ static inline void rte_pause(void)
#ifdef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED
-/* Send an event to quit WFE. */
+/* Send a local event to quit WFE. */
#define __RTE_ARM_SEVL() { asm volatile("sevl" : : : "memory"); }
+/* Send a global event to quit WFE for all cores. */
+#define __RTE_ARM_SEV() { asm volatile("sev" : : : "memory"); }
+
/* Put processor into low power WFE(Wait For Event) state. */
#define __RTE_ARM_WFE() { asm volatile("wfe" : : : "memory"); }
@@ -163,4 +163,9 @@ void
rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
{
memset(intrinsics, 0, sizeof(*intrinsics));
+
+#ifdef RTE_ARM_USE_WFE
+ intrinsics->power_monitor = 1;
+#endif
+
}
@@ -6,17 +6,75 @@
#include "rte_power_intrinsics.h"
+#ifdef RTE_ARM_USE_WFE
+static inline int
+__check_val_size(const uint8_t sz)
+{
+ switch (sz) {
+ case sizeof(uint8_t): /* fall-through */
+ case sizeof(uint16_t): /* fall-through */
+ case sizeof(uint32_t): /* fall-through */
+ case sizeof(uint64_t): /* fall-through */
+ return 0;
+ default:
+ /* unexpected size */
+ return -1;
+ }
+}
+#endif
+
/**
- * This function is not supported on ARM.
+ * This function uses WFE instruction to make lcore suspend
+ * execution on ARM.
+ * Note that timestamp based timeout is not supported yet.
*/
int
rte_power_monitor(const struct rte_power_monitor_cond *pmc,
const uint64_t tsc_timestamp)
{
- RTE_SET_USED(pmc);
RTE_SET_USED(tsc_timestamp);
+#ifdef RTE_ARM_USE_WFE
+ const unsigned int lcore_id = rte_lcore_id();
+ uint64_t cur_value;
+
+ /* prevent non-EAL thread from using this API */
+ if (lcore_id >= RTE_MAX_LCORE)
+ return -EINVAL;
+
+ if (pmc == NULL)
+ return -EINVAL;
+
+ if (__check_val_size(pmc->size) < 0)
+ return -EINVAL;
+
+ if (pmc->fn == NULL)
+ return -EINVAL;
+
+ switch (pmc->size) {
+ case sizeof(uint8_t):
+ __RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value, __ATOMIC_RELAXED);
+ __RTE_ARM_WFE()
+ break;
+ case sizeof(uint16_t):
+ __RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value, __ATOMIC_RELAXED);
+ __RTE_ARM_WFE()
+ break;
+ case sizeof(uint32_t):
+ __RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value, __ATOMIC_RELAXED);
+ __RTE_ARM_WFE()
+ break;
+ case sizeof(uint64_t):
+ __RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value, __ATOMIC_RELAXED);
+ __RTE_ARM_WFE()
+ }
+
+ return 0;
+#else
+ RTE_SET_USED(pmc);
+
return -ENOTSUP;
+#endif
}
/**
@@ -31,14 +89,22 @@ rte_power_pause(const uint64_t tsc_timestamp)
}
/**
- * This function is not supported on ARM.
+ * This function uses SEV instruction to wake up all cores
+ * on ARM.
+ * Note that lcore_id is not used here.
*/
int
rte_power_monitor_wakeup(const unsigned int lcore_id)
{
RTE_SET_USED(lcore_id);
+#ifdef RTE_ARM_USE_WFE
+ __RTE_ARM_SEV()
+
+ return 0;
+#else
return -ENOTSUP;
+#endif
}
int