[v4,3/3] doc: simplify and clarify the configuration steps

Message ID 20221128231940.15961-4-nicolas.chautru@intel.com (mailing list archive)
State Superseded
Delegated to: Thomas Monjalon
Headers
Series doc: simplify bbdev PMD steps |

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Commit Message

Chautru, Nicolas Nov. 28, 2022, 11:19 p.m. UTC
  Simplification of the device configuration steps which had
become a bit stale over time.
Next level of details captured in pf_bb_config
if required for maintanability.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
 doc/guides/bbdevs/acc100.rst        | 13 ++---
 doc/guides/bbdevs/acc200.rst        | 19 ++++---
 doc/guides/bbdevs/fpga_5gnr_fec.rst | 81 +++--------------------------
 doc/guides/bbdevs/fpga_lte_fec.rst  | 81 +++--------------------------
 4 files changed, 30 insertions(+), 164 deletions(-)
  

Patch

diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst
index 60fccd3bc8..ddcab078fd 100644
--- a/doc/guides/bbdevs/acc100.rst
+++ b/doc/guides/bbdevs/acc100.rst
@@ -111,18 +111,19 @@  See :ref:`linux_gsg_binding_kernel` section for more details, notably with regar
 generic kernel modules binding and VF enablement.
 More details on usage model is captured in the :ref:`pf_bb_config_acc100` section.
 
+Device configuration
+~~~~~~~~~~~~~~~~~~~~
 
-Configure the VFs through PF
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The PCI virtual functions must be configured before working or getting assigned
-to VMs/Containers. The configuration involves allocating the number of hardware
+The device must be configured to work properly.
+The configuration involves allocating the number of hardware
 queues, priorities, load balance, bandwidth and other settings necessary for the
 device to perform FEC functions.
 
 This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the functions ``rte_acc10x_configure()``,
+be achieved by either using ``pf_bb_config`` or the function ``rte_acc10x_configure()``,
 which sets up the parameters defined in the compatible ``acc100_conf`` structure.
+This is the method used in the bbdev-test test application.
+
 
 Test Application
 ----------------
diff --git a/doc/guides/bbdevs/acc200.rst b/doc/guides/bbdevs/acc200.rst
index 410f18d9bc..7a663c835c 100644
--- a/doc/guides/bbdevs/acc200.rst
+++ b/doc/guides/bbdevs/acc200.rst
@@ -120,19 +120,18 @@  See :ref:`linux_gsg_binding_kernel` section for more details, notably with regar
 generic kernel modules binding and VF enablement.
 More details on usage model is captured in the :ref:`pf_bb_config_acc200` section.
 
+Device configuration
+~~~~~~~~~~~~~~~~~~~~
 
-Configure the VFs through PF
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The device must be configured to work properly.
+The configuration involves allocating the number of hardware
+queues, priorities, load balance, bandwidth and other settings necessary for the
+device to perform FEC functions.
 
-The PCI virtual functions must be configured before working or getting assigned
-to VMs/Containers.
-The configuration involves allocating the number of hardware queues, priorities,
-load balance, bandwidth and other settings necessary for the device
-to perform FEC functions.
-
-This configuration needs to be executed at least once after reboot or PCI FLR
-and can be achieved by using the functions ``rte_acc200_configure()``,
+This configuration needs to be executed at least once after reboot or PCI FLR and can
+be achieved by either using ``pf_bb_config ``or the function ``rte_acc200_configure()``,
 which sets up the parameters defined in the compatible ``acc200_conf`` structure.
+This is the method used in the bbdev-test test application.
 
 
 Test Application
diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst
index b2afd1bb2a..09ad14c239 100644
--- a/doc/guides/bbdevs/fpga_5gnr_fec.rst
+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst
@@ -81,85 +81,18 @@  See :ref:`linux_gsg_binding_kernel` section for more details, notably with regar
 generic kernel modules binding and VF enablement.
 More details on usage model is captured in the :ref:`pf_bb_config_fpga_5gnr` section.
 
+Device configuration
+~~~~~~~~~~~~~~~~~~~~
 
-Configure the VFs through PF
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The PCI virtual functions must be configured before working or getting assigned
-to VMs/Containers. The configuration involves allocating the number of hardware
+The device must be configured to work properly.
+The configuration involves allocating the number of hardware
 queues, priorities, load balance, bandwidth and other settings necessary for the
 device to perform FEC functions.
 
 This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the function ``rte_fpga_5gnr_fec_configure()``, which sets up the
-parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
-
-.. code-block:: c
-
-  struct rte_fpga_5gnr_fec_conf {
-      bool pf_mode_en;
-      uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
-      uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
-      uint8_t ul_bandwidth;
-      uint8_t dl_bandwidth;
-      uint8_t ul_load_balance;
-      uint8_t dl_load_balance;
-      uint16_t flr_time_out;
-  };
-
-- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
-  VFs are mutually exclusive and cannot run simultaneously.
-  Set to 1 for PF mode enabled.
-  If PF mode is enabled all queues available in the device are assigned
-  exclusively to PF and 0 queues given to VFs.
-
-- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
-
-- ``*l_bandwidth``: in case of congestion on PCIe interface. The device
-  allocates different bandwidth to UL and DL. The weight is configured by this
-  setting. The unit of weight is 3 code blocks. For example, if the code block
-  cbps (code block per second) ratio between UL and DL is 12:1, then the
-  configuration value should be set to 36:3. The schedule algorithm is based
-  on code block regardless the length of each block.
-
-- ``*l_load_balance``: hardware queues are load-balanced in a round-robin
-  fashion. Queues get filled first-in first-out until they reach a pre-defined
-  watermark level, if exceeded, they won't get assigned new code blocks..
-  This watermark is defined by this setting.
-
-  If all hardware queues exceeds the watermark, no code blocks will be
-  streamed in from UL/DL code block FIFO.
-
-- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
-  time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
-  the FLR time out then set this setting to 0x262=610.
-
-
-An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown
-below:
-
-.. code-block:: c
-
-  struct rte_fpga_5gnr_fec_conf conf;
-  unsigned int i;
-
-  memset(&conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf));
-  conf.pf_mode_en = 1;
-
-  for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
-      conf.vf_ul_queues_number[i] = 4;
-      conf.vf_dl_queues_number[i] = 4;
-  }
-  conf.ul_bandwidth = 12;
-  conf.dl_bandwidth = 5;
-  conf.dl_load_balance = 64;
-  conf.ul_load_balance = 64;
-
-  /* setup FPGA PF */
-  ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);
-  TEST_ASSERT_SUCCESS(ret,
-      "Failed to configure 4G FPGA PF for bbdev %s",
-      info->dev_name);
+be achieved by either using ``pf_bb_config`` or the function ``rte_fpga_5gnr_fec_configure()``,
+which sets up the parameters defined in the compatible ``rte_fpga_5gnr_fec_conf`` structure.
+This is the method used in the bbdev-test test application.
 
 
 Test Application
diff --git a/doc/guides/bbdevs/fpga_lte_fec.rst b/doc/guides/bbdevs/fpga_lte_fec.rst
index 5e867c6bbd..a87f3103ca 100644
--- a/doc/guides/bbdevs/fpga_lte_fec.rst
+++ b/doc/guides/bbdevs/fpga_lte_fec.rst
@@ -80,85 +80,18 @@  See :ref:`linux_gsg_binding_kernel` section for more details, notably with regar
 generic kernel modules binding and VF enablement.
 More details on usage model is captured in the :ref:`pf_bb_config_fpga_lte` section.
 
+Device configuration
+~~~~~~~~~~~~~~~~~~~~
 
-Configure the VFs through PF
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The PCI virtual functions must be configured before working or getting assigned
-to VMs/Containers. The configuration involves allocating the number of hardware
+The device must be configured to work properly.
+The configuration involves allocating the number of hardware
 queues, priorities, load balance, bandwidth and other settings necessary for the
 device to perform FEC functions.
 
 This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the function ``rte_fpga_lte_fec_configure()``, which sets up the
-parameters defined in ``rte_fpga_lte_fec_conf`` structure:
-
-.. code-block:: c
-
-  struct rte_fpga_lte_fec_conf {
-      bool pf_mode_en;
-      uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS];
-      uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS];
-      uint8_t ul_bandwidth;
-      uint8_t dl_bandwidth;
-      uint8_t ul_load_balance;
-      uint8_t dl_load_balance;
-      uint16_t flr_time_out;
-  };
-
-- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
-  VFs are mutually exclusive and cannot run simultaneously.
-  Set to 1 for PF mode enabled.
-  If PF mode is enabled all queues available in the device are assigned
-  exclusively to PF and 0 queues given to VFs.
-
-- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
-
-- ``*l_bandwidth``: in case of congestion on PCIe interface. The device
-  allocates different bandwidth to UL and DL. The weight is configured by this
-  setting. The unit of weight is 3 code blocks. For example, if the code block
-  cbps (code block per second) ratio between UL and DL is 12:1, then the
-  configuration value should be set to 36:3. The schedule algorithm is based
-  on code block regardless the length of each block.
-
-- ``*l_load_balance``: hardware queues are load-balanced in a round-robin
-  fashion. Queues get filled first-in first-out until they reach a pre-defined
-  watermark level, if exceeded, they won't get assigned new code blocks..
-  This watermark is defined by this setting.
-
-  If all hardware queues exceeds the watermark, no code blocks will be
-  streamed in from UL/DL code block FIFO.
-
-- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
-  time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
-  the FLR time out then set this setting to 0x262=610.
-
-
-An example configuration code calling the function ``rte_fpga_lte_fec_configure()`` is shown
-below:
-
-.. code-block:: c
-
-  struct rte_fpga_lte_fec_conf conf;
-  unsigned int i;
-
-  memset(&conf, 0, sizeof(struct rte_fpga_lte_fec_conf));
-  conf.pf_mode_en = 1;
-
-  for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {
-      conf.vf_ul_queues_number[i] = 4;
-      conf.vf_dl_queues_number[i] = 4;
-  }
-  conf.ul_bandwidth = 12;
-  conf.dl_bandwidth = 5;
-  conf.dl_load_balance = 64;
-  conf.ul_load_balance = 64;
-
-  /* setup FPGA PF */
-  ret = rte_fpga_lte_fec_configure(info->dev_name, &conf);
-  TEST_ASSERT_SUCCESS(ret,
-      "Failed to configure 4G FPGA PF for bbdev %s",
-      info->dev_name);
+be achieved by either using ``pf_bb_config`` or the function ``rte_fpga_lte_fec_configure()``,
+which sets up the parameters defined in the compatible ``rte_fpga_lte_fec_conf`` structure.
+This is the method used in the bbdev-test test application.
 
 
 Test Application