diff mbox series

[1/2] examples/ipsec-secgw: use Tx cksum offload conditionally

Message ID 20220721153132.3570-1-ndabilpuram@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series [1/2] examples/ipsec-secgw: use Tx cksum offload conditionally |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram July 21, 2022, 3:31 p.m. UTC 
  Use Tx checksum offload only when all the ports have it enabled as
the qconf for a particular lcore stores ipv4_offloads for all the
Tx ports and each lcore can Tx to any port.

Fixes: 03128be4cd4d ("examples/ipsec-secgw: allow disabling some Rx/Tx offloads")
Cc: konstantin.ananyev@intel.com

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 examples/ipsec-secgw/ipsec-secgw.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

Comments

Akhil Goyal Aug. 25, 2022, 8:11 a.m. UTC | #1 
> Subject: [PATCH 1/2] examples/ipsec-secgw: use Tx cksum offload conditionally
> 
> Use Tx checksum offload only when all the ports have it enabled as
> the qconf for a particular lcore stores ipv4_offloads for all the
> Tx ports and each lcore can Tx to any port.
> 
> Fixes: 03128be4cd4d ("examples/ipsec-secgw: allow disabling some Rx/Tx
> offloads")
> Cc: konstantin.ananyev@intel.com
> 
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Akhil Goyal Aug. 28, 2022, 8:52 a.m. UTC | #2 
> Subject: [PATCH 1/2] examples/ipsec-secgw: use Tx cksum offload conditionally
> 
> Use Tx checksum offload only when all the ports have it enabled as
> the qconf for a particular lcore stores ipv4_offloads for all the
> Tx ports and each lcore can Tx to any port.
> 
> Fixes: 03128be4cd4d ("examples/ipsec-secgw: allow disabling some Rx/Tx
> offloads")
> Cc: konstantin.ananyev@intel.com
> 
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> ---
Series applied to dpdk-next-crypto

Thanks.
diff mbox series

Patch

diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c
index 815b925..8a25b83 100644
--- a/examples/ipsec-secgw/ipsec-secgw.c
+++ b/examples/ipsec-secgw/ipsec-secgw.c
@@ -1998,12 +1998,6 @@  port_init(uint16_t portid, uint64_t req_rx_offloads, uint64_t req_tx_offloads)
 		qconf = &lcore_conf[lcore_id];
 		qconf->tx_queue_id[portid] = tx_queueid;
 
-		/* Pre-populate pkt offloads based on capabilities */
-		qconf->outbound.ipv4_offloads = RTE_MBUF_F_TX_IPV4;
-		qconf->outbound.ipv6_offloads = RTE_MBUF_F_TX_IPV6;
-		if (local_port_conf.txmode.offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
-			qconf->outbound.ipv4_offloads |= RTE_MBUF_F_TX_IP_CKSUM;
-
 		tx_queueid++;
 
 		/* init RX queues */
@@ -2925,6 +2919,7 @@  main(int32_t argc, char **argv)
 	uint64_t req_rx_offloads[RTE_MAX_ETHPORTS];
 	uint64_t req_tx_offloads[RTE_MAX_ETHPORTS];
 	struct eh_conf *eh_conf = NULL;
+	uint32_t ipv4_cksum_port_mask = 0;
 	size_t sess_sz;
 
 	nb_bufs_in_pool = 0;
@@ -3046,6 +3041,20 @@  main(int32_t argc, char **argv)
 				&req_tx_offloads[portid]);
 		port_init(portid, req_rx_offloads[portid],
 				req_tx_offloads[portid]);
+		if ((req_tx_offloads[portid] & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
+			ipv4_cksum_port_mask = 1U << portid;
+	}
+
+	for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
+		if (rte_lcore_is_enabled(lcore_id) == 0)
+			continue;
+
+		/* Pre-populate pkt offloads based on capabilities */
+		lcore_conf[lcore_id].outbound.ipv4_offloads = RTE_MBUF_F_TX_IPV4;
+		lcore_conf[lcore_id].outbound.ipv6_offloads = RTE_MBUF_F_TX_IPV6;
+		/* Update per lcore checksum offload support only if all ports support it */
+		if (ipv4_cksum_port_mask == enabled_port_mask)
+			lcore_conf[lcore_id].outbound.ipv4_offloads |= RTE_MBUF_F_TX_IP_CKSUM;
 	}
 
 	/*