diff mbox series

[03/14] net/ice/base: post update double reset solution restriction

Message ID 20210302072357.1657556-4-qi.z.zhang@intel.com (mailing list archive)
State Accepted
Delegated to: Qi Zhang
Headers show
Series ice: base code update | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Zhang, Qi Z March 2, 2021, 7:23 a.m. UTC
Add capability which indicates double reset solution restriction.
Added "Post-update EMPR enabled" field to "Response Flags" field
(byte 19 in the response structure).

Signed-off-by: Amir Shay <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_adminq_cmd.h | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 3f2b4cd54b..a31c27a633 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -111,6 +111,7 @@  struct ice_aqc_list_caps_elem {
 #define ICE_AQC_CAPS_MAX_MTU				0x0047
 #define ICE_AQC_CAPS_IWARP				0x0051
 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE		0x0076
+#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT		0x0077
 #define ICE_AQC_CAPS_NVM_MGMT				0x0080
 
 	u8 major_ver;
@@ -1765,6 +1766,7 @@  struct ice_aqc_nvm {
 #define ICE_AQC_NVM_POR_FLAG	0	/* Used by NVM Write completion on ARQ */
 #define ICE_AQC_NVM_PERST_FLAG	1
 #define ICE_AQC_NVM_EMPR_FLAG	2
+#define ICE_AQC_NVM_EMPR_ENA		BIT(0)
 	__le16 module_typeid;
 	__le16 length;
 #define ICE_AQC_NVM_ERASE_LEN	0xFFFF