diff mbox series

[v1] eal/arm: fix clang build of native target

Message ID 20201112103157.53486-1-ruifeng.wang@arm.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers show
Series [v1] eal/arm: fix clang build of native target | expand

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ci/checkpatch warning coding style issues

Commit Message

Ruifeng Wang Nov. 12, 2020, 10:31 a.m. UTC
When doing Clang build with '-mcpu=native' on N1 platform, build failed
with:
../lib/librte_eal/arm/include/rte_atomic_64.h:76:39:
	error: instruction requires: lse
__ATOMIC128_CAS_OP(__cas_128_release, "caspl")

This is because native detection for Neoverse N1 was added in Clang-11.
Prior version of Clang's assembler doesn't know LSE support on hardware.
Fixed this for Clang earlier than version 11 by specifying architecture
for assembler.
Referred to [1] for this fix.

Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange")
Cc: stable@dpdk.org

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e0d5896bd356cd577f9710a02d7a474cdf58426b

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 lib/librte_eal/arm/include/rte_atomic_64.h | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Jerin Jacob Nov. 12, 2020, 4:37 p.m. UTC | #1
On Thu, Nov 12, 2020 at 4:02 PM Ruifeng Wang <ruifeng.wang@arm.com> wrote:
>
> When doing Clang build with '-mcpu=native' on N1 platform, build failed
> with:
> ../lib/librte_eal/arm/include/rte_atomic_64.h:76:39:
>         error: instruction requires: lse
> __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
>
> This is because native detection for Neoverse N1 was added in Clang-11.
> Prior version of Clang's assembler doesn't know LSE support on hardware.
> Fixed this for Clang earlier than version 11 by specifying architecture
> for assembler.
> Referred to [1] for this fix.
>
> Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange")
> Cc: stable@dpdk.org
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e0d5896bd356cd577f9710a02d7a474cdf58426b
>
> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>

Reviewed-by: Jerin Jacob <jerinj@marvell.com>



> ---
>  lib/librte_eal/arm/include/rte_atomic_64.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h
> index 2cef88629..7fcd17466 100644
> --- a/lib/librte_eal/arm/include/rte_atomic_64.h
> +++ b/lib/librte_eal/arm/include/rte_atomic_64.h
> @@ -46,6 +46,8 @@ rte_atomic_thread_fence(int memorder)
>  /*------------------------ 128 bit atomic operations -------------------------*/
>
>  #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
> +#define __LSE_PREAMBLE ".arch armv8-a+lse\n"
> +
>  #define __ATOMIC128_CAS_OP(cas_op_name, op_string)                          \
>  static __rte_noinline rte_int128_t                                          \
>  cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)      \
> @@ -59,6 +61,7 @@ cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)      \
>         register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0];        \
>         register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1];        \
>         asm volatile(                                                       \
> +               __LSE_PREAMBLE                                              \
>                 op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]"   \
>                 : [old0] "+r" (x0),                                         \
>                 [old1] "+r" (x1)                                            \
> @@ -76,6 +79,7 @@ __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
>  __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
>  __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
>
> +#undef __LSE_PREAMBLE
>  #undef __ATOMIC128_CAS_OP
>
>  #endif
> --
> 2.20.1
>
Honnappa Nagarahalli Nov. 12, 2020, 5:08 p.m. UTC | #2
<snip>

> 
> When doing Clang build with '-mcpu=native' on N1 platform, build failed
> with:
> ../lib/librte_eal/arm/include/rte_atomic_64.h:76:39:
> 	error: instruction requires: lse
> __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
> 
> This is because native detection for Neoverse N1 was added in Clang-11.
> Prior version of Clang's assembler doesn't know LSE support on hardware.
> Fixed this for Clang earlier than version 11 by specifying architecture for
> assembler.
> Referred to [1] for this fix.
> 
> Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange")
> Cc: stable@dpdk.org
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i
> d=e0d5896bd356cd577f9710a02d7a474cdf58426b
> 
> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>

> ---
>  lib/librte_eal/arm/include/rte_atomic_64.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h
> b/lib/librte_eal/arm/include/rte_atomic_64.h
> index 2cef88629..7fcd17466 100644
> --- a/lib/librte_eal/arm/include/rte_atomic_64.h
> +++ b/lib/librte_eal/arm/include/rte_atomic_64.h
> @@ -46,6 +46,8 @@ rte_atomic_thread_fence(int memorder)
>  /*------------------------ 128 bit atomic operations -------------------------*/
> 
>  #if defined(__ARM_FEATURE_ATOMICS) ||
> defined(RTE_ARM_FEATURE_ATOMICS)
> +#define __LSE_PREAMBLE	".arch armv8-a+lse\n"
> +
>  #define __ATOMIC128_CAS_OP(cas_op_name, op_string)                          \
>  static __rte_noinline rte_int128_t                                          \
>  cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)
> \
> @@ -59,6 +61,7 @@ cas_op_name(rte_int128_t *dst, rte_int128_t old,
> rte_int128_t updated)      \
>  	register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0];        \
>  	register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1];        \
>  	asm volatile(                                                       \
> +		__LSE_PREAMBLE
> 	    \
>  		op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]"   \
>  		: [old0] "+r" (x0),                                         \
>  		[old1] "+r" (x1)                                            \
> @@ -76,6 +79,7 @@ __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
> __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
> __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
> 
> +#undef __LSE_PREAMBLE
>  #undef __ATOMIC128_CAS_OP
> 
>  #endif
> --
> 2.20.1
Thomas Monjalon Nov. 13, 2020, 9:21 a.m. UTC | #3
> > When doing Clang build with '-mcpu=native' on N1 platform, build failed
> > with:
> > ../lib/librte_eal/arm/include/rte_atomic_64.h:76:39:
> > 	error: instruction requires: lse
> > __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
> > 
> > This is because native detection for Neoverse N1 was added in Clang-11.
> > Prior version of Clang's assembler doesn't know LSE support on hardware.
> > Fixed this for Clang earlier than version 11 by specifying architecture for
> > assembler.
> > Referred to [1] for this fix.
> > 
> > Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange")
> > Cc: stable@dpdk.org
> > 
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i
> > d=e0d5896bd356cd577f9710a02d7a474cdf58426b
> > 
> > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>

Applied, thanks
diff mbox series

Patch

diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h
index 2cef88629..7fcd17466 100644
--- a/lib/librte_eal/arm/include/rte_atomic_64.h
+++ b/lib/librte_eal/arm/include/rte_atomic_64.h
@@ -46,6 +46,8 @@  rte_atomic_thread_fence(int memorder)
 /*------------------------ 128 bit atomic operations -------------------------*/
 
 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
+#define __LSE_PREAMBLE	".arch armv8-a+lse\n"
+
 #define __ATOMIC128_CAS_OP(cas_op_name, op_string)                          \
 static __rte_noinline rte_int128_t                                          \
 cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)      \
@@ -59,6 +61,7 @@  cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)      \
 	register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0];        \
 	register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1];        \
 	asm volatile(                                                       \
+		__LSE_PREAMBLE						    \
 		op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]"   \
 		: [old0] "+r" (x0),                                         \
 		[old1] "+r" (x1)                                            \
@@ -76,6 +79,7 @@  __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
 __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
 __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
 
+#undef __LSE_PREAMBLE
 #undef __ATOMIC128_CAS_OP
 
 #endif