[v2,22/52] net/ice/base: increase timeout after PFR

Message ID 20200609120001.35110-23-qi.z.zhang@intel.com (mailing list archive)
State Superseded, archived
Delegated to: xiaolong ye
Headers
Series net/ice: base code update |

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Qi Zhang June 9, 2020, 11:59 a.m. UTC
  To allow for resets during package download, increase the timeout period
after performing a PFR. The time waited is the global config lock
timeout plus the normal PFSWR timeout.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_common.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
  

Comments

Ferruh Yigit June 11, 2020, 6:38 p.m. UTC | #1
On 6/9/2020 12:59 PM, Qi Zhang wrote:
> To allow for resets during package download, increase the timeout period
> after performing a PFR. The time waited is the global config lock
> timeout plus the normal PFSWR timeout.

Is PFR == PF Reset, right? And is this same as FLR?

> 
> Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
> Signed-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>

<...>
  
Qi Zhang June 15, 2020, 1:58 a.m. UTC | #2
> -----Original Message-----
> From: Yigit, Ferruh <ferruh.yigit@intel.com>
> Sent: Friday, June 12, 2020 2:38 AM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming <qiming.yang@intel.com>
> Cc: Ye, Xiaolong <xiaolong.ye@intel.com>; dev@dpdk.org; Nowlin, Dan
> <dan.nowlin@intel.com>; Stillwell Jr, Paul M <paul.m.stillwell.jr@intel.com>
> Subject: Re: [dpdk-dev] [PATCH v2 22/52] net/ice/base: increase timeout after
> PFR
> 
> On 6/9/2020 12:59 PM, Qi Zhang wrote:
> > To allow for resets during package download, increase the timeout
> > period after performing a PFR. The time waited is the global config
> > lock timeout plus the normal PFSWR timeout.
> 
> Is PFR == PF Reset, right? And is this same as FLR?
Yes, PFR is PF Reset, but its not same as FLR, FLR is PF level reset, which specific for operation system set FLR bit in the PCIe config
While FLR will trigger PF reset, but device driver can also setting specific register to reset the PF.

Regards
Qi
> 
> >
> > Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
> > Signed-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>
> > Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> 
> <...>
  

Patch

diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 8ba603242..a617643b6 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -912,7 +912,12 @@  static enum ice_status ice_pf_reset(struct ice_hw *hw)
 
 	wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
 
-	for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
+	/* Wait for the PFR to complete. The wait time is the global config lock
+	 * timeout plus the PFR timeout which will account for a possible reset
+	 * that is occurring during a download package operation.
+	 */
+	for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
+	     ICE_PF_RESET_WAIT_COUNT; cnt++) {
 		reg = rd32(hw, PFGEN_CTRL);
 		if (!(reg & PFGEN_CTRL_PFSWR_M))
 			break;