diff mbox series

[v3,01/11] common/mlx5: add DevX attributes for compress

Message ID 1611142175-409485-2-git-send-email-matan@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers show
Series add mlx5 compress PMD | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Matan Azrad Jan. 20, 2021, 11:29 a.m. UTC
Add the DevX attributes for compress related engines:
	- compress
	- decompress
	- dma

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 10 ++++++++++
 drivers/common/mlx5/mlx5_devx_cmds.h |  7 +++++++
 drivers/common/mlx5/mlx5_prm.h       | 18 ++++++++++++++++--
 3 files changed, 33 insertions(+), 2 deletions(-)

Comments

Tal Shnaiderman Jan. 21, 2021, 4:52 p.m. UTC | #1
> Subject: [dpdk-dev] [PATCH v3 01/11] common/mlx5: add DevX attributes
> for compress
> 
> Add the DevX attributes for compress related engines:
> 	- compress
> 	- decompress
> 	- dma
> 
> Signed-off-by: Matan Azrad <matan@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---
>  drivers/common/mlx5/mlx5_devx_cmds.c | 10 ++++++++++
> drivers/common/mlx5/mlx5_devx_cmds.h |  7 +++++++
>  drivers/common/mlx5/mlx5_prm.h       | 18 ++++++++++++++++--
>  3 files changed, 33 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index d5859c2..33acd73 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -732,6 +732,16 @@ struct mlx5_devx_obj *
>  	attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
>  	attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
>  	attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr,
> log_max_srq_sz);
> +	attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
> +	attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr,
> compress);
> +	attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr,
> decompress);
> +	attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
> +						 compress_min_block_size);
> +	attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr,
> log_dma_mmo_size);
> +	attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
> +					      log_compress_mmo_size);
> +	attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap,
> hcattr,
> +						log_decompress_mmo_size);
>  	if (attr->qos.sup) {
>  		MLX5_SET(query_hca_cap_in, in, op_mod,
>  			 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
> b/drivers/common/mlx5/mlx5_devx_cmds.h
> index bf83a90..696a981 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> @@ -130,6 +130,13 @@ struct mlx5_hca_attr {
>  	uint32_t log_max_srq;
>  	uint32_t log_max_srq_sz;
>  	uint32_t rss_ind_tbl_cap;
> +	uint32_t mmo_dma_en:1;
> +	uint32_t mmo_compress_en:1;
> +	uint32_t mmo_decompress_en:1;
> +	uint32_t compress_min_block_size:4;
> +	uint32_t log_max_mmo_dma:5;
> +	uint32_t log_max_mmo_compress:5;
> +	uint32_t log_max_mmo_decompress:5;
>  };
> 
>  struct mlx5_devx_wq_attr {
> diff --git a/drivers/common/mlx5/mlx5_prm.h
> b/drivers/common/mlx5/mlx5_prm.h index c9eba22..72c843f 100644
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -1127,7 +1127,15 @@ enum {
>  struct mlx5_ifc_cmd_hca_cap_bits {
>  	u8 reserved_at_0[0x30];
>  	u8 vhca_id[0x10];
> -	u8 reserved_at_40[0x40];
> +	u8 reserved_at_40[0x20];
> +	u8 reserved_at_60[0x3];
> +	u8 log_regexp_scatter_gather_size[0x5];
> +	u8 reserved_at_68[0x3];
> +	u8 log_dma_mmo_size[5];
> +	u8 reserved_at_70[0x3];
> +	u8 log_compress_mmo_size[5];
> +	u8 reserved_at_78[0x3];
> +	u8 log_decompress_mmo_size[5];

Small comment, PRM bit array size is always defined in hex format.

>  	u8 log_max_srq_sz[0x8];
>  	u8 log_max_qp_sz[0x8];
>  	u8 reserved_at_90[0x9];
> @@ -1175,7 +1183,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {
>  	u8 log_max_ra_res_dc[0x6];
>  	u8 reserved_at_140[0xa];
>  	u8 log_max_ra_req_qp[0x6];
> -	u8 reserved_at_150[0xa];
> +	u8 rtr2rts_qp_counters_set_id[1];
> +	u8 rts2rts_udp_sport[1];
> +	u8 rts2rts_lag_tx_port_affinity[1];
> +	u8 dma_mmo[1];
> +	u8 compress_min_block_size[4];
> +	u8 compress[1];
> +	u8 decompress[1];

Same.

>  	u8 log_max_ra_res_qp[0x6];
>  	u8 end_pad[0x1];
>  	u8 cc_query_allowed[0x1];
> --
> 1.8.3.1
Matan Azrad Jan. 21, 2021, 5:10 p.m. UTC | #2
From: Tal Shnaiderman
> Sent: Thursday, January 21, 2021 6:52 PM
> To: Matan Azrad <matan@nvidia.com>; dev@dpdk.org
> Cc: NBU-Contact-Thomas Monjalon <thomas@monjalon.net>; Ashish Gupta
> <ashish.gupta@marvell.com>; Fiona Trahe <fiona.trahe@intel.com>;
> akhil.goyal@nxp.com
> Subject: RE: [dpdk-dev] [PATCH v3 01/11] common/mlx5: add DevX attributes
> for compress
> 
> > Subject: [dpdk-dev] [PATCH v3 01/11] common/mlx5: add DevX attributes
> > for compress
> >
> > Add the DevX attributes for compress related engines:
> > 	- compress
> > 	- decompress
> > 	- dma
> >
> > Signed-off-by: Matan Azrad <matan@nvidia.com>
> > Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> > ---
> >  drivers/common/mlx5/mlx5_devx_cmds.c | 10 ++++++++++
> > drivers/common/mlx5/mlx5_devx_cmds.h |  7 +++++++
> >  drivers/common/mlx5/mlx5_prm.h       | 18 ++++++++++++++++--
> >  3 files changed, 33 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> > b/drivers/common/mlx5/mlx5_devx_cmds.c
> > index d5859c2..33acd73 100644
> > --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> > +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> > @@ -732,6 +732,16 @@ struct mlx5_devx_obj *
> >  	attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
> >  	attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
> >  	attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr,
> > log_max_srq_sz);
> > +	attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
> > +	attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr,
> > compress);
> > +	attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr,
> > decompress);
> > +	attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
> > +						 compress_min_block_size);
> > +	attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr,
> > log_dma_mmo_size);
> > +	attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
> > +					      log_compress_mmo_size);
> > +	attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap,
> > hcattr,
> > +						log_decompress_mmo_size);
> >  	if (attr->qos.sup) {
> >  		MLX5_SET(query_hca_cap_in, in, op_mod,
> >  			 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git
> > a/drivers/common/mlx5/mlx5_devx_cmds.h
> > b/drivers/common/mlx5/mlx5_devx_cmds.h
> > index bf83a90..696a981 100644
> > --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> > +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> > @@ -130,6 +130,13 @@ struct mlx5_hca_attr {
> >  	uint32_t log_max_srq;
> >  	uint32_t log_max_srq_sz;
> >  	uint32_t rss_ind_tbl_cap;
> > +	uint32_t mmo_dma_en:1;
> > +	uint32_t mmo_compress_en:1;
> > +	uint32_t mmo_decompress_en:1;
> > +	uint32_t compress_min_block_size:4;
> > +	uint32_t log_max_mmo_dma:5;
> > +	uint32_t log_max_mmo_compress:5;
> > +	uint32_t log_max_mmo_decompress:5;
> >  };
> >
> >  struct mlx5_devx_wq_attr {
> > diff --git a/drivers/common/mlx5/mlx5_prm.h
> > b/drivers/common/mlx5/mlx5_prm.h index c9eba22..72c843f 100644
> > --- a/drivers/common/mlx5/mlx5_prm.h
> > +++ b/drivers/common/mlx5/mlx5_prm.h
> > @@ -1127,7 +1127,15 @@ enum {
> >  struct mlx5_ifc_cmd_hca_cap_bits {
> >  	u8 reserved_at_0[0x30];
> >  	u8 vhca_id[0x10];
> > -	u8 reserved_at_40[0x40];
> > +	u8 reserved_at_40[0x20];
> > +	u8 reserved_at_60[0x3];
> > +	u8 log_regexp_scatter_gather_size[0x5];
> > +	u8 reserved_at_68[0x3];
> > +	u8 log_dma_mmo_size[5];
> > +	u8 reserved_at_70[0x3];
> > +	u8 log_compress_mmo_size[5];
> > +	u8 reserved_at_78[0x3];
> > +	u8 log_decompress_mmo_size[5];
> 
> Small comment, PRM bit array size is always defined in hex format.
> 
> >  	u8 log_max_srq_sz[0x8];
> >  	u8 log_max_qp_sz[0x8];
> >  	u8 reserved_at_90[0x9];
> > @@ -1175,7 +1183,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {
> >  	u8 log_max_ra_res_dc[0x6];
> >  	u8 reserved_at_140[0xa];
> >  	u8 log_max_ra_req_qp[0x6];
> > -	u8 reserved_at_150[0xa];
> > +	u8 rtr2rts_qp_counters_set_id[1];
> > +	u8 rts2rts_udp_sport[1];
> > +	u8 rts2rts_lag_tx_port_affinity[1];
> > +	u8 dma_mmo[1];
> > +	u8 compress_min_block_size[4];
> > +	u8 compress[1];
> > +	u8 decompress[1];
> 
> Same.
> 
> >  	u8 log_max_ra_res_qp[0x6];
> >  	u8 end_pad[0x1];
> >  	u8 cc_query_allowed[0x1];
> > --
> > 1.8.3.1

Yes, not look urgent, Akhil let me know if you can take it in integration or need to send more version for all the series because of it.
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index d5859c2..33acd73 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -732,6 +732,16 @@  struct mlx5_devx_obj *
 	attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 	attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 	attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
+	attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
+	attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
+	attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
+	attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
+						 compress_min_block_size);
+	attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
+	attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
+					      log_compress_mmo_size);
+	attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
+						log_decompress_mmo_size);
 	if (attr->qos.sup) {
 		MLX5_SET(query_hca_cap_in, in, op_mod,
 			 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index bf83a90..696a981 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -130,6 +130,13 @@  struct mlx5_hca_attr {
 	uint32_t log_max_srq;
 	uint32_t log_max_srq_sz;
 	uint32_t rss_ind_tbl_cap;
+	uint32_t mmo_dma_en:1;
+	uint32_t mmo_compress_en:1;
+	uint32_t mmo_decompress_en:1;
+	uint32_t compress_min_block_size:4;
+	uint32_t log_max_mmo_dma:5;
+	uint32_t log_max_mmo_compress:5;
+	uint32_t log_max_mmo_decompress:5;
 };
 
 struct mlx5_devx_wq_attr {
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index c9eba22..72c843f 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1127,7 +1127,15 @@  enum {
 struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 reserved_at_0[0x30];
 	u8 vhca_id[0x10];
-	u8 reserved_at_40[0x40];
+	u8 reserved_at_40[0x20];
+	u8 reserved_at_60[0x3];
+	u8 log_regexp_scatter_gather_size[0x5];
+	u8 reserved_at_68[0x3];
+	u8 log_dma_mmo_size[5];
+	u8 reserved_at_70[0x3];
+	u8 log_compress_mmo_size[5];
+	u8 reserved_at_78[0x3];
+	u8 log_decompress_mmo_size[5];
 	u8 log_max_srq_sz[0x8];
 	u8 log_max_qp_sz[0x8];
 	u8 reserved_at_90[0x9];
@@ -1175,7 +1183,13 @@  struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 log_max_ra_res_dc[0x6];
 	u8 reserved_at_140[0xa];
 	u8 log_max_ra_req_qp[0x6];
-	u8 reserved_at_150[0xa];
+	u8 rtr2rts_qp_counters_set_id[1];
+	u8 rts2rts_udp_sport[1];
+	u8 rts2rts_lag_tx_port_affinity[1];
+	u8 dma_mmo[1];
+	u8 compress_min_block_size[4];
+	u8 compress[1];
+	u8 decompress[1];
 	u8 log_max_ra_res_qp[0x6];
 	u8 end_pad[0x1];
 	u8 cc_query_allowed[0x1];