diff mbox series

[v1] config: enable c11 memory model for ARMv8 meson

Message ID 1544500550-193166-1-git-send-email-gavin.hu@arm.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers show
Series [v1] config: enable c11 memory model for ARMv8 meson | expand

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Performance-Testing success Performance Testing PASS
ci/mellanox-Performance-Testing success Performance Testing PASS

Commit Message

Gavin Hu Dec. 11, 2018, 3:55 a.m. UTC
This patch makes the configuration based on makefile and the
configuration based on meson to be the same.

Fixes: c6e536e38437 ("build: add more implementers IDs and PNs for ARM")
Cc: stable@dpdk.org

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Ruifeng Wang <Ruifeng.Wang@arm.com>
Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
---
 config/arm/meson.build | 3 +++
 1 file changed, 3 insertions(+)

Comments

Honnappa Nagarahalli Dec. 11, 2018, 6:02 a.m. UTC | #1
+ Bruce

> -----Original Message-----
> From: Gavin Hu <gavin.hu@arm.com>
> Sent: Monday, December 10, 2018 9:56 PM
> To: dev@dpdk.org
> Cc: thomas@monjalon.net; jerin.jacob@caviumnetworks.com;
> hemant.agrawal@nxp.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; stable@dpdk.org
> Subject: [PATCH v1] config: enable c11 memory model for ARMv8 meson
> 
> This patch makes the configuration based on makefile and the configuration
> based on meson to be the same.
> 
> Fixes: c6e536e38437 ("build: add more implementers IDs and PNs for ARM")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Ruifeng Wang <Ruifeng.Wang@arm.com>
> Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> ---
>  config/arm/meson.build | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> 3f91725..dae55d6 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -47,6 +47,7 @@ flags_common_default = [  flags_generic = [
>  	['RTE_MACHINE', '"armv8a"'],
>  	['RTE_MAX_LCORE', 256],
> +	['RTE_USE_C11_MEM_MODEL', true],
>  	['RTE_CACHE_LINE_SIZE', 128]]
>  flags_cavium = [
>  	['RTE_MACHINE', '"thunderx"'],
> @@ -57,11 +58,13 @@ flags_cavium = [
>  	['RTE_USE_C11_MEM_MODEL', false]]
>  flags_dpaa = [
>  	['RTE_MACHINE', '"dpaa"'],
> +	['RTE_USE_C11_MEM_MODEL', true],
>  	['RTE_CACHE_LINE_SIZE', 64],
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_MAX_LCORE', 16]]
>  flags_dpaa2 = [
>  	['RTE_MACHINE', '"dpaa2"'],
> +	['RTE_USE_C11_MEM_MODEL', true],
>  	['RTE_CACHE_LINE_SIZE', 64],
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_MAX_LCORE', 16],
> --
> 2.7.4
Bruce Richardson Dec. 12, 2018, 10:13 a.m. UTC | #2
On Tue, Dec 11, 2018 at 06:02:01AM +0000, Honnappa Nagarahalli wrote:
> + Bruce
> 
> > -----Original Message-----
> > From: Gavin Hu <gavin.hu@arm.com>
> > Sent: Monday, December 10, 2018 9:56 PM
> > To: dev@dpdk.org
> > Cc: thomas@monjalon.net; jerin.jacob@caviumnetworks.com;
> > hemant.agrawal@nxp.com; Honnappa Nagarahalli
> > <Honnappa.Nagarahalli@arm.com>; Gavin Hu (Arm Technology China)
> > <Gavin.Hu@arm.com>; stable@dpdk.org
> > Subject: [PATCH v1] config: enable c11 memory model for ARMv8 meson
> > 
> > This patch makes the configuration based on makefile and the configuration
> > based on meson to be the same.
> > 
> > Fixes: c6e536e38437 ("build: add more implementers IDs and PNs for ARM")
> > Cc: stable@dpdk.org
> > 
> > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > Reviewed-by: Ruifeng Wang <Ruifeng.Wang@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> > ---

I see no issues with this, it's just setting flags for arm platforms.

Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Thomas Monjalon Dec. 18, 2018, 11:36 p.m. UTC | #3
12/12/2018 11:13, Bruce Richardson:
> On Tue, Dec 11, 2018 at 06:02:01AM +0000, Honnappa Nagarahalli wrote:
> > + Bruce
> > 
> > From: Gavin Hu <gavin.hu@arm.com>
> > > 
> > > This patch makes the configuration based on makefile and the configuration
> > > based on meson to be the same.
> > > 
> > > Fixes: c6e536e38437 ("build: add more implementers IDs and PNs for ARM")
> > > Cc: stable@dpdk.org
> > > 
> > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > Reviewed-by: Ruifeng Wang <Ruifeng.Wang@arm.com>
> > > Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> > > ---
> 
> I see no issues with this, it's just setting flags for arm platforms.
> 
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Applied, thanks.

Note: according to the wording explained by Honnappa,
I change ARMv8 to armv8 in the title.
Please apply the official spelling in your updates, thanks.
	https://mails.dpdk.org/archives/dev/2018-October/115174.html
Honnappa Nagarahalli Dec. 19, 2018, 5:11 a.m. UTC | #4
> >
> > I see no issues with this, it's just setting flags for arm platforms.
> >
> > Acked-by: Bruce Richardson <bruce.richardson@intel.com>
> 
> Applied, thanks.
> 
> Note: according to the wording explained by Honnappa, I change ARMv8 to
> armv8 in the title.
> Please apply the official spelling in your updates, thanks.
> 	https://mails.dpdk.org/archives/dev/2018-October/115174.html
Thank you, we will try to catch more of these in internal reviews.

>
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 3f91725..dae55d6 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -47,6 +47,7 @@  flags_common_default = [
 flags_generic = [
 	['RTE_MACHINE', '"armv8a"'],
 	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
 	['RTE_MACHINE', '"thunderx"'],
@@ -57,11 +58,13 @@  flags_cavium = [
 	['RTE_USE_C11_MEM_MODEL', false]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
+	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 64],
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16]]
 flags_dpaa2 = [
 	['RTE_MACHINE', '"dpaa2"'],
+	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 64],
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],