diff mbox

[dpdk-dev] net/i40e: fix ethertype filter func fail on X722

Message ID 1486439539-11293-1-git-send-email-jia.guo@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel compilation fail Compilation issues

Commit Message

Guo, Jia Feb. 7, 2017, 3:52 a.m. UTC 
The GL_SWR_PRI_JOIN_MAP registers are affecting filters hit, modify
the register default value will result the ethertype filter function
fail. The GL_SWR_PRI_JOIN_MAP value is difference between different
NICs, should keep up the register value with default NVM value in X722.

Fixes: 973273c7a4b7 ("i40e: workaround for X710 performance")

Signed-off-by: Jeff Guo <jia.guo@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

Comments

Jingjing Wu Feb. 8, 2017, 9:31 a.m. UTC | #1 
> -----Original Message-----
> From: Guo, Jia
> Sent: Tuesday, February 7, 2017 11:52 AM
> To: Zhang, Helin <helin.zhang@intel.com>; Wu, Jingjing
> <jingjing.wu@intel.com>
> Cc: dev@dpdk.org; Guo, Jia <jia.guo@intel.com>
> Subject: [PATCH] net/i40e: fix ethertype filter func fail on X722
> 
> The GL_SWR_PRI_JOIN_MAP registers are affecting filters hit, modify the
> register default value will result the ethertype filter function fail. The
> GL_SWR_PRI_JOIN_MAP value is difference between different NICs, should
> keep up the register value with default NVM value in X722.
> 
> Fixes: 973273c7a4b7 ("i40e: workaround for X710 performance")
> 
> Signed-off-by: Jeff Guo <jia.guo@intel.com>

Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Ferruh Yigit Feb. 8, 2017, 1:59 p.m. UTC | #2 
On 2/8/2017 9:31 AM, Wu, Jingjing wrote:
> 
> 
>> -----Original Message-----
>> From: Guo, Jia
>> Sent: Tuesday, February 7, 2017 11:52 AM
>> To: Zhang, Helin <helin.zhang@intel.com>; Wu, Jingjing
>> <jingjing.wu@intel.com>
>> Cc: dev@dpdk.org; Guo, Jia <jia.guo@intel.com>
>> Subject: [PATCH] net/i40e: fix ethertype filter func fail on X722
>>
>> The GL_SWR_PRI_JOIN_MAP registers are affecting filters hit, modify the
>> register default value will result the ethertype filter function fail. The
>> GL_SWR_PRI_JOIN_MAP value is difference between different NICs, should
>> keep up the register value with default NVM value in X722.
>>
>> Fixes: 973273c7a4b7 ("i40e: workaround for X710 performance")
>>
>> Signed-off-by: Jeff Guo <jia.guo@intel.com>
> 
> Acked-by: Jingjing Wu <jingjing.wu@intel.com>

    net/i40e: fix ethertype filter on X722

    Fixes: 92fbf2cbdff4 ("i40e: support X722 and its A0 hardware")
    Cc: stable@dpdk.org

Applied to dpdk-next-net/master, thanks.
diff mbox

Patch

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 4492bcc..49ab0de 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -8732,6 +8732,10 @@  i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
 
+/* For X722 */
+#define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
+#define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
+
 /* For X710 */
 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
 /* For XL710 */
@@ -8754,7 +8758,6 @@  i40e_dev_sync_phy_type(struct i40e_hw *hw)
 	return 0;
 }
 
-
 static void
 i40e_configure_registers(struct i40e_hw *hw)
 {
@@ -8762,8 +8765,8 @@  i40e_configure_registers(struct i40e_hw *hw)
 		uint32_t addr;
 		uint64_t val;
 	} reg_table[] = {
-		{I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
-		{I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
+		{I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
+		{I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
 		{I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
 	};
 	uint64_t reg;
@@ -8771,6 +8774,24 @@  i40e_configure_registers(struct i40e_hw *hw)
 	int ret;
 
 	for (i = 0; i < RTE_DIM(reg_table); i++) {
+		if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
+			if (hw->mac.type == I40E_MAC_X722) /* For X722 */
+				reg_table[i].val =
+					I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
+			else /* For X710/XL710/XXV710 */
+				reg_table[i].val =
+					I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
+		}
+
+		if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
+			if (hw->mac.type == I40E_MAC_X722) /* For X722 */
+				reg_table[i].val =
+					I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
+			else /* For X710/XL710/XXV710 */
+				reg_table[i].val =
+					I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
+		}
+
 		if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
 			if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
 			    I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */