[dpdk-dev,03/39] net/ixgbe/base: change endianness of PHY data
Commit Message
The latest firmware reverses the endianness of the PHY data read and
written via host interface command, so make corresponding changes
to that.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
---
drivers/net/ixgbe/base/ixgbe_osdep.h | 1 +
drivers/net/ixgbe/base/ixgbe_type.h | 4 ++--
drivers/net/ixgbe/base/ixgbe_x550.c | 4 ++--
3 files changed, 5 insertions(+), 4 deletions(-)
Comments
On 8/27/2016 4:47 PM, Xiao Wang wrote:
> The latest firmware reverses the endianness of the PHY data read and
Good to add the fw version for future references
> written via host interface command, so make corresponding changes
> to that.
>
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Hi Ferruh,
> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Tuesday, September 20, 2016 1:01 AM
> To: Wang, Xiao W <xiao.w.wang@intel.com>; Lu, Wenzhuo
> <wenzhuo.lu@intel.com>
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 03/39] net/ixgbe/base: change endianness of
> PHY data
>
> On 8/27/2016 4:47 PM, Xiao Wang wrote:
> > The latest firmware reverses the endianness of the PHY data read and
>
> Good to add the fw version for future references
I consulted ND author of the this base driver patch and got that it was fw just for x550a.
The fw change has nothing to do with the other devices.
Will emphasize this on the v2 commit log.
>
> > written via host interface command, so make corresponding changes
> > to that.
> >
> > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
>
@@ -100,6 +100,7 @@ enum {
#define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
#define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)
#define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)
+#define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i)
typedef uint8_t u8;
typedef int8_t s8;
@@ -3136,13 +3136,13 @@ struct ixgbe_hic_internal_phy_req {
u8 command_type;
__be16 address;
u16 rsv1;
- __le32 write_data;
+ __be32 write_data;
u16 pad;
};
struct ixgbe_hic_internal_phy_resp {
struct ixgbe_hic_hdr hdr;
- __le32 read_data;
+ __be32 read_data;
};
#ifdef C99
@@ -1278,7 +1278,7 @@ s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
write_cmd.port_number = hw->bus.lan_id;
write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
- write_cmd.write_data = IXGBE_CPU_TO_LE32(data);
+ write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
sizeof(write_cmd),
@@ -1318,7 +1318,7 @@ s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
IXGBE_HI_COMMAND_TIMEOUT, true);
/* Extract the register value from the response. */
- *data = IXGBE_LE32_TO_CPU(hic.rsp.read_data);
+ *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
return status;
}