[dpdk-dev] ixgbe: return err for too many interrupt queues
Commit Message
The lower 16 bits of EICR register are used for queue interrupts,
dpdk framework take over the first bit for other interrupts like
LSC, so there're only 15 bits left for queue interrupts mapping.
This patch adds a check for the num of interrupt queues at
dev_start.
Signed-off-by: Wang Xiao W <xiao.w.wang@intel.com>
---
drivers/net/ixgbe/ixgbe_ethdev.c | 5 +++++
drivers/net/ixgbe/ixgbe_ethdev.h | 1 +
2 files changed, 6 insertions(+)
Comments
Hi,
> -----Original Message-----
> From: Wang, Xiao W
> Sent: Monday, March 28, 2016 8:40 AM
> To: Lu, Wenzhuo
> Cc: dev@dpdk.org; Wang, Xiao W
> Subject: [PATCH] ixgbe: return err for too many interrupt queues
>
> The lower 16 bits of EICR register are used for queue interrupts, dpdk framework
> take over the first bit for other interrupts like LSC, so there're only 15 bits left for
> queue interrupts mapping.
> This patch adds a check for the num of interrupt queues at dev_start.
>
> Signed-off-by: Wang Xiao W <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
> > The lower 16 bits of EICR register are used for queue interrupts, dpdk framework
> > take over the first bit for other interrupts like LSC, so there're only 15 bits left for
> > queue interrupts mapping.
> > This patch adds a check for the num of interrupt queues at dev_start.
> >
> > Signed-off-by: Wang Xiao W <xiao.w.wang@intel.com>
> Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Applied, thanks
@@ -2131,6 +2131,11 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
!RTE_ETH_DEV_SRIOV(dev).active) &&
dev->data->dev_conf.intr_conf.rxq != 0) {
intr_vector = dev->data->nb_rx_queues;
+ if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
+ PMD_INIT_LOG(ERR, "At most %d intr queues supported",
+ IXGBE_MAX_INTR_QUEUE_NUM);
+ return -ENOTSUP;
+ }
if (rte_intr_efd_enable(intr_handle, intr_vector))
return -1;
}
@@ -59,6 +59,7 @@
#define IXGBE_VFTA_SIZE 128
#define IXGBE_VLAN_TAG_SIZE 4
#define IXGBE_MAX_RX_QUEUE_NUM 128
+#define IXGBE_MAX_INTR_QUEUE_NUM 15
#define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
#define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
#define IXGBE_NONE_MODE_TX_NB_QUEUES 64