net/mlx5: fix bit field compiling error

Message ID 1603733085-271968-1-git-send-email-bingz@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix bit field compiling error |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS

Commit Message

Bing Zhao Oct. 26, 2020, 5:24 p.m. UTC
  Some old compilers and old specification will not support bit field
with other types except integer or unsigned integer.
Since the next and previous items are 64b and/or 32b aligned, bit
field with "unsigned char" type will not save any space and the
compiler will complain.
Changing it to "unsigned int" type bit field will solve the issue.

Fixes: f711b60d400b ("net/mlx5: modify hash Rx queue objects")
Cc: andreyv@nvidia.com

Signed-off-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/net/mlx5/mlx5.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Comments

Raslan Darawsheh Oct. 26, 2020, 6:07 p.m. UTC | #1
Hi,


> -----Original Message-----
> From: Bing Zhao <bingz@nvidia.com>
> Sent: Monday, October 26, 2020 7:25 PM
> To: viacheslavo@mellanox.com; matan@mellanox.com
> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; Andrey Vesnovaty <andreyv@nvidia.com>
> Subject: [PATCH] net/mlx5: fix bit field compiling error
> 
> Some old compilers and old specification will not support bit field
> with other types except integer or unsigned integer.
> Since the next and previous items are 64b and/or 32b aligned, bit
> field with "unsigned char" type will not save any space and the
> compiler will complain.
> Changing it to "unsigned int" type bit field will solve the issue.
> 
> Fixes: f711b60d400b ("net/mlx5: modify hash Rx queue objects")
> Cc: andreyv@nvidia.com
> 
> Signed-off-by: Bing Zhao <bingz@nvidia.com>
> ---
>  drivers/net/mlx5/mlx5.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
> index c537af9..e5640c1 100644
> --- a/drivers/net/mlx5/mlx5.h
> +++ b/drivers/net/mlx5/mlx5.h
> @@ -733,7 +733,7 @@ struct mlx5_ind_table_obj {
>  struct mlx5_hrxq {
>  	ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
>  	rte_atomic32_t refcnt; /* Reference counter. */
> -	uint8_t shared:1; /* This object used in shared action. */
> +	uint32_t shared:1; /* This object used in shared action. */
>  	struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
>  	RTE_STD_C11
>  	union {
> --
> 1.8.3.1

Patch squashed into relevant commit in next-net-mlx,

Kindest regards
Raslan Darawsheh
  
Ferruh Yigit Oct. 29, 2020, 2:28 p.m. UTC | #2
On 10/26/2020 6:07 PM, Raslan Darawsheh wrote:
> Hi,
> 
> 
>> -----Original Message-----
>> From: Bing Zhao <bingz@nvidia.com>
>> Sent: Monday, October 26, 2020 7:25 PM
>> To: viacheslavo@mellanox.com; matan@mellanox.com
>> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>; Raslan Darawsheh
>> <rasland@nvidia.com>; Andrey Vesnovaty <andreyv@nvidia.com>
>> Subject: [PATCH] net/mlx5: fix bit field compiling error
>>
>> Some old compilers and old specification will not support bit field
>> with other types except integer or unsigned integer.
>> Since the next and previous items are 64b and/or 32b aligned, bit
>> field with "unsigned char" type will not save any space and the
>> compiler will complain.
>> Changing it to "unsigned int" type bit field will solve the issue.
>>
>> Fixes: f711b60d400b ("net/mlx5: modify hash Rx queue objects")
>> Cc: andreyv@nvidia.com
>>
>> Signed-off-by: Bing Zhao <bingz@nvidia.com>
>> ---
>>   drivers/net/mlx5/mlx5.h | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
>> index c537af9..e5640c1 100644
>> --- a/drivers/net/mlx5/mlx5.h
>> +++ b/drivers/net/mlx5/mlx5.h
>> @@ -733,7 +733,7 @@ struct mlx5_ind_table_obj {
>>   struct mlx5_hrxq {
>>   	ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
>>   	rte_atomic32_t refcnt; /* Reference counter. */
>> -	uint8_t shared:1; /* This object used in shared action. */
>> +	uint32_t shared:1; /* This object used in shared action. */
>>   	struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
>>   	RTE_STD_C11
>>   	union {
>> --
>> 1.8.3.1
> 
> Patch squashed into relevant commit in next-net-mlx,
> 

Hi Raslan,

Updating patches that has been pulled by next-net makes very hard to pull your tree.

Can you please squash only ones that are still only in the mlx tree, for others 
I can update in the next-net which is easier than resolving conflicts on merge.

Thanks,
ferruh
  
Raslan Darawsheh Nov. 1, 2020, 7:36 a.m. UTC | #3
Hi,

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@intel.com>
> Sent: Thursday, October 29, 2020 4:28 PM
> To: Raslan Darawsheh <rasland@nvidia.com>; Bing Zhao
> <bingz@nvidia.com>; viacheslavo@mellanox.com; matan@mellanox.com
> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>; Andrey Vesnovaty
> <andreyv@nvidia.com>
> Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix bit field compiling error
> 
> On 10/26/2020 6:07 PM, Raslan Darawsheh wrote:
> > Hi,
> >
> >
> >> -----Original Message-----
> >> From: Bing Zhao <bingz@nvidia.com>
> >> Sent: Monday, October 26, 2020 7:25 PM
> >> To: viacheslavo@mellanox.com; matan@mellanox.com
> >> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>; Raslan Darawsheh
> >> <rasland@nvidia.com>; Andrey Vesnovaty <andreyv@nvidia.com>
> >> Subject: [PATCH] net/mlx5: fix bit field compiling error
> >>
> >> Some old compilers and old specification will not support bit field
> >> with other types except integer or unsigned integer.
> >> Since the next and previous items are 64b and/or 32b aligned, bit
> >> field with "unsigned char" type will not save any space and the
> >> compiler will complain.
> >> Changing it to "unsigned int" type bit field will solve the issue.
> >>
> >> Fixes: f711b60d400b ("net/mlx5: modify hash Rx queue objects")
> >> Cc: andreyv@nvidia.com
> >>
> >> Signed-off-by: Bing Zhao <bingz@nvidia.com>
> >> ---
> >>   drivers/net/mlx5/mlx5.h | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
> >> index c537af9..e5640c1 100644
> >> --- a/drivers/net/mlx5/mlx5.h
> >> +++ b/drivers/net/mlx5/mlx5.h
> >> @@ -733,7 +733,7 @@ struct mlx5_ind_table_obj {
> >>   struct mlx5_hrxq {
> >>   	ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
> >>   	rte_atomic32_t refcnt; /* Reference counter. */
> >> -	uint8_t shared:1; /* This object used in shared action. */
> >> +	uint32_t shared:1; /* This object used in shared action. */
> >>   	struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
> >>   	RTE_STD_C11
> >>   	union {
> >> --
> >> 1.8.3.1
> >
> > Patch squashed into relevant commit in next-net-mlx,
> >
> 
> Hi Raslan,
> 
> Updating patches that has been pulled by next-net makes very hard to pull
> your tree.
> 
> Can you please squash only ones that are still only in the mlx tree, for others
> I can update in the next-net which is easier than resolving conflicts on merge.
> 
Sure, and that's what I usually do not sure what happened and caused a squash for some pulled patches already. 

> Thanks,
> Ferruh
Kindest regards
Raslan Darawsheh
  

Patch

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index c537af9..e5640c1 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -733,7 +733,7 @@  struct mlx5_ind_table_obj {
 struct mlx5_hrxq {
 	ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
 	rte_atomic32_t refcnt; /* Reference counter. */
-	uint8_t shared:1; /* This object used in shared action. */
+	uint32_t shared:1; /* This object used in shared action. */
 	struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
 	RTE_STD_C11
 	union {