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[v1,2/4] net/hinic: optimize Rx performance for x86

Message ID 806d3d4f94ae0f8b6bcfd78ae3211259bc06978e.1595648149.git.cloud.wangxiaoyun@huawei.com (mailing list archive)
State Superseded, archived
Delegated to: Ferruh Yigit
Headers
Series some bugs fixes |

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/Intel-compilation success Compilation OK

Commit Message

Wangxiaoyun (Cloud) July 25, 2020, 3:48 a.m. UTC 
  For x86 platform, the rq cqe without cache aligned, which can
improve performace for some gateway scenarios.

Fixes: 361a9ccf81d6 ("net/hinic: optimize Rx performance")

Cc: stable@dpdk.org
Signed-off-by: Xiaoyun wang <cloud.wangxiaoyun@huawei.com>
---
 drivers/net/hinic/hinic_pmd_rx.h | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/drivers/net/hinic/hinic_pmd_rx.h b/drivers/net/hinic/hinic_pmd_rx.h
index 49fa565..8a45f2d 100644
--- a/drivers/net/hinic/hinic_pmd_rx.h
+++ b/drivers/net/hinic/hinic_pmd_rx.h
@@ -35,7 +35,11 @@  struct hinic_rq_cqe {
 	u32 rss_hash;
 
 	u32 rsvd[4];
+#if defined(RTE_ARCH_ARM64)
 } __rte_cache_aligned;
+#else
+};
+#endif
 
 struct hinic_rq_cqe_sect {
 	struct hinic_sge	sge;