diff mbox series

[v1,1/1] net/octeontx2: add routines to set/clear interrupt enable registers

Message ID 20200403022016.2676-1-vattunuru@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series [v1,1/1] net/octeontx2: add routines to set/clear interrupt enable registers |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/Intel-compilation success Compilation OK
ci/iol-testing success Testing PASS

Commit Message

Vamsi Krishna Attunuru April 3, 2020, 2:20 a.m. UTC 
  From: Vamsi Attunuru <vattunuru@marvell.com>

Patch adds routines to set/clear nix lf error & ras interrupt enable
registers. These nix lf error interrupts get triggered if there are
any failures during nix lf configuration. This interrupts are enabled
before any hardware configurations initiated on the allocated nix lf.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
---
 drivers/net/octeontx2/otx2_ethdev.c     |  3 +++
 drivers/net/octeontx2/otx2_ethdev.h     |  2 ++
 drivers/net/octeontx2/otx2_ethdev_irq.c | 35 +++++++++++++++++++++++++++------
 3 files changed, 34 insertions(+), 6 deletions(-)

Comments

Andrzej Ostruszka [C] April 3, 2020, 1:34 p.m. UTC | #1 
On 4/3/20 4:20 AM, vattunuru@marvell.com wrote:
> From: Vamsi Attunuru <vattunuru@marvell.com>
> 
> Patch adds routines to set/clear nix lf error & ras interrupt enable
> registers. These nix lf error interrupts get triggered if there are
> any failures during nix lf configuration. This interrupts are enabled
> before any hardware configurations initiated on the allocated nix lf.
> 
> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> ---

Acked-by: Andrzej Ostruszka <aostruszka@marvell.com>
Jerin Jacob April 5, 2020, 8:20 p.m. UTC | #2 
On Fri, Apr 3, 2020 at 7:05 PM Andrzej Ostruszka [C]
<aostruszka@marvell.com> wrote:
>
> On 4/3/20 4:20 AM, vattunuru@marvell.com wrote:
> > From: Vamsi Attunuru <vattunuru@marvell.com>
> >
> > Patch adds routines to set/clear nix lf error & ras interrupt enable
> > registers. These nix lf error interrupts get triggered if there are
> > any failures during nix lf configuration. This interrupts are enabled
> > before any hardware configurations initiated on the allocated nix lf.
> >
> > Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> > ---
>
> Acked-by: Andrzej Ostruszka <aostruszka@marvell.com>

Changed the subject to "net/octeontx2: enable error and ras interrupt
in configure".

Applied to dpdk-next-net-mrvl/master. Thanks
diff mbox series

Patch

diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index e60f490..1a7ca2a 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -1660,6 +1660,9 @@  otx2_nix_configure(struct rte_eth_dev *eth_dev)
 		goto fail_offloads;
 	}
 
+	otx2_nix_err_intr_enb_dis(eth_dev, true);
+	otx2_nix_ras_intr_enb_dis(eth_dev, true);
+
 	if (dev->ptp_en &&
 	    dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
 		otx2_err("Both PTP and switch header enabled");
diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
index e5684f9..22a4ea9 100644
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -445,6 +445,8 @@  int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
+void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
+void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
 
 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 				  uint16_t rx_queue_id);
diff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c
index 2256e40..96b848a 100644
--- a/drivers/net/octeontx2/otx2_ethdev_irq.c
+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c
@@ -41,11 +41,11 @@  nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+	otx2_nix_err_intr_enb_dis(eth_dev, false);
 	/* Set used interrupt vectors */
 	rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
 	/* Enable all dev interrupt except for RQ_DISABLED */
-	otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
+	otx2_nix_err_intr_enb_dis(eth_dev, true);
 
 	return rc;
 }
@@ -61,7 +61,7 @@  nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+	otx2_nix_err_intr_enb_dis(eth_dev, false);
 	otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
 }
 
@@ -97,11 +97,11 @@  nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+	otx2_nix_ras_intr_enb_dis(eth_dev, false);
 	/* Set used interrupt vectors */
 	rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
 	/* Enable dev interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+	otx2_nix_ras_intr_enb_dis(eth_dev, true);
 
 	return rc;
 }
@@ -117,7 +117,7 @@  nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+	otx2_nix_ras_intr_enb_dis(eth_dev, false);
 	otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
 }
 
@@ -466,3 +466,26 @@  otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 
 	return 0;
 }
+
+void
+otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+	/* Enable all nix lf error interrupts except for RQ_DISABLED */
+	if (enb)
+		otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
+	else
+		otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+}
+
+void
+otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+	if (enb)
+		otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+	else
+		otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+}