| Message ID | 1565253974-183591-14-git-send-email-rosen.xu@intel.com |
|---|---|
| State | New |
| Delegated to: | Qi Zhang |
| Headers | show |
| Series |
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| Related | show |
| Context | Check | Description |
|---|---|---|
| ci/Intel-compilation | fail | Compilation issues |
| ci/checkpatch | success | coding style OK |
This patch set both line side and nic side MTU when Hardware init, and init to IPN3KE_MAC_FRAME_SIZE_MAX. -----Original Message----- From: Xu, Rosen Sent: Thursday, August 8, 2019 4:46 PM To: dev@dpdk.org Cc: Yigit, Ferruh <ferruh.yigit@intel.com>; Zhang, Tianfei <tianfei.zhang@intel.com>; Xu, Rosen <rosen.xu@intel.com>; Pei, Andy <andy.pei@intel.com>; Lomartire, David <david.lomartire@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Ye, Xiaolong <xiaolong.ye@intel.com> Subject: [PATCH v3 13/13] net/ipn3ke: add FPGA network side port MTU configuration Add FPGA network side port MTU configuration in initialization. Signed-off-by: Rosen Xu <rosen.xu@intel.com> --- drivers/net/ipn3ke/ipn3ke_ethdev.c | 8 ++++++ drivers/net/ipn3ke/ipn3ke_ethdev.h | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c index 363a5f1..7e7fa25 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c @@ -292,6 +292,10 @@ /* Clear line RX statistics counters */ ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0); + + /* set mtu to max */ + ipn3ke_10G_mtu_setup(hw, i, 0); + ipn3ke_10G_mtu_setup(hw, i, 1); } } else if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { @@ -308,6 +312,10 @@ /* Clear line side RX statistics counters */ ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0); + + /* set mtu to max */ + ipn3ke_25G_mtu_setup(hw, i, 0); + ipn3ke_25G_mtu_setup(hw, i, 1); } } diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h index c7b336b..b04e5d3 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h @@ -654,6 +654,25 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \ IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT) +/* Additional Feature Register */ +#define ADD_PHY_CTRL 0x0 +#define PHY_RESET BIT(0) +/* registers for 25G/40G mac */ +#define MAC_CONFIG 0x310 +#define MAC_RESET_MASK GENMASK(2, 0) + +#define IPN3KE_MAX_MTU 0xffff + +#define IPN3KE_25G_PHY_PMA_SLOOP 0x313 +#define IPN3KE_25G_TX_FLOW_CTRL 0x640 +#define IPN3KE_25G_MAX_TX_SIZE_CONFIG 0x407 +#define IPN3KE_25G_MAX_RX_SIZE_CONFIG 0x506 + +#define IPN3KE_10G_TX_PAUSE_FRAME_QUANTA 0x42 +#define IPN3KE_10G_TX_PAUSE_FRAME_HOLDOFF 0x43 +#define IPN3KE_10G_TX_FRAME_MAXLENGTH 0x2c +#define IPN3KE_10G_RX_FRAME_MAXLENGTH 0xae + #define IPN3KE_REGISTER_WIDTH 32 /*Bits[2:0]: Configuration of TX statistics counters: @@ -1076,4 +1095,40 @@ static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw, eth_group_sel); } +static inline void ipn3ke_10G_mtu_setup (struct ipn3ke_hw *hw, uint32_t +mac_num, uint32_t eth_group_sel) { + uint32_t tmp = IPN3KE_MAC_FRAME_SIZE_MAX; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_TX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_RX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); +} + +static inline void ipn3ke_25G_mtu_setup (struct ipn3ke_hw *hw, uint32_t +mac_num, uint32_t eth_group_sel) { + uint32_t tmp = IPN3KE_MAC_FRAME_SIZE_MAX; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_TX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_RX_SIZE_CONFIG, + mac_num, + eth_group_sel); +} + #endif /* _IPN3KE_ETHDEV_H_ */ -- 1.8.3.1
diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c index 363a5f1..7e7fa25 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c @@ -292,6 +292,10 @@ /* Clear line RX statistics counters */ ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0); + + /* set mtu to max */ + ipn3ke_10G_mtu_setup(hw, i, 0); + ipn3ke_10G_mtu_setup(hw, i, 1); } } else if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { @@ -308,6 +312,10 @@ /* Clear line side RX statistics counters */ ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0); + + /* set mtu to max */ + ipn3ke_25G_mtu_setup(hw, i, 0); + ipn3ke_25G_mtu_setup(hw, i, 1); } } diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h index c7b336b..b04e5d3 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h @@ -654,6 +654,25 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \ IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT) +/* Additional Feature Register */ +#define ADD_PHY_CTRL 0x0 +#define PHY_RESET BIT(0) +/* registers for 25G/40G mac */ +#define MAC_CONFIG 0x310 +#define MAC_RESET_MASK GENMASK(2, 0) + +#define IPN3KE_MAX_MTU 0xffff + +#define IPN3KE_25G_PHY_PMA_SLOOP 0x313 +#define IPN3KE_25G_TX_FLOW_CTRL 0x640 +#define IPN3KE_25G_MAX_TX_SIZE_CONFIG 0x407 +#define IPN3KE_25G_MAX_RX_SIZE_CONFIG 0x506 + +#define IPN3KE_10G_TX_PAUSE_FRAME_QUANTA 0x42 +#define IPN3KE_10G_TX_PAUSE_FRAME_HOLDOFF 0x43 +#define IPN3KE_10G_TX_FRAME_MAXLENGTH 0x2c +#define IPN3KE_10G_RX_FRAME_MAXLENGTH 0xae + #define IPN3KE_REGISTER_WIDTH 32 /*Bits[2:0]: Configuration of TX statistics counters: @@ -1076,4 +1095,40 @@ static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw, eth_group_sel); } +static inline void ipn3ke_10G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tmp = IPN3KE_MAC_FRAME_SIZE_MAX; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_TX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_RX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); +} + +static inline void ipn3ke_25G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tmp = IPN3KE_MAC_FRAME_SIZE_MAX; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_TX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_RX_SIZE_CONFIG, + mac_num, + eth_group_sel); +} + #endif /* _IPN3KE_ETHDEV_H_ */
Add FPGA network side port MTU configuration in initialization. Signed-off-by: Rosen Xu <rosen.xu@intel.com> --- drivers/net/ipn3ke/ipn3ke_ethdev.c | 8 ++++++ drivers/net/ipn3ke/ipn3ke_ethdev.h | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)