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GET /api/patches/99611/?format=api
{ "id": 99611, "url": "http://patches.dpdk.org/api/patches/99611/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210924143335.1092300-3-conor.walsh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210924143335.1092300-3-conor.walsh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210924143335.1092300-3-conor.walsh@intel.com", "date": "2021-09-24T14:33:25", "name": "[v5,02/12] dma/ioat: create dmadev instances on PCI probe", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1966848f3d7dbb854acf678c47e3bb6c84588c0e", "submitter": { "id": 1935, "url": "http://patches.dpdk.org/api/people/1935/?format=api", "name": "Conor Walsh", "email": "conor.walsh@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210924143335.1092300-3-conor.walsh@intel.com/mbox/", "series": [ { "id": 19145, "url": "http://patches.dpdk.org/api/series/19145/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19145", "date": "2021-09-24T14:33:23", "name": "dma: add dmadev driver for ioat devices", "version": 5, "mbox": "http://patches.dpdk.org/series/19145/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/99611/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/99611/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EB1EDA0548;\n\tFri, 24 Sep 2021 16:33:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C8F994132B;\n\tFri, 24 Sep 2021 16:33:47 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 0710C41319\n for <dev@dpdk.org>; Fri, 24 Sep 2021 16:33:43 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Sep 2021 07:33:43 -0700", "from silpixa00401160.ir.intel.com ([10.55.129.96])\n by fmsmga006.fm.intel.com with ESMTP; 24 Sep 2021 07:33:41 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10116\"; a=\"309640132\"", "E=Sophos;i=\"5.85,320,1624345200\"; d=\"scan'208\";a=\"309640132\"", "E=Sophos;i=\"5.85,320,1624345200\"; d=\"scan'208\";a=\"703871429\"" ], "X-ExtLoop1": "1", "From": "Conor Walsh <conor.walsh@intel.com>", "To": "bruce.richardson@intel.com, fengchengwen@huawei.com, jerinj@marvell.com,\n kevin.laatz@intel.com", "Cc": "dev@dpdk.org,\n\tConor Walsh <conor.walsh@intel.com>", "Date": "Fri, 24 Sep 2021 14:33:25 +0000", "Message-Id": "<20210924143335.1092300-3-conor.walsh@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210924143335.1092300-1-conor.walsh@intel.com>", "References": "<20210827172550.1522362-1-conor.walsh@intel.com>\n <20210924143335.1092300-1-conor.walsh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 02/12] dma/ioat: create dmadev instances on\n PCI probe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When a suitable device is found during the PCI probe, create a dmadev\ninstance for each channel. Internal structures and HW definitions required\nfor device creation are also included.\n\nSigned-off-by: Conor Walsh <conor.walsh@intel.com>\nReviewed-by: Kevin Laatz <kevin.laatz@intel.com>\n---\n drivers/dma/ioat/ioat_dmadev.c | 102 ++++++++++++++++++++++++++++++-\n drivers/dma/ioat/ioat_hw_defs.h | 45 ++++++++++++++\n drivers/dma/ioat/ioat_internal.h | 27 ++++++++\n 3 files changed, 172 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/dma/ioat/ioat_dmadev.c b/drivers/dma/ioat/ioat_dmadev.c\nindex f3491d45b1..df3c72363a 100644\n--- a/drivers/dma/ioat/ioat_dmadev.c\n+++ b/drivers/dma/ioat/ioat_dmadev.c\n@@ -4,6 +4,7 @@\n \n #include <rte_bus_pci.h>\n #include <rte_dmadev_pmd.h>\n+#include <rte_malloc.h>\n \n #include \"ioat_internal.h\"\n \n@@ -14,6 +15,103 @@ RTE_LOG_REGISTER_DEFAULT(ioat_pmd_logtype, INFO);\n #define IOAT_PMD_NAME dmadev_ioat\n #define IOAT_PMD_NAME_STR RTE_STR(IOAT_PMD_NAME)\n \n+/* Create a DMA device. */\n+static int\n+ioat_dmadev_create(const char *name, struct rte_pci_device *dev)\n+{\n+\tstatic const struct rte_dma_dev_ops ioat_dmadev_ops = { };\n+\n+\tstruct rte_dma_dev *dmadev = NULL;\n+\tstruct ioat_dmadev *ioat = NULL;\n+\tint retry = 0;\n+\n+\tif (!name) {\n+\t\tIOAT_PMD_ERR(\"Invalid name of the device!\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Allocate device structure. */\n+\tdmadev = rte_dma_pmd_allocate(name, dev->device.numa_node, sizeof(*ioat));\n+\tif (dmadev == NULL) {\n+\t\tIOAT_PMD_ERR(\"Unable to allocate dma device\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tdmadev->device = &dev->device;\n+\n+\tdmadev->dev_private = dmadev->data->dev_private;\n+\n+\tdmadev->dev_ops = &ioat_dmadev_ops;\n+\n+\tioat = dmadev->data->dev_private;\n+\tioat->regs = dev->mem_resource[0].addr;\n+\tioat->doorbell = &ioat->regs->dmacount;\n+\tioat->qcfg.nb_desc = 0;\n+\tioat->desc_ring = NULL;\n+\tioat->version = ioat->regs->cbver;\n+\n+\t/* Do device initialization - reset and set error behaviour. */\n+\tif (ioat->regs->chancnt != 1)\n+\t\tIOAT_PMD_WARN(\"%s: Channel count == %d\\n\", __func__,\n+\t\t\t\tioat->regs->chancnt);\n+\n+\t/* Locked by someone else. */\n+\tif (ioat->regs->chanctrl & IOAT_CHANCTRL_CHANNEL_IN_USE) {\n+\t\tIOAT_PMD_WARN(\"%s: Channel appears locked\\n\", __func__);\n+\t\tioat->regs->chanctrl = 0;\n+\t}\n+\n+\t/* clear any previous errors */\n+\tif (ioat->regs->chanerr != 0) {\n+\t\tuint32_t val = ioat->regs->chanerr;\n+\t\tioat->regs->chanerr = val;\n+\t}\n+\n+\tioat->regs->chancmd = IOAT_CHANCMD_SUSPEND;\n+\trte_delay_ms(1);\n+\tioat->regs->chancmd = IOAT_CHANCMD_RESET;\n+\trte_delay_ms(1);\n+\twhile (ioat->regs->chancmd & IOAT_CHANCMD_RESET) {\n+\t\tioat->regs->chainaddr = 0;\n+\t\trte_delay_ms(1);\n+\t\tif (++retry >= 200) {\n+\t\t\tIOAT_PMD_ERR(\"%s: cannot reset device. CHANCMD=%#\"PRIx8\n+\t\t\t\t\t\", CHANSTS=%#\"PRIx64\", CHANERR=%#\"PRIx32\"\\n\",\n+\t\t\t\t\t__func__,\n+\t\t\t\t\tioat->regs->chancmd,\n+\t\t\t\t\tioat->regs->chansts,\n+\t\t\t\t\tioat->regs->chanerr);\n+\t\t\trte_dma_pmd_release(name);\n+\t\t\treturn -EIO;\n+\t\t}\n+\t}\n+\tioat->regs->chanctrl = IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\n+\t\t\tIOAT_CHANCTRL_ERR_COMPLETION_EN;\n+\n+\tdmadev->state = RTE_DMA_DEV_READY;\n+\n+\treturn 0;\n+\n+}\n+\n+/* Destroy a DMA device. */\n+static int\n+ioat_dmadev_destroy(const char *name)\n+{\n+\tint ret;\n+\n+\tif (!name) {\n+\t\tIOAT_PMD_ERR(\"Invalid device name\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = rte_dma_pmd_release(name);\n+\tif (ret)\n+\t\tIOAT_PMD_DEBUG(\"Device cleanup failed\");\n+\n+\treturn 0;\n+}\n+\n /* Probe DMA device. */\n static int\n ioat_dmadev_probe(struct rte_pci_driver *drv, struct rte_pci_device *dev)\n@@ -24,7 +122,7 @@ ioat_dmadev_probe(struct rte_pci_driver *drv, struct rte_pci_device *dev)\n \tIOAT_PMD_INFO(\"Init %s on NUMA node %d\", name, dev->device.numa_node);\n \n \tdev->device.driver = &drv->driver;\n-\treturn 0;\n+\treturn ioat_dmadev_create(name, dev);\n }\n \n /* Remove DMA device. */\n@@ -38,7 +136,7 @@ ioat_dmadev_remove(struct rte_pci_device *dev)\n \tIOAT_PMD_INFO(\"Closing %s on NUMA node %d\",\n \t\t\tname, dev->device.numa_node);\n \n-\treturn 0;\n+\treturn ioat_dmadev_destroy(name);\n }\n \n static const struct rte_pci_id pci_id_ioat_map[] = {\ndiff --git a/drivers/dma/ioat/ioat_hw_defs.h b/drivers/dma/ioat/ioat_hw_defs.h\nindex eeabba41ef..73bdf548b3 100644\n--- a/drivers/dma/ioat/ioat_hw_defs.h\n+++ b/drivers/dma/ioat/ioat_hw_defs.h\n@@ -11,6 +11,8 @@ extern \"C\" {\n \n #include <stdint.h>\n \n+#define IOAT_PCI_CHANERR_INT_OFFSET\t0x180\n+\n #define IOAT_VER_3_0\t0x30\n #define IOAT_VER_3_3\t0x33\n \n@@ -28,6 +30,49 @@ extern \"C\" {\n #define IOAT_DEVICE_ID_BDXF\t0x6f2F\n #define IOAT_DEVICE_ID_ICX\t0x0b00\n \n+#define IOAT_COMP_UPDATE_SHIFT\t3\n+#define IOAT_CMD_OP_SHIFT\t24\n+\n+/* DMA Channel Registers */\n+#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK\t\t0xF000\n+#define IOAT_CHANCTRL_COMPL_DCA_EN\t\t\t0x0200\n+#define IOAT_CHANCTRL_CHANNEL_IN_USE\t\t\t0x0100\n+#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL\t0x0020\n+#define IOAT_CHANCTRL_ERR_INT_EN\t\t\t0x0010\n+#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN\t\t\t0x0008\n+#define IOAT_CHANCTRL_ERR_COMPLETION_EN\t\t\t0x0004\n+#define IOAT_CHANCTRL_INT_REARM\t\t\t\t0x0001\n+\n+struct ioat_registers {\n+\tuint8_t\t\tchancnt;\n+\tuint8_t\t\txfercap;\n+\tuint8_t\t\tgenctrl;\n+\tuint8_t\t\tintrctrl;\n+\tuint32_t\tattnstatus;\n+\tuint8_t\t\tcbver;\t\t/* 0x08 */\n+\tuint8_t\t\treserved4[0x3]; /* 0x09 */\n+\tuint16_t\tintrdelay;\t/* 0x0C */\n+\tuint16_t\tcs_status;\t/* 0x0E */\n+\tuint32_t\tdmacapability;\t/* 0x10 */\n+\tuint8_t\t\treserved5[0x6C]; /* 0x14 */\n+\tuint16_t\tchanctrl;\t/* 0x80 */\n+\tuint8_t\t\treserved6[0x2];\t/* 0x82 */\n+\tuint8_t\t\tchancmd;\t/* 0x84 */\n+\tuint8_t\t\treserved3[1];\t/* 0x85 */\n+\tuint16_t\tdmacount;\t/* 0x86 */\n+\tuint64_t\tchansts;\t/* 0x88 */\n+\tuint64_t\tchainaddr;\t/* 0x90 */\n+\tuint64_t\tchancmp;\t/* 0x98 */\n+\tuint8_t\t\treserved2[0x8];\t/* 0xA0 */\n+\tuint32_t\tchanerr;\t/* 0xA8 */\n+\tuint32_t\tchanerrmask;\t/* 0xAC */\n+} __rte_packed;\n+\n+#define IOAT_CHANCMD_RESET\t0x20\n+#define IOAT_CHANCMD_SUSPEND\t0x04\n+\n+#define IOAT_CHANCMP_ALIGN\t8 /* CHANCMP address must be 64-bit aligned */\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/dma/ioat/ioat_internal.h b/drivers/dma/ioat/ioat_internal.h\nindex f1ec12a919..83ef5973f5 100644\n--- a/drivers/dma/ioat/ioat_internal.h\n+++ b/drivers/dma/ioat/ioat_internal.h\n@@ -7,6 +7,33 @@\n \n #include \"ioat_hw_defs.h\"\n \n+struct ioat_dmadev {\n+\tstruct rte_dma_dev_data *dmadev;\n+\tstruct rte_dma_vchan_conf qcfg;\n+\tstruct rte_dma_stats stats;\n+\n+\tvolatile uint16_t *doorbell __rte_cache_aligned;\n+\tphys_addr_t status_addr;\n+\tphys_addr_t ring_addr;\n+\n+\tstruct ioat_dma_hw_desc *desc_ring;\n+\n+\tunsigned short next_read;\n+\tunsigned short next_write;\n+\tunsigned short last_write; /* Used to compute submitted count. */\n+\tunsigned short offset; /* Used after a device recovery when counts -> 0. */\n+\tunsigned int failure; /* Used to store chanerr for error handling. */\n+\n+\t/* To report completions, the device will write status back here. */\n+\tvolatile uint64_t status __rte_cache_aligned;\n+\n+\t/* Pointer to the register bar. */\n+\tvolatile struct ioat_registers *regs;\n+\n+\t/* Store the IOAT version. */\n+\tuint8_t version;\n+};\n+\n extern int ioat_pmd_logtype;\n \n #define IOAT_PMD_LOG(level, fmt, args...) rte_log(RTE_LOG_ ## level, \\\n", "prefixes": [ "v5", "02/12" ] }