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GET /api/patches/99357/?format=api
{ "id": 99357, "url": "http://patches.dpdk.org/api/patches/99357/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210921132009.3461020-6-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210921132009.3461020-6-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210921132009.3461020-6-qi.z.zhang@intel.com", "date": "2021-09-21T13:19:54", "name": "[v3,05/20] net/ice/base: init boost TCAM table for parser", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1afac87e626ccd34cf5ce22bd6201109a4f24eb5", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210921132009.3461020-6-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 19057, "url": "http://patches.dpdk.org/api/series/19057/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19057", "date": "2021-09-21T13:19:49", "name": "ice/base: add parser module", "version": 3, "mbox": "http://patches.dpdk.org/series/19057/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/99357/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/99357/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4D3F4A0C4C;\n\tTue, 21 Sep 2021 15:17:52 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5F0F641156;\n\tTue, 21 Sep 2021 15:17:19 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 6B7B54113F\n for <dev@dpdk.org>; Tue, 21 Sep 2021 15:17:13 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Sep 2021 06:17:12 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by orsmga008.jf.intel.com with ESMTP; 21 Sep 2021 06:17:11 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10113\"; a=\"202847438\"", "E=Sophos;i=\"5.85,311,1624345200\"; d=\"scan'208\";a=\"202847438\"", "E=Sophos;i=\"5.85,311,1624345200\"; d=\"scan'208\";a=\"484173837\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com,\n\tdev@dpdk.org,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Tue, 21 Sep 2021 21:19:54 +0800", "Message-Id": "<20210921132009.3461020-6-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210921132009.3461020-1-qi.z.zhang@intel.com>", "References": "<20210921132009.3461020-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 05/20] net/ice/base: init boost TCAM table for\n parser", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Parse DDP section ICE_SID_RXPARSER_CAM into an array of\nice_bst_tcam_item.\nParse DDP section ICE_SID_LBL_RXPARSER_TMEM into an array of\nice_lbl_item.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/ice/base/ice_bst_tcam.c | 241 +++++++++++++++++++++++++\n drivers/net/ice/base/ice_bst_tcam.h | 28 +++\n drivers/net/ice/base/ice_imem.c | 2 +-\n drivers/net/ice/base/ice_metainit.c | 2 +-\n drivers/net/ice/base/ice_parser.c | 48 ++++-\n drivers/net/ice/base/ice_parser.h | 5 +\n drivers/net/ice/base/ice_parser_util.h | 12 +-\n drivers/net/ice/base/ice_pg_cam.c | 8 +-\n drivers/net/ice/base/meson.build | 1 +\n 9 files changed, 337 insertions(+), 10 deletions(-)\n create mode 100644 drivers/net/ice/base/ice_bst_tcam.c\n create mode 100644 drivers/net/ice/base/ice_bst_tcam.h", "diff": "diff --git a/drivers/net/ice/base/ice_bst_tcam.c b/drivers/net/ice/base/ice_bst_tcam.c\nnew file mode 100644\nindex 0000000000..1c82359681\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_bst_tcam.c\n@@ -0,0 +1,241 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2021 Intel Corporation\n+ */\n+\n+#include \"ice_common.h\"\n+#include \"ice_parser_util.h\"\n+\n+#define ICE_BST_TCAM_TABLE_SIZE 256\n+\n+static void _bst_np_kb_dump(struct ice_hw *hw, struct ice_np_keybuilder *kb)\n+{\n+\tice_info(hw, \"next proto key builder:\\n\");\n+\tice_info(hw, \"\\tops = %d\\n\", kb->ops);\n+\tice_info(hw, \"\\tstart_or_reg0 = %d\\n\", kb->start_or_reg0);\n+\tice_info(hw, \"\\tlen_or_reg1 = %d\\n\", kb->len_or_reg1);\n+}\n+\n+static void _bst_pg_kb_dump(struct ice_hw *hw, struct ice_pg_keybuilder *kb)\n+{\n+\tice_info(hw, \"parse graph key builder:\\n\");\n+\tice_info(hw, \"\\tflag0_ena = %d\\n\", kb->flag0_ena);\n+\tice_info(hw, \"\\tflag1_ena = %d\\n\", kb->flag1_ena);\n+\tice_info(hw, \"\\tflag2_ena = %d\\n\", kb->flag2_ena);\n+\tice_info(hw, \"\\tflag3_ena = %d\\n\", kb->flag3_ena);\n+\tice_info(hw, \"\\tflag0_idx = %d\\n\", kb->flag0_idx);\n+\tice_info(hw, \"\\tflag1_idx = %d\\n\", kb->flag1_idx);\n+\tice_info(hw, \"\\tflag2_idx = %d\\n\", kb->flag2_idx);\n+\tice_info(hw, \"\\tflag3_idx = %d\\n\", kb->flag3_idx);\n+\tice_info(hw, \"\\talu_reg_idx = %d\\n\", kb->alu_reg_idx);\n+}\n+\n+static void _bst_alu_dump(struct ice_hw *hw, struct ice_alu *alu, int index)\n+{\n+\tice_info(hw, \"alu%d:\\n\", index);\n+\tice_info(hw, \"\\topc = %d\\n\", alu->opc);\n+\tice_info(hw, \"\\tsrc_start = %d\\n\", alu->src_start);\n+\tice_info(hw, \"\\tsrc_len = %d\\n\", alu->src_len);\n+\tice_info(hw, \"\\tshift_xlate_select = %d\\n\", alu->shift_xlate_select);\n+\tice_info(hw, \"\\tshift_xlate_key = %d\\n\", alu->shift_xlate_key);\n+\tice_info(hw, \"\\tsrc_reg_id = %d\\n\", alu->src_reg_id);\n+\tice_info(hw, \"\\tdst_reg_id = %d\\n\", alu->dst_reg_id);\n+\tice_info(hw, \"\\tinc0 = %d\\n\", alu->inc0);\n+\tice_info(hw, \"\\tinc1 = %d\\n\", alu->inc1);\n+\tice_info(hw, \"\\tproto_offset_opc = %d\\n\", alu->proto_offset_opc);\n+\tice_info(hw, \"\\tproto_offset = %d\\n\", alu->proto_offset);\n+\tice_info(hw, \"\\tbranch_addr = %d\\n\", alu->branch_addr);\n+\tice_info(hw, \"\\timm = %d\\n\", alu->imm);\n+\tice_info(hw, \"\\tdst_start = %d\\n\", alu->dst_start);\n+\tice_info(hw, \"\\tdst_len = %d\\n\", alu->dst_len);\n+\tice_info(hw, \"\\tflags_extr_imm = %d\\n\", alu->flags_extr_imm);\n+\tice_info(hw, \"\\tflags_start_imm= %d\\n\", alu->flags_start_imm);\n+}\n+\n+/**\n+ * ice_bst_tcam_dump - dump a boost tcam info\n+ * @ice_hw: pointer to the hardware structure\n+ * @item: boost tcam to dump\n+ */\n+void ice_bst_tcam_dump(struct ice_hw *hw, struct ice_bst_tcam_item *item)\n+{\n+\tint i;\n+\n+\tice_info(hw, \"address = %d\\n\", item->address);\n+\tice_info(hw, \"key :\");\n+\tfor (i = 0; i < 20; i++)\n+\t\tice_info(hw, \"%02x \", item->key[i]);\n+\tice_info(hw, \"\\n\");\n+\tice_info(hw, \"key_inv:\");\n+\tfor (i = 0; i < 20; i++)\n+\t\tice_info(hw, \"%02x \", item->key_inv[i]);\n+\tice_info(hw, \"\\n\");\n+\tice_info(hw, \"hit_idx_grp = %d\\n\", item->hit_idx_grp);\n+\tice_info(hw, \"pg_pri = %d\\n\", item->pg_pri);\n+\t_bst_np_kb_dump(hw, &item->np_kb);\n+\t_bst_pg_kb_dump(hw, &item->pg_kb);\n+\t_bst_alu_dump(hw, &item->alu0, 0);\n+\t_bst_alu_dump(hw, &item->alu1, 1);\n+\t_bst_alu_dump(hw, &item->alu2, 2);\n+}\n+\n+/** The function parses a 96 bits ALU entry with below format:\n+ * BIT 0-5:\tOpcode (alu->opc)\n+ * BIT 6-13:\tSource Start (alu->src_start)\n+ * BIT 14-18:\tSource Length (alu->src_len)\n+ * BIT 19:\tShift/Xlate Select (alu->shift_xlate_select)\n+ * BIT 20-23:\tShift/Xlate Key (alu->shift_xlate_key)\n+ * BIT 24-30:\tSource Register ID (alu->src_reg_id)\n+ * BIT 31-37:\tDest. Register ID (alu->dst_reg_id)\n+ * BIT 38:\tInc0 (alu->inc0)\n+ * BIT 39:\tInc1:(alu->inc1)\n+ * BIT 40:41\tProtocol Offset Opcode (alu->proto_offset_opc)\n+ * BIT 42:49\tProtocol Offset (alu->proto_offset)\n+ * BIT 50:57\tBranch Address (alu->branch_addr)\n+ * BIT 58:73\tImmediate (alu->imm)\n+ * BIT 74\tDedicated Flags Enable (alu->dedicate_flags_ena)\n+ * BIT 75:80\tDest. Start (alu->dst_start)\n+ * BIT 81:86\tDest. Length (alu->dst_len)\n+ * BIT 87\tFlags Extract Imm. (alu->flags_extr_imm)\n+ * BIT 88:95\tFlags Start/Immediate (alu->flags_start_imm)\n+ *\n+ * NOTE: the first 7 bits are skipped as the start bit is not\n+ * byte aligned.\n+ */\n+static void _bst_alu_init(struct ice_alu *alu, u8 *data)\n+{\n+\tu64 d64 = *(u64 *)data >> 7;\n+\n+\talu->opc = (enum ice_alu_opcode)(d64 & 0x3f);\n+\talu->src_start = (u8)((d64 >> 6) & 0xff);\n+\talu->src_len = (u8)((d64 >> 14) & 0x1f);\n+\talu->shift_xlate_select = ((d64 >> 19) & 0x1) != 0;\n+\talu->shift_xlate_key = (u8)((d64 >> 20) & 0xf);\n+\talu->src_reg_id = (u8)((d64 >> 24) & 0x7f);\n+\talu->dst_reg_id = (u8)((d64 >> 31) & 0x7f);\n+\talu->inc0 = ((d64 >> 38) & 0x1) != 0;\n+\talu->inc1 = ((d64 >> 39) & 0x1) != 0;\n+\talu->proto_offset_opc = (u8)((d64 >> 40) & 0x3);\n+\talu->proto_offset = (u8)((d64 >> 42) & 0xff);\n+\n+\td64 = *(u64 *)(&data[6]) >> 9;\n+\n+\talu->branch_addr = (u8)(d64 & 0xff);\n+\talu->imm = (u16)((d64 >> 8) & 0xffff);\n+\talu->dedicate_flags_ena = ((d64 >> 24) & 0x1) != 0;\n+\talu->dst_start = (u8)((d64 >> 25) & 0x3f);\n+\talu->dst_len = (u8)((d64 >> 31) & 0x3f);\n+\talu->flags_extr_imm = ((d64 >> 37) & 0x1) != 0;\n+\talu->flags_start_imm = (u8)((d64 >> 38) & 0xff);\n+}\n+\n+/** The function parses a 35 bits Parse Graph Key Build with below format:\n+ * BIT 0:\tFlag 0 Enable (kb->flag0_ena)\n+ * BIT 1-6:\tFlag 0 Index (kb->flag0_idx)\n+ * BIT 7:\tFlag 1 Enable (kb->flag1_ena)\n+ * BIT 8-13:\tFlag 1 Index (kb->flag1_idx)\n+ * BIT 14:\tFlag 2 Enable (kb->flag2_ena)\n+ * BIT 15-20:\tFlag 2 Index (kb->flag2_idx)\n+ * BIT 21:\tFlag 3 Enable (kb->flag3_ena)\n+ * BIT 22-27:\tFlag 3 Index (kb->flag3_idx)\n+ * BIT 28-34:\tALU Register Index (kb->alu_reg_idx)\n+ */\n+static void _bst_pgkb_init(struct ice_pg_keybuilder *kb, u64 data)\n+{\n+\tkb->flag0_ena = (data & 0x1) != 0;\n+\tkb->flag0_idx = (u8)((data >> 1) & 0x3f);\n+\tkb->flag1_ena = ((data >> 7) & 0x1) != 0;\n+\tkb->flag1_idx = (u8)((data >> 8) & 0x3f);\n+\tkb->flag2_ena = ((data >> 14) & 0x1) != 0;\n+\tkb->flag2_idx = (u8)((data >> 15) & 0x3f);\n+\tkb->flag3_ena = ((data >> 21) & 0x1) != 0;\n+\tkb->flag3_idx = (u8)((data >> 22) & 0x3f);\n+\tkb->alu_reg_idx = (u8)((data >> 28) & 0x7f);\n+}\n+\n+/** The function parses a 18 bits Next Protocol Key Build with below format:\n+ * BIT 0-1:\tOpcode kb->ops\n+ * BIT 2-9:\tStart / Reg 0 (kb->start_or_reg0)\n+ * BIT 10-17:\tLength / Reg 1 (kb->len_or_reg1)\n+ */\n+static void _bst_npkb_init(struct ice_np_keybuilder *kb, u32 data)\n+{\n+\tkb->ops = (u8)(data & 0x3);\n+\tkb->start_or_reg0 = (u8)((data >> 2) & 0xff);\n+\tkb->len_or_reg1 = (u8)((data >> 10) & 0xff);\n+}\n+\n+/** The function parses a 704 bits Boost TCAM entry with below format:\n+ * BIT 0-15:\tAddress (ti->address)\n+ * BIT 16-31:\treserved\n+ * BIT 32-191: Key (ti->key)\n+ * BIT 192-351:Key Invert (ti->key_inv)\n+ * BIT 352-359:Boost Hit Index Group (ti->hit_idx_grp)\n+ * BIT 360-361:PG Priority (ti->pg_pri)\n+ * BIT 362-379:Next Proto Key Build (ti->np_kb)\n+ * BIT 380-414:PG Key Build (ti->pg_kb)\n+ * BIT 415-510:ALU 0 (ti->alu0)\n+ * BIT 511-606:ALU 1 (ti->alu1)\n+ * BIT 607-702:ALU 2 (ti->alu2)\n+ * BIT 703:\treserved\n+ */\n+static void _bst_parse_item(struct ice_hw *hw, u16 idx, void *item,\n+\t\t\t void *data, int size)\n+{\n+\tstruct ice_bst_tcam_item *ti = (struct ice_bst_tcam_item *)item;\n+\tu8 *buf = (u8 *)data;\n+\tint i;\n+\n+\tti->address = *(u16 *)buf;\n+\n+\tfor (i = 0; i < 20; i++)\n+\t\tti->key[i] = buf[4 + i];\n+\tfor (i = 0; i < 20; i++)\n+\t\tti->key_inv[i] = buf[24 + i];\n+\tti->hit_idx_grp = buf[44];\n+\tti->pg_pri = buf[45] & 0x3;\n+\t_bst_npkb_init(&ti->np_kb, *(u32 *)&buf[45] >> 2);\n+\t_bst_pgkb_init(&ti->pg_kb, *(u64 *)&buf[47] >> 4);\n+\t_bst_alu_init(&ti->alu0, &buf[51]);\n+\t_bst_alu_init(&ti->alu1, &buf[63]);\n+\t_bst_alu_init(&ti->alu2, &buf[75]);\n+\n+\tif (hw->debug_mask & ICE_DBG_PARSER)\n+\t\tice_bst_tcam_dump(hw, ti);\n+}\n+\n+/**\n+ * ice_bst_tcam_table_get - create a boost tcam table\n+ * @ice_hw: pointer to the hardware structure\n+ */\n+struct ice_bst_tcam_item *ice_bst_tcam_table_get(struct ice_hw *hw)\n+{\n+\treturn (struct ice_bst_tcam_item *)\n+\t\tice_parser_create_table(hw, ICE_SID_RXPARSER_BOOST_TCAM,\n+\t\t\t\t\tsizeof(struct ice_bst_tcam_item),\n+\t\t\t\t\tICE_BST_TCAM_TABLE_SIZE,\n+\t\t\t\t\tice_parser_sect_item_get,\n+\t\t\t\t\t_bst_parse_item, true);\n+}\n+\n+static void _parse_lbl_item(struct ice_hw *hw, u16 idx, void *item,\n+\t\t\t void *data, int size)\n+{\n+\tice_parse_item_dflt(hw, idx, item, data, size);\n+\n+\tif (hw->debug_mask & ICE_DBG_PARSER)\n+\t\tice_lbl_dump(hw, (struct ice_lbl_item *)item);\n+}\n+\n+/**\n+ * ice_bst_lbl_table_get - create a boost label table\n+ * @ice_hw: pointer to the hardware structure\n+ */\n+struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw)\n+{\n+\treturn (struct ice_lbl_item *)\n+\t\tice_parser_create_table(hw, ICE_SID_LBL_RXPARSER_TMEM,\n+\t\t\t\t\tsizeof(struct ice_lbl_item),\n+\t\t\t\t\tICE_BST_TCAM_TABLE_SIZE,\n+\t\t\t\t\tice_parser_sect_item_get,\n+\t\t\t\t\t_parse_lbl_item, true);\n+}\ndiff --git a/drivers/net/ice/base/ice_bst_tcam.h b/drivers/net/ice/base/ice_bst_tcam.h\nnew file mode 100644\nindex 0000000000..a4ab40721f\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_bst_tcam.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2021 Intel Corporation\n+ */\n+\n+#ifndef _ICE_BST_TCAM_H_\n+#define _ICE_BST_TCAM_H_\n+\n+#include \"ice_imem.h\"\n+\n+struct ice_bst_tcam_item {\n+\tu16 address;\n+\tu8 key[20];\n+\tu8 key_inv[20];\n+\tu8 hit_idx_grp;\n+\tu8 pg_pri;\n+\tstruct ice_np_keybuilder np_kb;\n+\tstruct ice_pg_keybuilder pg_kb;\n+\tstruct ice_alu alu0;\n+\tstruct ice_alu alu1;\n+\tstruct ice_alu alu2;\n+};\n+\n+void ice_bst_tcam_dump(struct ice_hw *hw, struct ice_bst_tcam_item *item);\n+\n+struct ice_bst_tcam_item *ice_bst_tcam_table_get(struct ice_hw *hw);\n+\n+struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw);\n+#endif /*_ICE_BST_TCAM_H_ */\ndiff --git a/drivers/net/ice/base/ice_imem.c b/drivers/net/ice/base/ice_imem.c\nindex aefc7132eb..2136e0393b 100644\n--- a/drivers/net/ice/base/ice_imem.c\n+++ b/drivers/net/ice/base/ice_imem.c\n@@ -240,5 +240,5 @@ struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw)\n \t\t\t\t\tsizeof(struct ice_imem_item),\n \t\t\t\t\tICE_IMEM_TABLE_SIZE,\n \t\t\t\t\tice_parser_sect_item_get,\n-\t\t\t\t\t_imem_parse_item);\n+\t\t\t\t\t_imem_parse_item, false);\n }\ndiff --git a/drivers/net/ice/base/ice_metainit.c b/drivers/net/ice/base/ice_metainit.c\nindex 5d49c6861d..3f9e5d6833 100644\n--- a/drivers/net/ice/base/ice_metainit.c\n+++ b/drivers/net/ice/base/ice_metainit.c\n@@ -139,5 +139,5 @@ struct ice_metainit_item *ice_metainit_table_get(struct ice_hw *hw)\n \t\t\t\t\tsizeof(struct ice_metainit_item),\n \t\t\t\t\tICE_METAINIT_TABLE_SIZE,\n \t\t\t\t\tice_parser_sect_item_get,\n-\t\t\t\t\t_metainit_parse_item);\n+\t\t\t\t\t_metainit_parse_item, false);\n }\ndiff --git a/drivers/net/ice/base/ice_parser.c b/drivers/net/ice/base/ice_parser.c\nindex f6a1c821f1..594f802800 100644\n--- a/drivers/net/ice/base/ice_parser.c\n+++ b/drivers/net/ice/base/ice_parser.c\n@@ -12,6 +12,22 @@\n #define ICE_SID_RXPARSER_PG_SPILL_ENTRY_SIZE\t\t17\n #define ICE_SID_RXPARSER_NOMATCH_CAM_ENTRY_SIZE\t\t12\n #define ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE\t13\n+#define ICE_SID_RXPARSER_BOOST_TCAM_ENTRY_SIZE\t\t88\n+\n+#define ICE_SEC_LBL_DATA_OFFSET\t\t\t\t2\n+#define ICE_SID_LBL_ENTRY_SIZE\t\t\t\t66\n+\n+void ice_lbl_dump(struct ice_hw *hw, struct ice_lbl_item *item)\n+{\n+\tice_info(hw, \"index = %d\\n\", item->idx);\n+\tice_info(hw, \"label = %s\\n\", item->label);\n+}\n+\n+void ice_parse_item_dflt(struct ice_hw *hw, u16 idx, void *item,\n+\t\t\t void *data, int size)\n+{\n+\tice_memcpy(item, data, size, ICE_DMA_TO_NONDMA);\n+}\n \n /**\n * ice_parser_sect_item_get - parse a item from a section\n@@ -49,6 +65,13 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section,\n \tcase ICE_SID_RXPARSER_NOMATCH_SPILL:\n \t\tsize = ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE;\n \t\tbreak;\n+\tcase ICE_SID_RXPARSER_BOOST_TCAM:\n+\t\tsize = ICE_SID_RXPARSER_BOOST_TCAM_ENTRY_SIZE;\n+\t\tbreak;\n+\tcase ICE_SID_LBL_RXPARSER_TMEM:\n+\t\tdata_off = ICE_SEC_LBL_DATA_OFFSET;\n+\t\tsize = ICE_SID_LBL_ENTRY_SIZE;\n+\t\tbreak;\n \tdefault:\n \t\treturn NULL;\n \t}\n@@ -68,6 +91,7 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section,\n * @length: number of items in the table to create\n * @item_get: the function will be parsed to ice_pkg_enum_entry\n * @parser_item: the function to parse the item\n+ * @no_offset: ignore header offset, calculate index from 0\n */\n void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,\n \t\t\t u32 item_size, u32 length,\n@@ -75,11 +99,12 @@ void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,\n \t\t\t\t\t\tu32 index, u32 *offset),\n \t\t\t void (*parse_item)(struct ice_hw *hw, u16 idx,\n \t\t\t\t\t\t void *item, void *data,\n-\t\t\t\t\t\t int size))\n+\t\t\t\t\t\t int size),\n+\t\t\t bool no_offset)\n {\n \tstruct ice_seg *seg = hw->seg;\n \tstruct ice_pkg_enum state;\n-\tu16 idx = 0;\n+\tu16 idx = 0xffff;\n \tvoid *table;\n \tvoid *data;\n \n@@ -102,7 +127,10 @@ void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,\n \t\t\tstruct ice_pkg_sect_hdr *hdr =\n \t\t\t\t(struct ice_pkg_sect_hdr *)state.sect;\n \n-\t\t\tidx = hdr->offset + state.entry_idx;\n+\t\t\tif (no_offset)\n+\t\t\t\tidx++;\n+\t\t\telse\n+\t\t\t\tidx = hdr->offset + state.entry_idx;\n \t\t\tparse_item(hw, idx,\n \t\t\t\t (void *)((uintptr_t)table + idx * item_size),\n \t\t\t\t data, item_size);\n@@ -165,6 +193,18 @@ enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)\n \t\tgoto err;\n \t}\n \n+\tp->bst_tcam_table = ice_bst_tcam_table_get(hw);\n+\tif (!p->bst_tcam_table) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto err;\n+\t}\n+\n+\tp->bst_lbl_table = ice_bst_lbl_table_get(hw);\n+\tif (!p->bst_lbl_table) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto err;\n+\t}\n+\n \t*psr = p;\n \treturn ICE_SUCCESS;\n err:\n@@ -184,6 +224,8 @@ void ice_parser_destroy(struct ice_parser *psr)\n \tice_free(psr->hw, psr->pg_sp_cam_table);\n \tice_free(psr->hw, psr->pg_nm_cam_table);\n \tice_free(psr->hw, psr->pg_nm_sp_cam_table);\n+\tice_free(psr->hw, psr->bst_tcam_table);\n+\tice_free(psr->hw, psr->bst_lbl_table);\n \n \tice_free(psr->hw, psr);\n }\ndiff --git a/drivers/net/ice/base/ice_parser.h b/drivers/net/ice/base/ice_parser.h\nindex b157e27510..319648970a 100644\n--- a/drivers/net/ice/base/ice_parser.h\n+++ b/drivers/net/ice/base/ice_parser.h\n@@ -8,6 +8,7 @@\n #include \"ice_metainit.h\"\n #include \"ice_imem.h\"\n #include \"ice_pg_cam.h\"\n+#include \"ice_bst_tcam.h\"\n \n struct ice_parser {\n \tstruct ice_hw *hw; /* pointer to the hardware structure */\n@@ -24,6 +25,10 @@ struct ice_parser {\n \tstruct ice_pg_nm_cam_item *pg_nm_cam_table;\n \t/* load data from section ICE_SID_RXPARSER_NOMATCH_SPILL */\n \tstruct ice_pg_nm_cam_item *pg_nm_sp_cam_table;\n+\t/* load data from section ICE_SID_RXPARSER_BOOST_TCAM */\n+\tstruct ice_bst_tcam_item *bst_tcam_table;\n+\t/* load data from section ICE_SID_LBL_RXPARSER_TMEM */\n+\tstruct ice_lbl_item *bst_lbl_table;\n };\n \n enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr);\ndiff --git a/drivers/net/ice/base/ice_parser_util.h b/drivers/net/ice/base/ice_parser_util.h\nindex e2054cb7d4..cf0222bed8 100644\n--- a/drivers/net/ice/base/ice_parser_util.h\n+++ b/drivers/net/ice/base/ice_parser_util.h\n@@ -8,11 +8,20 @@\n #include \"ice_imem.h\"\n #include \"ice_metainit.h\"\n \n+struct ice_lbl_item {\n+\tu16 idx;\n+\tchar label[64];\n+};\n+\n struct ice_pkg_sect_hdr {\n \t__le16 count;\n \t__le16 offset;\n };\n \n+void ice_lbl_dump(struct ice_hw *hw, struct ice_lbl_item *item);\n+void ice_parse_item_dflt(struct ice_hw *hw, u16 idx, void *item,\n+\t\t\t void *data, int size);\n+\n void *ice_parser_sect_item_get(u32 sect_type, void *section,\n \t\t\t u32 index, u32 *offset);\n \n@@ -22,5 +31,6 @@ void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,\n \t\t\t\t\t u32 index, u32 *offset),\n \t\t\t void (*parse_item)(struct ice_hw *hw, u16 idx,\n \t\t\t\t\t\t void *item, void *data,\n-\t\t\t\t\t\t int size));\n+\t\t\t\t\t\t int size),\n+\t\t\t bool no_offset);\n #endif /* _ICE_PARSER_UTIL_H_ */\ndiff --git a/drivers/net/ice/base/ice_pg_cam.c b/drivers/net/ice/base/ice_pg_cam.c\nindex 171986bf3d..03484d6a91 100644\n--- a/drivers/net/ice/base/ice_pg_cam.c\n+++ b/drivers/net/ice/base/ice_pg_cam.c\n@@ -252,7 +252,7 @@ struct ice_pg_cam_item *ice_pg_cam_table_get(struct ice_hw *hw)\n \t\t\t\t\tsizeof(struct ice_pg_cam_item),\n \t\t\t\t\tICE_PG_CAM_TABLE_SIZE,\n \t\t\t\t\tice_parser_sect_item_get,\n-\t\t\t\t\t_pg_cam_parse_item);\n+\t\t\t\t\t_pg_cam_parse_item, false);\n }\n \n /**\n@@ -266,7 +266,7 @@ struct ice_pg_cam_item *ice_pg_sp_cam_table_get(struct ice_hw *hw)\n \t\t\t\t\tsizeof(struct ice_pg_cam_item),\n \t\t\t\t\tICE_PG_SP_CAM_TABLE_SIZE,\n \t\t\t\t\tice_parser_sect_item_get,\n-\t\t\t\t\t_pg_sp_cam_parse_item);\n+\t\t\t\t\t_pg_sp_cam_parse_item, false);\n }\n \n /**\n@@ -280,7 +280,7 @@ struct ice_pg_nm_cam_item *ice_pg_nm_cam_table_get(struct ice_hw *hw)\n \t\t\t\t\tsizeof(struct ice_pg_nm_cam_item),\n \t\t\t\t\tICE_PG_NM_CAM_TABLE_SIZE,\n \t\t\t\t\tice_parser_sect_item_get,\n-\t\t\t\t\t_pg_nm_cam_parse_item);\n+\t\t\t\t\t_pg_nm_cam_parse_item, false);\n }\n \n /**\n@@ -294,5 +294,5 @@ struct ice_pg_nm_cam_item *ice_pg_nm_sp_cam_table_get(struct ice_hw *hw)\n \t\t\t\t\tsizeof(struct ice_pg_nm_cam_item),\n \t\t\t\t\tICE_PG_NM_SP_CAM_TABLE_SIZE,\n \t\t\t\t\tice_parser_sect_item_get,\n-\t\t\t\t\t_pg_nm_sp_cam_parse_item);\n+\t\t\t\t\t_pg_nm_sp_cam_parse_item, false);\n }\ndiff --git a/drivers/net/ice/base/meson.build b/drivers/net/ice/base/meson.build\nindex 56dfb390e8..105ae411d3 100644\n--- a/drivers/net/ice/base/meson.build\n+++ b/drivers/net/ice/base/meson.build\n@@ -19,6 +19,7 @@ sources = [\n \t'ice_imem.c',\n \t'ice_metainit.c',\n \t'ice_pg_cam.c',\n+\t'ice_bst_tcam.c',\n ]\n \n error_cflags = [\n", "prefixes": [ "v3", "05/20" ] }