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GET /api/patches/99354/?format=api
{ "id": 99354, "url": "http://patches.dpdk.org/api/patches/99354/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210921132009.3461020-3-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210921132009.3461020-3-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210921132009.3461020-3-qi.z.zhang@intel.com", "date": "2021-09-21T13:19:51", "name": "[v3,02/20] net/ice/base: init imem table for parser", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b7298f5cdeb67464b10cde453320d520331d2e80", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210921132009.3461020-3-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 19057, "url": "http://patches.dpdk.org/api/series/19057/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19057", "date": "2021-09-21T13:19:49", "name": "ice/base: add parser module", "version": 3, "mbox": "http://patches.dpdk.org/series/19057/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/99354/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/99354/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C5EA8A0C4C;\n\tTue, 21 Sep 2021 15:17:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EC9A341134;\n\tTue, 21 Sep 2021 15:17:10 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 85B2F41120\n for <dev@dpdk.org>; Tue, 21 Sep 2021 15:17:08 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Sep 2021 06:17:07 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by orsmga008.jf.intel.com with ESMTP; 21 Sep 2021 06:17:05 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10113\"; a=\"202847423\"", "E=Sophos;i=\"5.85,311,1624345200\"; d=\"scan'208\";a=\"202847423\"", "E=Sophos;i=\"5.85,311,1624345200\"; d=\"scan'208\";a=\"484173823\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com,\n\tdev@dpdk.org,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Tue, 21 Sep 2021 21:19:51 +0800", "Message-Id": "<20210921132009.3461020-3-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210921132009.3461020-1-qi.z.zhang@intel.com>", "References": "<20210921132009.3461020-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 02/20] net/ice/base: init imem table for parser", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Parse DDP section ICE_SID_RXPARSER_IMEM into an array of\nstruct ice_imem_item.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/ice/base/ice_imem.c | 244 +++++++++++++++++++++++++\n drivers/net/ice/base/ice_imem.h | 109 +++++++++++\n drivers/net/ice/base/ice_parser.c | 100 ++++++++++\n drivers/net/ice/base/ice_parser.h | 3 +\n drivers/net/ice/base/ice_parser_util.h | 25 +++\n drivers/net/ice/base/ice_type.h | 1 +\n drivers/net/ice/base/meson.build | 1 +\n 7 files changed, 483 insertions(+)\n create mode 100644 drivers/net/ice/base/ice_imem.c\n create mode 100644 drivers/net/ice/base/ice_imem.h\n create mode 100644 drivers/net/ice/base/ice_parser_util.h", "diff": "diff --git a/drivers/net/ice/base/ice_imem.c b/drivers/net/ice/base/ice_imem.c\nnew file mode 100644\nindex 0000000000..aefc7132eb\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_imem.c\n@@ -0,0 +1,244 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2021 Intel Corporation\n+ */\n+\n+#include \"ice_common.h\"\n+#include \"ice_parser_util.h\"\n+\n+#define ICE_IMEM_TABLE_SIZE 192\n+\n+static void _imem_bst_bm_dump(struct ice_hw *hw, struct ice_bst_main *bm)\n+{\n+\tice_info(hw, \"boost main:\\n\");\n+\tice_info(hw, \"\\tal0 = %d\\n\", bm->al0);\n+\tice_info(hw, \"\\tal1 = %d\\n\", bm->al1);\n+\tice_info(hw, \"\\tal2 = %d\\n\", bm->al2);\n+\tice_info(hw, \"\\tpg = %d\\n\", bm->pg);\n+}\n+\n+static void _imem_bst_kb_dump(struct ice_hw *hw, struct ice_bst_keybuilder *kb)\n+{\n+\tice_info(hw, \"boost key builder:\\n\");\n+\tice_info(hw, \"\\tpriority = %d\\n\", kb->priority);\n+\tice_info(hw, \"\\ttsr_ctrl = %d\\n\", kb->tsr_ctrl);\n+}\n+\n+static void _imem_np_kb_dump(struct ice_hw *hw, struct ice_np_keybuilder *kb)\n+{\n+\tice_info(hw, \"next proto key builder:\\n\");\n+\tice_info(hw, \"\\tops = %d\\n\", kb->ops);\n+\tice_info(hw, \"\\tstart_or_reg0 = %d\\n\", kb->start_or_reg0);\n+\tice_info(hw, \"\\tlen_or_reg1 = %d\\n\", kb->len_or_reg1);\n+}\n+\n+static void _imem_pg_kb_dump(struct ice_hw *hw, struct ice_pg_keybuilder *kb)\n+{\n+\tice_info(hw, \"parse graph key builder:\\n\");\n+\tice_info(hw, \"\\tflag0_ena = %d\\n\", kb->flag0_ena);\n+\tice_info(hw, \"\\tflag1_ena = %d\\n\", kb->flag1_ena);\n+\tice_info(hw, \"\\tflag2_ena = %d\\n\", kb->flag2_ena);\n+\tice_info(hw, \"\\tflag3_ena = %d\\n\", kb->flag3_ena);\n+\tice_info(hw, \"\\tflag0_idx = %d\\n\", kb->flag0_idx);\n+\tice_info(hw, \"\\tflag1_idx = %d\\n\", kb->flag1_idx);\n+\tice_info(hw, \"\\tflag2_idx = %d\\n\", kb->flag2_idx);\n+\tice_info(hw, \"\\tflag3_idx = %d\\n\", kb->flag3_idx);\n+\tice_info(hw, \"\\talu_reg_idx = %d\\n\", kb->alu_reg_idx);\n+}\n+\n+static void _imem_alu_dump(struct ice_hw *hw, struct ice_alu *alu, int index)\n+{\n+\tice_info(hw, \"alu%d:\\n\", index);\n+\tice_info(hw, \"\\topc = %d\\n\", alu->opc);\n+\tice_info(hw, \"\\tsrc_start = %d\\n\", alu->src_start);\n+\tice_info(hw, \"\\tsrc_len = %d\\n\", alu->src_len);\n+\tice_info(hw, \"\\tshift_xlate_select = %d\\n\", alu->shift_xlate_select);\n+\tice_info(hw, \"\\tshift_xlate_key = %d\\n\", alu->shift_xlate_key);\n+\tice_info(hw, \"\\tsrc_reg_id = %d\\n\", alu->src_reg_id);\n+\tice_info(hw, \"\\tdst_reg_id = %d\\n\", alu->dst_reg_id);\n+\tice_info(hw, \"\\tinc0 = %d\\n\", alu->inc0);\n+\tice_info(hw, \"\\tinc1 = %d\\n\", alu->inc1);\n+\tice_info(hw, \"\\tproto_offset_opc = %d\\n\", alu->proto_offset_opc);\n+\tice_info(hw, \"\\tproto_offset = %d\\n\", alu->proto_offset);\n+\tice_info(hw, \"\\tbranch_addr = %d\\n\", alu->branch_addr);\n+\tice_info(hw, \"\\timm = %d\\n\", alu->imm);\n+\tice_info(hw, \"\\tdst_start = %d\\n\", alu->dst_start);\n+\tice_info(hw, \"\\tdst_len = %d\\n\", alu->dst_len);\n+\tice_info(hw, \"\\tflags_extr_imm = %d\\n\", alu->flags_extr_imm);\n+\tice_info(hw, \"\\tflags_start_imm= %d\\n\", alu->flags_start_imm);\n+}\n+\n+/**\n+ * ice_imem_dump - dump an imem item info\n+ * @ice_hw: pointer to the hardware structure\n+ * @item: imem item to dump\n+ */\n+void ice_imem_dump(struct ice_hw *hw, struct ice_imem_item *item)\n+{\n+\tice_info(hw, \"index = %d\\n\", item->idx);\n+\t_imem_bst_bm_dump(hw, &item->b_m);\n+\t_imem_bst_kb_dump(hw, &item->b_kb);\n+\tice_info(hw, \"pg priority = %d\\n\", item->pg);\n+\t_imem_np_kb_dump(hw, &item->np_kb);\n+\t_imem_pg_kb_dump(hw, &item->pg_kb);\n+\t_imem_alu_dump(hw, &item->alu0, 0);\n+\t_imem_alu_dump(hw, &item->alu1, 1);\n+\t_imem_alu_dump(hw, &item->alu2, 2);\n+}\n+\n+/** The function parses a 4 bits Boost Main with below format:\n+ * BIT 0: ALU 0 (bm->alu0)\n+ * BIT 1: ALU 1 (bm->alu1)\n+ * BIT 2: ALU 2 (bm->alu2)\n+ * BIT 3: Parge Graph (bm->pg)\n+ */\n+static void _imem_bm_init(struct ice_bst_main *bm, u8 data)\n+{\n+\tbm->al0 = (data & 0x1) != 0;\n+\tbm->al1 = (data & 0x2) != 0;\n+\tbm->al2 = (data & 0x4) != 0;\n+\tbm->pg = (data & 0x8) != 0;\n+}\n+\n+/** The function parses a 10 bits Boost Main Build with below format:\n+ * BIT 0-7:\tPriority (bkb->priority)\n+ * BIT 8:\tTSR Control (bkb->tsr_ctrl)\n+ * BIT 9:\tReserved\n+ */\n+static void _imem_bkb_init(struct ice_bst_keybuilder *bkb, u16 data)\n+{\n+\tbkb->priority = (u8)(data & 0xff);\n+\tbkb->tsr_ctrl = (data & 0x100) != 0;\n+}\n+\n+/** The function parses a 18 bits Next Protocol Key Build with below format:\n+ * BIT 0-1:\tOpcode kb->ops\n+ * BIT 2-9:\tStart / Reg 0 (kb->start_or_reg0)\n+ * BIT 10-17:\tLength / Reg 1 (kb->len_or_reg1)\n+ */\n+static void _imem_npkb_init(struct ice_np_keybuilder *kb, u32 data)\n+{\n+\tkb->ops = (u8)(data & 0x3);\n+\tkb->start_or_reg0 = (u8)((data >> 2) & 0xff);\n+\tkb->len_or_reg1 = (u8)((data >> 10) & 0xff);\n+}\n+\n+/** The function parses a 35 bits Parse Graph Key Build with below format:\n+ * BIT 0:\tFlag 0 Enable (kb->flag0_ena)\n+ * BIT 1-6:\tFlag 0 Index (kb->flag0_idx)\n+ * BIT 7:\tFlag 1 Enable (kb->flag1_ena)\n+ * BIT 8-13:\tFlag 1 Index (kb->flag1_idx)\n+ * BIT 14:\tFlag 2 Enable (kb->flag2_ena)\n+ * BIT 15-20:\tFlag 2 Index (kb->flag2_idx)\n+ * BIT 21:\tFlag 3 Enable (kb->flag3_ena)\n+ * BIT 22-27:\tFlag 3 Index (kb->flag3_idx)\n+ * BIT 28-34:\tALU Register Index (kb->alu_reg_idx)\n+ */\n+static void _imem_pgkb_init(struct ice_pg_keybuilder *kb, u64 data)\n+{\n+\tkb->flag0_ena = (data & 0x1) != 0;\n+\tkb->flag0_idx = (u8)((data >> 1) & 0x3f);\n+\tkb->flag1_ena = ((data >> 7) & 0x1) != 0;\n+\tkb->flag1_idx = (u8)((data >> 8) & 0x3f);\n+\tkb->flag2_ena = ((data >> 14) & 0x1) != 0;\n+\tkb->flag2_idx = (u8)((data >> 15) & 0x3f);\n+\tkb->flag3_ena = ((data >> 21) & 0x1) != 0;\n+\tkb->flag3_idx = (u8)((data >> 22) & 0x3f);\n+\tkb->alu_reg_idx = (u8)((data >> 28) & 0x7f);\n+}\n+\n+/** The function parses a 96 bits ALU entry with below format:\n+ * BIT 0-5:\tOpcode (alu->opc)\n+ * BIT 6-13:\tSource Start (alu->src_start)\n+ * BIT 14-18:\tSource Length (alu->src_len)\n+ * BIT 19:\tShift/Xlate Select (alu->shift_xlate_select)\n+ * BIT 20-23:\tShift/Xlate Key (alu->shift_xlate_key)\n+ * BIT 24-30:\tSource Register ID (alu->src_reg_id)\n+ * BIT 31-37:\tDest. Register ID (alu->dst_reg_id)\n+ * BIT 38:\tInc0 (alu->inc0)\n+ * BIT 39:\tInc1:(alu->inc1)\n+ * BIT 40:41\tProtocol Offset Opcode (alu->proto_offset_opc)\n+ * BIT 42:49\tProtocol Offset (alu->proto_offset)\n+ * BIT 50:57\tBranch Address (alu->branch_addr)\n+ * BIT 58:73\tImmediate (alu->imm)\n+ * BIT 74\tDedicated Flags Enable (alu->dedicate_flags_ena)\n+ * BIT 75:80\tDest. Start (alu->dst_start)\n+ * BIT 81:86\tDest. Length (alu->dst_len)\n+ * BIT 87\tFlags Extract Imm. (alu->flags_extr_imm)\n+ * BIT 88:95\tFlags Start/Immediate (alu->flags_start_imm)\n+ *\n+ * NOTE: the first 5 bits are skipped as the start bit is not\n+ * byte aligned.\n+ */\n+static void _imem_alu_init(struct ice_alu *alu, u8 *data)\n+{\n+\tu64 d64 = *(u64 *)data >> 5;\n+\n+\talu->opc = (enum ice_alu_opcode)(d64 & 0x3f);\n+\talu->src_start = (u8)((d64 >> 6) & 0xff);\n+\talu->src_len = (u8)((d64 >> 14) & 0x1f);\n+\talu->shift_xlate_select = ((d64 >> 19) & 0x1) != 0;\n+\talu->shift_xlate_key = (u8)((d64 >> 20) & 0xf);\n+\talu->src_reg_id = (u8)((d64 >> 24) & 0x7f);\n+\talu->dst_reg_id = (u8)((d64 >> 31) & 0x7f);\n+\talu->inc0 = ((d64 >> 38) & 0x1) != 0;\n+\talu->inc1 = ((d64 >> 39) & 0x1) != 0;\n+\talu->proto_offset_opc = (u8)((d64 >> 40) & 0x3);\n+\talu->proto_offset = (u8)((d64 >> 42) & 0xff);\n+\talu->branch_addr = (u8)((d64 >> 50) & 0xff);\n+\n+\td64 = *(u64 *)(&data[7]) >> 7;\n+\n+\talu->imm = (u16)(d64 & 0xffff);\n+\talu->dedicate_flags_ena = ((d64 >> 16) & 0x1) != 0;\n+\talu->dst_start = (u8)((d64 >> 17) & 0x3f);\n+\talu->dst_len = (u8)((d64 >> 23) & 0x3f);\n+\talu->flags_extr_imm = ((d64 >> 29) & 0x1) != 0;\n+\talu->flags_start_imm = (u8)((d64 >> 30) & 0xff);\n+}\n+\n+/** The function parses a 384 bits IMEM entry with below format:\n+ * BIT 0-3:\tBoost Main (ii->b_m)\n+ * BIT 4-13:\tBoost Key Build (ii->b_kb)\n+ * BIT 14-15:\tPG Priority (ii->pg)\n+ * BIT 16-33:\tNext Proto Key Build (ii->np_kb)\n+ * BIT 34-68:\tPG Key Build (ii->pg_kb)\n+ * BIT 69-164:\tALU0 (ii->alu0)\n+ * BIT 165-260:ALU1 (ii->alu1)\n+ * BIT 261-356:ALU2 (ii->alu2)\n+ * BIT 357-383:Reserved\n+ */\n+static void _imem_parse_item(struct ice_hw *hw, u16 idx, void *item,\n+\t\t\t void *data, int size)\n+{\n+\tstruct ice_imem_item *ii = (struct ice_imem_item *)item;\n+\tu8 *buf = (u8 *)data;\n+\n+\tii->idx = idx;\n+\n+\t_imem_bm_init(&ii->b_m, buf[0]);\n+\t_imem_bkb_init(&ii->b_kb, *((u16 *)(&buf[0])) >> 4);\n+\n+\tii->pg = (u8)((buf[1] & 0xc0) >> 6);\n+\t_imem_npkb_init(&ii->np_kb, *((u32 *)(&buf[2])));\n+\t_imem_pgkb_init(&ii->pg_kb, *((u64 *)(&buf[2])) >> 18);\n+\t_imem_alu_init(&ii->alu0, &buf[8]);\n+\t_imem_alu_init(&ii->alu1, &buf[20]);\n+\t_imem_alu_init(&ii->alu2, &buf[32]);\n+\n+\tif (hw->debug_mask & ICE_DBG_PARSER)\n+\t\tice_imem_dump(hw, ii);\n+}\n+\n+/**\n+ * ice_imem_table_get - create an imem table\n+ * @ice_hw: pointer to the hardware structure\n+ */\n+struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw)\n+{\n+\treturn (struct ice_imem_item *)\n+\t\tice_parser_create_table(hw, ICE_SID_RXPARSER_IMEM,\n+\t\t\t\t\tsizeof(struct ice_imem_item),\n+\t\t\t\t\tICE_IMEM_TABLE_SIZE,\n+\t\t\t\t\tice_parser_sect_item_get,\n+\t\t\t\t\t_imem_parse_item);\n+}\ndiff --git a/drivers/net/ice/base/ice_imem.h b/drivers/net/ice/base/ice_imem.h\nnew file mode 100644\nindex 0000000000..8b1eccc1b9\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_imem.h\n@@ -0,0 +1,109 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2021 Intel Corporation\n+ */\n+\n+#ifndef _ICE_IMEM_H_\n+#define _ICE_IMEM_H_\n+\n+struct ice_bst_main {\n+\tbool al0;\n+\tbool al1;\n+\tbool al2;\n+\tbool pg;\n+};\n+\n+struct ice_bst_keybuilder {\n+\tu8 priority;\n+\tbool tsr_ctrl;\n+};\n+\n+struct ice_np_keybuilder {\n+\tu8 ops;\n+\tu8 start_or_reg0;\n+\tu8 len_or_reg1;\n+};\n+\n+struct ice_pg_keybuilder {\n+\tbool flag0_ena;\n+\tbool flag1_ena;\n+\tbool flag2_ena;\n+\tbool flag3_ena;\n+\tu8 flag0_idx;\n+\tu8 flag1_idx;\n+\tu8 flag2_idx;\n+\tu8 flag3_idx;\n+\tu8 alu_reg_idx;\n+};\n+\n+enum ice_alu_opcode {\n+\tICE_ALU_PARK = 0,\n+\tICE_ALU_MOV_ADD = 1,\n+\tICE_ALU_ADD = 2,\n+\tICE_ALU_MOV_AND = 4,\n+\tICE_ALU_AND = 5,\n+\tICE_ALU_AND_IMM = 6,\n+\tICE_ALU_MOV_OR = 7,\n+\tICE_ALU_OR = 8,\n+\tICE_ALU_MOV_XOR = 9,\n+\tICE_ALU_XOR = 10,\n+\tICE_ALU_NOP = 11,\n+\tICE_ALU_BR = 12,\n+\tICE_ALU_BREQ = 13,\n+\tICE_ALU_BRNEQ = 14,\n+\tICE_ALU_BRGT = 15,\n+\tICE_ALU_BRLT = 16,\n+\tICE_ALU_BRGEQ = 17,\n+\tICE_ALU_BRLEG = 18,\n+\tICE_ALU_SETEQ = 19,\n+\tICE_ALU_ANDEQ = 20,\n+\tICE_ALU_OREQ = 21,\n+\tICE_ALU_SETNEQ = 22,\n+\tICE_ALU_ANDNEQ = 23,\n+\tICE_ALU_ORNEQ = 24,\n+\tICE_ALU_SETGT = 25,\n+\tICE_ALU_ANDGT = 26,\n+\tICE_ALU_ORGT = 27,\n+\tICE_ALU_SETLT = 28,\n+\tICE_ALU_ANDLT = 29,\n+\tICE_ALU_ORLT = 30,\n+\tICE_ALU_MOV_SUB = 31,\n+\tICE_ALU_SUB = 32,\n+\tICE_ALU_INVALID = 64,\n+};\n+\n+struct ice_alu {\n+\tenum ice_alu_opcode opc;\n+\tu8 src_start;\n+\tu8 src_len;\n+\tbool shift_xlate_select;\n+\tu8 shift_xlate_key;\n+\tu8 src_reg_id;\n+\tu8 dst_reg_id;\n+\tbool inc0;\n+\tbool inc1;\n+\tu8 proto_offset_opc;\n+\tu8 proto_offset;\n+\tu8 branch_addr;\n+\tu16 imm;\n+\tbool dedicate_flags_ena;\n+\tu8 dst_start;\n+\tu8 dst_len;\n+\tbool flags_extr_imm;\n+\tu8 flags_start_imm;\n+};\n+\n+struct ice_imem_item {\n+\tu16 idx;\n+\tstruct ice_bst_main b_m;\n+\tstruct ice_bst_keybuilder b_kb;\n+\tu8 pg;\n+\tstruct ice_np_keybuilder np_kb;\n+\tstruct ice_pg_keybuilder pg_kb;\n+\tstruct ice_alu alu0;\n+\tstruct ice_alu alu1;\n+\tstruct ice_alu alu2;\n+};\n+\n+void ice_imem_dump(struct ice_hw *hw, struct ice_imem_item *item);\n+struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw);\n+#endif /* _ICE_IMEM_H_ */\ndiff --git a/drivers/net/ice/base/ice_parser.c b/drivers/net/ice/base/ice_parser.c\nindex c08decaf0d..0e52fd1ebf 100644\n--- a/drivers/net/ice/base/ice_parser.c\n+++ b/drivers/net/ice/base/ice_parser.c\n@@ -3,6 +3,94 @@\n */\n \n #include \"ice_common.h\"\n+#include \"ice_parser_util.h\"\n+\n+#define ICE_SEC_DATA_OFFSET\t\t\t4\n+#define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE\t48\n+\n+/**\n+ * ice_parser_sect_item_get - parse a item from a section\n+ * @sect_type: section type\n+ * @section: section object\n+ * @index: index of the item to get\n+ * @offset: dummy as prototype of ice_pkg_enum_entry's last parameter\n+ */\n+void *ice_parser_sect_item_get(u32 sect_type, void *section,\n+\t\t\t u32 index, u32 *offset)\n+{\n+\tstruct ice_pkg_sect_hdr *hdr;\n+\tint data_off = ICE_SEC_DATA_OFFSET;\n+\tint size;\n+\n+\tif (!section)\n+\t\treturn NULL;\n+\n+\tswitch (sect_type) {\n+\tcase ICE_SID_RXPARSER_IMEM:\n+\t\tsize = ICE_SID_RXPARSER_IMEM_ENTRY_SIZE;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+\n+\thdr = (struct ice_pkg_sect_hdr *)section;\n+\tif (index >= LE16_TO_CPU(hdr->count))\n+\t\treturn NULL;\n+\n+\treturn (void *)((uintptr_t)section + data_off + index * size);\n+}\n+\n+/**\n+ * ice_parser_create_table - create a item table from a section\n+ * @hw: pointer to the hardware structure\n+ * @sect_type: section type\n+ * @item_size: item size in byte\n+ * @length: number of items in the table to create\n+ * @item_get: the function will be parsed to ice_pkg_enum_entry\n+ * @parser_item: the function to parse the item\n+ */\n+void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,\n+\t\t\t u32 item_size, u32 length,\n+\t\t\t void *(*item_get)(u32 sect_type, void *section,\n+\t\t\t\t\t\tu32 index, u32 *offset),\n+\t\t\t void (*parse_item)(struct ice_hw *hw, u16 idx,\n+\t\t\t\t\t\t void *item, void *data,\n+\t\t\t\t\t\t int size))\n+{\n+\tstruct ice_seg *seg = hw->seg;\n+\tstruct ice_pkg_enum state;\n+\tu16 idx = 0;\n+\tvoid *table;\n+\tvoid *data;\n+\n+\tif (!seg)\n+\t\treturn NULL;\n+\n+\ttable = ice_malloc(hw, item_size * length);\n+\tif (!table) {\n+\t\tice_debug(hw, ICE_DBG_PARSER, \"failed to allocate memory for table type %d.\\n\",\n+\t\t\t sect_type);\n+\t\treturn NULL;\n+\t}\n+\n+\tice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM);\n+\tdo {\n+\t\tdata = ice_pkg_enum_entry(seg, &state, sect_type, NULL,\n+\t\t\t\t\t item_get);\n+\t\tseg = NULL;\n+\t\tif (data) {\n+\t\t\tstruct ice_pkg_sect_hdr *hdr =\n+\t\t\t\t(struct ice_pkg_sect_hdr *)state.sect;\n+\n+\t\t\tidx = hdr->offset + state.entry_idx;\n+\t\t\tparse_item(hw, idx,\n+\t\t\t\t (void *)((uintptr_t)table + idx * item_size),\n+\t\t\t\t data, item_size);\n+\t\t}\n+\t} while (data);\n+\n+\treturn table;\n+}\n \n /**\n * ice_parser_create - create a parser instance\n@@ -11,6 +99,7 @@\n */\n enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)\n {\n+\tenum ice_status status;\n \tstruct ice_parser *p;\n \n \tp = (struct ice_parser *)ice_malloc(hw, sizeof(struct ice_parser));\n@@ -20,8 +109,17 @@ enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)\n \n \tp->hw = hw;\n \n+\tp->imem_table = ice_imem_table_get(hw);\n+\tif (!p->imem_table) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto err;\n+\t}\n+\n \t*psr = p;\n \treturn ICE_SUCCESS;\n+err:\n+\tice_parser_destroy(p);\n+\treturn status;\n }\n \n /**\n@@ -30,5 +128,7 @@ enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)\n */\n void ice_parser_destroy(struct ice_parser *psr)\n {\n+\tice_free(psr->hw, psr->imem_table);\n+\n \tice_free(psr->hw, psr);\n }\ndiff --git a/drivers/net/ice/base/ice_parser.h b/drivers/net/ice/base/ice_parser.h\nindex 5964bf4e49..13dd83cbda 100644\n--- a/drivers/net/ice/base/ice_parser.h\n+++ b/drivers/net/ice/base/ice_parser.h\n@@ -7,6 +7,9 @@\n \n struct ice_parser {\n \tstruct ice_hw *hw; /* pointer to the hardware structure */\n+\n+\t/* load data from section ICE_SID_RX_PARSER_IMEM */\n+\tstruct ice_imem_item *imem_table;\n };\n \n enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr);\ndiff --git a/drivers/net/ice/base/ice_parser_util.h b/drivers/net/ice/base/ice_parser_util.h\nnew file mode 100644\nindex 0000000000..5941a293e0\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_parser_util.h\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2021 Intel Corporation\n+ */\n+\n+#ifndef _ICE_PARSER_UTIL_H_\n+#define _ICE_PARSER_UTIL_H_\n+\n+#include \"ice_imem.h\"\n+\n+struct ice_pkg_sect_hdr {\n+\t__le16 count;\n+\t__le16 offset;\n+};\n+\n+void *ice_parser_sect_item_get(u32 sect_type, void *section,\n+\t\t\t u32 index, u32 *offset);\n+\n+void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,\n+\t\t\t u32 item_size, u32 length,\n+\t\t\t void *(*handler)(u32 sect_type, void *section,\n+\t\t\t\t\t u32 index, u32 *offset),\n+\t\t\t void (*parse_item)(struct ice_hw *hw, u16 idx,\n+\t\t\t\t\t\t void *item, void *data,\n+\t\t\t\t\t\t int size));\n+#endif /* _ICE_PARSER_UTIL_H_ */\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 72cda11a4f..d81984633a 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -141,6 +141,7 @@ static inline u32 ice_round_to_num(u32 N, u32 R)\n \t\t\t\t ICE_DBG_AQ_DESC\t| \\\n \t\t\t\t ICE_DBG_AQ_DESC_BUF\t| \\\n \t\t\t\t ICE_DBG_AQ_CMD)\n+#define ICE_DBG_PARSER\t\tBIT_ULL(28)\n \n #define ICE_DBG_USER\t\tBIT_ULL(31)\n #define ICE_DBG_ALL\t\t0xFFFFFFFFFFFFFFFFULL\ndiff --git a/drivers/net/ice/base/meson.build b/drivers/net/ice/base/meson.build\nindex 2b0af54a5c..d5170d972d 100644\n--- a/drivers/net/ice/base/meson.build\n+++ b/drivers/net/ice/base/meson.build\n@@ -16,6 +16,7 @@ sources = [\n 'ice_vlan_mode.c',\n 'ice_ptp_hw.c',\n \t'ice_parser.c',\n+\t'ice_imem.c',\n ]\n \n error_cflags = [\n", "prefixes": [ "v3", "02/20" ] }