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{
    "id": 99127,
    "url": "http://patches.dpdk.org/api/patches/99127/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210917110242.3127658-18-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210917110242.3127658-18-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210917110242.3127658-18-qi.z.zhang@intel.com",
    "date": "2021-09-17T11:02:39",
    "name": "[17/20] net/ice/base: add parser execution main loop",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "a2892d0f2bc29dc69c1ba0e6fcbbf36c63412785",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210917110242.3127658-18-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 19007,
            "url": "http://patches.dpdk.org/api/series/19007/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19007",
            "date": "2021-09-17T11:02:22",
            "name": "ice/base: add parser module",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/19007/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/99127/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/99127/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1E876A0C46;\n\tFri, 17 Sep 2021 13:01:50 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2AF8841173;\n\tFri, 17 Sep 2021 13:00:06 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id F38C441164\n for <dev@dpdk.org>; Fri, 17 Sep 2021 13:00:03 +0200 (CEST)",
            "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Sep 2021 04:00:03 -0700",
            "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga006.fm.intel.com with ESMTP; 17 Sep 2021 04:00:01 -0700"
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10109\"; a=\"286458761\"",
            "E=Sophos;i=\"5.85,301,1624345200\"; d=\"scan'208\";a=\"286458761\"",
            "E=Sophos;i=\"5.85,301,1624345200\"; d=\"scan'208\";a=\"699441062\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "junfeng.guo@intel.com,\n\tdev@dpdk.org,\n\tQi Zhang <qi.z.zhang@intel.com>",
        "Date": "Fri, 17 Sep 2021 19:02:39 +0800",
        "Message-Id": "<20210917110242.3127658-18-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.26.2",
        "In-Reply-To": "<20210917110242.3127658-1-qi.z.zhang@intel.com>",
        "References": "<20210917110242.3127658-1-qi.z.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 17/20] net/ice/base: add parser execution main\n loop",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Implement function ice_parser_rt_execute which perform the main\nloop of the parser.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_parser_rt.c | 777 ++++++++++++++++++++++++++-\n drivers/net/ice/base/ice_parser_rt.h |  20 +\n 2 files changed, 793 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_parser_rt.c b/drivers/net/ice/base/ice_parser_rt.c\nindex d62d0170e5..682e34e885 100644\n--- a/drivers/net/ice/base/ice_parser_rt.c\n+++ b/drivers/net/ice/base/ice_parser_rt.c\n@@ -34,12 +34,40 @@ static void _rt_nn_set(struct ice_parser_rt *rt, u16 node)\n \trt->gpr[GPR_NN_IDX] = node;\n }\n \n-static void _rt_flag_set(struct ice_parser_rt *rt, int idx)\n+static void _rt_flag_set(struct ice_parser_rt *rt, int idx, bool val)\n {\n \tint y = idx / 16;\n \tint x = idx % 16;\n \n-\trt->gpr[GPR_FLG_IDX + y] |= (u16)(1 << x);\n+\tif (val)\n+\t\trt->gpr[GPR_FLG_IDX + y] |= (u16)(1 << x);\n+\telse\n+\t\trt->gpr[GPR_FLG_IDX + y] &= ~(u16)(1 << x);\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Set parser flag %d value %d\\n\",\n+\t\t  idx, val);\n+}\n+\n+static void _rt_gpr_set(struct ice_parser_rt *rt, int idx, u16 val)\n+{\n+\tif (idx == GPR_HO_IDX)\n+\t\t_rt_ho_set(rt, val);\n+\telse\n+\t\trt->gpr[idx] = val;\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Set GPR %d value %d\\n\",\n+\t\t  idx, val);\n+}\n+\n+static void _rt_err_set(struct ice_parser_rt *rt, int idx, bool val)\n+{\n+\tif (val)\n+\t\trt->gpr[GPR_ERR_IDX] |= (u16)(1 << idx);\n+\telse\n+\t\trt->gpr[GPR_ERR_IDX] &= ~(u16)(1 << idx);\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Set parser error %d value %d\\n\",\n+\t\t  idx, val);\n }\n \n /**\n@@ -61,7 +89,7 @@ void ice_parser_rt_reset(struct ice_parser_rt *rt)\n \n \tfor (i = 0; i < 64; i++) {\n \t\tif ((mi->flags & (1ul << i)) != 0ul)\n-\t\t\t_rt_flag_set(rt, i);\n+\t\t\t_rt_flag_set(rt, i, true);\n \t}\n \n \trt->psr = psr;\n@@ -86,6 +114,650 @@ void ice_parser_rt_pktbuf_set(struct ice_parser_rt *rt, const u8 *pkt_buf,\n \t\t   ICE_NONDMA_TO_NONDMA);\n }\n \n+static void _bst_key_init(struct ice_parser_rt *rt, struct ice_imem_item *imem)\n+{\n+\tu8 tsr = (u8)rt->gpr[GPR_TSR_IDX];\n+\tu16 ho = rt->gpr[GPR_HO_IDX];\n+\tu8 *key = rt->bst_key;\n+\tint i, j;\n+\n+\tif (imem->b_kb.tsr_ctrl)\n+\t\tkey[19] = (u8)tsr;\n+\telse\n+\t\tkey[19] = imem->b_kb.priority;\n+\n+\tfor (i = 18; i >= 0; i--) {\n+\t\tj = ho + 18 - i;\n+\t\tif (j < ICE_PARSER_MAX_PKT_LEN)\n+\t\t\tkey[i] = rt->pkt_buf[ho + 18 - i];\n+\t\telse\n+\t\t\tkey[i] = 0;\n+\t}\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Generated Boost TCAM Key:\\n\");\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\\n\",\n+\t\t  key[0], key[1], key[2], key[3], key[4],\n+\t\t  key[5], key[6], key[7], key[8], key[9],\n+\t\t  key[10], key[11], key[12], key[13], key[14],\n+\t\t  key[15], key[16], key[17], key[18], key[19]);\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"\\n\");\n+}\n+\n+static u8 _bit_rev_u8(u8 v)\n+{\n+\tu8 r = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < 8; i++) {\n+\t\tr |= (u8)((v & 0x1) << (7 - i));\n+\t\tv >>= 1;\n+\t}\n+\n+\treturn r;\n+}\n+\n+static u8 _bit_rev_u16(u16 v, int len)\n+{\n+\tu16 r = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < len; i++) {\n+\t\tr |= (u16)((v & 0x1) << (len - 1 - i));\n+\t\tv >>= 1;\n+\t}\n+\n+\treturn r;\n+}\n+\n+static u32 _bit_rev_u32(u32 v, int len)\n+{\n+\tu32 r = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < len; i++) {\n+\t\tr |= (u32)((v & 0x1) << (len - 1 - i));\n+\t\tv >>= 1;\n+\t}\n+\n+\treturn r;\n+}\n+\n+static u32 _hv_bit_sel(struct ice_parser_rt *rt, int start, int len)\n+{\n+\tu64 d64, msk;\n+\tu8 b[8];\n+\tint i;\n+\n+\tint offset = GPR_HB_IDX + start / 16;\n+\n+\tice_memcpy(b, &rt->gpr[offset], 8, ICE_NONDMA_TO_NONDMA);\n+\n+\tfor (i = 0; i < 8; i++)\n+\t\tb[i] = _bit_rev_u8(b[i]);\n+\n+\td64 = *(u64 *)b;\n+\tmsk = (1ul << len) - 1;\n+\n+\treturn _bit_rev_u32((u32)((d64 >> (start % 16)) & msk), len);\n+}\n+\n+static u32 _pk_build(struct ice_parser_rt *rt, struct ice_np_keybuilder *kb)\n+{\n+\tif (kb->ops == 0)\n+\t\treturn _hv_bit_sel(rt, kb->start_or_reg0, kb->len_or_reg1);\n+\telse if (kb->ops == 1)\n+\t\treturn rt->gpr[kb->start_or_reg0] |\n+\t\t       ((u32)rt->gpr[kb->len_or_reg1] << 16);\n+\telse if (kb->ops == 2)\n+\t\treturn 0;\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Unsupported ops %d\\n\", kb->ops);\n+\treturn 0xffffffff;\n+}\n+\n+static bool _flag_get(struct ice_parser_rt *rt, int index)\n+{\n+\tint y = index / 16;\n+\tint x = index % 16;\n+\n+\treturn (rt->gpr[GPR_FLG_IDX + y] & (u16)(1 << x)) != 0;\n+}\n+\n+static void _imem_pgk_init(struct ice_parser_rt *rt, struct ice_imem_item *imem)\n+{\n+\tice_memset(&rt->pg_key, 0, sizeof(rt->pg_key), ICE_NONDMA_MEM);\n+\trt->pg_key.next_proto = _pk_build(rt, &imem->np_kb);\n+\n+\tif (imem->pg_kb.flag0_ena)\n+\t\trt->pg_key.flag0 = _flag_get(rt, imem->pg_kb.flag0_idx);\n+\tif (imem->pg_kb.flag1_ena)\n+\t\trt->pg_key.flag1 = _flag_get(rt, imem->pg_kb.flag1_idx);\n+\tif (imem->pg_kb.flag2_ena)\n+\t\trt->pg_key.flag2 = _flag_get(rt, imem->pg_kb.flag2_idx);\n+\tif (imem->pg_kb.flag3_ena)\n+\t\trt->pg_key.flag3 = _flag_get(rt, imem->pg_kb.flag3_idx);\n+\n+\trt->pg_key.alu_reg = rt->gpr[imem->pg_kb.alu_reg_idx];\n+\trt->pg_key.node_id = rt->gpr[GPR_NN_IDX];\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Generate Parse Graph Key: node_id(%d),flag0(%d), flag1(%d), flag2(%d), flag3(%d), boost_idx(%d), alu_reg(0x%04x), next_proto(0x%08x)\\n\",\n+\t\t  rt->pg_key.node_id,\n+\t\t  rt->pg_key.flag0,\n+\t\t  rt->pg_key.flag1,\n+\t\t  rt->pg_key.flag2,\n+\t\t  rt->pg_key.flag3,\n+\t\t  rt->pg_key.boost_idx,\n+\t\t  rt->pg_key.alu_reg,\n+\t\t  rt->pg_key.next_proto);\n+}\n+\n+static void _imem_alu0_set(struct ice_parser_rt *rt, struct ice_imem_item *imem)\n+{\n+\trt->alu0 = &imem->alu0;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load ALU0 from imem pc %d\\n\",\n+\t\t  imem->idx);\n+}\n+\n+static void _imem_alu1_set(struct ice_parser_rt *rt, struct ice_imem_item *imem)\n+{\n+\trt->alu1 = &imem->alu1;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load ALU1 from imem pc %d\\n\",\n+\t\t  imem->idx);\n+}\n+\n+static void _imem_alu2_set(struct ice_parser_rt *rt, struct ice_imem_item *imem)\n+{\n+\trt->alu2 = &imem->alu2;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load ALU2 from imem pc %d\\n\",\n+\t\t  imem->idx);\n+}\n+\n+static void _imem_pgp_set(struct ice_parser_rt *rt, struct ice_imem_item *imem)\n+{\n+\trt->pg = imem->pg;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load PG priority %d from imem pc %d\\n\",\n+\t\t  rt->pg, imem->idx);\n+}\n+\n+static void\n+_bst_pgk_init(struct ice_parser_rt *rt, struct ice_bst_tcam_item *bst)\n+{\n+\tice_memset(&rt->pg_key, 0, sizeof(rt->pg_key), ICE_NONDMA_MEM);\n+\trt->pg_key.boost_idx = bst->hit_idx_grp;\n+\trt->pg_key.next_proto = _pk_build(rt, &bst->np_kb);\n+\n+\tif (bst->pg_kb.flag0_ena)\n+\t\trt->pg_key.flag0 = _flag_get(rt, bst->pg_kb.flag0_idx);\n+\tif (bst->pg_kb.flag1_ena)\n+\t\trt->pg_key.flag1 = _flag_get(rt, bst->pg_kb.flag1_idx);\n+\tif (bst->pg_kb.flag2_ena)\n+\t\trt->pg_key.flag2 = _flag_get(rt, bst->pg_kb.flag2_idx);\n+\tif (bst->pg_kb.flag3_ena)\n+\t\trt->pg_key.flag3 = _flag_get(rt, bst->pg_kb.flag3_idx);\n+\n+\trt->pg_key.alu_reg = rt->gpr[bst->pg_kb.alu_reg_idx];\n+\trt->pg_key.node_id = rt->gpr[GPR_NN_IDX];\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Generate Parse Graph Key: node_id(%d),flag0(%d), flag1(%d), flag2(%d), flag3(%d), boost_idx(%d), alu_reg(0x%04x), next_proto(0x%08x)\\n\",\n+\t\t  rt->pg_key.node_id,\n+\t\t  rt->pg_key.flag0,\n+\t\t  rt->pg_key.flag1,\n+\t\t  rt->pg_key.flag2,\n+\t\t  rt->pg_key.flag3,\n+\t\t  rt->pg_key.boost_idx,\n+\t\t  rt->pg_key.alu_reg,\n+\t\t  rt->pg_key.next_proto);\n+}\n+\n+static void _bst_alu0_set(struct ice_parser_rt *rt,\n+\t\t\t  struct ice_bst_tcam_item *bst)\n+{\n+\trt->alu0 = &bst->alu0;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load ALU0 from boost address %d\\n\",\n+\t\t  bst->address);\n+}\n+\n+static void _bst_alu1_set(struct ice_parser_rt *rt,\n+\t\t\t  struct ice_bst_tcam_item *bst)\n+{\n+\trt->alu1 = &bst->alu1;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load ALU1 from boost address %d\\n\",\n+\t\t  bst->address);\n+}\n+\n+static void _bst_alu2_set(struct ice_parser_rt *rt,\n+\t\t\t  struct ice_bst_tcam_item *bst)\n+{\n+\trt->alu2 = &bst->alu2;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load ALU2 from boost address %d\\n\",\n+\t\t  bst->address);\n+}\n+\n+static void _bst_pgp_set(struct ice_parser_rt *rt,\n+\t\t\t struct ice_bst_tcam_item *bst)\n+{\n+\trt->pg = bst->pg_pri;\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load PG priority %d from boost address %d\\n\",\n+\t\t  rt->pg, bst->address);\n+}\n+\n+static struct ice_pg_cam_item *_pg_cam_match(struct ice_parser_rt *rt)\n+{\n+\tstruct ice_parser *psr = rt->psr;\n+\tstruct ice_pg_cam_item *item;\n+\n+\titem = ice_pg_cam_match(psr->pg_cam_table, ICE_PG_CAM_TABLE_SIZE,\n+\t\t\t\t&rt->pg_key);\n+\tif (item)\n+\t\treturn item;\n+\n+\titem = ice_pg_cam_match(psr->pg_sp_cam_table, ICE_PG_SP_CAM_TABLE_SIZE,\n+\t\t\t\t&rt->pg_key);\n+\treturn item;\n+}\n+\n+static struct ice_pg_nm_cam_item *_pg_nm_cam_match(struct ice_parser_rt *rt)\n+{\n+\tstruct ice_parser *psr = rt->psr;\n+\tstruct ice_pg_nm_cam_item *item;\n+\n+\titem = ice_pg_nm_cam_match(psr->pg_nm_cam_table,\n+\t\t\t\t   ICE_PG_NM_CAM_TABLE_SIZE, &rt->pg_key);\n+\n+\tif (item)\n+\t\treturn item;\n+\n+\titem = ice_pg_nm_cam_match(psr->pg_nm_sp_cam_table,\n+\t\t\t\t   ICE_PG_NM_SP_CAM_TABLE_SIZE,\n+\t\t\t\t   &rt->pg_key);\n+\treturn item;\n+}\n+\n+static void _gpr_add(struct ice_parser_rt *rt, int idx, u16 val)\n+{\n+\trt->pu.gpr_val_upd[idx] = true;\n+\trt->pu.gpr_val[idx] = val;\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Pending update for register %d value %d\\n\",\n+\t\t  idx, val);\n+}\n+\n+static void _pg_exe(struct ice_parser_rt *rt)\n+{\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ParseGraph action ...\\n\");\n+\n+\t_gpr_add(rt, GPR_NP_IDX, rt->action->next_pc);\n+\t_gpr_add(rt, GPR_NN_IDX, rt->action->next_node);\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ParseGraph action done.\\n\");\n+}\n+\n+static void _flg_add(struct ice_parser_rt *rt, int idx, bool val)\n+{\n+\trt->pu.flg_msk |= (1ul << idx);\n+\tif (val)\n+\t\trt->pu.flg_val |= (1ul << idx);\n+\telse\n+\t\trt->pu.flg_val &= ~(1ul << idx);\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Pending update for flag %d value %d\\n\",\n+\t\t  idx, val);\n+}\n+\n+static void _flg_update(struct ice_parser_rt *rt, struct ice_alu *alu)\n+{\n+\tint i;\n+\n+\tif (alu->dedicate_flags_ena) {\n+\t\tif (alu->flags_extr_imm) {\n+\t\t\tfor (i = 0; i < alu->dst_len; i++)\n+\t\t\t\t_flg_add(rt, alu->dst_start + i,\n+\t\t\t\t\t (alu->flags_start_imm &\n+\t\t\t\t\t  (1u << i)) != 0);\n+\t\t} else {\n+\t\t\tfor (i = 0; i < alu->dst_len; i++) {\n+\t\t\t\t_flg_add(rt, alu->dst_start + i,\n+\t\t\t\t\t _hv_bit_sel(rt,\n+\t\t\t\t\t\t     alu->flags_start_imm + i,\n+\t\t\t\t\t\t     1) != 0);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+static void _po_update(struct ice_parser_rt *rt, struct ice_alu *alu)\n+{\n+\tif (alu->proto_offset_opc == 1)\n+\t\trt->po = (u16)(rt->gpr[GPR_HO_IDX] + alu->proto_offset);\n+\telse if (alu->proto_offset_opc == 2)\n+\t\trt->po = (u16)(rt->gpr[GPR_HO_IDX] - alu->proto_offset);\n+\telse if (alu->proto_offset_opc == 0)\n+\t\trt->po = rt->gpr[GPR_HO_IDX];\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Update Protocol Offset = %d\\n\",\n+\t\t  rt->po);\n+}\n+\n+static u16 _reg_bit_sel(struct ice_parser_rt *rt, int reg_idx,\n+\t\t\tint start, int len)\n+{\n+\tu32 d32, msk;\n+\tu8 b[4];\n+\tu8 v[4];\n+\n+\tice_memcpy(b, &rt->gpr[reg_idx + start / 16], 4, ICE_NONDMA_TO_NONDMA);\n+\n+\tv[0] = _bit_rev_u8(b[0]);\n+\tv[1] = _bit_rev_u8(b[1]);\n+\tv[2] = _bit_rev_u8(b[2]);\n+\tv[3] = _bit_rev_u8(b[3]);\n+\n+\td32 = *(u32 *)v;\n+\tmsk = (1u << len) - 1;\n+\n+\treturn _bit_rev_u16((u16)((d32 >> (start % 16)) & msk), len);\n+}\n+\n+static void _err_add(struct ice_parser_rt *rt, int idx, bool val)\n+{\n+\trt->pu.err_msk |= (u16)(1 << idx);\n+\tif (val)\n+\t\trt->pu.flg_val |= (u16)(1 << idx);\n+\telse\n+\t\trt->pu.flg_val &= ~(u16)(1 << idx);\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Pending update for error %d value %d\\n\",\n+\t\t  idx, val);\n+}\n+\n+static void _dst_reg_bit_set(struct ice_parser_rt *rt, struct ice_alu *alu,\n+\t\t\t     bool val)\n+{\n+\tu16 flg_idx;\n+\n+\tif (alu->dedicate_flags_ena) {\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"DedicatedFlagsEnable should not be enabled in opcode %d\\n\",\n+\t\t\t  alu->opc);\n+\t\treturn;\n+\t}\n+\n+\tif (alu->dst_reg_id == GPR_ERR_IDX) {\n+\t\tif (alu->dst_start >= 16) {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Invalid error %d\\n\",\n+\t\t\t\t  alu->dst_start);\n+\t\t\treturn;\n+\t\t}\n+\t\t_err_add(rt, alu->dst_start, val);\n+\t} else if (alu->dst_reg_id >= GPR_FLG_IDX) {\n+\t\tflg_idx = (u16)(((alu->dst_reg_id - GPR_FLG_IDX) << 4) +\n+\t\t\t\talu->dst_start);\n+\n+\t\tif (flg_idx >= 64) {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Invalid flag %d\\n\",\n+\t\t\t\t  flg_idx);\n+\t\t\treturn;\n+\t\t}\n+\t\t_flg_add(rt, flg_idx, val);\n+\t} else {\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Unexpected Dest Register Bit set, RegisterID %d Start %d\\n\",\n+\t\t\t  alu->dst_reg_id, alu->dst_start);\n+\t}\n+}\n+\n+static void _alu_exe(struct ice_parser_rt *rt, struct ice_alu *alu)\n+{\n+\tu16 dst, src, shift, imm;\n+\n+\tif (alu->shift_xlate_select) {\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"shift_xlate_select != 0 is not expected\\n\");\n+\t\treturn;\n+\t}\n+\n+\t_po_update(rt, alu);\n+\t_flg_update(rt, alu);\n+\n+\tdst = rt->gpr[alu->dst_reg_id];\n+\tsrc = _reg_bit_sel(rt, alu->src_reg_id, alu->src_start, alu->src_len);\n+\tshift = alu->shift_xlate_key;\n+\timm = alu->imm;\n+\n+\tswitch (alu->opc) {\n+\tcase ICE_ALU_PARK:\n+\t\tbreak;\n+\tcase ICE_ALU_MOV_ADD:\n+\t\tdst = (u16)((src << shift) + imm);\n+\t\t_gpr_add(rt, alu->dst_reg_id, dst);\n+\t\tbreak;\n+\tcase ICE_ALU_ADD:\n+\t\tdst += (u16)((src << shift) + imm);\n+\t\t_gpr_add(rt, alu->dst_reg_id, dst);\n+\t\tbreak;\n+\tcase ICE_ALU_ORLT:\n+\t\tif (src < imm)\n+\t\t\t_dst_reg_bit_set(rt, alu, true);\n+\t\t_gpr_add(rt, GPR_NP_IDX, alu->branch_addr);\n+\t\tbreak;\n+\tcase ICE_ALU_OREQ:\n+\t\tif (src == imm)\n+\t\t\t_dst_reg_bit_set(rt, alu, true);\n+\t\t_gpr_add(rt, GPR_NP_IDX, alu->branch_addr);\n+\t\tbreak;\n+\tcase ICE_ALU_SETEQ:\n+\t\tif (src == imm)\n+\t\t\t_dst_reg_bit_set(rt, alu, true);\n+\t\telse\n+\t\t\t_dst_reg_bit_set(rt, alu, false);\n+\t\t_gpr_add(rt, GPR_NP_IDX, alu->branch_addr);\n+\t\tbreak;\n+\tcase ICE_ALU_MOV_XOR:\n+\t\tdst = (u16)((u16)(src << shift) ^ (u16)imm);\n+\t\t_gpr_add(rt, alu->dst_reg_id, dst);\n+\t\tbreak;\n+\tdefault:\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Unsupported ALU instruction %d\\n\",\n+\t\t\t  alu->opc);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void _alu0_exe(struct ice_parser_rt *rt)\n+{\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ALU0 ...\\n\");\n+\t_alu_exe(rt, rt->alu0);\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ALU0 done.\\n\");\n+}\n+\n+static void _alu1_exe(struct ice_parser_rt *rt)\n+{\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ALU1 ...\\n\");\n+\t_alu_exe(rt, rt->alu1);\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ALU1 done.\\n\");\n+}\n+\n+static void _alu2_exe(struct ice_parser_rt *rt)\n+{\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ALU2 ...\\n\");\n+\t_alu_exe(rt, rt->alu2);\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Executing ALU2 done.\\n\");\n+}\n+\n+static void _pu_exe(struct ice_parser_rt *rt)\n+{\n+\tstruct ice_gpr_pu *pu = &rt->pu;\n+\tint i;\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Updating Registers ...\\n\");\n+\n+\tfor (i = 0; i < 128; i++) {\n+\t\tif (pu->gpr_val_upd[i])\n+\t\t\t_rt_gpr_set(rt, i, pu->gpr_val[i]);\n+\t}\n+\n+\tfor (i = 0; i < 64; i++) {\n+\t\tif (pu->flg_msk & (1ul << i))\n+\t\t\t_rt_flag_set(rt, i, pu->flg_val & (1ul << i));\n+\t}\n+\n+\tfor (i = 0; i < 16; i++) {\n+\t\tif (pu->err_msk & (1u << 1))\n+\t\t\t_rt_err_set(rt, i, pu->err_val & (1u << i));\n+\t}\n+\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Updating Registers done.\\n\");\n+}\n+\n+static void _alu_pg_exe(struct ice_parser_rt *rt)\n+{\n+\tice_memset(&rt->pu, 0, sizeof(rt->pu), ICE_NONDMA_MEM);\n+\n+\tif (rt->pg == 0) {\n+\t\t_pg_exe(rt);\n+\t\t_alu0_exe(rt);\n+\t\t_alu1_exe(rt);\n+\t\t_alu2_exe(rt);\n+\t} else if (rt->pg == 1) {\n+\t\t_alu0_exe(rt);\n+\t\t_pg_exe(rt);\n+\t\t_alu1_exe(rt);\n+\t\t_alu2_exe(rt);\n+\t} else if (rt->pg == 2) {\n+\t\t_alu0_exe(rt);\n+\t\t_alu1_exe(rt);\n+\t\t_pg_exe(rt);\n+\t\t_alu2_exe(rt);\n+\t} else if (rt->pg == 3) {\n+\t\t_alu0_exe(rt);\n+\t\t_alu1_exe(rt);\n+\t\t_alu2_exe(rt);\n+\t\t_pg_exe(rt);\n+\t}\n+\n+\t_pu_exe(rt);\n+\n+\tif (rt->action->ho_inc == 0)\n+\t\treturn;\n+\n+\tif (rt->action->ho_polarity)\n+\t\t_rt_ho_set(rt, rt->gpr[GPR_HO_IDX] + rt->action->ho_inc);\n+\telse\n+\t\t_rt_ho_set(rt, rt->gpr[GPR_HO_IDX] - rt->action->ho_inc);\n+}\n+\n+static void _proto_off_update(struct ice_parser_rt *rt)\n+{\n+\tstruct ice_parser *psr = rt->psr;\n+\tint i;\n+\n+\tif (rt->action->is_pg) {\n+\t\tstruct ice_proto_grp_item *proto_grp =\n+\t\t\t&psr->proto_grp_table[rt->action->proto_id];\n+\t\tu16 po;\n+\n+\t\tfor (i = 0; i < 8; i++) {\n+\t\t\tstruct ice_proto_off *entry = &proto_grp->po[i];\n+\n+\t\t\tif (entry->proto_id == 0xff)\n+\t\t\t\tbreak;\n+\n+\t\t\tif (!entry->polarity)\n+\t\t\t\tpo = (u16)(rt->po + entry->offset);\n+\t\t\telse\n+\t\t\t\tpo = (u16)(rt->po - entry->offset);\n+\n+\t\t\trt->protocols[entry->proto_id] = true;\n+\t\t\trt->offsets[entry->proto_id] = po;\n+\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Set Protocol %d at offset %d\\n\",\n+\t\t\t\t  entry->proto_id, po);\n+\t\t}\n+\t} else {\n+\t\trt->protocols[rt->action->proto_id] = true;\n+\t\trt->offsets[rt->action->proto_id] = rt->po;\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Set Protocol %d at offset %d\\n\",\n+\t\t\t  rt->action->proto_id, rt->po);\n+\t}\n+}\n+\n+static void _marker_set(struct ice_parser_rt *rt, int idx)\n+{\n+\tint x = idx / 8;\n+\tint y = idx % 8;\n+\n+\trt->markers[x] |= (u8)(1u << y);\n+}\n+\n+static void _marker_update(struct ice_parser_rt *rt)\n+{\n+\tstruct ice_parser *psr = rt->psr;\n+\tint i;\n+\n+\tif (rt->action->is_mg) {\n+\t\tstruct ice_mk_grp_item *mk_grp =\n+\t\t\t&psr->mk_grp_table[rt->action->marker_id];\n+\n+\t\tfor (i = 0; i < 8; i++) {\n+\t\t\tu8 marker = mk_grp->markers[i];\n+\n+\t\t\tif (marker == 71)\n+\t\t\t\tbreak;\n+\n+\t\t\t_marker_set(rt, marker);\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Set Marker %d\\n\",\n+\t\t\t\t  marker);\n+\t\t}\n+\t} else {\n+\t\tif (rt->action->marker_id != 71)\n+\t\t\t_marker_set(rt, rt->action->marker_id);\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Set Marker %d\\n\",\n+\t\t\t  rt->action->marker_id);\n+\t}\n+}\n+\n+static u16 _ptype_resolve(struct ice_parser_rt *rt)\n+{\n+\tstruct ice_parser *psr = rt->psr;\n+\tstruct ice_ptype_mk_tcam_item *item;\n+\n+\titem = ice_ptype_mk_tcam_match(psr->ptype_mk_tcam_table,\n+\t\t\t\t       rt->markers, 9);\n+\tif (item)\n+\t\treturn item->ptype;\n+\treturn 0xffff;\n+}\n+\n+static void _proto_off_resolve(struct ice_parser_rt *rt,\n+\t\t\t       struct ice_parser_result *rslt)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < 255; i++) {\n+\t\tif (rt->protocols[i]) {\n+\t\t\trslt->po[rslt->po_num].proto_id = (u8)i;\n+\t\t\trslt->po[rslt->po_num].offset = rt->offsets[i];\n+\t\t\trslt->po_num++;\n+\t\t}\n+\t}\n+}\n+\n+static void _result_resolve(struct ice_parser_rt *rt,\n+\t\t\t    struct ice_parser_result *rslt)\n+{\n+\tstruct ice_parser *psr = rt->psr;\n+\n+\tice_memset(rslt, 0, sizeof(*rslt), ICE_NONDMA_MEM);\n+\n+\trslt->ptype = _ptype_resolve(rt);\n+\n+\tice_memcpy(&rslt->flags_psr, &rt->gpr[GPR_FLG_IDX], 8,\n+\t\t   ICE_NONDMA_TO_NONDMA);\n+\trslt->flags_pkt = ice_flg_redirect(psr->flg_rd_table, rslt->flags_psr);\n+\trslt->flags_sw = ice_xlt_kb_flag_get(psr->xlt_kb_sw, rslt->flags_pkt);\n+\trslt->flags_fd = ice_xlt_kb_flag_get(psr->xlt_kb_fd, rslt->flags_pkt);\n+\trslt->flags_rss = ice_xlt_kb_flag_get(psr->xlt_kb_rss, rslt->flags_pkt);\n+\n+\t_proto_off_resolve(rt, rslt);\n+}\n+\n /**\n  * ice_parser_rt_execute - parser execution routine\n  * @rt: pointer to the parser runtime\n@@ -94,5 +766,102 @@ void ice_parser_rt_pktbuf_set(struct ice_parser_rt *rt, const u8 *pkt_buf,\n enum ice_status ice_parser_rt_execute(struct ice_parser_rt *rt,\n \t\t\t\t      struct ice_parser_result *rslt)\n {\n-\treturn ICE_ERR_NOT_IMPL;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_pg_nm_cam_item *pg_nm_cam;\n+\tstruct ice_parser *psr = rt->psr;\n+\tstruct ice_pg_cam_item *pg_cam;\n+\tstruct ice_bst_tcam_item *bst;\n+\tstruct ice_imem_item *imem;\n+\tu16 node;\n+\tu16 pc;\n+\n+\tnode = rt->gpr[GPR_NN_IDX];\n+\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Start with Node: %d\\n\", node);\n+\n+\twhile (true) {\n+\t\tpc = rt->gpr[GPR_NP_IDX];\n+\t\timem = &psr->imem_table[pc];\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Load imem at pc: %d\\n\",\n+\t\t\t  pc);\n+\n+\t\t_bst_key_init(rt, imem);\n+\t\tbst = ice_bst_tcam_match(psr->bst_tcam_table, rt->bst_key);\n+\n+\t\tif (!bst) {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"No Boost TCAM Match\\n\");\n+\t\t\t_imem_pgk_init(rt, imem);\n+\t\t\t_imem_alu0_set(rt, imem);\n+\t\t\t_imem_alu1_set(rt, imem);\n+\t\t\t_imem_alu2_set(rt, imem);\n+\t\t\t_imem_pgp_set(rt, imem);\n+\t\t} else {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Boost TCAM Match address: %d\\n\",\n+\t\t\t\t  bst->address);\n+\t\t\tif (imem->b_m.pg) {\n+\t\t\t\t_bst_pgk_init(rt, bst);\n+\t\t\t\t_bst_pgp_set(rt, bst);\n+\t\t\t} else {\n+\t\t\t\t_imem_pgk_init(rt, imem);\n+\t\t\t\t_imem_pgp_set(rt, imem);\n+\t\t\t}\n+\n+\t\t\tif (imem->b_m.al0)\n+\t\t\t\t_bst_alu0_set(rt, bst);\n+\t\t\telse\n+\t\t\t\t_imem_alu0_set(rt, imem);\n+\n+\t\t\tif (imem->b_m.al1)\n+\t\t\t\t_bst_alu1_set(rt, bst);\n+\t\t\telse\n+\t\t\t\t_imem_alu1_set(rt, imem);\n+\n+\t\t\tif (imem->b_m.al2)\n+\t\t\t\t_bst_alu2_set(rt, bst);\n+\t\t\telse\n+\t\t\t\t_imem_alu2_set(rt, imem);\n+\t\t}\n+\n+\t\trt->action = NULL;\n+\t\tpg_cam = _pg_cam_match(rt);\n+\t\tif (!pg_cam) {\n+\t\t\tpg_nm_cam = _pg_nm_cam_match(rt);\n+\t\t\tif (pg_nm_cam) {\n+\t\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Match ParseGraph Nomatch CAM Address %d\\n\",\n+\t\t\t\t\t  pg_nm_cam->idx);\n+\t\t\t\trt->action = &pg_nm_cam->action;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Match ParseGraph CAM Address %d\\n\",\n+\t\t\t\t  pg_cam->idx);\n+\t\t\trt->action = &pg_cam->action;\n+\t\t}\n+\n+\t\tif (!rt->action) {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Failed to match ParseGraph CAM, stop parsing.\\n\");\n+\t\t\tstatus = ICE_ERR_PARAM;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t_alu_pg_exe(rt);\n+\t\t_marker_update(rt);\n+\t\t_proto_off_update(rt);\n+\n+\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Go to node %d\\n\",\n+\t\t\t  rt->action->next_node);\n+\n+\t\tif (rt->action->is_last_round) {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Last Round in ParseGraph Action, stop parsing.\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (rt->gpr[GPR_HO_IDX] >= rt->pkt_len) {\n+\t\t\tice_debug(rt->psr->hw, ICE_DBG_PARSER, \"Header Offset %d is larger than packet len %d, stop parsing\\n\",\n+\t\t\t\t  rt->gpr[GPR_HO_IDX], rt->pkt_len);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t_result_resolve(rt, rslt);\n+\n+\treturn status;\n }\ndiff --git a/drivers/net/ice/base/ice_parser_rt.h b/drivers/net/ice/base/ice_parser_rt.h\nindex 32fa7f6579..2a11087e3a 100644\n--- a/drivers/net/ice/base/ice_parser_rt.h\n+++ b/drivers/net/ice/base/ice_parser_rt.h\n@@ -10,12 +10,32 @@ struct ice_parser_ctx;\n #define ICE_PARSER_MAX_PKT_LEN 504\n #define ICE_PARSER_GPR_NUM 128\n \n+struct ice_gpr_pu {\n+\tbool gpr_val_upd[128]; /* flag to indicate if GRP needs to be updated */\n+\tu16 gpr_val[128];\n+\tu64 flg_msk;\n+\tu64 flg_val;\n+\tu16 err_msk;\n+\tu16 err_val;\n+};\n+\n struct ice_parser_rt {\n \tstruct ice_parser *psr;\n \tu16 gpr[ICE_PARSER_GPR_NUM];\n \tu8 pkt_buf[ICE_PARSER_MAX_PKT_LEN + 32];\n \tu16 pkt_len;\n \tu16 po;\n+\tu8 bst_key[20];\n+\tstruct ice_pg_cam_key pg_key;\n+\tstruct ice_alu *alu0;\n+\tstruct ice_alu *alu1;\n+\tstruct ice_alu *alu2;\n+\tstruct ice_pg_cam_action *action;\n+\tu8 pg;\n+\tstruct ice_gpr_pu pu;\n+\tu8 markers[9]; /* 8 * 9 = 72 bits*/\n+\tbool protocols[256];\n+\tu16 offsets[256];\n };\n \n void ice_parser_rt_reset(struct ice_parser_rt *rt);\n",
    "prefixes": [
        "17/20"
    ]
}