Patch Detail
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Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/99019/?format=api
{ "id": 99019, "url": "http://patches.dpdk.org/api/patches/99019/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210916095304.3058210-13-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210916095304.3058210-13-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210916095304.3058210-13-qi.z.zhang@intel.com", "date": "2021-09-16T09:53:04", "name": "[12/12] net/ice/base: update auto generated hardware register", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5b7c052664fb587eaa7ca9f92ccedae4b9c4dd31", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210916095304.3058210-13-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18975, "url": "http://patches.dpdk.org/api/series/18975/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18975", "date": "2021-09-16T09:52:52", "name": "ice base code batch 2 for DPDK 21.11", "version": 1, "mbox": "http://patches.dpdk.org/series/18975/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/99019/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/99019/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8EE1EA0C41;\n\tThu, 16 Sep 2021 11:51:04 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B3A01410FF;\n\tThu, 16 Sep 2021 11:50:28 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 9F380410F0\n for <dev@dpdk.org>; Thu, 16 Sep 2021 11:50:26 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Sep 2021 02:50:26 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 16 Sep 2021 02:50:23 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10108\"; a=\"222185900\"", "E=Sophos;i=\"5.85,298,1624345200\"; d=\"scan'208\";a=\"222185900\"", "E=Sophos;i=\"5.85,298,1624345200\"; d=\"scan'208\";a=\"509247062\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Scott W Taylor <scott.w.taylor@intel.com>", "Date": "Thu, 16 Sep 2021 17:53:04 +0800", "Message-Id": "<20210916095304.3058210-13-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210916095304.3058210-1-qi.z.zhang@intel.com>", "References": "<20210916095304.3058210-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 12/12] net/ice/base: update auto generated\n hardware register", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update ice_hw_autogen.h.\nRemove duplicated one in ice_nvm.h.\nReplace ICE_NVM_ACCESS_GL_HIBA_MAX with GL_HIBA_MAX_INDEX.\n\nSigned-off-by: Scott W Taylor <scott.w.taylor@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_hw_autogen.h | 148 ++++++++++++++------------\n drivers/net/ice/base/ice_nvm.c | 4 +-\n drivers/net/ice/base/ice_nvm.h | 13 ---\n 3 files changed, 81 insertions(+), 84 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h\nindex cbca4b0629..10b1116931 100644\n--- a/drivers/net/ice/base/ice_hw_autogen.h\n+++ b/drivers/net/ice/base/ice_hw_autogen.h\n@@ -2,10 +2,20 @@\n * Copyright(c) 2001-2021 Intel Corporation\n */\n \n-/* Machine-generated file; do not edit */\n+/* Machine generated file. Do not edit. */\n+\n #ifndef _ICE_HW_AUTOGEN_H_\n #define _ICE_HW_AUTOGEN_H_\n \n+#define GL_HIDA(_i)\t\t\t(0x00082000 + ((_i) * 4))\n+#define GL_HIBA(_i)\t\t\t(0x00081000 + ((_i) * 4))\n+#define GL_HICR\t\t\t\t0x00082040\n+#define GL_HICR_EN\t\t\t0x00082044\n+#define GLGEN_CSR_DEBUG_C\t\t0x00075750\n+#define GLNVM_GENS\t\t\t0x000B6100\n+#define GLNVM_FLA\t\t\t0x000B6108\n+#define GL_HIDA_MAX_INDEX\t\t15\n+#define GL_HIBA_MAX_INDEX\t\t1023\n #define GL_RDPU_CNTRL\t\t\t\t0x00052054 /* Reset Source: CORER */\n #define GL_RDPU_CNTRL_RX_PAD_EN_S\t\t0\n #define GL_RDPU_CNTRL_RX_PAD_EN_M\t\tBIT(0)\n@@ -448,8 +458,8 @@\n #define PF0INT_OICR_CPM_PAGE_RSV3_M\t\tBIT(23)\n #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S\t24\n #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M\tBIT(24)\n-#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25\n-#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)\n+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S\t25\n+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M\tBIT(25)\n #define PF0INT_OICR_CPM_PAGE_HMC_ERR_S\t\t26\n #define PF0INT_OICR_CPM_PAGE_HMC_ERR_M\t\tBIT(26)\n #define PF0INT_OICR_CPM_PAGE_PE_PUSH_S\t\t27\n@@ -512,8 +522,8 @@\n #define PF0INT_OICR_HLP_PAGE_RSV3_M\t\tBIT(23)\n #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S\t24\n #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M\tBIT(24)\n-#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25\n-#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)\n+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S\t25\n+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M\tBIT(25)\n #define PF0INT_OICR_HLP_PAGE_HMC_ERR_S\t\t26\n #define PF0INT_OICR_HLP_PAGE_HMC_ERR_M\t\tBIT(26)\n #define PF0INT_OICR_HLP_PAGE_PE_PUSH_S\t\t27\n@@ -561,8 +571,8 @@\n #define PF0INT_OICR_PSM_PAGE_RSV3_M\t\tBIT(23)\n #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S\t24\n #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M\tBIT(24)\n-#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25\n-#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)\n+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S\t25\n+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M\tBIT(25)\n #define PF0INT_OICR_PSM_PAGE_HMC_ERR_S\t\t26\n #define PF0INT_OICR_PSM_PAGE_HMC_ERR_M\t\tBIT(26)\n #define PF0INT_OICR_PSM_PAGE_PE_PUSH_S\t\t27\n@@ -702,8 +712,8 @@\n #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M\tMAKEMASK(0x1F, 8)\n #define GL_ACL_PROFILE_DWSB_SEL(_i)\t\t(0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n #define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX\t15\n-#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0\n-#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)\n+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S\t0\n+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M\tMAKEMASK(0xF, 0)\n #define GL_ACL_PROFILE_PF_CFG(_i)\t\t(0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n #define GL_ACL_PROFILE_PF_CFG_MAX_INDEX\t\t7\n #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S\t0\n@@ -861,8 +871,8 @@\n #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M\tBIT(6)\n #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7\n #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)\n-#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14\n-#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)\n+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S\t14\n+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M\tMAKEMASK(0xFF, 14)\n #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S\t22\n #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M\tMAKEMASK(0x3FF, 22)\n #define GLTCLAN_CQ_CNTX0(_CQ)\t\t\t(0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n@@ -2205,8 +2215,8 @@\n #define PRTDCB_TX_DSCP2UP_CTL\t\t\t0x00040980 /* Reset Source: CORER */\n #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S\t0\n #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M\tBIT(0)\n-#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1\n-#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)\n+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S\t1\n+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M\tMAKEMASK(0x7, 1)\n #define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i)\t\t(0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */\n #define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX\t7\n #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0\n@@ -2354,8 +2364,8 @@\n #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0\n #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)\n #define TPB_PRTTCB_LL_DWRR_WB_CREDITS\t\t0x00099320 /* Reset Source: CORER */\n-#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0\n-#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)\n+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S\t0\n+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M\tMAKEMASK(0x3FFFF, 0)\n #define TPB_WB_RL_TC_CFG(_i)\t\t\t(0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n #define TPB_WB_RL_TC_CFG_MAX_INDEX\t\t31\n #define TPB_WB_RL_TC_CFG_TOKENS_S\t\t0\n@@ -2420,8 +2430,8 @@\n #define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX\t2\n #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S\t0\n #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M\tMAKEMASK(0xF, 0)\n-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31\n-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)\n+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S\t31\n+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M\tBIT(31)\n #define GL_ACLEXT_FORCE_PID(_i)\t\t\t(0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n #define GL_ACLEXT_FORCE_PID_MAX_INDEX\t\t2\n #define GL_ACLEXT_FORCE_PID_STATIC_PID_S\t0\n@@ -2614,8 +2624,8 @@\n #define GL_PREEXT_FORCE_L1CDID_MAX_INDEX\t2\n #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S\t0\n #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M\tMAKEMASK(0xF, 0)\n-#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31\n-#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)\n+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S\t31\n+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M\tBIT(31)\n #define GL_PREEXT_FORCE_PID(_i)\t\t\t(0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n #define GL_PREEXT_FORCE_PID_MAX_INDEX\t\t2\n #define GL_PREEXT_FORCE_PID_STATIC_PID_S\t0\n@@ -2816,8 +2826,8 @@\n #define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX\t2\n #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S\t0\n #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M\tMAKEMASK(0xF, 0)\n-#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31\n-#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)\n+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S\t31\n+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M\tBIT(31)\n #define GL_PSTEXT_FORCE_PID(_i)\t\t\t(0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n #define GL_PSTEXT_FORCE_PID_MAX_INDEX\t\t2\n #define GL_PSTEXT_FORCE_PID_STATIC_PID_S\t0\n@@ -2984,10 +2994,10 @@\n #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)\n #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8\n #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)\n-#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12\n-#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)\n-#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14\n-#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S\t12\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M\tMAKEMASK(0x3, 12)\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S\t14\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M\tMAKEMASK(0x3, 14)\n #define GLFLXP_RX_CMD_PROTIDS(_i, _j)\t\t(0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */\n #define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX\t\t255\n #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S\t0\n@@ -3066,8 +3076,8 @@\n #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M\tMAKEMASK(0xFF, 0)\n #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S\t8\n #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M\tMAKEMASK(0x1F, 8)\n-#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16\n-#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)\n+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S\t16\n+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M\tMAKEMASK(0xFF, 16)\n #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S\t24\n #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M\tMAKEMASK(0x1F, 24)\n #define QRXFLXP_CNTXT(_QRX)\t\t\t(0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n@@ -3280,18 +3290,18 @@\n #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)\n #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9\n #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)\n-#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14\n-#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)\n+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S\t14\n+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M\tMAKEMASK(0x3, 14)\n #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S\t16\n #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M\tMAKEMASK(0xF, 16)\n-#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20\n-#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)\n+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S\t20\n+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M\tBIT(20)\n #define GLGEN_ANA_TX_ABORT_PTYPE\t\t0x0020D21C /* Reset Source: CORER */\n #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S\t0\n #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M\tMAKEMASK(0x3FF, 0)\n #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT\t0x0020D208 /* Reset Source: CORER */\n-#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0\n-#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)\n+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S\t0\n+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M\tMAKEMASK(0xFF, 0)\n #define GLGEN_ANA_TX_CFG_CTRL\t\t\t0x0020D104 /* Reset Source: CORER */\n #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S\t0\n #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M\tMAKEMASK(0x3FFFF, 0)\n@@ -3317,10 +3327,10 @@\n #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S\t0\n #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT\t0x0020D15C /* Reset Source: CORER */\n-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0\n-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)\n-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1\n-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)\n+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S\t0\n+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M\tBIT(0)\n+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S\t1\n+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M\tMAKEMASK(0x7, 1)\n #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4\n #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)\n #define GLGEN_ANA_TX_CFG_WRDATA\t\t\t0x0020D108 /* Reset Source: CORER */\n@@ -3639,8 +3649,8 @@\n #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S\t0\n #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLHMC_FWSDDATAHIGH_FPMAT\t\t0x00102078 /* Reset Source: CORER */\n-#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0\n-#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S\t0\n+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLHMC_FWSDDATALOW\t\t\t0x00522074 /* Reset Source: CORER */\n #define GLHMC_FWSDDATALOW_PMSDVALID_S\t\t0\n #define GLHMC_FWSDDATALOW_PMSDVALID_M\t\tBIT(0)\n@@ -4038,8 +4048,8 @@\n #define GLHMC_VFPEMRCNT_FPMPEMRSZ_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n #define GLHMC_VFPEOOISCBASE(_i)\t\t\t(0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n #define GLHMC_VFPEOOISCBASE_MAX_INDEX\t\t31\n-#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0\n-#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S\t0\n+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLHMC_VFPEOOISCCNT(_i)\t\t\t(0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n #define GLHMC_VFPEOOISCCNT_MAX_INDEX\t\t31\n #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S\t0\n@@ -4086,8 +4096,8 @@\n #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLHMC_VFPERRFFLBASE(_i)\t\t\t(0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n #define GLHMC_VFPERRFFLBASE_MAX_INDEX\t\t31\n-#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0\n-#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S\t0\n+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLHMC_VFPETIMERBASE(_i)\t\t\t(0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n #define GLHMC_VFPETIMERBASE_MAX_INDEX\t\t31\n #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S\t0\n@@ -4114,8 +4124,8 @@\n #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLHMC_VFSDDATAHIGH_FPMAT(_i)\t\t(0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n #define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX\t31\n-#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0\n-#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S\t0\n+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLHMC_VFSDDATALOW(_i)\t\t\t(0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n #define GLHMC_VFSDDATALOW_MAX_INDEX\t\t31\n #define GLHMC_VFSDDATALOW_PMSDVALID_S\t\t0\n@@ -4221,8 +4231,8 @@\n #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M\tBIT(7)\n #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S\t8\n #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M\tMAKEMASK(0xF, 8)\n-#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16\n-#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)\n+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S\t16\n+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M\tMAKEMASK(0x1F, 16)\n #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S\t31\n #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M\tBIT(31)\n #define PFHMC_PDINV\t\t\t\t0x00520300 /* Reset Source: PFR */\n@@ -4309,8 +4319,8 @@\n #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)\n #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12\n #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)\n-#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13\n-#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)\n+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S\t13\n+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M\tBIT(13)\n #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14\n #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)\n #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15\n@@ -5205,10 +5215,10 @@\n #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL\t0x001E36C0 /* Reset Source: GLOBR */\n #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0\n #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)\n-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1\t0x001E3220 /* Reset Source: GLOBR */\n #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0\n #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)\n-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2\t0x001E3240 /* Reset Source: GLOBR */\n #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0\n #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)\n #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE\t\t0x001E3180 /* Reset Source: GLOBR */\n@@ -5309,10 +5319,10 @@\n #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M\tBIT(17)\n #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S\t18\n #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M\tBIT(18)\n-#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19\n-#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)\n-#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20\n-#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)\n+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S\t19\n+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M\tBIT(19)\n+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S\t20\n+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M\tBIT(20)\n #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S\t21\n #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M\tBIT(21)\n #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22\n@@ -5331,8 +5341,8 @@\n #define GL_MDCK_TX_TDPU\t\t\t\t0x00049348 /* Reset Source: CORER */\n #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S\t0\n #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M\tBIT(0)\n-#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1\n-#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)\n+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S\t1\n+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M\tBIT(1)\n #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S\t2\n #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M\tBIT(2)\n #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S\t3\n@@ -5345,8 +5355,8 @@\n #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)\n #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S\t7\n #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M\tBIT(7)\n-#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8\n-#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)\n+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S\t8\n+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M\tBIT(8)\n #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9\n #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)\n #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S\t10\n@@ -5428,8 +5438,8 @@\n #define VP_MDET_TX_TDPU_VALID_M\t\t\tBIT(0)\n #define GENERAL_MNG_FW_DBG_CSR(_i)\t\t(0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */\n #define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX\t9\n-#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0\n-#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S\t0\n+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GL_FWRESETCNT\t\t\t\t0x00083100 /* Reset Source: POR */\n #define GL_FWRESETCNT_FWRESETCNT_S\t\t0\n #define GL_FWRESETCNT_FWRESETCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n@@ -5841,8 +5851,8 @@\n #define GL_XLR_MARKER_TRIG_RCU_PRS\t\t0x002001C0 /* Reset Source: CORER */\n #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S\t0\n #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M\tMAKEMASK(0x3FF, 0)\n-#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10\n-#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S\t10\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M\tMAKEMASK(0x3, 10)\n #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S\t12\n #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M\tMAKEMASK(0x7, 12)\n #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S\t16\n@@ -6721,11 +6731,11 @@\n #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S\t0\n #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLPES_TCPRXFOURHOLEHI\t\t\t0x0055E03C /* Reset Source: CORER */\n-#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0\n-#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S\t0\n+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M\tMAKEMASK(0xFFFFFF, 0)\n #define GLPES_TCPRXFOURHOLELO\t\t\t0x0055E038 /* Reset Source: CORER */\n-#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0\n-#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S\t0\n+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define GLPES_TCPRXONEHOLEHI\t\t\t0x0055E024 /* Reset Source: CORER */\n #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S\t0\n #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M\tMAKEMASK(0xFFFFFF, 0)\n@@ -8206,7 +8216,7 @@\n #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S\t0\n #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i)\t(0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n-#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63\n+#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX\t63\n #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S\t0\n #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n #define EMP_SWT_PRUNIND\t\t\t\t0x00204020 /* Reset Source: CORER */\n@@ -9448,5 +9458,5 @@\n #define VFPE_WQEALLOC1_PEQPID_M\t\t\tMAKEMASK(0x3FFFF, 0)\n #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S\t\t20\n #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M\t\tMAKEMASK(0xFFF, 20)\n+#endif /* !_ICE_HW_AUTOGEN_H_ */\n \n-#endif\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 2b76a11e22..7860006206 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -1214,11 +1214,11 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)\n \t\tbreak;\n \t}\n \n-\tfor (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)\n+\tfor (i = 0; i <= GL_HIDA_MAX_INDEX; i++)\n \t\tif (offset == (u32)GL_HIDA(i))\n \t\t\treturn ICE_SUCCESS;\n \n-\tfor (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)\n+\tfor (i = 0; i <= GL_HIBA_MAX_INDEX; i++)\n \t\tif (offset == (u32)GL_HIBA(i))\n \t\t\treturn ICE_SUCCESS;\n \ndiff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h\nindex af18344cf8..52e8853b19 100644\n--- a/drivers/net/ice/base/ice_nvm.h\n+++ b/drivers/net/ice/base/ice_nvm.h\n@@ -67,19 +67,6 @@ union ice_nvm_access_data {\n \tstruct ice_nvm_features drv_features; /* NVM features */\n };\n \n-/* NVM Access registers */\n-#define GL_HIDA(_i)\t\t\t(0x00082000 + ((_i) * 4))\n-#define GL_HIBA(_i)\t\t\t(0x00081000 + ((_i) * 4))\n-#define GL_HICR\t\t\t\t0x00082040\n-#define GL_HICR_EN\t\t\t0x00082044\n-#define GLGEN_CSR_DEBUG_C\t\t0x00075750\n-#define GLPCI_LBARCTRL\t\t\t0x0009DE74\n-#define GLNVM_GENS\t\t\t0x000B6100\n-#define GLNVM_FLA\t\t\t0x000B6108\n-\n-#define ICE_NVM_ACCESS_GL_HIDA_MAX\t15\n-#define ICE_NVM_ACCESS_GL_HIBA_MAX\t1023\n-\n u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);\n u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);\n u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);\n", "prefixes": [ "12/12" ] }