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GET /api/patches/99010/?format=api
{ "id": 99010, "url": "http://patches.dpdk.org/api/patches/99010/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210916095304.3058210-4-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210916095304.3058210-4-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210916095304.3058210-4-qi.z.zhang@intel.com", "date": "2021-09-16T09:52:55", "name": "[03/12] net/ice/base: use macro instead of open-coded division", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "dc6a0186419676ae2b30650302e4f7d7e90ce505", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210916095304.3058210-4-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18975, "url": "http://patches.dpdk.org/api/series/18975/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18975", "date": "2021-09-16T09:52:52", "name": "ice base code batch 2 for DPDK 21.11", "version": 1, "mbox": "http://patches.dpdk.org/series/18975/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/99010/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/99010/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CF46FA0C41;\n\tThu, 16 Sep 2021 11:50:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8CBC6410F8;\n\tThu, 16 Sep 2021 11:50:08 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 2BD01410EF\n for <dev@dpdk.org>; Thu, 16 Sep 2021 11:50:07 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Sep 2021 02:50:06 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 16 Sep 2021 02:50:04 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10108\"; a=\"222185854\"", "E=Sophos;i=\"5.85,298,1624345200\"; d=\"scan'208\";a=\"222185854\"", "E=Sophos;i=\"5.85,298,1624345200\"; d=\"scan'208\";a=\"509246900\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Thu, 16 Sep 2021 17:52:55 +0800", "Message-Id": "<20210916095304.3058210-4-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210916095304.3058210-1-qi.z.zhang@intel.com>", "References": "<20210916095304.3058210-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 03/12] net/ice/base: use macro instead of\n open-coded division", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "For some operating systems, 64-bit division requires using specific\nimplementations. Use the DIV_64BIT macro to replace open-coded division\nso that the driver may convert this to the appropriate operating-system\nspecific implementation when necessary.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 53 +++++++++++++++++++------------\n 1 file changed, 32 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 8ea75538fa..70eb87abf9 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -1634,7 +1634,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)\n #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */\n \n \t/* Program the 10Gb/40Gb conversion ratio */\n-\tuix = (tu_per_sec * LINE_UI_10G_40G) / 390625000;\n+\tuix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);\n \n \tstatus = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,\n \t\t\t\t\t uix);\n@@ -1645,7 +1645,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)\n \t}\n \n \t/* Program the 25Gb/100Gb conversion ratio */\n-\tuix = (tu_per_sec * LINE_UI_25G_100G) / 390625000;\n+\tuix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);\n \n \tstatus = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,\n \t\t\t\t\t uix);\n@@ -1727,7 +1727,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PAR_TX_TUS */\n \tif (e822_vernier[link_spd].tx_par_clk)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].tx_par_clk;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_par_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1738,7 +1739,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PAR_RX_TUS */\n \tif (e822_vernier[link_spd].rx_par_clk)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].rx_par_clk;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_par_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1749,7 +1751,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PCS_TX_TUS */\n \tif (e822_vernier[link_spd].tx_pcs_clk)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].tx_pcs_clk;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_pcs_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1760,7 +1763,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PCS_RX_TUS */\n \tif (e822_vernier[link_spd].rx_pcs_clk)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].rx_pcs_clk;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_pcs_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1771,7 +1775,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PAR_TX_TUS */\n \tif (e822_vernier[link_spd].tx_desk_rsgb_par)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_par;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_desk_rsgb_par);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1782,7 +1787,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PAR_RX_TUS */\n \tif (e822_vernier[link_spd].rx_desk_rsgb_par)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_par;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_desk_rsgb_par);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1793,7 +1799,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PCS_TX_TUS */\n \tif (e822_vernier[link_spd].tx_desk_rsgb_pcs)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_pcs;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_desk_rsgb_pcs);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1804,7 +1811,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PCS_RX_TUS */\n \tif (e822_vernier[link_spd].rx_desk_rsgb_pcs)\n-\t\tphy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_pcs;\n+\t\tphy_tus = DIV_64BIT(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_desk_rsgb_pcs);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1836,9 +1844,9 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)\n \t * overflows 64 bit integer arithmetic, so break it up into two\n \t * divisions by 1e4 first then by 1e7.\n \t */\n-\tfixed_offset = tu_per_sec / 10000;\n+\tfixed_offset = DIV_64BIT(tu_per_sec, 10000);\n \tfixed_offset *= e822_vernier[link_spd].tx_fixed_delay;\n-\tfixed_offset /= 10000000;\n+\tfixed_offset = DIV_64BIT(fixed_offset, 10000000);\n \n \treturn fixed_offset;\n }\n@@ -1982,9 +1990,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t\t\t enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)\n {\n \tu64 cur_freq, clk_incval, tu_per_sec, mult, adj;\n+\tu32 pmd_adj_divisor, val;\n \tenum ice_status status;\n \tu8 pmd_align;\n-\tu32 val;\n \n \tstatus = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);\n \tif (status) {\n@@ -2001,6 +2009,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t/* Calculate TUs per second */\n \ttu_per_sec = cur_freq * clk_incval;\n \n+\t/* Get the link speed dependent PMD adjustment divisor */\n+\tpmd_adj_divisor = e822_vernier[link_spd].pmd_adj_divisor;\n+\n \t/* The PMD alignment adjustment measurement depends on the link speed,\n \t * and whether FEC is enabled. For each link speed, the alignment\n \t * adjustment is calculated by dividing a value by the length of\n@@ -2063,9 +2074,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t * divide by 125, and then handle remaining divisor based on the link\n \t * speed pmd_adj_divisor value.\n \t */\n-\tadj = tu_per_sec / 125;\n+\tadj = DIV_64BIT(tu_per_sec, 125);\n \tadj *= mult;\n-\tadj /= e822_vernier[link_spd].pmd_adj_divisor;\n+\tadj = DIV_64BIT(adj, pmd_adj_divisor);\n \n \t/* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx\n \t * cycle count is necessary.\n@@ -2086,9 +2097,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t\tif (rx_cycle) {\n \t\t\tmult = (4 - rx_cycle) * 40;\n \n-\t\t\tcycle_adj = tu_per_sec / 125;\n+\t\t\tcycle_adj = DIV_64BIT(tu_per_sec, 125);\n \t\t\tcycle_adj *= mult;\n-\t\t\tcycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;\n+\t\t\tcycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);\n \n \t\t\tadj += cycle_adj;\n \t\t}\n@@ -2108,9 +2119,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t\tif (rx_cycle) {\n \t\t\tmult = rx_cycle * 40;\n \n-\t\t\tcycle_adj = tu_per_sec / 125;\n+\t\t\tcycle_adj = DIV_64BIT(tu_per_sec, 125);\n \t\t\tcycle_adj *= mult;\n-\t\t\tcycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;\n+\t\t\tcycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);\n \n \t\t\tadj += cycle_adj;\n \t\t}\n@@ -2146,9 +2157,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)\n \t * overflows 64 bit integer arithmetic, so break it up into two\n \t * divisions by 1e4 first then by 1e7.\n \t */\n-\tfixed_offset = tu_per_sec / 10000;\n+\tfixed_offset = DIV_64BIT(tu_per_sec, 10000);\n \tfixed_offset *= e822_vernier[link_spd].rx_fixed_delay;\n-\tfixed_offset /= 10000000;\n+\tfixed_offset = DIV_64BIT(fixed_offset, 10000000);\n \n \treturn fixed_offset;\n }\n", "prefixes": [ "03/12" ] }