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{
    "id": 98733,
    "url": "http://patches.dpdk.org/api/patches/98733/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210911153041.28510-7-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210911153041.28510-7-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210911153041.28510-7-venkatkumar.duvvuru@broadcom.com",
    "date": "2021-09-11T15:30:34",
    "name": "[v3,06/13] net/bnxt: add support for tunnel offloads",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "da0c24b9a936861daa29488ca1ad5b9384941b9f",
    "submitter": {
        "id": 1635,
        "url": "http://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210911153041.28510-7-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 18856,
            "url": "http://patches.dpdk.org/api/series/18856/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18856",
            "date": "2021-09-11T15:30:28",
            "name": "enhancements to host based flow table management",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/18856/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/98733/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/98733/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9EF47A0C4B;\n\tMon, 13 Sep 2021 10:06:21 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1C70B40151;\n\tMon, 13 Sep 2021 10:06:21 +0200 (CEST)",
            "from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com\n [192.19.166.228])\n by mails.dpdk.org (Postfix) with ESMTP id EC11E410F1\n for <dev@dpdk.org>; Sat, 11 Sep 2021 17:30:55 +0200 (CEST)",
            "from S60.dhcp.broadcom.net (unknown [10.123.66.170])\n (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n (No client certificate requested)\n by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 87A9F80DE;\n Sat, 11 Sep 2021 08:30:53 -0700 (PDT)"
        ],
        "DKIM-Filter": "OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 87A9F80DE",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1631374255;\n bh=yoSP1lLzHdCfLfTD/2giZoTz47h6g7YqIlhe7kfKWxc=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=wR9YJlWScLZBdVru+6OesHVvyGqJqDndZANkYOc5GStepNIIVpJk7B06gZDTqgupc\n rLSNJg5lyepktGpapU9wXdL9Q4M+8m1/6x87+pI3LFUsUOEFUY8R49KQh+1HG7Z1F/\n bT8hV3/B77zcBxXbTH5qejgqL8OW2fwHm7Ehgqig=",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "Date": "Sat, 11 Sep 2021 21:00:34 +0530",
        "Message-Id": "<20210911153041.28510-7-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210911153041.28510-1-venkatkumar.duvvuru@broadcom.com>",
        "References": "<20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com>\n <20210911153041.28510-1-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailman-Approved-At": "Mon, 13 Sep 2021 10:06:19 +0200",
        "Subject": "[dpdk-dev] [PATCH v3 06/13] net/bnxt: add support for tunnel\n offloads",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\nAdded support for tunnel offloads, this includes the support for\nVXLAN decap action where two flows indicate tunnel offload rule. The\nfirst flow indicate the tunnel properties and second flow indicates the\ninner packet structure. The templates are updated to support this\nfeature.\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>\n---\n drivers/net/bnxt/tf_ulp/bnxt_tf_common.h      |    4 +-\n drivers/net/bnxt/tf_ulp/bnxt_ulp.c            |   12 +-\n drivers/net/bnxt/tf_ulp/bnxt_ulp.h            |   20 +-\n drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c       |  212 +-\n .../generic_templates/ulp_template_db_act.c   |    2 +-\n .../generic_templates/ulp_template_db_class.c | 8541 +++++++++++-----\n .../generic_templates/ulp_template_db_enum.h  |  210 +-\n .../generic_templates/ulp_template_db_field.h |  654 +-\n .../generic_templates/ulp_template_db_tbl.c   |  645 +-\n .../ulp_template_db_thor_class.c              |  110 +-\n .../ulp_template_db_wh_plus_act.c             |    2 +-\n .../ulp_template_db_wh_plus_class.c           | 8577 +++++++++++------\n drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c          |   46 +-\n drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h          |    8 +-\n drivers/net/bnxt/tf_ulp/ulp_flow_db.c         |  562 +-\n drivers/net/bnxt/tf_ulp/ulp_flow_db.h         |   44 +-\n drivers/net/bnxt/tf_ulp/ulp_mapper.c          |   52 +-\n drivers/net/bnxt/tf_ulp/ulp_mapper.h          |    6 +-\n drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c |   31 +\n drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |  134 +-\n drivers/net/bnxt/tf_ulp/ulp_rte_parser.h      |   10 +-\n drivers/net/bnxt/tf_ulp/ulp_template_struct.h |   10 +-\n drivers/net/bnxt/tf_ulp/ulp_tun.c             |  541 +-\n drivers/net/bnxt/tf_ulp/ulp_tun.h             |   89 +-\n 24 files changed, 13810 insertions(+), 6712 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h\nindex e0ebed3fed..6c4bcd2d90 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h\n@@ -37,9 +37,7 @@\n enum bnxt_tf_rc {\n \tBNXT_TF_RC_PARSE_ERR\t= -2,\n \tBNXT_TF_RC_ERROR\t= -1,\n-\tBNXT_TF_RC_SUCCESS\t= 0,\n-\tBNXT_TF_RC_NORMAL\t= 1,\n-\tBNXT_TF_RC_FID\t\t= 2,\n+\tBNXT_TF_RC_SUCCESS\t= 0\n };\n \n /* eth IPv4 Type */\ndiff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\nindex 475c7a6cdf..dfafd9ff5b 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\n@@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp,\n \tif (rc)\n \t\tgoto error_deinit;\n \n-\tulp_tun_tbl_init(ulp_data->tun_tbl);\n-\n \tbnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);\n \treturn rc;\n \n@@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void)\n {\n \trte_spinlock_unlock(&bnxt_ulp_ctxt_lock);\n }\n+\n+/* Function to get the app tunnel details from the ulp context. */\n+struct bnxt_flow_app_tun_ent *\n+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)\n+{\n+\tif (!ulp || !ulp->cfg_data)\n+\t\treturn NULL;\n+\n+\treturn ulp->cfg_data->app_tun;\n+}\ndiff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h\nindex 082ca501b6..006df9cbc5 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h\n@@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type {\n \tBNXT_ULP_FLOW_MEM_TYPE_LAST = 3\n };\n \n+enum bnxt_rte_flow_item_type {\n+\tBNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN,\n+\tBNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP,\n+\tBNXT_RTE_FLOW_ITEM_TYPE_LAST\n+};\n+\n+enum bnxt_rte_flow_action_type {\n+\tBNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN,\n+\tBNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP,\n+\tBNXT_RTE_FLOW_ACTION_TYPE_LAST\n+};\n+\n struct bnxt_ulp_df_rule_info {\n \tuint32_t\t\t\tdef_port_flow_id;\n \tuint8_t\t\t\t\tvalid;\n@@ -79,6 +91,7 @@ struct bnxt_ulp_data {\n \tbool\t\t\t\taccum_stats;\n \tuint8_t\t\t\t\tapp_id;\n \tuint8_t\t\t\t\tnum_shared_clients;\n+\tstruct bnxt_flow_app_tun_ent\tapp_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];\n };\n \n struct bnxt_ulp_context {\n@@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context\t*ulp_ctx);\n void\n bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context\t*ulp_ctx);\n \n-int32_t\n-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params);\n-\n struct bnxt_ulp_glb_resource_info *\n bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);\n \n@@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void);\n \n uint8_t\n bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);\n+\n+struct bnxt_flow_app_tun_ent *\n+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);\n+\n #endif /* _BNXT_ULP_H_ */\ndiff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\nindex 238b1d9657..3daf5942e8 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\n@@ -12,6 +12,7 @@\n #include \"ulp_fc_mgr.h\"\n #include \"ulp_port_db.h\"\n #include \"ulp_ha_mgr.h\"\n+#include \"ulp_tun.h\"\n #include <rte_malloc.h>\n #ifdef\tRTE_LIBRTE_BNXT_TRUFLOW_DEBUG\n #include \"ulp_template_debug_proto.h\"\n@@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,\n \tmapper_cparms->act_prop = &params->act_prop;\n \tmapper_cparms->flow_id = params->fid;\n \tmapper_cparms->parent_flow = params->parent_flow;\n-\tmapper_cparms->parent_fid = params->parent_fid;\n+\tmapper_cparms->child_flow = params->child_flow;\n \tmapper_cparms->fld_bitmap = &params->fld_bitmap;\n \tmapper_cparms->flow_pattern_id = params->flow_pattern_id;\n \tmapper_cparms->act_pattern_id = params->act_pattern_id;\n \tmapper_cparms->app_id = params->app_id;\n \tmapper_cparms->port_id = params->port_id;\n+\tmapper_cparms->tun_idx = params->tun_idx;\n \n \t/* update the signature fields into the computed field list */\n \tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,\n@@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,\n \tparams.func_id = func_id;\n \tparams.priority = attr->priority;\n \tparams.port_id = dev->data->port_id;\n+\n \t/* Perform the rte flow post process */\n-\tret = bnxt_ulp_rte_parser_post_process(&params);\n+\tbnxt_ulp_rte_parser_post_process(&params);\n+\n+\t/* do the tunnel offload process if any */\n+\tret = ulp_tunnel_offload_process(&params);\n \tif (ret == BNXT_TF_RC_ERROR)\n \t\tgoto free_fid;\n-\telse if (ret == BNXT_TF_RC_FID)\n-\t\tgoto return_fid;\n \n #ifdef\tRTE_LIBRTE_BNXT_TRUFLOW_DEBUG\n #ifdef\tRTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER\n@@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,\n \tif (ret)\n \t\tgoto free_fid;\n \n-return_fid:\n \tbnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);\n \n \tflow_id = (struct rte_flow *)((uintptr_t)fid);\n@@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,\n \t\tgoto parse_error;\n \n \t/* Perform the rte flow post process */\n-\tret = bnxt_ulp_rte_parser_post_process(&params);\n+\tbnxt_ulp_rte_parser_post_process(&params);\n+\n+\t/* do the tunnel offload process if any */\n+\tret = ulp_tunnel_offload_process(&params);\n \tif (ret == BNXT_TF_RC_ERROR)\n \t\tgoto parse_error;\n-\telse if (ret == BNXT_TF_RC_FID)\n-\t\treturn 0;\n \n \tret = ulp_matcher_pattern_match(&params, &class_id);\n \n@@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,\n \treturn rc;\n }\n \n+/* Tunnel offload Apis */\n+#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS\t1\n+\n+static int\n+bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev,\n+\t\t\t  struct rte_flow_tunnel *tunnel,\n+\t\t\t  struct rte_flow_action **pmd_actions,\n+\t\t\t  uint32_t *num_of_actions,\n+\t\t\t  struct rte_flow_error *error)\n+{\n+\tstruct bnxt_ulp_context *ulp_ctx;\n+\tstruct bnxt_flow_app_tun_ent *tun_entry;\n+\tint32_t rc = 0;\n+\n+\tulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);\n+\tif (ulp_ctx == NULL) {\n+\t\tBNXT_TF_DBG(ERR, \"ULP context is not initialized\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"ULP context uninitialized\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (tunnel == NULL) {\n+\t\tBNXT_TF_DBG(ERR, \"No tunnel specified\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"no tunnel specified\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {\n+\t\tBNXT_TF_DBG(ERR, \"Tunnel type unsupported\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"tunnel type unsupported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);\n+\tif (rc < 0) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"tunnel decap set failed\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trc = ulp_app_tun_entry_set_decap_action(tun_entry);\n+\tif (rc < 0) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"tunnel decap set failed\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*pmd_actions = &tun_entry->action;\n+\t*num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev,\n+\t\t      struct rte_flow_tunnel *tunnel,\n+\t\t      struct rte_flow_item **pmd_items,\n+\t\t      uint32_t *num_of_items,\n+\t\t      struct rte_flow_error *error)\n+{\n+\tstruct bnxt_ulp_context *ulp_ctx;\n+\tstruct bnxt_flow_app_tun_ent *tun_entry;\n+\tint32_t rc = 0;\n+\n+\tulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);\n+\tif (ulp_ctx == NULL) {\n+\t\tBNXT_TF_DBG(ERR, \"ULP context is not initialized\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"ULP context uninitialized\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (tunnel == NULL) {\n+\t\tBNXT_TF_DBG(ERR, \"No tunnel specified\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"no tunnel specified\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {\n+\t\tBNXT_TF_DBG(ERR, \"Tunnel type unsupported\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"tunnel type unsupported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);\n+\tif (rc < 0) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"tunnel match set failed\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trc = ulp_app_tun_entry_set_decap_item(tun_entry);\n+\tif (rc < 0) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"tunnel match set failed\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*pmd_items = &tun_entry->item;\n+\t*num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev,\n+\t\t\t      struct rte_flow_action *pmd_actions,\n+\t\t\t      uint32_t num_actions,\n+\t\t\t      struct rte_flow_error *error)\n+{\n+\tstruct bnxt_ulp_context *ulp_ctx;\n+\tstruct bnxt_flow_app_tun_ent *tun_entry;\n+\tconst struct rte_flow_action *action_item = pmd_actions;\n+\n+\tulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);\n+\tif (ulp_ctx == NULL) {\n+\t\tBNXT_TF_DBG(ERR, \"ULP context is not initialized\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"ULP context uninitialized\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {\n+\t\tBNXT_TF_DBG(ERR, \"num actions is invalid\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"num actions is invalid\");\n+\t\treturn -EINVAL;\n+\t}\n+\twhile (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {\n+\t\tif (action_item->type == (typeof(tun_entry->action.type))\n+\t\t    BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) {\n+\t\t\ttun_entry = ulp_app_tun_match_entry(ulp_ctx,\n+\t\t\t\t\t\t\t    action_item->conf);\n+\t\t\tulp_app_tun_entry_delete(tun_entry);\n+\t\t}\n+\t\taction_item++;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev,\n+\t\t\t     struct rte_flow_item *pmd_items,\n+\t\t\t     uint32_t num_items,\n+\t\t\t     struct rte_flow_error *error)\n+{\n+\tstruct bnxt_ulp_context *ulp_ctx;\n+\tstruct bnxt_flow_app_tun_ent *tun_entry;\n+\n+\tulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);\n+\tif (ulp_ctx == NULL) {\n+\t\tBNXT_TF_DBG(ERR, \"ULP context is not initialized\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"ULP context uninitialized\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {\n+\t\tBNXT_TF_DBG(ERR, \"num items is invalid\\n\");\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t   \"num items is invalid\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec);\n+\tulp_app_tun_entry_delete(tun_entry);\n+\treturn 0;\n+}\n+\n const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {\n \t.validate = bnxt_ulp_flow_validate,\n \t.create = bnxt_ulp_flow_create,\n \t.destroy = bnxt_ulp_flow_destroy,\n \t.flush = bnxt_ulp_flow_flush,\n \t.query = bnxt_ulp_flow_query,\n-\t.isolate = NULL\n+\t.isolate = NULL,\n+\t/* Tunnel offload callbacks */\n+\t.tunnel_decap_set = bnxt_ulp_tunnel_decap_set,\n+\t.tunnel_match = bnxt_ulp_tunnel_match,\n+\t.tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release,\n+\t.tunnel_item_release = bnxt_ulp_tunnel_item_release,\n+\t.get_restore_info = NULL\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c\nindex e18f314856..0da6070d7d 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Wed Mar 17 11:31:19 2021 */\n+/* date: Mon May 17 15:30:41 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c\nindex 9c419f6a15..f74687acfa 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Wed Mar 17 11:31:19 2021 */\n+/* date: Thu May 20 11:56:39 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -360,348 +360,510 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {\n \t[BNXT_ULP_CLASS_HID_15db] = 342,\n \t[BNXT_ULP_CLASS_HID_1151] = 343,\n \t[BNXT_ULP_CLASS_HID_315d] = 344,\n-\t[BNXT_ULP_CLASS_HID_34c6] = 345,\n-\t[BNXT_ULP_CLASS_HID_0c22] = 346,\n-\t[BNXT_ULP_CLASS_HID_1cbe] = 347,\n-\t[BNXT_ULP_CLASS_HID_179a] = 348,\n-\t[BNXT_ULP_CLASS_HID_59be] = 349,\n-\t[BNXT_ULP_CLASS_HID_515a] = 350,\n-\t[BNXT_ULP_CLASS_HID_1c72] = 351,\n-\t[BNXT_ULP_CLASS_HID_171e] = 352,\n-\t[BNXT_ULP_CLASS_HID_19c8] = 353,\n-\t[BNXT_ULP_CLASS_HID_112c] = 354,\n-\t[BNXT_ULP_CLASS_HID_4d68] = 355,\n-\t[BNXT_ULP_CLASS_HID_444c] = 356,\n-\t[BNXT_ULP_CLASS_HID_0e8c] = 357,\n-\t[BNXT_ULP_CLASS_HID_09e0] = 358,\n-\t[BNXT_ULP_CLASS_HID_1af0] = 359,\n-\t[BNXT_ULP_CLASS_HID_15d4] = 360,\n-\t[BNXT_ULP_CLASS_HID_1dd0] = 361,\n-\t[BNXT_ULP_CLASS_HID_14f4] = 362,\n-\t[BNXT_ULP_CLASS_HID_70b0] = 363,\n-\t[BNXT_ULP_CLASS_HID_4854] = 364,\n-\t[BNXT_ULP_CLASS_HID_3dd4] = 365,\n-\t[BNXT_ULP_CLASS_HID_34f8] = 366,\n-\t[BNXT_ULP_CLASS_HID_09e8] = 367,\n-\t[BNXT_ULP_CLASS_HID_008c] = 368,\n-\t[BNXT_ULP_CLASS_HID_34e6] = 369,\n-\t[BNXT_ULP_CLASS_HID_0c02] = 370,\n-\t[BNXT_ULP_CLASS_HID_1c9e] = 371,\n-\t[BNXT_ULP_CLASS_HID_17ba] = 372,\n-\t[BNXT_ULP_CLASS_HID_429e] = 373,\n-\t[BNXT_ULP_CLASS_HID_5dba] = 374,\n-\t[BNXT_ULP_CLASS_HID_2a16] = 375,\n-\t[BNXT_ULP_CLASS_HID_2532] = 376,\n-\t[BNXT_ULP_CLASS_HID_2da2] = 377,\n-\t[BNXT_ULP_CLASS_HID_24fe] = 378,\n-\t[BNXT_ULP_CLASS_HID_355a] = 379,\n-\t[BNXT_ULP_CLASS_HID_0c76] = 380,\n-\t[BNXT_ULP_CLASS_HID_13e6] = 381,\n-\t[BNXT_ULP_CLASS_HID_7276] = 382,\n-\t[BNXT_ULP_CLASS_HID_42d2] = 383,\n-\t[BNXT_ULP_CLASS_HID_5dee] = 384,\n-\t[BNXT_ULP_CLASS_HID_59de] = 385,\n-\t[BNXT_ULP_CLASS_HID_513a] = 386,\n-\t[BNXT_ULP_CLASS_HID_1c12] = 387,\n-\t[BNXT_ULP_CLASS_HID_177e] = 388,\n-\t[BNXT_ULP_CLASS_HID_0e92] = 389,\n-\t[BNXT_ULP_CLASS_HID_09fe] = 390,\n-\t[BNXT_ULP_CLASS_HID_5c1a] = 391,\n-\t[BNXT_ULP_CLASS_HID_5746] = 392,\n-\t[BNXT_ULP_CLASS_HID_79da] = 393,\n-\t[BNXT_ULP_CLASS_HID_7106] = 394,\n-\t[BNXT_ULP_CLASS_HID_3c1e] = 395,\n-\t[BNXT_ULP_CLASS_HID_377a] = 396,\n-\t[BNXT_ULP_CLASS_HID_2e9e] = 397,\n-\t[BNXT_ULP_CLASS_HID_29fa] = 398,\n-\t[BNXT_ULP_CLASS_HID_14d2] = 399,\n-\t[BNXT_ULP_CLASS_HID_7742] = 400,\n-\t[BNXT_ULP_CLASS_HID_3706] = 401,\n-\t[BNXT_ULP_CLASS_HID_0fe2] = 402,\n-\t[BNXT_ULP_CLASS_HID_1f7e] = 403,\n-\t[BNXT_ULP_CLASS_HID_145a] = 404,\n-\t[BNXT_ULP_CLASS_HID_417e] = 405,\n-\t[BNXT_ULP_CLASS_HID_5e5a] = 406,\n-\t[BNXT_ULP_CLASS_HID_29f6] = 407,\n-\t[BNXT_ULP_CLASS_HID_26d2] = 408,\n-\t[BNXT_ULP_CLASS_HID_2e42] = 409,\n-\t[BNXT_ULP_CLASS_HID_271e] = 410,\n-\t[BNXT_ULP_CLASS_HID_36ba] = 411,\n-\t[BNXT_ULP_CLASS_HID_0f96] = 412,\n-\t[BNXT_ULP_CLASS_HID_1006] = 413,\n-\t[BNXT_ULP_CLASS_HID_7196] = 414,\n-\t[BNXT_ULP_CLASS_HID_4132] = 415,\n-\t[BNXT_ULP_CLASS_HID_5e0e] = 416,\n-\t[BNXT_ULP_CLASS_HID_59fe] = 417,\n-\t[BNXT_ULP_CLASS_HID_511a] = 418,\n-\t[BNXT_ULP_CLASS_HID_1c32] = 419,\n-\t[BNXT_ULP_CLASS_HID_175e] = 420,\n-\t[BNXT_ULP_CLASS_HID_0eb2] = 421,\n-\t[BNXT_ULP_CLASS_HID_09de] = 422,\n-\t[BNXT_ULP_CLASS_HID_5c3a] = 423,\n-\t[BNXT_ULP_CLASS_HID_5766] = 424,\n-\t[BNXT_ULP_CLASS_HID_79fa] = 425,\n-\t[BNXT_ULP_CLASS_HID_7126] = 426,\n-\t[BNXT_ULP_CLASS_HID_3c3e] = 427,\n-\t[BNXT_ULP_CLASS_HID_375a] = 428,\n-\t[BNXT_ULP_CLASS_HID_2ebe] = 429,\n-\t[BNXT_ULP_CLASS_HID_29da] = 430,\n-\t[BNXT_ULP_CLASS_HID_14f2] = 431,\n-\t[BNXT_ULP_CLASS_HID_7762] = 432,\n-\t[BNXT_ULP_CLASS_HID_19e8] = 433,\n-\t[BNXT_ULP_CLASS_HID_110c] = 434,\n-\t[BNXT_ULP_CLASS_HID_4d48] = 435,\n-\t[BNXT_ULP_CLASS_HID_446c] = 436,\n-\t[BNXT_ULP_CLASS_HID_0eac] = 437,\n-\t[BNXT_ULP_CLASS_HID_09c0] = 438,\n-\t[BNXT_ULP_CLASS_HID_1ad0] = 439,\n-\t[BNXT_ULP_CLASS_HID_15f4] = 440,\n-\t[BNXT_ULP_CLASS_HID_39ec] = 441,\n-\t[BNXT_ULP_CLASS_HID_3100] = 442,\n-\t[BNXT_ULP_CLASS_HID_0210] = 443,\n-\t[BNXT_ULP_CLASS_HID_1d34] = 444,\n-\t[BNXT_ULP_CLASS_HID_2ea0] = 445,\n-\t[BNXT_ULP_CLASS_HID_29c4] = 446,\n-\t[BNXT_ULP_CLASS_HID_3ad4] = 447,\n-\t[BNXT_ULP_CLASS_HID_35e8] = 448,\n-\t[BNXT_ULP_CLASS_HID_5d80] = 449,\n-\t[BNXT_ULP_CLASS_HID_54a4] = 450,\n-\t[BNXT_ULP_CLASS_HID_29b4] = 451,\n-\t[BNXT_ULP_CLASS_HID_20c8] = 452,\n-\t[BNXT_ULP_CLASS_HID_7244] = 453,\n-\t[BNXT_ULP_CLASS_HID_4d98] = 454,\n-\t[BNXT_ULP_CLASS_HID_5e68] = 455,\n-\t[BNXT_ULP_CLASS_HID_598c] = 456,\n-\t[BNXT_ULP_CLASS_HID_1248] = 457,\n-\t[BNXT_ULP_CLASS_HID_74d8] = 458,\n-\t[BNXT_ULP_CLASS_HID_49a8] = 459,\n-\t[BNXT_ULP_CLASS_HID_40cc] = 460,\n-\t[BNXT_ULP_CLASS_HID_0b0c] = 461,\n-\t[BNXT_ULP_CLASS_HID_0220] = 462,\n-\t[BNXT_ULP_CLASS_HID_1730] = 463,\n-\t[BNXT_ULP_CLASS_HID_7980] = 464,\n-\t[BNXT_ULP_CLASS_HID_1db0] = 465,\n-\t[BNXT_ULP_CLASS_HID_1494] = 466,\n-\t[BNXT_ULP_CLASS_HID_70d0] = 467,\n-\t[BNXT_ULP_CLASS_HID_4834] = 468,\n-\t[BNXT_ULP_CLASS_HID_3db4] = 469,\n-\t[BNXT_ULP_CLASS_HID_3498] = 470,\n-\t[BNXT_ULP_CLASS_HID_0988] = 471,\n-\t[BNXT_ULP_CLASS_HID_00ec] = 472,\n-\t[BNXT_ULP_CLASS_HID_3f44] = 473,\n-\t[BNXT_ULP_CLASS_HID_36a8] = 474,\n-\t[BNXT_ULP_CLASS_HID_0b58] = 475,\n-\t[BNXT_ULP_CLASS_HID_02bc] = 476,\n-\t[BNXT_ULP_CLASS_HID_5f48] = 477,\n-\t[BNXT_ULP_CLASS_HID_56ac] = 478,\n-\t[BNXT_ULP_CLASS_HID_2b5c] = 479,\n-\t[BNXT_ULP_CLASS_HID_2280] = 480,\n-\t[BNXT_ULP_CLASS_HID_4000] = 481,\n-\t[BNXT_ULP_CLASS_HID_5b64] = 482,\n-\t[BNXT_ULP_CLASS_HID_2c14] = 483,\n-\t[BNXT_ULP_CLASS_HID_2778] = 484,\n-\t[BNXT_ULP_CLASS_HID_18f8] = 485,\n-\t[BNXT_ULP_CLASS_HID_13dc] = 486,\n-\t[BNXT_ULP_CLASS_HID_4c18] = 487,\n-\t[BNXT_ULP_CLASS_HID_477c] = 488,\n-\t[BNXT_ULP_CLASS_HID_1a88] = 489,\n-\t[BNXT_ULP_CLASS_HID_15ec] = 490,\n-\t[BNXT_ULP_CLASS_HID_4e28] = 491,\n-\t[BNXT_ULP_CLASS_HID_490c] = 492,\n-\t[BNXT_ULP_CLASS_HID_3a8c] = 493,\n-\t[BNXT_ULP_CLASS_HID_35f0] = 494,\n-\t[BNXT_ULP_CLASS_HID_06e0] = 495,\n-\t[BNXT_ULP_CLASS_HID_01c4] = 496,\n-\t[BNXT_ULP_CLASS_HID_1a08] = 497,\n-\t[BNXT_ULP_CLASS_HID_12ec] = 498,\n-\t[BNXT_ULP_CLASS_HID_4ea8] = 499,\n-\t[BNXT_ULP_CLASS_HID_478c] = 500,\n-\t[BNXT_ULP_CLASS_HID_0d4c] = 501,\n-\t[BNXT_ULP_CLASS_HID_0a20] = 502,\n-\t[BNXT_ULP_CLASS_HID_1930] = 503,\n-\t[BNXT_ULP_CLASS_HID_1614] = 504,\n-\t[BNXT_ULP_CLASS_HID_3a0c] = 505,\n-\t[BNXT_ULP_CLASS_HID_32e0] = 506,\n-\t[BNXT_ULP_CLASS_HID_01f0] = 507,\n-\t[BNXT_ULP_CLASS_HID_1ed4] = 508,\n-\t[BNXT_ULP_CLASS_HID_2d40] = 509,\n-\t[BNXT_ULP_CLASS_HID_2a24] = 510,\n-\t[BNXT_ULP_CLASS_HID_3934] = 511,\n-\t[BNXT_ULP_CLASS_HID_3608] = 512,\n-\t[BNXT_ULP_CLASS_HID_5e60] = 513,\n-\t[BNXT_ULP_CLASS_HID_5744] = 514,\n-\t[BNXT_ULP_CLASS_HID_2a54] = 515,\n-\t[BNXT_ULP_CLASS_HID_2328] = 516,\n-\t[BNXT_ULP_CLASS_HID_71a4] = 517,\n-\t[BNXT_ULP_CLASS_HID_4e78] = 518,\n-\t[BNXT_ULP_CLASS_HID_5d88] = 519,\n-\t[BNXT_ULP_CLASS_HID_5a6c] = 520,\n-\t[BNXT_ULP_CLASS_HID_11a8] = 521,\n-\t[BNXT_ULP_CLASS_HID_7738] = 522,\n-\t[BNXT_ULP_CLASS_HID_4a48] = 523,\n-\t[BNXT_ULP_CLASS_HID_432c] = 524,\n-\t[BNXT_ULP_CLASS_HID_08ec] = 525,\n-\t[BNXT_ULP_CLASS_HID_01c0] = 526,\n-\t[BNXT_ULP_CLASS_HID_14d0] = 527,\n-\t[BNXT_ULP_CLASS_HID_7a60] = 528,\n-\t[BNXT_ULP_CLASS_HID_1d90] = 529,\n-\t[BNXT_ULP_CLASS_HID_14b4] = 530,\n-\t[BNXT_ULP_CLASS_HID_70f0] = 531,\n-\t[BNXT_ULP_CLASS_HID_4814] = 532,\n-\t[BNXT_ULP_CLASS_HID_3d94] = 533,\n-\t[BNXT_ULP_CLASS_HID_34b8] = 534,\n-\t[BNXT_ULP_CLASS_HID_09a8] = 535,\n-\t[BNXT_ULP_CLASS_HID_00cc] = 536,\n-\t[BNXT_ULP_CLASS_HID_3f64] = 537,\n-\t[BNXT_ULP_CLASS_HID_3688] = 538,\n-\t[BNXT_ULP_CLASS_HID_0b78] = 539,\n-\t[BNXT_ULP_CLASS_HID_029c] = 540,\n-\t[BNXT_ULP_CLASS_HID_5f68] = 541,\n-\t[BNXT_ULP_CLASS_HID_568c] = 542,\n-\t[BNXT_ULP_CLASS_HID_2b7c] = 543,\n-\t[BNXT_ULP_CLASS_HID_22a0] = 544,\n-\t[BNXT_ULP_CLASS_HID_4020] = 545,\n-\t[BNXT_ULP_CLASS_HID_5b44] = 546,\n-\t[BNXT_ULP_CLASS_HID_2c34] = 547,\n-\t[BNXT_ULP_CLASS_HID_2758] = 548,\n-\t[BNXT_ULP_CLASS_HID_18d8] = 549,\n-\t[BNXT_ULP_CLASS_HID_13fc] = 550,\n-\t[BNXT_ULP_CLASS_HID_4c38] = 551,\n-\t[BNXT_ULP_CLASS_HID_475c] = 552,\n-\t[BNXT_ULP_CLASS_HID_1aa8] = 553,\n-\t[BNXT_ULP_CLASS_HID_15cc] = 554,\n-\t[BNXT_ULP_CLASS_HID_4e08] = 555,\n-\t[BNXT_ULP_CLASS_HID_492c] = 556,\n-\t[BNXT_ULP_CLASS_HID_3aac] = 557,\n-\t[BNXT_ULP_CLASS_HID_35d0] = 558,\n-\t[BNXT_ULP_CLASS_HID_06c0] = 559,\n-\t[BNXT_ULP_CLASS_HID_01e4] = 560,\n-\t[BNXT_ULP_CLASS_HID_4d32] = 561,\n-\t[BNXT_ULP_CLASS_HID_54aa] = 562,\n-\t[BNXT_ULP_CLASS_HID_0686] = 563,\n-\t[BNXT_ULP_CLASS_HID_540e] = 564,\n-\t[BNXT_ULP_CLASS_HID_2e3c] = 565,\n-\t[BNXT_ULP_CLASS_HID_3a20] = 566,\n-\t[BNXT_ULP_CLASS_HID_46f0] = 567,\n-\t[BNXT_ULP_CLASS_HID_52e4] = 568,\n-\t[BNXT_ULP_CLASS_HID_55e4] = 569,\n-\t[BNXT_ULP_CLASS_HID_21f8] = 570,\n-\t[BNXT_ULP_CLASS_HID_75e8] = 571,\n-\t[BNXT_ULP_CLASS_HID_41fc] = 572,\n-\t[BNXT_ULP_CLASS_HID_4d12] = 573,\n-\t[BNXT_ULP_CLASS_HID_548a] = 574,\n-\t[BNXT_ULP_CLASS_HID_3356] = 575,\n-\t[BNXT_ULP_CLASS_HID_1ace] = 576,\n-\t[BNXT_ULP_CLASS_HID_1a9a] = 577,\n-\t[BNXT_ULP_CLASS_HID_4d46] = 578,\n-\t[BNXT_ULP_CLASS_HID_2812] = 579,\n-\t[BNXT_ULP_CLASS_HID_338a] = 580,\n-\t[BNXT_ULP_CLASS_HID_06e6] = 581,\n-\t[BNXT_ULP_CLASS_HID_546e] = 582,\n-\t[BNXT_ULP_CLASS_HID_46ee] = 583,\n-\t[BNXT_ULP_CLASS_HID_0d22] = 584,\n-\t[BNXT_ULP_CLASS_HID_26e2] = 585,\n-\t[BNXT_ULP_CLASS_HID_746a] = 586,\n-\t[BNXT_ULP_CLASS_HID_1fa6] = 587,\n-\t[BNXT_ULP_CLASS_HID_2d2e] = 588,\n-\t[BNXT_ULP_CLASS_HID_4ef2] = 589,\n-\t[BNXT_ULP_CLASS_HID_576a] = 590,\n-\t[BNXT_ULP_CLASS_HID_30b6] = 591,\n-\t[BNXT_ULP_CLASS_HID_192e] = 592,\n-\t[BNXT_ULP_CLASS_HID_197a] = 593,\n-\t[BNXT_ULP_CLASS_HID_4ea6] = 594,\n-\t[BNXT_ULP_CLASS_HID_2bf2] = 595,\n-\t[BNXT_ULP_CLASS_HID_306a] = 596,\n-\t[BNXT_ULP_CLASS_HID_06c6] = 597,\n-\t[BNXT_ULP_CLASS_HID_544e] = 598,\n-\t[BNXT_ULP_CLASS_HID_46ce] = 599,\n-\t[BNXT_ULP_CLASS_HID_0d02] = 600,\n-\t[BNXT_ULP_CLASS_HID_26c2] = 601,\n-\t[BNXT_ULP_CLASS_HID_744a] = 602,\n-\t[BNXT_ULP_CLASS_HID_1f86] = 603,\n-\t[BNXT_ULP_CLASS_HID_2d0e] = 604,\n-\t[BNXT_ULP_CLASS_HID_2e1c] = 605,\n-\t[BNXT_ULP_CLASS_HID_3a00] = 606,\n-\t[BNXT_ULP_CLASS_HID_46d0] = 607,\n-\t[BNXT_ULP_CLASS_HID_52c4] = 608,\n-\t[BNXT_ULP_CLASS_HID_4e10] = 609,\n-\t[BNXT_ULP_CLASS_HID_5a04] = 610,\n-\t[BNXT_ULP_CLASS_HID_1f98] = 611,\n-\t[BNXT_ULP_CLASS_HID_72f8] = 612,\n-\t[BNXT_ULP_CLASS_HID_0a78] = 613,\n-\t[BNXT_ULP_CLASS_HID_166c] = 614,\n-\t[BNXT_ULP_CLASS_HID_233c] = 615,\n-\t[BNXT_ULP_CLASS_HID_0f20] = 616,\n-\t[BNXT_ULP_CLASS_HID_2a7c] = 617,\n-\t[BNXT_ULP_CLASS_HID_3660] = 618,\n-\t[BNXT_ULP_CLASS_HID_4330] = 619,\n-\t[BNXT_ULP_CLASS_HID_2f24] = 620,\n-\t[BNXT_ULP_CLASS_HID_5584] = 621,\n-\t[BNXT_ULP_CLASS_HID_2198] = 622,\n-\t[BNXT_ULP_CLASS_HID_7588] = 623,\n-\t[BNXT_ULP_CLASS_HID_419c] = 624,\n-\t[BNXT_ULP_CLASS_HID_7758] = 625,\n-\t[BNXT_ULP_CLASS_HID_43ac] = 626,\n-\t[BNXT_ULP_CLASS_HID_0c10] = 627,\n-\t[BNXT_ULP_CLASS_HID_1864] = 628,\n-\t[BNXT_ULP_CLASS_HID_30c8] = 629,\n-\t[BNXT_ULP_CLASS_HID_1cdc] = 630,\n-\t[BNXT_ULP_CLASS_HID_50cc] = 631,\n-\t[BNXT_ULP_CLASS_HID_3d20] = 632,\n-\t[BNXT_ULP_CLASS_HID_529c] = 633,\n-\t[BNXT_ULP_CLASS_HID_3ef0] = 634,\n-\t[BNXT_ULP_CLASS_HID_72e0] = 635,\n-\t[BNXT_ULP_CLASS_HID_5ef4] = 636,\n-\t[BNXT_ULP_CLASS_HID_2dfc] = 637,\n-\t[BNXT_ULP_CLASS_HID_39e0] = 638,\n-\t[BNXT_ULP_CLASS_HID_4530] = 639,\n-\t[BNXT_ULP_CLASS_HID_5124] = 640,\n-\t[BNXT_ULP_CLASS_HID_4df0] = 641,\n-\t[BNXT_ULP_CLASS_HID_59e4] = 642,\n-\t[BNXT_ULP_CLASS_HID_1c78] = 643,\n-\t[BNXT_ULP_CLASS_HID_7118] = 644,\n-\t[BNXT_ULP_CLASS_HID_0998] = 645,\n-\t[BNXT_ULP_CLASS_HID_158c] = 646,\n-\t[BNXT_ULP_CLASS_HID_20dc] = 647,\n-\t[BNXT_ULP_CLASS_HID_0cc0] = 648,\n-\t[BNXT_ULP_CLASS_HID_299c] = 649,\n-\t[BNXT_ULP_CLASS_HID_3580] = 650,\n-\t[BNXT_ULP_CLASS_HID_40d0] = 651,\n-\t[BNXT_ULP_CLASS_HID_2cc4] = 652,\n-\t[BNXT_ULP_CLASS_HID_55a4] = 653,\n-\t[BNXT_ULP_CLASS_HID_21b8] = 654,\n-\t[BNXT_ULP_CLASS_HID_75a8] = 655,\n-\t[BNXT_ULP_CLASS_HID_41bc] = 656,\n-\t[BNXT_ULP_CLASS_HID_7778] = 657,\n-\t[BNXT_ULP_CLASS_HID_438c] = 658,\n-\t[BNXT_ULP_CLASS_HID_0c30] = 659,\n-\t[BNXT_ULP_CLASS_HID_1844] = 660,\n-\t[BNXT_ULP_CLASS_HID_30e8] = 661,\n-\t[BNXT_ULP_CLASS_HID_1cfc] = 662,\n-\t[BNXT_ULP_CLASS_HID_50ec] = 663,\n-\t[BNXT_ULP_CLASS_HID_3d00] = 664,\n-\t[BNXT_ULP_CLASS_HID_52bc] = 665,\n-\t[BNXT_ULP_CLASS_HID_3ed0] = 666,\n-\t[BNXT_ULP_CLASS_HID_72c0] = 667,\n-\t[BNXT_ULP_CLASS_HID_5ed4] = 668,\n-\t[BNXT_ULP_CLASS_HID_3866] = 669,\n-\t[BNXT_ULP_CLASS_HID_381e] = 670,\n-\t[BNXT_ULP_CLASS_HID_3860] = 671,\n-\t[BNXT_ULP_CLASS_HID_0454] = 672,\n-\t[BNXT_ULP_CLASS_HID_3818] = 673,\n-\t[BNXT_ULP_CLASS_HID_042c] = 674,\n-\t[BNXT_ULP_CLASS_HID_3846] = 675,\n-\t[BNXT_ULP_CLASS_HID_387e] = 676,\n-\t[BNXT_ULP_CLASS_HID_3ba6] = 677,\n-\t[BNXT_ULP_CLASS_HID_385e] = 678,\n-\t[BNXT_ULP_CLASS_HID_3840] = 679,\n-\t[BNXT_ULP_CLASS_HID_0474] = 680,\n-\t[BNXT_ULP_CLASS_HID_3878] = 681,\n-\t[BNXT_ULP_CLASS_HID_044c] = 682,\n-\t[BNXT_ULP_CLASS_HID_3ba0] = 683,\n-\t[BNXT_ULP_CLASS_HID_0794] = 684,\n-\t[BNXT_ULP_CLASS_HID_3858] = 685,\n-\t[BNXT_ULP_CLASS_HID_046c] = 686\n+\t[BNXT_ULP_CLASS_HID_3612] = 345,\n+\t[BNXT_ULP_CLASS_HID_66da] = 346,\n+\t[BNXT_ULP_CLASS_HID_6165] = 347,\n+\t[BNXT_ULP_CLASS_HID_2aa1] = 348,\n+\t[BNXT_ULP_CLASS_HID_09cd] = 349,\n+\t[BNXT_ULP_CLASS_HID_3845] = 350,\n+\t[BNXT_ULP_CLASS_HID_11e9] = 351,\n+\t[BNXT_ULP_CLASS_HID_4361] = 352,\n+\t[BNXT_ULP_CLASS_HID_218d] = 353,\n+\t[BNXT_ULP_CLASS_HID_5105] = 354,\n+\t[BNXT_ULP_CLASS_HID_0c89] = 355,\n+\t[BNXT_ULP_CLASS_HID_3e81] = 356,\n+\t[BNXT_ULP_CLASS_HID_1dad] = 357,\n+\t[BNXT_ULP_CLASS_HID_4ca5] = 358,\n+\t[BNXT_ULP_CLASS_HID_25c9] = 359,\n+\t[BNXT_ULP_CLASS_HID_57c1] = 360,\n+\t[BNXT_ULP_CLASS_HID_33ed] = 361,\n+\t[BNXT_ULP_CLASS_HID_65e5] = 362,\n+\t[BNXT_ULP_CLASS_HID_6dd9] = 363,\n+\t[BNXT_ULP_CLASS_HID_261d] = 364,\n+\t[BNXT_ULP_CLASS_HID_0571] = 365,\n+\t[BNXT_ULP_CLASS_HID_34f9] = 366,\n+\t[BNXT_ULP_CLASS_HID_1d55] = 367,\n+\t[BNXT_ULP_CLASS_HID_4fdd] = 368,\n+\t[BNXT_ULP_CLASS_HID_2d31] = 369,\n+\t[BNXT_ULP_CLASS_HID_5db9] = 370,\n+\t[BNXT_ULP_CLASS_HID_0035] = 371,\n+\t[BNXT_ULP_CLASS_HID_323d] = 372,\n+\t[BNXT_ULP_CLASS_HID_1111] = 373,\n+\t[BNXT_ULP_CLASS_HID_4019] = 374,\n+\t[BNXT_ULP_CLASS_HID_2975] = 375,\n+\t[BNXT_ULP_CLASS_HID_5b7d] = 376,\n+\t[BNXT_ULP_CLASS_HID_3f51] = 377,\n+\t[BNXT_ULP_CLASS_HID_6959] = 378,\n+\t[BNXT_ULP_CLASS_HID_0e85] = 379,\n+\t[BNXT_ULP_CLASS_HID_380d] = 380,\n+\t[BNXT_ULP_CLASS_HID_1f21] = 381,\n+\t[BNXT_ULP_CLASS_HID_4ea9] = 382,\n+\t[BNXT_ULP_CLASS_HID_1705] = 383,\n+\t[BNXT_ULP_CLASS_HID_418d] = 384,\n+\t[BNXT_ULP_CLASS_HID_2721] = 385,\n+\t[BNXT_ULP_CLASS_HID_57a9] = 386,\n+\t[BNXT_ULP_CLASS_HID_1a25] = 387,\n+\t[BNXT_ULP_CLASS_HID_342d] = 388,\n+\t[BNXT_ULP_CLASS_HID_2b01] = 389,\n+\t[BNXT_ULP_CLASS_HID_5a09] = 390,\n+\t[BNXT_ULP_CLASS_HID_2325] = 391,\n+\t[BNXT_ULP_CLASS_HID_5d2d] = 392,\n+\t[BNXT_ULP_CLASS_HID_3101] = 393,\n+\t[BNXT_ULP_CLASS_HID_6309] = 394,\n+\t[BNXT_ULP_CLASS_HID_0bad] = 395,\n+\t[BNXT_ULP_CLASS_HID_2535] = 396,\n+\t[BNXT_ULP_CLASS_HID_1869] = 397,\n+\t[BNXT_ULP_CLASS_HID_4bf1] = 398,\n+\t[BNXT_ULP_CLASS_HID_136d] = 399,\n+\t[BNXT_ULP_CLASS_HID_43f5] = 400,\n+\t[BNXT_ULP_CLASS_HID_2129] = 401,\n+\t[BNXT_ULP_CLASS_HID_53b1] = 402,\n+\t[BNXT_ULP_CLASS_HID_072d] = 403,\n+\t[BNXT_ULP_CLASS_HID_3135] = 404,\n+\t[BNXT_ULP_CLASS_HID_1429] = 405,\n+\t[BNXT_ULP_CLASS_HID_4731] = 406,\n+\t[BNXT_ULP_CLASS_HID_2f6d] = 407,\n+\t[BNXT_ULP_CLASS_HID_5f75] = 408,\n+\t[BNXT_ULP_CLASS_HID_3d69] = 409,\n+\t[BNXT_ULP_CLASS_HID_6f71] = 410,\n+\t[BNXT_ULP_CLASS_HID_0dbd] = 411,\n+\t[BNXT_ULP_CLASS_HID_3f25] = 412,\n+\t[BNXT_ULP_CLASS_HID_1239] = 413,\n+\t[BNXT_ULP_CLASS_HID_4da1] = 414,\n+\t[BNXT_ULP_CLASS_HID_153d] = 415,\n+\t[BNXT_ULP_CLASS_HID_45a5] = 416,\n+\t[BNXT_ULP_CLASS_HID_3bb9] = 417,\n+\t[BNXT_ULP_CLASS_HID_55a1] = 418,\n+\t[BNXT_ULP_CLASS_HID_193d] = 419,\n+\t[BNXT_ULP_CLASS_HID_4b25] = 420,\n+\t[BNXT_ULP_CLASS_HID_2e39] = 421,\n+\t[BNXT_ULP_CLASS_HID_5921] = 422,\n+\t[BNXT_ULP_CLASS_HID_213d] = 423,\n+\t[BNXT_ULP_CLASS_HID_5125] = 424,\n+\t[BNXT_ULP_CLASS_HID_3739] = 425,\n+\t[BNXT_ULP_CLASS_HID_093d] = 426,\n+\t[BNXT_ULP_CLASS_HID_684d] = 427,\n+\t[BNXT_ULP_CLASS_HID_2389] = 428,\n+\t[BNXT_ULP_CLASS_HID_00e5] = 429,\n+\t[BNXT_ULP_CLASS_HID_316d] = 430,\n+\t[BNXT_ULP_CLASS_HID_18c1] = 431,\n+\t[BNXT_ULP_CLASS_HID_4a49] = 432,\n+\t[BNXT_ULP_CLASS_HID_28a5] = 433,\n+\t[BNXT_ULP_CLASS_HID_582d] = 434,\n+\t[BNXT_ULP_CLASS_HID_05a1] = 435,\n+\t[BNXT_ULP_CLASS_HID_37a9] = 436,\n+\t[BNXT_ULP_CLASS_HID_1485] = 437,\n+\t[BNXT_ULP_CLASS_HID_458d] = 438,\n+\t[BNXT_ULP_CLASS_HID_2ce1] = 439,\n+\t[BNXT_ULP_CLASS_HID_5ee9] = 440,\n+\t[BNXT_ULP_CLASS_HID_3ac5] = 441,\n+\t[BNXT_ULP_CLASS_HID_6ccd] = 442,\n+\t[BNXT_ULP_CLASS_HID_0b11] = 443,\n+\t[BNXT_ULP_CLASS_HID_3d99] = 444,\n+\t[BNXT_ULP_CLASS_HID_1ab5] = 445,\n+\t[BNXT_ULP_CLASS_HID_4b3d] = 446,\n+\t[BNXT_ULP_CLASS_HID_1291] = 447,\n+\t[BNXT_ULP_CLASS_HID_4419] = 448,\n+\t[BNXT_ULP_CLASS_HID_22b5] = 449,\n+\t[BNXT_ULP_CLASS_HID_523d] = 450,\n+\t[BNXT_ULP_CLASS_HID_1fb1] = 451,\n+\t[BNXT_ULP_CLASS_HID_31b9] = 452,\n+\t[BNXT_ULP_CLASS_HID_2e95] = 453,\n+\t[BNXT_ULP_CLASS_HID_5f9d] = 454,\n+\t[BNXT_ULP_CLASS_HID_26b1] = 455,\n+\t[BNXT_ULP_CLASS_HID_58b9] = 456,\n+\t[BNXT_ULP_CLASS_HID_3495] = 457,\n+\t[BNXT_ULP_CLASS_HID_669d] = 458,\n+\t[BNXT_ULP_CLASS_HID_0e39] = 459,\n+\t[BNXT_ULP_CLASS_HID_20a1] = 460,\n+\t[BNXT_ULP_CLASS_HID_1dfd] = 461,\n+\t[BNXT_ULP_CLASS_HID_4e65] = 462,\n+\t[BNXT_ULP_CLASS_HID_16f9] = 463,\n+\t[BNXT_ULP_CLASS_HID_4661] = 464,\n+\t[BNXT_ULP_CLASS_HID_24bd] = 465,\n+\t[BNXT_ULP_CLASS_HID_5625] = 466,\n+\t[BNXT_ULP_CLASS_HID_02b9] = 467,\n+\t[BNXT_ULP_CLASS_HID_34a1] = 468,\n+\t[BNXT_ULP_CLASS_HID_11bd] = 469,\n+\t[BNXT_ULP_CLASS_HID_42a5] = 470,\n+\t[BNXT_ULP_CLASS_HID_2af9] = 471,\n+\t[BNXT_ULP_CLASS_HID_5ae1] = 472,\n+\t[BNXT_ULP_CLASS_HID_38fd] = 473,\n+\t[BNXT_ULP_CLASS_HID_6ae5] = 474,\n+\t[BNXT_ULP_CLASS_HID_0829] = 475,\n+\t[BNXT_ULP_CLASS_HID_3ab1] = 476,\n+\t[BNXT_ULP_CLASS_HID_17ad] = 477,\n+\t[BNXT_ULP_CLASS_HID_4835] = 478,\n+\t[BNXT_ULP_CLASS_HID_10a9] = 479,\n+\t[BNXT_ULP_CLASS_HID_4031] = 480,\n+\t[BNXT_ULP_CLASS_HID_3e2d] = 481,\n+\t[BNXT_ULP_CLASS_HID_5035] = 482,\n+\t[BNXT_ULP_CLASS_HID_1ca9] = 483,\n+\t[BNXT_ULP_CLASS_HID_4eb1] = 484,\n+\t[BNXT_ULP_CLASS_HID_2bad] = 485,\n+\t[BNXT_ULP_CLASS_HID_5cb5] = 486,\n+\t[BNXT_ULP_CLASS_HID_24a9] = 487,\n+\t[BNXT_ULP_CLASS_HID_54b1] = 488,\n+\t[BNXT_ULP_CLASS_HID_32ad] = 489,\n+\t[BNXT_ULP_CLASS_HID_0ca9] = 490,\n+\t[BNXT_ULP_CLASS_HID_7f35] = 491,\n+\t[BNXT_ULP_CLASS_HID_34f1] = 492,\n+\t[BNXT_ULP_CLASS_HID_179d] = 493,\n+\t[BNXT_ULP_CLASS_HID_2615] = 494,\n+\t[BNXT_ULP_CLASS_HID_0fb9] = 495,\n+\t[BNXT_ULP_CLASS_HID_5d31] = 496,\n+\t[BNXT_ULP_CLASS_HID_3fdd] = 497,\n+\t[BNXT_ULP_CLASS_HID_4f55] = 498,\n+\t[BNXT_ULP_CLASS_HID_12d9] = 499,\n+\t[BNXT_ULP_CLASS_HID_20d1] = 500,\n+\t[BNXT_ULP_CLASS_HID_03fd] = 501,\n+\t[BNXT_ULP_CLASS_HID_52f5] = 502,\n+\t[BNXT_ULP_CLASS_HID_3b99] = 503,\n+\t[BNXT_ULP_CLASS_HID_4991] = 504,\n+\t[BNXT_ULP_CLASS_HID_2dbd] = 505,\n+\t[BNXT_ULP_CLASS_HID_7bb5] = 506,\n+\t[BNXT_ULP_CLASS_HID_34c6] = 507,\n+\t[BNXT_ULP_CLASS_HID_0c22] = 508,\n+\t[BNXT_ULP_CLASS_HID_1cbe] = 509,\n+\t[BNXT_ULP_CLASS_HID_179a] = 510,\n+\t[BNXT_ULP_CLASS_HID_59be] = 511,\n+\t[BNXT_ULP_CLASS_HID_515a] = 512,\n+\t[BNXT_ULP_CLASS_HID_1c72] = 513,\n+\t[BNXT_ULP_CLASS_HID_171e] = 514,\n+\t[BNXT_ULP_CLASS_HID_19c8] = 515,\n+\t[BNXT_ULP_CLASS_HID_112c] = 516,\n+\t[BNXT_ULP_CLASS_HID_4d68] = 517,\n+\t[BNXT_ULP_CLASS_HID_444c] = 518,\n+\t[BNXT_ULP_CLASS_HID_0e8c] = 519,\n+\t[BNXT_ULP_CLASS_HID_09e0] = 520,\n+\t[BNXT_ULP_CLASS_HID_1af0] = 521,\n+\t[BNXT_ULP_CLASS_HID_15d4] = 522,\n+\t[BNXT_ULP_CLASS_HID_1dd0] = 523,\n+\t[BNXT_ULP_CLASS_HID_14f4] = 524,\n+\t[BNXT_ULP_CLASS_HID_70b0] = 525,\n+\t[BNXT_ULP_CLASS_HID_4854] = 526,\n+\t[BNXT_ULP_CLASS_HID_3dd4] = 527,\n+\t[BNXT_ULP_CLASS_HID_34f8] = 528,\n+\t[BNXT_ULP_CLASS_HID_09e8] = 529,\n+\t[BNXT_ULP_CLASS_HID_008c] = 530,\n+\t[BNXT_ULP_CLASS_HID_34e6] = 531,\n+\t[BNXT_ULP_CLASS_HID_0c02] = 532,\n+\t[BNXT_ULP_CLASS_HID_1c9e] = 533,\n+\t[BNXT_ULP_CLASS_HID_17ba] = 534,\n+\t[BNXT_ULP_CLASS_HID_429e] = 535,\n+\t[BNXT_ULP_CLASS_HID_5dba] = 536,\n+\t[BNXT_ULP_CLASS_HID_2a16] = 537,\n+\t[BNXT_ULP_CLASS_HID_2532] = 538,\n+\t[BNXT_ULP_CLASS_HID_2da2] = 539,\n+\t[BNXT_ULP_CLASS_HID_24fe] = 540,\n+\t[BNXT_ULP_CLASS_HID_355a] = 541,\n+\t[BNXT_ULP_CLASS_HID_0c76] = 542,\n+\t[BNXT_ULP_CLASS_HID_13e6] = 543,\n+\t[BNXT_ULP_CLASS_HID_7276] = 544,\n+\t[BNXT_ULP_CLASS_HID_42d2] = 545,\n+\t[BNXT_ULP_CLASS_HID_5dee] = 546,\n+\t[BNXT_ULP_CLASS_HID_59de] = 547,\n+\t[BNXT_ULP_CLASS_HID_513a] = 548,\n+\t[BNXT_ULP_CLASS_HID_1c12] = 549,\n+\t[BNXT_ULP_CLASS_HID_177e] = 550,\n+\t[BNXT_ULP_CLASS_HID_0e92] = 551,\n+\t[BNXT_ULP_CLASS_HID_09fe] = 552,\n+\t[BNXT_ULP_CLASS_HID_5c1a] = 553,\n+\t[BNXT_ULP_CLASS_HID_5746] = 554,\n+\t[BNXT_ULP_CLASS_HID_79da] = 555,\n+\t[BNXT_ULP_CLASS_HID_7106] = 556,\n+\t[BNXT_ULP_CLASS_HID_3c1e] = 557,\n+\t[BNXT_ULP_CLASS_HID_377a] = 558,\n+\t[BNXT_ULP_CLASS_HID_2e9e] = 559,\n+\t[BNXT_ULP_CLASS_HID_29fa] = 560,\n+\t[BNXT_ULP_CLASS_HID_14d2] = 561,\n+\t[BNXT_ULP_CLASS_HID_7742] = 562,\n+\t[BNXT_ULP_CLASS_HID_3706] = 563,\n+\t[BNXT_ULP_CLASS_HID_0fe2] = 564,\n+\t[BNXT_ULP_CLASS_HID_1f7e] = 565,\n+\t[BNXT_ULP_CLASS_HID_145a] = 566,\n+\t[BNXT_ULP_CLASS_HID_417e] = 567,\n+\t[BNXT_ULP_CLASS_HID_5e5a] = 568,\n+\t[BNXT_ULP_CLASS_HID_29f6] = 569,\n+\t[BNXT_ULP_CLASS_HID_26d2] = 570,\n+\t[BNXT_ULP_CLASS_HID_2e42] = 571,\n+\t[BNXT_ULP_CLASS_HID_271e] = 572,\n+\t[BNXT_ULP_CLASS_HID_36ba] = 573,\n+\t[BNXT_ULP_CLASS_HID_0f96] = 574,\n+\t[BNXT_ULP_CLASS_HID_1006] = 575,\n+\t[BNXT_ULP_CLASS_HID_7196] = 576,\n+\t[BNXT_ULP_CLASS_HID_4132] = 577,\n+\t[BNXT_ULP_CLASS_HID_5e0e] = 578,\n+\t[BNXT_ULP_CLASS_HID_59fe] = 579,\n+\t[BNXT_ULP_CLASS_HID_511a] = 580,\n+\t[BNXT_ULP_CLASS_HID_1c32] = 581,\n+\t[BNXT_ULP_CLASS_HID_175e] = 582,\n+\t[BNXT_ULP_CLASS_HID_0eb2] = 583,\n+\t[BNXT_ULP_CLASS_HID_09de] = 584,\n+\t[BNXT_ULP_CLASS_HID_5c3a] = 585,\n+\t[BNXT_ULP_CLASS_HID_5766] = 586,\n+\t[BNXT_ULP_CLASS_HID_79fa] = 587,\n+\t[BNXT_ULP_CLASS_HID_7126] = 588,\n+\t[BNXT_ULP_CLASS_HID_3c3e] = 589,\n+\t[BNXT_ULP_CLASS_HID_375a] = 590,\n+\t[BNXT_ULP_CLASS_HID_2ebe] = 591,\n+\t[BNXT_ULP_CLASS_HID_29da] = 592,\n+\t[BNXT_ULP_CLASS_HID_14f2] = 593,\n+\t[BNXT_ULP_CLASS_HID_7762] = 594,\n+\t[BNXT_ULP_CLASS_HID_19e8] = 595,\n+\t[BNXT_ULP_CLASS_HID_110c] = 596,\n+\t[BNXT_ULP_CLASS_HID_4d48] = 597,\n+\t[BNXT_ULP_CLASS_HID_446c] = 598,\n+\t[BNXT_ULP_CLASS_HID_0eac] = 599,\n+\t[BNXT_ULP_CLASS_HID_09c0] = 600,\n+\t[BNXT_ULP_CLASS_HID_1ad0] = 601,\n+\t[BNXT_ULP_CLASS_HID_15f4] = 602,\n+\t[BNXT_ULP_CLASS_HID_39ec] = 603,\n+\t[BNXT_ULP_CLASS_HID_3100] = 604,\n+\t[BNXT_ULP_CLASS_HID_0210] = 605,\n+\t[BNXT_ULP_CLASS_HID_1d34] = 606,\n+\t[BNXT_ULP_CLASS_HID_2ea0] = 607,\n+\t[BNXT_ULP_CLASS_HID_29c4] = 608,\n+\t[BNXT_ULP_CLASS_HID_3ad4] = 609,\n+\t[BNXT_ULP_CLASS_HID_35e8] = 610,\n+\t[BNXT_ULP_CLASS_HID_5d80] = 611,\n+\t[BNXT_ULP_CLASS_HID_54a4] = 612,\n+\t[BNXT_ULP_CLASS_HID_29b4] = 613,\n+\t[BNXT_ULP_CLASS_HID_20c8] = 614,\n+\t[BNXT_ULP_CLASS_HID_7244] = 615,\n+\t[BNXT_ULP_CLASS_HID_4d98] = 616,\n+\t[BNXT_ULP_CLASS_HID_5e68] = 617,\n+\t[BNXT_ULP_CLASS_HID_598c] = 618,\n+\t[BNXT_ULP_CLASS_HID_1248] = 619,\n+\t[BNXT_ULP_CLASS_HID_74d8] = 620,\n+\t[BNXT_ULP_CLASS_HID_49a8] = 621,\n+\t[BNXT_ULP_CLASS_HID_40cc] = 622,\n+\t[BNXT_ULP_CLASS_HID_0b0c] = 623,\n+\t[BNXT_ULP_CLASS_HID_0220] = 624,\n+\t[BNXT_ULP_CLASS_HID_1730] = 625,\n+\t[BNXT_ULP_CLASS_HID_7980] = 626,\n+\t[BNXT_ULP_CLASS_HID_1db0] = 627,\n+\t[BNXT_ULP_CLASS_HID_1494] = 628,\n+\t[BNXT_ULP_CLASS_HID_70d0] = 629,\n+\t[BNXT_ULP_CLASS_HID_4834] = 630,\n+\t[BNXT_ULP_CLASS_HID_3db4] = 631,\n+\t[BNXT_ULP_CLASS_HID_3498] = 632,\n+\t[BNXT_ULP_CLASS_HID_0988] = 633,\n+\t[BNXT_ULP_CLASS_HID_00ec] = 634,\n+\t[BNXT_ULP_CLASS_HID_3f44] = 635,\n+\t[BNXT_ULP_CLASS_HID_36a8] = 636,\n+\t[BNXT_ULP_CLASS_HID_0b58] = 637,\n+\t[BNXT_ULP_CLASS_HID_02bc] = 638,\n+\t[BNXT_ULP_CLASS_HID_5f48] = 639,\n+\t[BNXT_ULP_CLASS_HID_56ac] = 640,\n+\t[BNXT_ULP_CLASS_HID_2b5c] = 641,\n+\t[BNXT_ULP_CLASS_HID_2280] = 642,\n+\t[BNXT_ULP_CLASS_HID_4000] = 643,\n+\t[BNXT_ULP_CLASS_HID_5b64] = 644,\n+\t[BNXT_ULP_CLASS_HID_2c14] = 645,\n+\t[BNXT_ULP_CLASS_HID_2778] = 646,\n+\t[BNXT_ULP_CLASS_HID_18f8] = 647,\n+\t[BNXT_ULP_CLASS_HID_13dc] = 648,\n+\t[BNXT_ULP_CLASS_HID_4c18] = 649,\n+\t[BNXT_ULP_CLASS_HID_477c] = 650,\n+\t[BNXT_ULP_CLASS_HID_1a88] = 651,\n+\t[BNXT_ULP_CLASS_HID_15ec] = 652,\n+\t[BNXT_ULP_CLASS_HID_4e28] = 653,\n+\t[BNXT_ULP_CLASS_HID_490c] = 654,\n+\t[BNXT_ULP_CLASS_HID_3a8c] = 655,\n+\t[BNXT_ULP_CLASS_HID_35f0] = 656,\n+\t[BNXT_ULP_CLASS_HID_06e0] = 657,\n+\t[BNXT_ULP_CLASS_HID_01c4] = 658,\n+\t[BNXT_ULP_CLASS_HID_1a08] = 659,\n+\t[BNXT_ULP_CLASS_HID_12ec] = 660,\n+\t[BNXT_ULP_CLASS_HID_4ea8] = 661,\n+\t[BNXT_ULP_CLASS_HID_478c] = 662,\n+\t[BNXT_ULP_CLASS_HID_0d4c] = 663,\n+\t[BNXT_ULP_CLASS_HID_0a20] = 664,\n+\t[BNXT_ULP_CLASS_HID_1930] = 665,\n+\t[BNXT_ULP_CLASS_HID_1614] = 666,\n+\t[BNXT_ULP_CLASS_HID_3a0c] = 667,\n+\t[BNXT_ULP_CLASS_HID_32e0] = 668,\n+\t[BNXT_ULP_CLASS_HID_01f0] = 669,\n+\t[BNXT_ULP_CLASS_HID_1ed4] = 670,\n+\t[BNXT_ULP_CLASS_HID_2d40] = 671,\n+\t[BNXT_ULP_CLASS_HID_2a24] = 672,\n+\t[BNXT_ULP_CLASS_HID_3934] = 673,\n+\t[BNXT_ULP_CLASS_HID_3608] = 674,\n+\t[BNXT_ULP_CLASS_HID_5e60] = 675,\n+\t[BNXT_ULP_CLASS_HID_5744] = 676,\n+\t[BNXT_ULP_CLASS_HID_2a54] = 677,\n+\t[BNXT_ULP_CLASS_HID_2328] = 678,\n+\t[BNXT_ULP_CLASS_HID_71a4] = 679,\n+\t[BNXT_ULP_CLASS_HID_4e78] = 680,\n+\t[BNXT_ULP_CLASS_HID_5d88] = 681,\n+\t[BNXT_ULP_CLASS_HID_5a6c] = 682,\n+\t[BNXT_ULP_CLASS_HID_11a8] = 683,\n+\t[BNXT_ULP_CLASS_HID_7738] = 684,\n+\t[BNXT_ULP_CLASS_HID_4a48] = 685,\n+\t[BNXT_ULP_CLASS_HID_432c] = 686,\n+\t[BNXT_ULP_CLASS_HID_08ec] = 687,\n+\t[BNXT_ULP_CLASS_HID_01c0] = 688,\n+\t[BNXT_ULP_CLASS_HID_14d0] = 689,\n+\t[BNXT_ULP_CLASS_HID_7a60] = 690,\n+\t[BNXT_ULP_CLASS_HID_1d90] = 691,\n+\t[BNXT_ULP_CLASS_HID_14b4] = 692,\n+\t[BNXT_ULP_CLASS_HID_70f0] = 693,\n+\t[BNXT_ULP_CLASS_HID_4814] = 694,\n+\t[BNXT_ULP_CLASS_HID_3d94] = 695,\n+\t[BNXT_ULP_CLASS_HID_34b8] = 696,\n+\t[BNXT_ULP_CLASS_HID_09a8] = 697,\n+\t[BNXT_ULP_CLASS_HID_00cc] = 698,\n+\t[BNXT_ULP_CLASS_HID_3f64] = 699,\n+\t[BNXT_ULP_CLASS_HID_3688] = 700,\n+\t[BNXT_ULP_CLASS_HID_0b78] = 701,\n+\t[BNXT_ULP_CLASS_HID_029c] = 702,\n+\t[BNXT_ULP_CLASS_HID_5f68] = 703,\n+\t[BNXT_ULP_CLASS_HID_568c] = 704,\n+\t[BNXT_ULP_CLASS_HID_2b7c] = 705,\n+\t[BNXT_ULP_CLASS_HID_22a0] = 706,\n+\t[BNXT_ULP_CLASS_HID_4020] = 707,\n+\t[BNXT_ULP_CLASS_HID_5b44] = 708,\n+\t[BNXT_ULP_CLASS_HID_2c34] = 709,\n+\t[BNXT_ULP_CLASS_HID_2758] = 710,\n+\t[BNXT_ULP_CLASS_HID_18d8] = 711,\n+\t[BNXT_ULP_CLASS_HID_13fc] = 712,\n+\t[BNXT_ULP_CLASS_HID_4c38] = 713,\n+\t[BNXT_ULP_CLASS_HID_475c] = 714,\n+\t[BNXT_ULP_CLASS_HID_1aa8] = 715,\n+\t[BNXT_ULP_CLASS_HID_15cc] = 716,\n+\t[BNXT_ULP_CLASS_HID_4e08] = 717,\n+\t[BNXT_ULP_CLASS_HID_492c] = 718,\n+\t[BNXT_ULP_CLASS_HID_3aac] = 719,\n+\t[BNXT_ULP_CLASS_HID_35d0] = 720,\n+\t[BNXT_ULP_CLASS_HID_06c0] = 721,\n+\t[BNXT_ULP_CLASS_HID_01e4] = 722,\n+\t[BNXT_ULP_CLASS_HID_4d32] = 723,\n+\t[BNXT_ULP_CLASS_HID_54aa] = 724,\n+\t[BNXT_ULP_CLASS_HID_0686] = 725,\n+\t[BNXT_ULP_CLASS_HID_540e] = 726,\n+\t[BNXT_ULP_CLASS_HID_2e3c] = 727,\n+\t[BNXT_ULP_CLASS_HID_3a20] = 728,\n+\t[BNXT_ULP_CLASS_HID_46f0] = 729,\n+\t[BNXT_ULP_CLASS_HID_52e4] = 730,\n+\t[BNXT_ULP_CLASS_HID_55e4] = 731,\n+\t[BNXT_ULP_CLASS_HID_21f8] = 732,\n+\t[BNXT_ULP_CLASS_HID_75e8] = 733,\n+\t[BNXT_ULP_CLASS_HID_41fc] = 734,\n+\t[BNXT_ULP_CLASS_HID_4d12] = 735,\n+\t[BNXT_ULP_CLASS_HID_548a] = 736,\n+\t[BNXT_ULP_CLASS_HID_3356] = 737,\n+\t[BNXT_ULP_CLASS_HID_1ace] = 738,\n+\t[BNXT_ULP_CLASS_HID_1a9a] = 739,\n+\t[BNXT_ULP_CLASS_HID_4d46] = 740,\n+\t[BNXT_ULP_CLASS_HID_2812] = 741,\n+\t[BNXT_ULP_CLASS_HID_338a] = 742,\n+\t[BNXT_ULP_CLASS_HID_06e6] = 743,\n+\t[BNXT_ULP_CLASS_HID_546e] = 744,\n+\t[BNXT_ULP_CLASS_HID_46ee] = 745,\n+\t[BNXT_ULP_CLASS_HID_0d22] = 746,\n+\t[BNXT_ULP_CLASS_HID_26e2] = 747,\n+\t[BNXT_ULP_CLASS_HID_746a] = 748,\n+\t[BNXT_ULP_CLASS_HID_1fa6] = 749,\n+\t[BNXT_ULP_CLASS_HID_2d2e] = 750,\n+\t[BNXT_ULP_CLASS_HID_4ef2] = 751,\n+\t[BNXT_ULP_CLASS_HID_576a] = 752,\n+\t[BNXT_ULP_CLASS_HID_30b6] = 753,\n+\t[BNXT_ULP_CLASS_HID_192e] = 754,\n+\t[BNXT_ULP_CLASS_HID_197a] = 755,\n+\t[BNXT_ULP_CLASS_HID_4ea6] = 756,\n+\t[BNXT_ULP_CLASS_HID_2bf2] = 757,\n+\t[BNXT_ULP_CLASS_HID_306a] = 758,\n+\t[BNXT_ULP_CLASS_HID_06c6] = 759,\n+\t[BNXT_ULP_CLASS_HID_544e] = 760,\n+\t[BNXT_ULP_CLASS_HID_46ce] = 761,\n+\t[BNXT_ULP_CLASS_HID_0d02] = 762,\n+\t[BNXT_ULP_CLASS_HID_26c2] = 763,\n+\t[BNXT_ULP_CLASS_HID_744a] = 764,\n+\t[BNXT_ULP_CLASS_HID_1f86] = 765,\n+\t[BNXT_ULP_CLASS_HID_2d0e] = 766,\n+\t[BNXT_ULP_CLASS_HID_2e1c] = 767,\n+\t[BNXT_ULP_CLASS_HID_3a00] = 768,\n+\t[BNXT_ULP_CLASS_HID_46d0] = 769,\n+\t[BNXT_ULP_CLASS_HID_52c4] = 770,\n+\t[BNXT_ULP_CLASS_HID_4e10] = 771,\n+\t[BNXT_ULP_CLASS_HID_5a04] = 772,\n+\t[BNXT_ULP_CLASS_HID_1f98] = 773,\n+\t[BNXT_ULP_CLASS_HID_72f8] = 774,\n+\t[BNXT_ULP_CLASS_HID_0a78] = 775,\n+\t[BNXT_ULP_CLASS_HID_166c] = 776,\n+\t[BNXT_ULP_CLASS_HID_233c] = 777,\n+\t[BNXT_ULP_CLASS_HID_0f20] = 778,\n+\t[BNXT_ULP_CLASS_HID_2a7c] = 779,\n+\t[BNXT_ULP_CLASS_HID_3660] = 780,\n+\t[BNXT_ULP_CLASS_HID_4330] = 781,\n+\t[BNXT_ULP_CLASS_HID_2f24] = 782,\n+\t[BNXT_ULP_CLASS_HID_5584] = 783,\n+\t[BNXT_ULP_CLASS_HID_2198] = 784,\n+\t[BNXT_ULP_CLASS_HID_7588] = 785,\n+\t[BNXT_ULP_CLASS_HID_419c] = 786,\n+\t[BNXT_ULP_CLASS_HID_7758] = 787,\n+\t[BNXT_ULP_CLASS_HID_43ac] = 788,\n+\t[BNXT_ULP_CLASS_HID_0c10] = 789,\n+\t[BNXT_ULP_CLASS_HID_1864] = 790,\n+\t[BNXT_ULP_CLASS_HID_30c8] = 791,\n+\t[BNXT_ULP_CLASS_HID_1cdc] = 792,\n+\t[BNXT_ULP_CLASS_HID_50cc] = 793,\n+\t[BNXT_ULP_CLASS_HID_3d20] = 794,\n+\t[BNXT_ULP_CLASS_HID_529c] = 795,\n+\t[BNXT_ULP_CLASS_HID_3ef0] = 796,\n+\t[BNXT_ULP_CLASS_HID_72e0] = 797,\n+\t[BNXT_ULP_CLASS_HID_5ef4] = 798,\n+\t[BNXT_ULP_CLASS_HID_2dfc] = 799,\n+\t[BNXT_ULP_CLASS_HID_39e0] = 800,\n+\t[BNXT_ULP_CLASS_HID_4530] = 801,\n+\t[BNXT_ULP_CLASS_HID_5124] = 802,\n+\t[BNXT_ULP_CLASS_HID_4df0] = 803,\n+\t[BNXT_ULP_CLASS_HID_59e4] = 804,\n+\t[BNXT_ULP_CLASS_HID_1c78] = 805,\n+\t[BNXT_ULP_CLASS_HID_7118] = 806,\n+\t[BNXT_ULP_CLASS_HID_0998] = 807,\n+\t[BNXT_ULP_CLASS_HID_158c] = 808,\n+\t[BNXT_ULP_CLASS_HID_20dc] = 809,\n+\t[BNXT_ULP_CLASS_HID_0cc0] = 810,\n+\t[BNXT_ULP_CLASS_HID_299c] = 811,\n+\t[BNXT_ULP_CLASS_HID_3580] = 812,\n+\t[BNXT_ULP_CLASS_HID_40d0] = 813,\n+\t[BNXT_ULP_CLASS_HID_2cc4] = 814,\n+\t[BNXT_ULP_CLASS_HID_55a4] = 815,\n+\t[BNXT_ULP_CLASS_HID_21b8] = 816,\n+\t[BNXT_ULP_CLASS_HID_75a8] = 817,\n+\t[BNXT_ULP_CLASS_HID_41bc] = 818,\n+\t[BNXT_ULP_CLASS_HID_7778] = 819,\n+\t[BNXT_ULP_CLASS_HID_438c] = 820,\n+\t[BNXT_ULP_CLASS_HID_0c30] = 821,\n+\t[BNXT_ULP_CLASS_HID_1844] = 822,\n+\t[BNXT_ULP_CLASS_HID_30e8] = 823,\n+\t[BNXT_ULP_CLASS_HID_1cfc] = 824,\n+\t[BNXT_ULP_CLASS_HID_50ec] = 825,\n+\t[BNXT_ULP_CLASS_HID_3d00] = 826,\n+\t[BNXT_ULP_CLASS_HID_52bc] = 827,\n+\t[BNXT_ULP_CLASS_HID_3ed0] = 828,\n+\t[BNXT_ULP_CLASS_HID_72c0] = 829,\n+\t[BNXT_ULP_CLASS_HID_5ed4] = 830,\n+\t[BNXT_ULP_CLASS_HID_3866] = 831,\n+\t[BNXT_ULP_CLASS_HID_381e] = 832,\n+\t[BNXT_ULP_CLASS_HID_3860] = 833,\n+\t[BNXT_ULP_CLASS_HID_0454] = 834,\n+\t[BNXT_ULP_CLASS_HID_3818] = 835,\n+\t[BNXT_ULP_CLASS_HID_042c] = 836,\n+\t[BNXT_ULP_CLASS_HID_3846] = 837,\n+\t[BNXT_ULP_CLASS_HID_387e] = 838,\n+\t[BNXT_ULP_CLASS_HID_3ba6] = 839,\n+\t[BNXT_ULP_CLASS_HID_385e] = 840,\n+\t[BNXT_ULP_CLASS_HID_3840] = 841,\n+\t[BNXT_ULP_CLASS_HID_0474] = 842,\n+\t[BNXT_ULP_CLASS_HID_3878] = 843,\n+\t[BNXT_ULP_CLASS_HID_044c] = 844,\n+\t[BNXT_ULP_CLASS_HID_3ba0] = 845,\n+\t[BNXT_ULP_CLASS_HID_0794] = 846,\n+\t[BNXT_ULP_CLASS_HID_3858] = 847,\n+\t[BNXT_ULP_CLASS_HID_046c] = 848\n };\n \n /* Array for the proto matcher list */\n@@ -6964,8 +7126,3839 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }\n \t},\n \t[345] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_34c6,\n+\t.class_hid = BNXT_ULP_CLASS_HID_3612,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 81920,\n+\t.flow_pattern_id = 0,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_F1 |\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }\n+\t},\n+\t[346] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_66da,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 81928,\n+\t.flow_pattern_id = 0,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_F1 |\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }\n+\t},\n+\t[347] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_6165,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 1313792,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[348] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2aa1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 1321984,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[349] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_09cd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 3410944,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[350] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3845,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 3419136,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[351] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11e9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 2148797440,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[352] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4361,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 2148805632,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[353] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_218d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 2150894592,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[354] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5105,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 2150902784,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[355] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0c89,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4296281088,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[356] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3e81,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4296289280,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[357] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dad,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4298378240,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[358] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4ca5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4298386432,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[359] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25c9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 6443764736,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[360] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_57c1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 6443772928,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[361] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33ed,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 6445861888,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[362] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_65e5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 6445870080,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[363] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_6dd9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 1313792,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[364] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_261d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 1321984,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[365] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0571,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 3410944,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[366] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34f9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 3419136,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[367] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d55,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 2148797440,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[368] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4fdd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 2148805632,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[369] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d31,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 2150894592,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[370] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5db9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 2150902784,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[371] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0035,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 4296281088,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[372] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_323d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 4296289280,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[373] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1111,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 4298378240,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[374] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4019,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 4298386432,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[375] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2975,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6443764736,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[376] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5b7d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6443772928,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[377] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3f51,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6445861888,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[378] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_6959,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6445870080,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[379] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e85,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 8591248384,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[380] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_380d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 8591256576,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[381] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f21,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 8593345536,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[382] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4ea9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 8593353728,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[383] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1705,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 10738732032,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[384] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_418d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 10738740224,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[385] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2721,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 10740829184,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[386] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_57a9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 10740837376,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[387] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a25,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 12886215680,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[388] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_342d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 12886223872,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[389] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b01,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 12888312832,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[390] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5a09,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 12888321024,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[391] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2325,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 15033699328,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[392] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5d2d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 15033707520,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[393] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3101,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 15035796480,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[394] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_6309,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 15035804672,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }\n+\t},\n+\t[395] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0bad,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 17181182976,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[396] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2535,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 17181191168,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[397] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1869,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 17183280128,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[398] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4bf1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 17183288320,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[399] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_136d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 19328666624,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[400] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_43f5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 19328674816,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[401] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2129,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 19330763776,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[402] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_53b1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 19330771968,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[403] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_072d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 21476150272,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[404] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3135,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 21476158464,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[405] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1429,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 21478247424,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[406] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4731,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 21478255616,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[407] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2f6d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 23623633920,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[408] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5f75,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 23623642112,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[409] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d69,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 23625731072,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[410] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_6f71,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 23625739264,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[411] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0dbd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 25771117568,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[412] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3f25,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 25771125760,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[413] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1239,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 25773214720,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[414] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4da1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 25773222912,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[415] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_153d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 27918601216,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[416] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_45a5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 27918609408,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[417] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bb9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 27920698368,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[418] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_55a1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 27920706560,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[419] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_193d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 30066084864,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[420] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b25,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 30066093056,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[421] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2e39,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 30068182016,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[422] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5921,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 30068190208,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[423] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_213d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 32213568512,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[424] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5125,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 32213576704,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[425] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3739,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 32215665664,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[426] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_093d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 32215673856,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }\n+\t},\n+\t[427] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_684d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1313792,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[428] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2389,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 1321984,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[429] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00e5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3410944,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[430] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_316d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 3419136,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[431] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18c1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2148797440,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[432] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4a49,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2148805632,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[433] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28a5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2150894592,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[434] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_582d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 2150902784,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[435] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05a1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4296281088,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[436] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_37a9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4296289280,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[437] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1485,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4298378240,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[438] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_458d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 4298386432,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[439] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ce1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6443764736,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[440] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ee9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6443772928,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[441] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ac5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6445861888,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[442] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_6ccd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6445870080,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[443] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0b11,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8591248384,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[444] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d99,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8591256576,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[445] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ab5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8593345536,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[446] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b3d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8593353728,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[447] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1291,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 10738732032,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[448] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4419,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 10738740224,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[449] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22b5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 10740829184,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[450] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_523d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 10740837376,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[451] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 12886215680,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[452] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31b9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 12886223872,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[453] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2e95,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 12888312832,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[454] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5f9d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 12888321024,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[455] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_26b1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 15033699328,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[456] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_58b9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 15033707520,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[457] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3495,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 15035796480,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[458] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_669d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 15035804672,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }\n+\t},\n+\t[459] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e39,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 17181182976,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[460] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20a1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 17181191168,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[461] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dfd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 17183280128,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[462] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4e65,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 17183288320,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[463] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_16f9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 19328666624,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[464] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4661,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 19328674816,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[465] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24bd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 19330763776,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[466] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5625,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 19330771968,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[467] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02b9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 21476150272,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[468] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34a1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 21476158464,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[469] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11bd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 21478247424,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[470] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_42a5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 21478255616,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[471] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2af9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 23623633920,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[472] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ae1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 23623642112,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[473] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38fd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 23625731072,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[474] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_6ae5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 23625739264,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[475] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0829,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 25771117568,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[476] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ab1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 25771125760,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[477] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_17ad,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 25773214720,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[478] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4835,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 25773222912,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[479] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10a9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 27918601216,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[480] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4031,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 27918609408,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[481] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3e2d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 27920698368,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[482] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5035,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 27920706560,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[483] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ca9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 30066084864,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[484] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4eb1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 30066093056,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[485] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bad,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 30068182016,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[486] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5cb5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 30068190208,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[487] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24a9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 32213568512,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[488] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_54b1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 32213576704,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[489] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32ad,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 32215665664,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[490] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0ca9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 32215673856,\n+\t.flow_pattern_id = 1,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }\n+\t},\n+\t[491] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_7f35,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 1313792,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[492] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34f1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 1321984,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }\n+\t},\n+\t[493] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_179d,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 3410944,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[494] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2615,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 3419136,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }\n+\t},\n+\t[495] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0fb9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2148797440,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[496] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5d31,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2148805632,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[497] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3fdd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2150894592,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[498] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f55,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 2150902784,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }\n+\t},\n+\t[499] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12d9,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4296281088,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[500] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20d1,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4296289280,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[501] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03fd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4298378240,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[502] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_52f5,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 4298386432,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[503] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b99,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6443764736,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[504] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4991,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6443772928,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[505] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dbd,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6445861888,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[506] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_7bb5,\n \t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 6445870080,\n+\t.flow_pattern_id = 2,\n+\t.app_sig = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_T_VXLAN |\n+\t\tBNXT_ULP_HDR_BIT_I_ETH |\n+\t\tBNXT_ULP_HDR_BIT_I_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_I_ICMP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }\n+\t},\n+\t[507] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34c6,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 4096,\n \t.flow_pattern_id = 0,\n@@ -6975,12 +10968,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[346] = {\n+\t[508] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c22,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 4100,\n \t.flow_pattern_id = 0,\n@@ -6990,13 +10983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[347] = {\n+\t[509] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1cbe,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 6144,\n \t.flow_pattern_id = 0,\n@@ -7006,13 +10999,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[348] = {\n+\t[510] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_179a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 6148,\n \t.flow_pattern_id = 0,\n@@ -7022,14 +11015,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[349] = {\n+\t[511] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59be,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 16384,\n \t.flow_pattern_id = 0,\n@@ -7039,12 +11032,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[350] = {\n+\t[512] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_515a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 16388,\n \t.flow_pattern_id = 0,\n@@ -7054,13 +11047,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[351] = {\n+\t[513] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c72,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 24576,\n \t.flow_pattern_id = 0,\n@@ -7070,13 +11063,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[352] = {\n+\t[514] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_171e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 24580,\n \t.flow_pattern_id = 0,\n@@ -7086,14 +11079,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[353] = {\n+\t[515] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_19c8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 32768,\n \t.flow_pattern_id = 0,\n@@ -7104,12 +11097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[354] = {\n+\t[516] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_112c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 32772,\n \t.flow_pattern_id = 0,\n@@ -7120,13 +11113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[355] = {\n+\t[517] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d68,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 32832,\n \t.flow_pattern_id = 0,\n@@ -7137,13 +11130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[356] = {\n+\t[518] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_444c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 32836,\n \t.flow_pattern_id = 0,\n@@ -7154,14 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[357] = {\n+\t[519] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0e8c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 0,\n@@ -7172,13 +11165,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[358] = {\n+\t[520] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09e0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 49156,\n \t.flow_pattern_id = 0,\n@@ -7189,14 +11182,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[359] = {\n+\t[521] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1af0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 49216,\n \t.flow_pattern_id = 0,\n@@ -7207,14 +11200,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[360] = {\n+\t[522] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15d4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 49220,\n \t.flow_pattern_id = 0,\n@@ -7225,15 +11218,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[361] = {\n+\t[523] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1dd0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 131072,\n \t.flow_pattern_id = 0,\n@@ -7244,12 +11237,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[362] = {\n+\t[524] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14f4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 131076,\n \t.flow_pattern_id = 0,\n@@ -7260,13 +11253,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[363] = {\n+\t[525] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_70b0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 131136,\n \t.flow_pattern_id = 0,\n@@ -7277,13 +11270,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[364] = {\n+\t[526] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4854,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 131140,\n \t.flow_pattern_id = 0,\n@@ -7294,14 +11287,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[365] = {\n+\t[527] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3dd4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 196608,\n \t.flow_pattern_id = 0,\n@@ -7312,13 +11305,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[366] = {\n+\t[528] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_34f8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 196612,\n \t.flow_pattern_id = 0,\n@@ -7329,14 +11322,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[367] = {\n+\t[529] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09e8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 196672,\n \t.flow_pattern_id = 0,\n@@ -7347,14 +11340,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[368] = {\n+\t[530] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_008c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 196676,\n \t.flow_pattern_id = 0,\n@@ -7365,15 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[369] = {\n+\t[531] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_34e6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 4096,\n \t.flow_pattern_id = 0,\n@@ -7384,12 +11377,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[370] = {\n+\t[532] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c02,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 4100,\n \t.flow_pattern_id = 0,\n@@ -7400,13 +11393,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[371] = {\n+\t[533] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c9e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 6144,\n \t.flow_pattern_id = 0,\n@@ -7417,13 +11410,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[372] = {\n+\t[534] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_17ba,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 6148,\n \t.flow_pattern_id = 0,\n@@ -7434,14 +11427,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[373] = {\n+\t[535] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_429e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 12288,\n \t.flow_pattern_id = 0,\n@@ -7452,13 +11445,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[374] = {\n+\t[536] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5dba,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 12292,\n \t.flow_pattern_id = 0,\n@@ -7469,14 +11462,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[375] = {\n+\t[537] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a16,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 14336,\n \t.flow_pattern_id = 0,\n@@ -7487,14 +11480,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[376] = {\n+\t[538] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2532,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 14340,\n \t.flow_pattern_id = 0,\n@@ -7505,15 +11498,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[377] = {\n+\t[539] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2da2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 20480,\n \t.flow_pattern_id = 0,\n@@ -7524,13 +11517,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[378] = {\n+\t[540] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_24fe,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 20484,\n \t.flow_pattern_id = 0,\n@@ -7541,14 +11534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[379] = {\n+\t[541] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_355a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 22528,\n \t.flow_pattern_id = 0,\n@@ -7559,14 +11552,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[380] = {\n+\t[542] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c76,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 22532,\n \t.flow_pattern_id = 0,\n@@ -7577,15 +11570,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[381] = {\n+\t[543] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_13e6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 28672,\n \t.flow_pattern_id = 0,\n@@ -7596,14 +11589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[382] = {\n+\t[544] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7276,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 28676,\n \t.flow_pattern_id = 0,\n@@ -7614,15 +11607,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[383] = {\n+\t[545] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_42d2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 30720,\n \t.flow_pattern_id = 0,\n@@ -7633,15 +11626,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[384] = {\n+\t[546] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5dee,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 30724,\n \t.flow_pattern_id = 0,\n@@ -7652,16 +11645,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[385] = {\n+\t[547] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59de,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 16384,\n \t.flow_pattern_id = 0,\n@@ -7672,12 +11665,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[386] = {\n+\t[548] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_513a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 16388,\n \t.flow_pattern_id = 0,\n@@ -7688,13 +11681,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[387] = {\n+\t[549] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c12,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 24576,\n \t.flow_pattern_id = 0,\n@@ -7705,13 +11698,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[388] = {\n+\t[550] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_177e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 24580,\n \t.flow_pattern_id = 0,\n@@ -7722,14 +11715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[389] = {\n+\t[551] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0e92,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 0,\n@@ -7740,13 +11733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[390] = {\n+\t[552] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09fe,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 49156,\n \t.flow_pattern_id = 0,\n@@ -7757,14 +11750,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[391] = {\n+\t[553] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5c1a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 57344,\n \t.flow_pattern_id = 0,\n@@ -7775,14 +11768,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[392] = {\n+\t[554] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5746,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 57348,\n \t.flow_pattern_id = 0,\n@@ -7793,15 +11786,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[393] = {\n+\t[555] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_79da,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 81920,\n \t.flow_pattern_id = 0,\n@@ -7812,13 +11805,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[394] = {\n+\t[556] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7106,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 81924,\n \t.flow_pattern_id = 0,\n@@ -7829,14 +11822,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[395] = {\n+\t[557] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3c1e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 90112,\n \t.flow_pattern_id = 0,\n@@ -7847,14 +11840,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[396] = {\n+\t[558] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_377a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 90116,\n \t.flow_pattern_id = 0,\n@@ -7865,15 +11858,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[397] = {\n+\t[559] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e9e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 0,\n@@ -7884,14 +11877,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[398] = {\n+\t[560] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29fa,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 114692,\n \t.flow_pattern_id = 0,\n@@ -7902,15 +11895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[399] = {\n+\t[561] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14d2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 122880,\n \t.flow_pattern_id = 0,\n@@ -7921,15 +11914,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[400] = {\n+\t[562] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7742,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 122884,\n \t.flow_pattern_id = 0,\n@@ -7940,16 +11933,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[401] = {\n+\t[563] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3706,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 4096,\n \t.flow_pattern_id = 0,\n@@ -7960,12 +11953,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[402] = {\n+\t[564] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0fe2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 4100,\n \t.flow_pattern_id = 0,\n@@ -7976,13 +11969,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[403] = {\n+\t[565] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1f7e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 6144,\n \t.flow_pattern_id = 0,\n@@ -7993,13 +11986,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[404] = {\n+\t[566] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_145a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 6148,\n \t.flow_pattern_id = 0,\n@@ -8010,14 +12003,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[405] = {\n+\t[567] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_417e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 12288,\n \t.flow_pattern_id = 0,\n@@ -8028,13 +12021,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[406] = {\n+\t[568] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e5a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 12292,\n \t.flow_pattern_id = 0,\n@@ -8045,14 +12038,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[407] = {\n+\t[569] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29f6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 14336,\n \t.flow_pattern_id = 0,\n@@ -8063,14 +12056,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[408] = {\n+\t[570] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_26d2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 14340,\n \t.flow_pattern_id = 0,\n@@ -8081,15 +12074,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[409] = {\n+\t[571] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e42,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 20480,\n \t.flow_pattern_id = 0,\n@@ -8100,13 +12093,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[410] = {\n+\t[572] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_271e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 20484,\n \t.flow_pattern_id = 0,\n@@ -8117,14 +12110,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[411] = {\n+\t[573] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_36ba,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 22528,\n \t.flow_pattern_id = 0,\n@@ -8135,14 +12128,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[412] = {\n+\t[574] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0f96,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 22532,\n \t.flow_pattern_id = 0,\n@@ -8153,15 +12146,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[413] = {\n+\t[575] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1006,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 28672,\n \t.flow_pattern_id = 0,\n@@ -8172,14 +12165,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[414] = {\n+\t[576] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7196,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 28676,\n \t.flow_pattern_id = 0,\n@@ -8190,15 +12183,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[415] = {\n+\t[577] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4132,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 30720,\n \t.flow_pattern_id = 0,\n@@ -8209,15 +12202,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[416] = {\n+\t[578] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e0e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 30724,\n \t.flow_pattern_id = 0,\n@@ -8228,16 +12221,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[417] = {\n+\t[579] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59fe,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 16384,\n \t.flow_pattern_id = 0,\n@@ -8248,12 +12241,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[418] = {\n+\t[580] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_511a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 16388,\n \t.flow_pattern_id = 0,\n@@ -8264,13 +12257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[419] = {\n+\t[581] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c32,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 24576,\n \t.flow_pattern_id = 0,\n@@ -8281,13 +12274,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[420] = {\n+\t[582] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_175e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 24580,\n \t.flow_pattern_id = 0,\n@@ -8298,14 +12291,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[421] = {\n+\t[583] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0eb2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 0,\n@@ -8316,13 +12309,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[422] = {\n+\t[584] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09de,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 49156,\n \t.flow_pattern_id = 0,\n@@ -8333,14 +12326,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[423] = {\n+\t[585] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5c3a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 57344,\n \t.flow_pattern_id = 0,\n@@ -8351,14 +12344,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[424] = {\n+\t[586] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5766,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 57348,\n \t.flow_pattern_id = 0,\n@@ -8369,15 +12362,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[425] = {\n+\t[587] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_79fa,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 81920,\n \t.flow_pattern_id = 0,\n@@ -8388,13 +12381,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[426] = {\n+\t[588] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7126,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 81924,\n \t.flow_pattern_id = 0,\n@@ -8405,14 +12398,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[427] = {\n+\t[589] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3c3e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 90112,\n \t.flow_pattern_id = 0,\n@@ -8423,14 +12416,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[428] = {\n+\t[590] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_375a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 90116,\n \t.flow_pattern_id = 0,\n@@ -8441,15 +12434,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[429] = {\n+\t[591] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2ebe,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 0,\n@@ -8460,14 +12453,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[430] = {\n+\t[592] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29da,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 114692,\n \t.flow_pattern_id = 0,\n@@ -8478,15 +12471,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[431] = {\n+\t[593] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14f2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 122880,\n \t.flow_pattern_id = 0,\n@@ -8497,15 +12490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[432] = {\n+\t[594] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7762,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 122884,\n \t.flow_pattern_id = 0,\n@@ -8516,16 +12509,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[433] = {\n+\t[595] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_19e8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 32768,\n \t.flow_pattern_id = 0,\n@@ -8537,12 +12530,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[434] = {\n+\t[596] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_110c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 32772,\n \t.flow_pattern_id = 0,\n@@ -8554,13 +12547,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[435] = {\n+\t[597] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d48,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 32832,\n \t.flow_pattern_id = 0,\n@@ -8572,13 +12565,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[436] = {\n+\t[598] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_446c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 32836,\n \t.flow_pattern_id = 0,\n@@ -8590,14 +12583,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[437] = {\n+\t[599] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0eac,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 0,\n@@ -8609,13 +12602,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[438] = {\n+\t[600] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09c0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 49156,\n \t.flow_pattern_id = 0,\n@@ -8627,14 +12620,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[439] = {\n+\t[601] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1ad0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 49216,\n \t.flow_pattern_id = 0,\n@@ -8646,14 +12639,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[440] = {\n+\t[602] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15f4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 49220,\n \t.flow_pattern_id = 0,\n@@ -8665,15 +12658,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[441] = {\n+\t[603] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_39ec,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 98304,\n \t.flow_pattern_id = 0,\n@@ -8685,13 +12678,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[442] = {\n+\t[604] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3100,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 98308,\n \t.flow_pattern_id = 0,\n@@ -8703,14 +12696,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[443] = {\n+\t[605] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0210,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 98368,\n \t.flow_pattern_id = 0,\n@@ -8722,14 +12715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[444] = {\n+\t[606] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1d34,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 98372,\n \t.flow_pattern_id = 0,\n@@ -8741,15 +12734,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[445] = {\n+\t[607] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2ea0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 0,\n@@ -8761,14 +12754,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[446] = {\n+\t[608] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29c4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 114692,\n \t.flow_pattern_id = 0,\n@@ -8780,15 +12773,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[447] = {\n+\t[609] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ad4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 114752,\n \t.flow_pattern_id = 0,\n@@ -8800,15 +12793,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[448] = {\n+\t[610] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_35e8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 114756,\n \t.flow_pattern_id = 0,\n@@ -8820,16 +12813,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[449] = {\n+\t[611] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5d80,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 163840,\n \t.flow_pattern_id = 0,\n@@ -8841,13 +12834,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[450] = {\n+\t[612] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_54a4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 163844,\n \t.flow_pattern_id = 0,\n@@ -8859,14 +12852,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[451] = {\n+\t[613] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_29b4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 163904,\n \t.flow_pattern_id = 0,\n@@ -8878,14 +12871,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[452] = {\n+\t[614] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_20c8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 163908,\n \t.flow_pattern_id = 0,\n@@ -8897,15 +12890,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[453] = {\n+\t[615] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7244,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 180224,\n \t.flow_pattern_id = 0,\n@@ -8917,14 +12910,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[454] = {\n+\t[616] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d98,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 180228,\n \t.flow_pattern_id = 0,\n@@ -8936,15 +12929,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[455] = {\n+\t[617] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e68,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 180288,\n \t.flow_pattern_id = 0,\n@@ -8956,15 +12949,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[456] = {\n+\t[618] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_598c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 180292,\n \t.flow_pattern_id = 0,\n@@ -8976,16 +12969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[457] = {\n+\t[619] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1248,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 229376,\n \t.flow_pattern_id = 0,\n@@ -8997,14 +12990,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[458] = {\n+\t[620] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_74d8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 229380,\n \t.flow_pattern_id = 0,\n@@ -9016,15 +13009,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[459] = {\n+\t[621] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_49a8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 229440,\n \t.flow_pattern_id = 0,\n@@ -9036,15 +13029,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[460] = {\n+\t[622] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_40cc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 229444,\n \t.flow_pattern_id = 0,\n@@ -9056,16 +13049,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[461] = {\n+\t[623] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0b0c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 245760,\n \t.flow_pattern_id = 0,\n@@ -9077,15 +13070,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[462] = {\n+\t[624] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0220,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 245764,\n \t.flow_pattern_id = 0,\n@@ -9097,16 +13090,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[463] = {\n+\t[625] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1730,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 245824,\n \t.flow_pattern_id = 0,\n@@ -9118,16 +13111,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[464] = {\n+\t[626] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7980,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 245828,\n \t.flow_pattern_id = 0,\n@@ -9139,17 +13132,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[465] = {\n+\t[627] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1db0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 131072,\n \t.flow_pattern_id = 0,\n@@ -9161,12 +13154,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[466] = {\n+\t[628] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1494,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 131076,\n \t.flow_pattern_id = 0,\n@@ -9178,13 +13171,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[467] = {\n+\t[629] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_70d0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 131136,\n \t.flow_pattern_id = 0,\n@@ -9196,13 +13189,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[468] = {\n+\t[630] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4834,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 131140,\n \t.flow_pattern_id = 0,\n@@ -9214,14 +13207,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[469] = {\n+\t[631] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3db4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 196608,\n \t.flow_pattern_id = 0,\n@@ -9233,13 +13226,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[470] = {\n+\t[632] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3498,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 196612,\n \t.flow_pattern_id = 0,\n@@ -9251,14 +13244,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[471] = {\n+\t[633] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0988,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 196672,\n \t.flow_pattern_id = 0,\n@@ -9270,14 +13263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[472] = {\n+\t[634] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_00ec,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 196676,\n \t.flow_pattern_id = 0,\n@@ -9289,15 +13282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[473] = {\n+\t[635] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3f44,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 393216,\n \t.flow_pattern_id = 0,\n@@ -9309,13 +13302,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[474] = {\n+\t[636] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_36a8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 393220,\n \t.flow_pattern_id = 0,\n@@ -9327,14 +13320,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[475] = {\n+\t[637] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0b58,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 393280,\n \t.flow_pattern_id = 0,\n@@ -9346,14 +13339,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[476] = {\n+\t[638] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_02bc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 393284,\n \t.flow_pattern_id = 0,\n@@ -9365,15 +13358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[477] = {\n+\t[639] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5f48,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 458752,\n \t.flow_pattern_id = 0,\n@@ -9385,14 +13378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[478] = {\n+\t[640] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_56ac,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 458756,\n \t.flow_pattern_id = 0,\n@@ -9404,15 +13397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[479] = {\n+\t[641] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2b5c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 458816,\n \t.flow_pattern_id = 0,\n@@ -9424,15 +13417,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[480] = {\n+\t[642] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2280,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 458820,\n \t.flow_pattern_id = 0,\n@@ -9444,16 +13437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[481] = {\n+\t[643] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4000,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 655360,\n \t.flow_pattern_id = 0,\n@@ -9465,13 +13458,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[482] = {\n+\t[644] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5b64,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 655364,\n \t.flow_pattern_id = 0,\n@@ -9483,14 +13476,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[483] = {\n+\t[645] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2c14,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 655424,\n \t.flow_pattern_id = 0,\n@@ -9502,14 +13495,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[484] = {\n+\t[646] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2778,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 655428,\n \t.flow_pattern_id = 0,\n@@ -9521,15 +13514,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[485] = {\n+\t[647] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_18f8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 720896,\n \t.flow_pattern_id = 0,\n@@ -9541,14 +13534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[486] = {\n+\t[648] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_13dc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 720900,\n \t.flow_pattern_id = 0,\n@@ -9560,15 +13553,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[487] = {\n+\t[649] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4c18,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 720960,\n \t.flow_pattern_id = 0,\n@@ -9580,15 +13573,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[488] = {\n+\t[650] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_477c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 720964,\n \t.flow_pattern_id = 0,\n@@ -9600,16 +13593,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[489] = {\n+\t[651] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1a88,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 917504,\n \t.flow_pattern_id = 0,\n@@ -9621,14 +13614,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[490] = {\n+\t[652] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15ec,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 917508,\n \t.flow_pattern_id = 0,\n@@ -9640,15 +13633,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[491] = {\n+\t[653] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e28,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 917568,\n \t.flow_pattern_id = 0,\n@@ -9660,15 +13653,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[492] = {\n+\t[654] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_490c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 917572,\n \t.flow_pattern_id = 0,\n@@ -9680,16 +13673,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[493] = {\n+\t[655] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a8c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 983040,\n \t.flow_pattern_id = 0,\n@@ -9701,15 +13694,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[494] = {\n+\t[656] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_35f0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 983044,\n \t.flow_pattern_id = 0,\n@@ -9721,16 +13714,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[495] = {\n+\t[657] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06e0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 983104,\n \t.flow_pattern_id = 0,\n@@ -9742,16 +13735,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[496] = {\n+\t[658] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01c4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 983108,\n \t.flow_pattern_id = 0,\n@@ -9763,17 +13756,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[497] = {\n+\t[659] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1a08,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 32768,\n \t.flow_pattern_id = 0,\n@@ -9785,12 +13778,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[498] = {\n+\t[660] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_12ec,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 32772,\n \t.flow_pattern_id = 0,\n@@ -9802,13 +13795,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[499] = {\n+\t[661] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4ea8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 32832,\n \t.flow_pattern_id = 0,\n@@ -9820,13 +13813,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[500] = {\n+\t[662] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_478c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 32836,\n \t.flow_pattern_id = 0,\n@@ -9838,14 +13831,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[501] = {\n+\t[663] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0d4c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 0,\n@@ -9857,13 +13850,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[502] = {\n+\t[664] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0a20,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 49156,\n \t.flow_pattern_id = 0,\n@@ -9875,14 +13868,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[503] = {\n+\t[665] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1930,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 49216,\n \t.flow_pattern_id = 0,\n@@ -9894,14 +13887,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[504] = {\n+\t[666] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1614,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 49220,\n \t.flow_pattern_id = 0,\n@@ -9913,15 +13906,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[505] = {\n+\t[667] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a0c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 98304,\n \t.flow_pattern_id = 0,\n@@ -9933,13 +13926,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[506] = {\n+\t[668] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_32e0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 98308,\n \t.flow_pattern_id = 0,\n@@ -9951,14 +13944,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[507] = {\n+\t[669] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01f0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 98368,\n \t.flow_pattern_id = 0,\n@@ -9970,14 +13963,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[508] = {\n+\t[670] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1ed4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 98372,\n \t.flow_pattern_id = 0,\n@@ -9989,15 +13982,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[509] = {\n+\t[671] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2d40,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 0,\n@@ -10009,14 +14002,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[510] = {\n+\t[672] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a24,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 114692,\n \t.flow_pattern_id = 0,\n@@ -10028,15 +14021,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[511] = {\n+\t[673] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3934,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 114752,\n \t.flow_pattern_id = 0,\n@@ -10048,15 +14041,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[512] = {\n+\t[674] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3608,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 114756,\n \t.flow_pattern_id = 0,\n@@ -10068,16 +14061,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[513] = {\n+\t[675] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5e60,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 163840,\n \t.flow_pattern_id = 0,\n@@ -10089,13 +14082,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[514] = {\n+\t[676] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5744,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 163844,\n \t.flow_pattern_id = 0,\n@@ -10107,14 +14100,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[515] = {\n+\t[677] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a54,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 163904,\n \t.flow_pattern_id = 0,\n@@ -10126,14 +14119,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[516] = {\n+\t[678] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2328,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 163908,\n \t.flow_pattern_id = 0,\n@@ -10145,15 +14138,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[517] = {\n+\t[679] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_71a4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 180224,\n \t.flow_pattern_id = 0,\n@@ -10165,14 +14158,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[518] = {\n+\t[680] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e78,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 180228,\n \t.flow_pattern_id = 0,\n@@ -10184,15 +14177,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[519] = {\n+\t[681] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5d88,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 180288,\n \t.flow_pattern_id = 0,\n@@ -10204,15 +14197,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[520] = {\n+\t[682] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5a6c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 180292,\n \t.flow_pattern_id = 0,\n@@ -10224,16 +14217,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[521] = {\n+\t[683] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_11a8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 229376,\n \t.flow_pattern_id = 0,\n@@ -10245,14 +14238,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[522] = {\n+\t[684] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7738,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 229380,\n \t.flow_pattern_id = 0,\n@@ -10264,15 +14257,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[523] = {\n+\t[685] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4a48,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 229440,\n \t.flow_pattern_id = 0,\n@@ -10284,15 +14277,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[524] = {\n+\t[686] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_432c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 229444,\n \t.flow_pattern_id = 0,\n@@ -10304,16 +14297,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[525] = {\n+\t[687] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_08ec,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 245760,\n \t.flow_pattern_id = 0,\n@@ -10325,15 +14318,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[526] = {\n+\t[688] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01c0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 245764,\n \t.flow_pattern_id = 0,\n@@ -10345,16 +14338,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[527] = {\n+\t[689] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14d0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 245824,\n \t.flow_pattern_id = 0,\n@@ -10366,16 +14359,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[528] = {\n+\t[690] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7a60,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 245828,\n \t.flow_pattern_id = 0,\n@@ -10387,17 +14380,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[529] = {\n+\t[691] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1d90,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 131072,\n \t.flow_pattern_id = 0,\n@@ -10409,12 +14402,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[530] = {\n+\t[692] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_14b4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 131076,\n \t.flow_pattern_id = 0,\n@@ -10426,13 +14419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[531] = {\n+\t[693] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_70f0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 131136,\n \t.flow_pattern_id = 0,\n@@ -10444,13 +14437,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[532] = {\n+\t[694] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4814,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 131140,\n \t.flow_pattern_id = 0,\n@@ -10462,14 +14455,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[533] = {\n+\t[695] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3d94,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 196608,\n \t.flow_pattern_id = 0,\n@@ -10481,13 +14474,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[534] = {\n+\t[696] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_34b8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 196612,\n \t.flow_pattern_id = 0,\n@@ -10499,14 +14492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[535] = {\n+\t[697] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_09a8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 196672,\n \t.flow_pattern_id = 0,\n@@ -10518,14 +14511,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[536] = {\n+\t[698] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_00cc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 196676,\n \t.flow_pattern_id = 0,\n@@ -10537,15 +14530,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[537] = {\n+\t[699] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3f64,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 393216,\n \t.flow_pattern_id = 0,\n@@ -10557,13 +14550,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[538] = {\n+\t[700] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3688,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 393220,\n \t.flow_pattern_id = 0,\n@@ -10575,14 +14568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[539] = {\n+\t[701] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0b78,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 393280,\n \t.flow_pattern_id = 0,\n@@ -10594,14 +14587,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[540] = {\n+\t[702] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_029c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 393284,\n \t.flow_pattern_id = 0,\n@@ -10613,15 +14606,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[541] = {\n+\t[703] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5f68,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 458752,\n \t.flow_pattern_id = 0,\n@@ -10633,14 +14626,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[542] = {\n+\t[704] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_568c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 458756,\n \t.flow_pattern_id = 0,\n@@ -10652,15 +14645,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[543] = {\n+\t[705] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2b7c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 458816,\n \t.flow_pattern_id = 0,\n@@ -10672,15 +14665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[544] = {\n+\t[706] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_22a0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 458820,\n \t.flow_pattern_id = 0,\n@@ -10692,16 +14685,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[545] = {\n+\t[707] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4020,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 655360,\n \t.flow_pattern_id = 0,\n@@ -10713,13 +14706,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[546] = {\n+\t[708] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5b44,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 655364,\n \t.flow_pattern_id = 0,\n@@ -10731,14 +14724,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[547] = {\n+\t[709] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2c34,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 655424,\n \t.flow_pattern_id = 0,\n@@ -10750,14 +14743,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[548] = {\n+\t[710] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2758,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 655428,\n \t.flow_pattern_id = 0,\n@@ -10769,15 +14762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[549] = {\n+\t[711] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_18d8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 720896,\n \t.flow_pattern_id = 0,\n@@ -10789,14 +14782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[550] = {\n+\t[712] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_13fc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 720900,\n \t.flow_pattern_id = 0,\n@@ -10808,15 +14801,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[551] = {\n+\t[713] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4c38,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 720960,\n \t.flow_pattern_id = 0,\n@@ -10828,15 +14821,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[552] = {\n+\t[714] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_475c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 720964,\n \t.flow_pattern_id = 0,\n@@ -10848,16 +14841,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[553] = {\n+\t[715] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1aa8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 917504,\n \t.flow_pattern_id = 0,\n@@ -10869,14 +14862,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[554] = {\n+\t[716] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_15cc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 917508,\n \t.flow_pattern_id = 0,\n@@ -10888,15 +14881,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[555] = {\n+\t[717] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e08,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 917568,\n \t.flow_pattern_id = 0,\n@@ -10908,15 +14901,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[556] = {\n+\t[718] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_492c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 917572,\n \t.flow_pattern_id = 0,\n@@ -10928,16 +14921,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[557] = {\n+\t[719] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3aac,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 983040,\n \t.flow_pattern_id = 0,\n@@ -10949,15 +14942,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[558] = {\n+\t[720] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_35d0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 983044,\n \t.flow_pattern_id = 0,\n@@ -10969,16 +14962,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[559] = {\n+\t[721] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06c0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 983104,\n \t.flow_pattern_id = 0,\n@@ -10990,16 +14983,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[560] = {\n+\t[722] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_01e4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 983108,\n \t.flow_pattern_id = 0,\n@@ -11011,17 +15004,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[561] = {\n+\t[723] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d32,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 4096,\n \t.flow_pattern_id = 1,\n@@ -11031,11 +15024,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[562] = {\n+\t[724] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_54aa,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 6144,\n \t.flow_pattern_id = 1,\n@@ -11045,12 +15038,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[563] = {\n+\t[725] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0686,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 16384,\n \t.flow_pattern_id = 1,\n@@ -11060,11 +15053,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[564] = {\n+\t[726] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_540e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 24576,\n \t.flow_pattern_id = 1,\n@@ -11074,12 +15067,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[565] = {\n+\t[727] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e3c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 32768,\n \t.flow_pattern_id = 1,\n@@ -11090,11 +15083,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[566] = {\n+\t[728] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a20,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 32832,\n \t.flow_pattern_id = 1,\n@@ -11105,12 +15098,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[567] = {\n+\t[729] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46f0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 1,\n@@ -11121,12 +15114,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[568] = {\n+\t[730] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_52e4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 49216,\n \t.flow_pattern_id = 1,\n@@ -11137,13 +15130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[569] = {\n+\t[731] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_55e4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 131072,\n \t.flow_pattern_id = 1,\n@@ -11154,11 +15147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[570] = {\n+\t[732] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_21f8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 131136,\n \t.flow_pattern_id = 1,\n@@ -11169,12 +15162,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[571] = {\n+\t[733] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_75e8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 196608,\n \t.flow_pattern_id = 1,\n@@ -11185,12 +15178,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[572] = {\n+\t[734] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_41fc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 196672,\n \t.flow_pattern_id = 1,\n@@ -11201,13 +15194,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[573] = {\n+\t[735] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d12,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 4096,\n \t.flow_pattern_id = 1,\n@@ -11218,11 +15211,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[574] = {\n+\t[736] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_548a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 6144,\n \t.flow_pattern_id = 1,\n@@ -11233,12 +15226,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[575] = {\n+\t[737] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3356,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 12288,\n \t.flow_pattern_id = 1,\n@@ -11249,12 +15242,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[576] = {\n+\t[738] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1ace,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 14336,\n \t.flow_pattern_id = 1,\n@@ -11265,13 +15258,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[577] = {\n+\t[739] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1a9a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 20480,\n \t.flow_pattern_id = 1,\n@@ -11282,12 +15275,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[578] = {\n+\t[740] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4d46,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 22528,\n \t.flow_pattern_id = 1,\n@@ -11298,13 +15291,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[579] = {\n+\t[741] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2812,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 28672,\n \t.flow_pattern_id = 1,\n@@ -11315,13 +15308,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[580] = {\n+\t[742] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_338a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 30720,\n \t.flow_pattern_id = 1,\n@@ -11332,14 +15325,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[581] = {\n+\t[743] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06e6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 16384,\n \t.flow_pattern_id = 1,\n@@ -11350,11 +15343,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[582] = {\n+\t[744] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_546e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 24576,\n \t.flow_pattern_id = 1,\n@@ -11365,12 +15358,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[583] = {\n+\t[745] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46ee,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 1,\n@@ -11381,12 +15374,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[584] = {\n+\t[746] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0d22,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 57344,\n \t.flow_pattern_id = 1,\n@@ -11397,13 +15390,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[585] = {\n+\t[747] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_26e2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 81920,\n \t.flow_pattern_id = 1,\n@@ -11414,12 +15407,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[586] = {\n+\t[748] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_746a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 90112,\n \t.flow_pattern_id = 1,\n@@ -11430,13 +15423,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[587] = {\n+\t[749] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1fa6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 1,\n@@ -11447,13 +15440,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[588] = {\n+\t[750] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2d2e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 122880,\n \t.flow_pattern_id = 1,\n@@ -11464,14 +15457,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[589] = {\n+\t[751] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4ef2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 4096,\n \t.flow_pattern_id = 1,\n@@ -11482,11 +15475,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[590] = {\n+\t[752] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_576a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 6144,\n \t.flow_pattern_id = 1,\n@@ -11497,12 +15490,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[591] = {\n+\t[753] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_30b6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 12288,\n \t.flow_pattern_id = 1,\n@@ -11513,12 +15506,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[592] = {\n+\t[754] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_192e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 14336,\n \t.flow_pattern_id = 1,\n@@ -11529,13 +15522,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[593] = {\n+\t[755] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_197a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 20480,\n \t.flow_pattern_id = 1,\n@@ -11546,12 +15539,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[594] = {\n+\t[756] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4ea6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 22528,\n \t.flow_pattern_id = 1,\n@@ -11562,13 +15555,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[595] = {\n+\t[757] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2bf2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 28672,\n \t.flow_pattern_id = 1,\n@@ -11579,13 +15572,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[596] = {\n+\t[758] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_306a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 30720,\n \t.flow_pattern_id = 1,\n@@ -11596,14 +15589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[597] = {\n+\t[759] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_06c6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 16384,\n \t.flow_pattern_id = 1,\n@@ -11614,11 +15607,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[598] = {\n+\t[760] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_544e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 24576,\n \t.flow_pattern_id = 1,\n@@ -11629,12 +15622,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[599] = {\n+\t[761] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46ce,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 1,\n@@ -11645,12 +15638,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[600] = {\n+\t[762] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0d02,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 57344,\n \t.flow_pattern_id = 1,\n@@ -11661,13 +15654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[601] = {\n+\t[763] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_26c2,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 81920,\n \t.flow_pattern_id = 1,\n@@ -11678,12 +15671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[602] = {\n+\t[764] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_744a,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 90112,\n \t.flow_pattern_id = 1,\n@@ -11694,13 +15687,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[603] = {\n+\t[765] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1f86,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 1,\n@@ -11711,13 +15704,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[604] = {\n+\t[766] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2d0e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 122880,\n \t.flow_pattern_id = 1,\n@@ -11728,14 +15721,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[605] = {\n+\t[767] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2e1c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 32768,\n \t.flow_pattern_id = 1,\n@@ -11747,11 +15740,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[606] = {\n+\t[768] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3a00,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 32832,\n \t.flow_pattern_id = 1,\n@@ -11763,12 +15756,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[607] = {\n+\t[769] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_46d0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 1,\n@@ -11780,12 +15773,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[608] = {\n+\t[770] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_52c4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 49216,\n \t.flow_pattern_id = 1,\n@@ -11797,13 +15790,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[609] = {\n+\t[771] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4e10,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 98304,\n \t.flow_pattern_id = 1,\n@@ -11815,12 +15808,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[610] = {\n+\t[772] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5a04,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 98368,\n \t.flow_pattern_id = 1,\n@@ -11832,13 +15825,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[611] = {\n+\t[773] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1f98,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 1,\n@@ -11850,13 +15843,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[612] = {\n+\t[774] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_72f8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 114752,\n \t.flow_pattern_id = 1,\n@@ -11868,14 +15861,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[613] = {\n+\t[775] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0a78,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 163840,\n \t.flow_pattern_id = 1,\n@@ -11887,12 +15880,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[614] = {\n+\t[776] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_166c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 163904,\n \t.flow_pattern_id = 1,\n@@ -11904,13 +15897,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[615] = {\n+\t[777] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_233c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 180224,\n \t.flow_pattern_id = 1,\n@@ -11922,13 +15915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[616] = {\n+\t[778] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0f20,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 180288,\n \t.flow_pattern_id = 1,\n@@ -11940,14 +15933,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[617] = {\n+\t[779] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2a7c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 229376,\n \t.flow_pattern_id = 1,\n@@ -11959,13 +15952,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[618] = {\n+\t[780] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3660,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 229440,\n \t.flow_pattern_id = 1,\n@@ -11977,14 +15970,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[619] = {\n+\t[781] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4330,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 245760,\n \t.flow_pattern_id = 1,\n@@ -11996,14 +15989,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[620] = {\n+\t[782] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2f24,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 245824,\n \t.flow_pattern_id = 1,\n@@ -12015,15 +16008,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[621] = {\n+\t[783] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5584,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 131072,\n \t.flow_pattern_id = 1,\n@@ -12035,11 +16028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[622] = {\n+\t[784] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2198,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 131136,\n \t.flow_pattern_id = 1,\n@@ -12051,12 +16044,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[623] = {\n+\t[785] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7588,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 196608,\n \t.flow_pattern_id = 1,\n@@ -12068,12 +16061,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[624] = {\n+\t[786] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_419c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 196672,\n \t.flow_pattern_id = 1,\n@@ -12085,13 +16078,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[625] = {\n+\t[787] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7758,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 393216,\n \t.flow_pattern_id = 1,\n@@ -12103,12 +16096,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[626] = {\n+\t[788] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_43ac,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 393280,\n \t.flow_pattern_id = 1,\n@@ -12120,13 +16113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[627] = {\n+\t[789] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c10,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 458752,\n \t.flow_pattern_id = 1,\n@@ -12138,13 +16131,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[628] = {\n+\t[790] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1864,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 458816,\n \t.flow_pattern_id = 1,\n@@ -12156,14 +16149,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }\n \t},\n-\t[629] = {\n+\t[791] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_30c8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 655360,\n \t.flow_pattern_id = 1,\n@@ -12175,12 +16168,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[630] = {\n+\t[792] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1cdc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 655424,\n \t.flow_pattern_id = 1,\n@@ -12192,13 +16185,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[631] = {\n+\t[793] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_50cc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 720896,\n \t.flow_pattern_id = 1,\n@@ -12210,13 +16203,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[632] = {\n+\t[794] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3d20,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 720960,\n \t.flow_pattern_id = 1,\n@@ -12228,14 +16221,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[633] = {\n+\t[795] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_529c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 917504,\n \t.flow_pattern_id = 1,\n@@ -12247,13 +16240,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[634] = {\n+\t[796] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ef0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 917568,\n \t.flow_pattern_id = 1,\n@@ -12265,14 +16258,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[635] = {\n+\t[797] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_72e0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 983040,\n \t.flow_pattern_id = 1,\n@@ -12284,14 +16277,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[636] = {\n+\t[798] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5ef4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 983104,\n \t.flow_pattern_id = 1,\n@@ -12303,15 +16296,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }\n \t},\n-\t[637] = {\n+\t[799] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2dfc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 32768,\n \t.flow_pattern_id = 1,\n@@ -12323,11 +16316,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[638] = {\n+\t[800] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_39e0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 32832,\n \t.flow_pattern_id = 1,\n@@ -12339,12 +16332,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[639] = {\n+\t[801] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4530,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 49152,\n \t.flow_pattern_id = 1,\n@@ -12356,12 +16349,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[640] = {\n+\t[802] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5124,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 49216,\n \t.flow_pattern_id = 1,\n@@ -12373,13 +16366,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }\n \t},\n-\t[641] = {\n+\t[803] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_4df0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 98304,\n \t.flow_pattern_id = 1,\n@@ -12391,12 +16384,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[642] = {\n+\t[804] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_59e4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 98368,\n \t.flow_pattern_id = 1,\n@@ -12408,13 +16401,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[643] = {\n+\t[805] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1c78,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 114688,\n \t.flow_pattern_id = 1,\n@@ -12426,13 +16419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[644] = {\n+\t[806] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7118,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 114752,\n \t.flow_pattern_id = 1,\n@@ -12444,14 +16437,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[645] = {\n+\t[807] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0998,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 163840,\n \t.flow_pattern_id = 1,\n@@ -12463,12 +16456,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[646] = {\n+\t[808] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_158c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 163904,\n \t.flow_pattern_id = 1,\n@@ -12480,13 +16473,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[647] = {\n+\t[809] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_20dc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 180224,\n \t.flow_pattern_id = 1,\n@@ -12498,13 +16491,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[648] = {\n+\t[810] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0cc0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 180288,\n \t.flow_pattern_id = 1,\n@@ -12516,14 +16509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[649] = {\n+\t[811] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_299c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 229376,\n \t.flow_pattern_id = 1,\n@@ -12535,13 +16528,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[650] = {\n+\t[812] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3580,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 229440,\n \t.flow_pattern_id = 1,\n@@ -12553,14 +16546,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[651] = {\n+\t[813] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_40d0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 245760,\n \t.flow_pattern_id = 1,\n@@ -12572,14 +16565,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[652] = {\n+\t[814] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_2cc4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 245824,\n \t.flow_pattern_id = 1,\n@@ -12591,15 +16584,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[653] = {\n+\t[815] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_55a4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 131072,\n \t.flow_pattern_id = 1,\n@@ -12611,11 +16604,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[654] = {\n+\t[816] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_21b8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 131136,\n \t.flow_pattern_id = 1,\n@@ -12627,12 +16620,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[655] = {\n+\t[817] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_75a8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 196608,\n \t.flow_pattern_id = 1,\n@@ -12644,12 +16637,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[656] = {\n+\t[818] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_41bc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 196672,\n \t.flow_pattern_id = 1,\n@@ -12661,13 +16654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }\n \t},\n-\t[657] = {\n+\t[819] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_7778,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 393216,\n \t.flow_pattern_id = 1,\n@@ -12679,12 +16672,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[658] = {\n+\t[820] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_438c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 393280,\n \t.flow_pattern_id = 1,\n@@ -12696,13 +16689,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[659] = {\n+\t[821] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0c30,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 458752,\n \t.flow_pattern_id = 1,\n@@ -12714,13 +16707,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[660] = {\n+\t[822] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1844,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 458816,\n \t.flow_pattern_id = 1,\n@@ -12732,14 +16725,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }\n \t},\n-\t[661] = {\n+\t[823] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_30e8,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 655360,\n \t.flow_pattern_id = 1,\n@@ -12751,12 +16744,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[662] = {\n+\t[824] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_1cfc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 655424,\n \t.flow_pattern_id = 1,\n@@ -12768,13 +16761,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[663] = {\n+\t[825] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_50ec,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 720896,\n \t.flow_pattern_id = 1,\n@@ -12786,13 +16779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[664] = {\n+\t[826] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3d00,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 720960,\n \t.flow_pattern_id = 1,\n@@ -12804,14 +16797,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[665] = {\n+\t[827] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_52bc,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 917504,\n \t.flow_pattern_id = 1,\n@@ -12823,13 +16816,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[666] = {\n+\t[828] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ed0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 917568,\n \t.flow_pattern_id = 1,\n@@ -12841,14 +16834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[667] = {\n+\t[829] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_72c0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 983040,\n \t.flow_pattern_id = 1,\n@@ -12860,14 +16853,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[668] = {\n+\t[830] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_5ed4,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 983104,\n \t.flow_pattern_id = 1,\n@@ -12879,15 +16872,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }\n \t},\n-\t[669] = {\n+\t[831] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3866,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -12897,12 +16890,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }\n \t},\n-\t[670] = {\n+\t[832] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_381e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -12912,12 +16905,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }\n \t},\n-\t[671] = {\n+\t[833] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3860,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -12928,12 +16921,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }\n \t},\n-\t[672] = {\n+\t[834] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0454,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 2,\n \t.flow_sig_id = 68,\n \t.flow_pattern_id = 2,\n@@ -12944,13 +16937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID }\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }\n \t},\n-\t[673] = {\n+\t[835] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3818,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -12961,12 +16954,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }\n \t},\n-\t[674] = {\n+\t[836] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_042c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 3,\n \t.flow_sig_id = 68,\n \t.flow_pattern_id = 2,\n@@ -12977,13 +16970,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID }\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }\n \t},\n-\t[675] = {\n+\t[837] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3846,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 4,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -12994,12 +16987,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }\n \t},\n-\t[676] = {\n+\t[838] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_387e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 5,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -13010,12 +17003,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }\n \t},\n-\t[677] = {\n+\t[839] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ba6,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 6,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -13026,12 +17019,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }\n \t},\n-\t[678] = {\n+\t[840] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_385e,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 7,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -13042,12 +17035,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }\n \t},\n-\t[679] = {\n+\t[841] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3840,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -13059,12 +17052,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }\n \t},\n-\t[680] = {\n+\t[842] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0474,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 8,\n \t.flow_sig_id = 68,\n \t.flow_pattern_id = 2,\n@@ -13076,13 +17069,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID }\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }\n \t},\n-\t[681] = {\n+\t[843] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3878,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -13094,12 +17087,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }\n \t},\n-\t[682] = {\n+\t[844] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_044c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 9,\n \t.flow_sig_id = 68,\n \t.flow_pattern_id = 2,\n@@ -13111,13 +17104,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID }\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }\n \t},\n-\t[683] = {\n+\t[845] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3ba0,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -13129,12 +17122,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }\n \t},\n-\t[684] = {\n+\t[846] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_0794,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 10,\n \t.flow_sig_id = 68,\n \t.flow_pattern_id = 2,\n@@ -13146,13 +17139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID }\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }\n \t},\n-\t[685] = {\n+\t[847] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_3858,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 4,\n \t.flow_pattern_id = 2,\n@@ -13164,12 +17157,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }\n \t},\n-\t[686] = {\n+\t[848] = {\n \t.class_hid = BNXT_ULP_CLASS_HID_046c,\n-\t.class_tid = 2,\n+\t.class_tid = 3,\n \t.hdr_sig_id = 11,\n \t.flow_sig_id = 68,\n \t.flow_pattern_id = 2,\n@@ -13181,8 +17174,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |\n-\t\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID }\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID }\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h\nindex b6db49cc5d..e55d0923a5 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu May 13 18:15:56 2021 */\n+/* date: Thu May 20 11:56:39 2021 */\n \n #ifndef ULP_TEMPLATE_DB_H_\n #define ULP_TEMPLATE_DB_H_\n@@ -11,13 +11,13 @@\n #define BNXT_ULP_REGFILE_MAX_SZ 40\n #define BNXT_ULP_MAX_NUM_DEVICES 4\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n-#define BNXT_ULP_GEN_TBL_MAX_SZ 10\n+#define BNXT_ULP_GEN_TBL_MAX_SZ 12\n #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768\n-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687\n+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849\n #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701\n #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907\n-#define BNXT_ULP_CLASS_HID_SHFTR 23\n-#define BNXT_ULP_CLASS_HID_SHFTL 23\n+#define BNXT_ULP_CLASS_HID_SHFTR 24\n+#define BNXT_ULP_CLASS_HID_SHFTL 24\n #define BNXT_ULP_CLASS_HID_MASK 32767\n #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048\n #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86\n@@ -36,14 +36,14 @@\n #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7\n #define BNXT_ULP_HDR_SIG_ID_SHIFT 4\n #define BNXT_ULP_APP_ID_SHIFT 4\n-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595\n-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5\n-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74\n-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495\n-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20\n-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546\n-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43\n-#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5\n+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643\n+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6\n+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89\n+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600\n+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26\n+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619\n+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49\n+#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6\n #define ULP_THOR_CLASS_TBL_LIST_SIZE 33\n #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242\n #define ULP_THOR_CLASS_IDENT_LIST_SIZE 8\n@@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit {\n \tBNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000010000,\n \tBNXT_ULP_HDR_BIT_I_ICMP              = 0x0000000000020000,\n \tBNXT_ULP_HDR_BIT_F1                  = 0x0000000000040000,\n-\tBNXT_ULP_HDR_BIT_LAST                = 0x0000000000080000\n+\tBNXT_ULP_HDR_BIT_F2                  = 0x0000000000080000,\n+\tBNXT_ULP_HDR_BIT_LAST                = 0x0000000000100000\n };\n \n enum bnxt_ulp_accept_opc {\n@@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx {\n \tBNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,\n \tBNXT_ULP_CF_IDX_WC_MATCH = 61,\n \tBNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,\n-\tBNXT_ULP_CF_IDX_F1_DMAC = 63,\n-\tBNXT_ULP_CF_IDX_LAST = 64\n+\tBNXT_ULP_CF_IDX_TUNNEL_ID = 63,\n+\tBNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,\n+\tBNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,\n+\tBNXT_ULP_CF_IDX_LAST = 66\n };\n \n enum bnxt_ulp_cond_list_opc {\n@@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc {\n \tBNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7,\n \tBNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,\n \tBNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,\n-\tBNXT_ULP_FUNC_OPC_LAST = 10\n+\tBNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,\n+\tBNXT_ULP_FUNC_OPC_LAST = 11\n };\n \n enum bnxt_ulp_func_src {\n@@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc {\n \tBNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,\n \tBNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3,\n \tBNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4,\n-\tBNXT_ULP_TCAM_TBL_OPC_LAST = 5\n+\tBNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5,\n+\tBNXT_ULP_TCAM_TBL_OPC_LAST = 6\n };\n \n enum bnxt_ulp_template_type {\n@@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type {\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,\n \tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,\n-\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4\n+\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,\n+\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5\n };\n \n enum bnxt_ulp_act_prop_sz {\n@@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid {\n \tBNXT_ULP_CLASS_HID_15db = 0x15db,\n \tBNXT_ULP_CLASS_HID_1151 = 0x1151,\n \tBNXT_ULP_CLASS_HID_315d = 0x315d,\n+\tBNXT_ULP_CLASS_HID_3612 = 0x3612,\n+\tBNXT_ULP_CLASS_HID_66da = 0x66da,\n+\tBNXT_ULP_CLASS_HID_6165 = 0x6165,\n+\tBNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,\n+\tBNXT_ULP_CLASS_HID_09cd = 0x09cd,\n+\tBNXT_ULP_CLASS_HID_3845 = 0x3845,\n+\tBNXT_ULP_CLASS_HID_11e9 = 0x11e9,\n+\tBNXT_ULP_CLASS_HID_4361 = 0x4361,\n+\tBNXT_ULP_CLASS_HID_218d = 0x218d,\n+\tBNXT_ULP_CLASS_HID_5105 = 0x5105,\n+\tBNXT_ULP_CLASS_HID_0c89 = 0x0c89,\n+\tBNXT_ULP_CLASS_HID_3e81 = 0x3e81,\n+\tBNXT_ULP_CLASS_HID_1dad = 0x1dad,\n+\tBNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,\n+\tBNXT_ULP_CLASS_HID_25c9 = 0x25c9,\n+\tBNXT_ULP_CLASS_HID_57c1 = 0x57c1,\n+\tBNXT_ULP_CLASS_HID_33ed = 0x33ed,\n+\tBNXT_ULP_CLASS_HID_65e5 = 0x65e5,\n+\tBNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,\n+\tBNXT_ULP_CLASS_HID_261d = 0x261d,\n+\tBNXT_ULP_CLASS_HID_0571 = 0x0571,\n+\tBNXT_ULP_CLASS_HID_34f9 = 0x34f9,\n+\tBNXT_ULP_CLASS_HID_1d55 = 0x1d55,\n+\tBNXT_ULP_CLASS_HID_4fdd = 0x4fdd,\n+\tBNXT_ULP_CLASS_HID_2d31 = 0x2d31,\n+\tBNXT_ULP_CLASS_HID_5db9 = 0x5db9,\n+\tBNXT_ULP_CLASS_HID_0035 = 0x0035,\n+\tBNXT_ULP_CLASS_HID_323d = 0x323d,\n+\tBNXT_ULP_CLASS_HID_1111 = 0x1111,\n+\tBNXT_ULP_CLASS_HID_4019 = 0x4019,\n+\tBNXT_ULP_CLASS_HID_2975 = 0x2975,\n+\tBNXT_ULP_CLASS_HID_5b7d = 0x5b7d,\n+\tBNXT_ULP_CLASS_HID_3f51 = 0x3f51,\n+\tBNXT_ULP_CLASS_HID_6959 = 0x6959,\n+\tBNXT_ULP_CLASS_HID_0e85 = 0x0e85,\n+\tBNXT_ULP_CLASS_HID_380d = 0x380d,\n+\tBNXT_ULP_CLASS_HID_1f21 = 0x1f21,\n+\tBNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,\n+\tBNXT_ULP_CLASS_HID_1705 = 0x1705,\n+\tBNXT_ULP_CLASS_HID_418d = 0x418d,\n+\tBNXT_ULP_CLASS_HID_2721 = 0x2721,\n+\tBNXT_ULP_CLASS_HID_57a9 = 0x57a9,\n+\tBNXT_ULP_CLASS_HID_1a25 = 0x1a25,\n+\tBNXT_ULP_CLASS_HID_342d = 0x342d,\n+\tBNXT_ULP_CLASS_HID_2b01 = 0x2b01,\n+\tBNXT_ULP_CLASS_HID_5a09 = 0x5a09,\n+\tBNXT_ULP_CLASS_HID_2325 = 0x2325,\n+\tBNXT_ULP_CLASS_HID_5d2d = 0x5d2d,\n+\tBNXT_ULP_CLASS_HID_3101 = 0x3101,\n+\tBNXT_ULP_CLASS_HID_6309 = 0x6309,\n+\tBNXT_ULP_CLASS_HID_0bad = 0x0bad,\n+\tBNXT_ULP_CLASS_HID_2535 = 0x2535,\n+\tBNXT_ULP_CLASS_HID_1869 = 0x1869,\n+\tBNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,\n+\tBNXT_ULP_CLASS_HID_136d = 0x136d,\n+\tBNXT_ULP_CLASS_HID_43f5 = 0x43f5,\n+\tBNXT_ULP_CLASS_HID_2129 = 0x2129,\n+\tBNXT_ULP_CLASS_HID_53b1 = 0x53b1,\n+\tBNXT_ULP_CLASS_HID_072d = 0x072d,\n+\tBNXT_ULP_CLASS_HID_3135 = 0x3135,\n+\tBNXT_ULP_CLASS_HID_1429 = 0x1429,\n+\tBNXT_ULP_CLASS_HID_4731 = 0x4731,\n+\tBNXT_ULP_CLASS_HID_2f6d = 0x2f6d,\n+\tBNXT_ULP_CLASS_HID_5f75 = 0x5f75,\n+\tBNXT_ULP_CLASS_HID_3d69 = 0x3d69,\n+\tBNXT_ULP_CLASS_HID_6f71 = 0x6f71,\n+\tBNXT_ULP_CLASS_HID_0dbd = 0x0dbd,\n+\tBNXT_ULP_CLASS_HID_3f25 = 0x3f25,\n+\tBNXT_ULP_CLASS_HID_1239 = 0x1239,\n+\tBNXT_ULP_CLASS_HID_4da1 = 0x4da1,\n+\tBNXT_ULP_CLASS_HID_153d = 0x153d,\n+\tBNXT_ULP_CLASS_HID_45a5 = 0x45a5,\n+\tBNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,\n+\tBNXT_ULP_CLASS_HID_55a1 = 0x55a1,\n+\tBNXT_ULP_CLASS_HID_193d = 0x193d,\n+\tBNXT_ULP_CLASS_HID_4b25 = 0x4b25,\n+\tBNXT_ULP_CLASS_HID_2e39 = 0x2e39,\n+\tBNXT_ULP_CLASS_HID_5921 = 0x5921,\n+\tBNXT_ULP_CLASS_HID_213d = 0x213d,\n+\tBNXT_ULP_CLASS_HID_5125 = 0x5125,\n+\tBNXT_ULP_CLASS_HID_3739 = 0x3739,\n+\tBNXT_ULP_CLASS_HID_093d = 0x093d,\n+\tBNXT_ULP_CLASS_HID_684d = 0x684d,\n+\tBNXT_ULP_CLASS_HID_2389 = 0x2389,\n+\tBNXT_ULP_CLASS_HID_00e5 = 0x00e5,\n+\tBNXT_ULP_CLASS_HID_316d = 0x316d,\n+\tBNXT_ULP_CLASS_HID_18c1 = 0x18c1,\n+\tBNXT_ULP_CLASS_HID_4a49 = 0x4a49,\n+\tBNXT_ULP_CLASS_HID_28a5 = 0x28a5,\n+\tBNXT_ULP_CLASS_HID_582d = 0x582d,\n+\tBNXT_ULP_CLASS_HID_05a1 = 0x05a1,\n+\tBNXT_ULP_CLASS_HID_37a9 = 0x37a9,\n+\tBNXT_ULP_CLASS_HID_1485 = 0x1485,\n+\tBNXT_ULP_CLASS_HID_458d = 0x458d,\n+\tBNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,\n+\tBNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,\n+\tBNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,\n+\tBNXT_ULP_CLASS_HID_6ccd = 0x6ccd,\n+\tBNXT_ULP_CLASS_HID_0b11 = 0x0b11,\n+\tBNXT_ULP_CLASS_HID_3d99 = 0x3d99,\n+\tBNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,\n+\tBNXT_ULP_CLASS_HID_4b3d = 0x4b3d,\n+\tBNXT_ULP_CLASS_HID_1291 = 0x1291,\n+\tBNXT_ULP_CLASS_HID_4419 = 0x4419,\n+\tBNXT_ULP_CLASS_HID_22b5 = 0x22b5,\n+\tBNXT_ULP_CLASS_HID_523d = 0x523d,\n+\tBNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,\n+\tBNXT_ULP_CLASS_HID_31b9 = 0x31b9,\n+\tBNXT_ULP_CLASS_HID_2e95 = 0x2e95,\n+\tBNXT_ULP_CLASS_HID_5f9d = 0x5f9d,\n+\tBNXT_ULP_CLASS_HID_26b1 = 0x26b1,\n+\tBNXT_ULP_CLASS_HID_58b9 = 0x58b9,\n+\tBNXT_ULP_CLASS_HID_3495 = 0x3495,\n+\tBNXT_ULP_CLASS_HID_669d = 0x669d,\n+\tBNXT_ULP_CLASS_HID_0e39 = 0x0e39,\n+\tBNXT_ULP_CLASS_HID_20a1 = 0x20a1,\n+\tBNXT_ULP_CLASS_HID_1dfd = 0x1dfd,\n+\tBNXT_ULP_CLASS_HID_4e65 = 0x4e65,\n+\tBNXT_ULP_CLASS_HID_16f9 = 0x16f9,\n+\tBNXT_ULP_CLASS_HID_4661 = 0x4661,\n+\tBNXT_ULP_CLASS_HID_24bd = 0x24bd,\n+\tBNXT_ULP_CLASS_HID_5625 = 0x5625,\n+\tBNXT_ULP_CLASS_HID_02b9 = 0x02b9,\n+\tBNXT_ULP_CLASS_HID_34a1 = 0x34a1,\n+\tBNXT_ULP_CLASS_HID_11bd = 0x11bd,\n+\tBNXT_ULP_CLASS_HID_42a5 = 0x42a5,\n+\tBNXT_ULP_CLASS_HID_2af9 = 0x2af9,\n+\tBNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,\n+\tBNXT_ULP_CLASS_HID_38fd = 0x38fd,\n+\tBNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,\n+\tBNXT_ULP_CLASS_HID_0829 = 0x0829,\n+\tBNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,\n+\tBNXT_ULP_CLASS_HID_17ad = 0x17ad,\n+\tBNXT_ULP_CLASS_HID_4835 = 0x4835,\n+\tBNXT_ULP_CLASS_HID_10a9 = 0x10a9,\n+\tBNXT_ULP_CLASS_HID_4031 = 0x4031,\n+\tBNXT_ULP_CLASS_HID_3e2d = 0x3e2d,\n+\tBNXT_ULP_CLASS_HID_5035 = 0x5035,\n+\tBNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,\n+\tBNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,\n+\tBNXT_ULP_CLASS_HID_2bad = 0x2bad,\n+\tBNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,\n+\tBNXT_ULP_CLASS_HID_24a9 = 0x24a9,\n+\tBNXT_ULP_CLASS_HID_54b1 = 0x54b1,\n+\tBNXT_ULP_CLASS_HID_32ad = 0x32ad,\n+\tBNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,\n+\tBNXT_ULP_CLASS_HID_7f35 = 0x7f35,\n+\tBNXT_ULP_CLASS_HID_34f1 = 0x34f1,\n+\tBNXT_ULP_CLASS_HID_179d = 0x179d,\n+\tBNXT_ULP_CLASS_HID_2615 = 0x2615,\n+\tBNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,\n+\tBNXT_ULP_CLASS_HID_5d31 = 0x5d31,\n+\tBNXT_ULP_CLASS_HID_3fdd = 0x3fdd,\n+\tBNXT_ULP_CLASS_HID_4f55 = 0x4f55,\n+\tBNXT_ULP_CLASS_HID_12d9 = 0x12d9,\n+\tBNXT_ULP_CLASS_HID_20d1 = 0x20d1,\n+\tBNXT_ULP_CLASS_HID_03fd = 0x03fd,\n+\tBNXT_ULP_CLASS_HID_52f5 = 0x52f5,\n+\tBNXT_ULP_CLASS_HID_3b99 = 0x3b99,\n+\tBNXT_ULP_CLASS_HID_4991 = 0x4991,\n+\tBNXT_ULP_CLASS_HID_2dbd = 0x2dbd,\n+\tBNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,\n \tBNXT_ULP_CLASS_HID_34c6 = 0x34c6,\n \tBNXT_ULP_CLASS_HID_0c22 = 0x0c22,\n \tBNXT_ULP_CLASS_HID_1cbe = 0x1cbe,\n@@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid {\n };\n \n enum bnxt_ulp_df_tpl {\n-\tBNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3,\n-\tBNXT_ULP_DF_TPL_DEFAULT_VFR = 4\n+\tBNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4,\n+\tBNXT_ULP_DF_TPL_DEFAULT_VFR = 5\n };\n \n #endif\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h\nindex 115bdc644c..1d7bbfe2cc 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Wed Mar 17 11:31:19 2021 */\n+/* date: Thu May 20 11:56:39 2021 */\n \n #ifndef ULP_HDR_FIELD_ENUMS_H_\n #define ULP_HDR_FIELD_ENUMS_H_\n@@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask {\n \tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n \tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n \tBNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER          = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC           = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL   = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID     = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR     = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR     = 0x0008000000000000\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER          = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS          = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID      = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF     = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM         = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR     = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR     = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT      = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT      = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH        = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM          = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0       = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI         = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1       = 0x0000020000000000\n };\n \n enum bnxt_ulp_hf_0_2_1_bitmask {\n \tBNXT_ULP_HF_0_2_1_BITMASK_WM                  = 0x8000000000000000,\n \tBNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER          = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS          = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN          = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID      = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF     = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM         = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR     = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR     = 0x0002000000000000\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID      = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF     = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR     = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT      = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH        = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM          = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS       = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0       = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI         = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000\n };\n \n enum bnxt_ulp_hf_0_2_2_bitmask {\n \tBNXT_ULP_HF_0_2_2_BITMASK_WM                  = 0x8000000000000000,\n \tBNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER          = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC           = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL   = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID     = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL          = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR     = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR     = 0x0001000000000000\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID      = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF     = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR     = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT      = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH        = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM          = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS       = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0       = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI         = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT      = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT      = 0x0000000020000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ      = 0x0000000010000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK      = 0x0000000008000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF      = 0x0000000004000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS     = 0x0000000002000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN        = 0x0000000001000000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM          = 0x0000000000800000,\n+\tBNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP           = 0x0000000000400000\n };\n \n enum bnxt_ulp_hf_0_2_3_bitmask {\n \tBNXT_ULP_HF_0_2_3_BITMASK_WM                  = 0x8000000000000000,\n \tBNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER          = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS          = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID      = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF     = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL          = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID     = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM         = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR     = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR     = 0x0000400000000000\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID      = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF     = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR     = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT      = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH        = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM          = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS       = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0       = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI         = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT      = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT      = 0x0000000020000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH        = 0x0000000010000000,\n+\tBNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM          = 0x0000000008000000\n };\n \n enum bnxt_ulp_hf_0_2_4_bitmask {\n \tBNXT_ULP_HF_0_2_4_BITMASK_WM                  = 0x8000000000000000,\n \tBNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER          = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC           = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL   = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID     = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR     = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR     = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT      = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT      = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ      = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK      = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF      = 0x0000400000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS     = 0x0000200000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN        = 0x0000100000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM          = 0x0000080000000000,\n-\tBNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP           = 0x0000040000000000\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID      = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF     = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR     = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT      = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH        = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM          = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS       = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0       = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI         = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1       = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC          = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS          = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN          = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID      = 0x0000002000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF     = 0x0000001000000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL          = 0x0000000800000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID     = 0x0000000400000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM         = 0x0000000200000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR     = 0x0000000100000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR     = 0x0000000080000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE         = 0x0000000040000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE         = 0x0000000020000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM         = 0x0000000010000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT        = 0x0000000008000000,\n+\tBNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM      = 0x0000000004000000\n };\n \n-enum bnxt_ulp_hf_0_2_5_bitmask {\n-\tBNXT_ULP_HF_0_2_5_BITMASK_WM                  = 0x8000000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER          = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS          = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN          = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID      = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF     = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM         = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR     = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR     = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT      = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT      = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ      = 0x0000400000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK      = 0x0000200000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF      = 0x0000100000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS     = 0x0000080000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN        = 0x0000040000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM          = 0x0000020000000000,\n-\tBNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP           = 0x0000010000000000\n+enum bnxt_ulp_hf_0_3_0_bitmask {\n+\tBNXT_ULP_HF_0_3_0_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER          = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC           = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL   = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID     = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR     = 0x0008000000000000\n };\n \n-enum bnxt_ulp_hf_0_2_6_bitmask {\n-\tBNXT_ULP_HF_0_2_6_BITMASK_WM                  = 0x8000000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER          = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC           = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL   = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID     = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR     = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR     = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT      = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT      = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH        = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM          = 0x0000800000000000\n+enum bnxt_ulp_hf_0_3_1_bitmask {\n+\tBNXT_ULP_HF_0_3_1_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER          = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS          = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID      = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF     = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM         = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR     = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR     = 0x0002000000000000\n };\n \n-enum bnxt_ulp_hf_0_2_7_bitmask {\n-\tBNXT_ULP_HF_0_2_7_BITMASK_WM                  = 0x8000000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER          = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS          = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN          = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID      = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF     = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM         = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR     = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR     = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT      = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT      = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH        = 0x0000400000000000,\n-\tBNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM          = 0x0000200000000000\n+enum bnxt_ulp_hf_0_3_2_bitmask {\n+\tBNXT_ULP_HF_0_3_2_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER          = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC           = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL   = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID     = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL          = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR     = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR     = 0x0001000000000000\n };\n \n-enum bnxt_ulp_hf_0_2_8_bitmask {\n-\tBNXT_ULP_HF_0_2_8_BITMASK_WM                  = 0x8000000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER          = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC           = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL   = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID     = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL          = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR     = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR     = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT      = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT      = 0x0000400000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ      = 0x0000200000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK      = 0x0000100000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF      = 0x0000080000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS     = 0x0000040000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN        = 0x0000020000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM          = 0x0000010000000000,\n-\tBNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP           = 0x0000008000000000\n+enum bnxt_ulp_hf_0_3_3_bitmask {\n+\tBNXT_ULP_HF_0_3_3_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER          = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS          = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID      = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF     = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL          = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID     = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM         = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR     = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR     = 0x0000400000000000\n };\n \n-enum bnxt_ulp_hf_0_2_9_bitmask {\n-\tBNXT_ULP_HF_0_2_9_BITMASK_WM                  = 0x8000000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER          = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS          = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN          = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID      = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF     = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL          = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID     = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM         = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR     = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR     = 0x0000400000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT      = 0x0000200000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT      = 0x0000100000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ      = 0x0000080000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK      = 0x0000040000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF      = 0x0000020000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS     = 0x0000010000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN        = 0x0000008000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM          = 0x0000004000000000,\n-\tBNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP           = 0x0000002000000000\n+enum bnxt_ulp_hf_0_3_4_bitmask {\n+\tBNXT_ULP_HF_0_3_4_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER          = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC           = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL   = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID     = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR     = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT      = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ      = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK      = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF      = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS     = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN        = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM          = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP           = 0x0000040000000000\n };\n \n-enum bnxt_ulp_hf_0_2_10_bitmask {\n-\tBNXT_ULP_HF_0_2_10_BITMASK_WM                 = 0x8000000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,\n-\tBNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM         = 0x0000100000000000\n+enum bnxt_ulp_hf_0_3_5_bitmask {\n+\tBNXT_ULP_HF_0_3_5_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER          = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS          = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID      = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF     = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM         = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR     = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR     = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT      = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT      = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ      = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK      = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF      = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS     = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN        = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM          = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP           = 0x0000010000000000\n };\n \n-enum bnxt_ulp_hf_0_2_11_bitmask {\n-\tBNXT_ULP_HF_0_2_11_BITMASK_WM                 = 0x8000000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n-\tBNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n+enum bnxt_ulp_hf_0_3_6_bitmask {\n+\tBNXT_ULP_HF_0_3_6_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER          = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC           = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL   = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID     = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR     = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT      = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT      = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH        = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM          = 0x0000800000000000\n+};\n+\n+enum bnxt_ulp_hf_0_3_7_bitmask {\n+\tBNXT_ULP_HF_0_3_7_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER          = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS          = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN          = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID      = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF     = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM         = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR     = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR     = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT      = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT      = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH        = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM          = 0x0000200000000000\n+};\n+\n+enum bnxt_ulp_hf_0_3_8_bitmask {\n+\tBNXT_ULP_HF_0_3_8_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER          = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC           = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL   = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN  = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID     = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL          = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR     = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR     = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT      = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT      = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ      = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK      = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF      = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS     = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN        = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM          = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP           = 0x0000008000000000\n+};\n+\n+enum bnxt_ulp_hf_0_3_9_bitmask {\n+\tBNXT_ULP_HF_0_3_9_BITMASK_WM                  = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX          = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC          = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC          = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE          = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI     = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID         = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE        = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER          = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS          = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN          = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID      = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF     = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL          = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID     = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM         = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR     = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR     = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT      = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT      = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ      = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK      = 0x0000040000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF      = 0x0000020000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS     = 0x0000010000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN        = 0x0000008000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM          = 0x0000004000000000,\n+\tBNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP           = 0x0000002000000000\n+};\n+\n+enum bnxt_ulp_hf_0_3_10_bitmask {\n+\tBNXT_ULP_HF_0_3_10_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM         = 0x0000100000000000\n+};\n+\n+enum bnxt_ulp_hf_0_3_11_bitmask {\n+\tBNXT_ULP_HF_0_3_11_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n+\tBNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n };\n \n #endif\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c\nindex 2debaea0ca..58b4dba63c 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu May 13 18:15:56 2021 */\n+/* date: Thu May 20 11:56:39 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {\n \t.num_buckets             = 0,\n \t.hash_tbl_entries        = 0,\n \t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |\n+\t\tBNXT_ULP_DIRECTION_INGRESS] = {\n+\t.name                    = \"INGRESS GENERIC_TABLE_TUNNEL_CACHE\",\n+\t.result_num_entries      = 256,\n+\t.result_num_bytes        = 7,\n+\t.key_num_bytes           = 2,\n+\t.num_buckets             = 8,\n+\t.hash_tbl_entries        = 1024,\n+\t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |\n+\t\tBNXT_ULP_DIRECTION_EGRESS] = {\n+\t.name                    = \"EGRESS GENERIC_TABLE_TUNNEL_CACHE\",\n+\t.result_num_entries      = 256,\n+\t.result_num_bytes        = 7,\n+\t.key_num_bytes           = 2,\n+\t.num_buckets             = 8,\n+\t.hash_tbl_entries        = 1024,\n+\t.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE\n \t}\n };\n \n@@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[4098] = 2,\n \t[4100] = 3,\n \t[4102] = 4,\n-\t[4136] = 5,\n-\t[4138] = 6,\n-\t[4140] = 7,\n-\t[4142] = 8,\n-\t[4144] = 9,\n-\t[4146] = 10,\n-\t[4148] = 11,\n-\t[4150] = 12,\n+\t[4116] = 5,\n+\t[4118] = 6,\n+\t[4120] = 7,\n+\t[4122] = 8,\n+\t[4124] = 9,\n+\t[4126] = 10,\n+\t[4128] = 11,\n+\t[4130] = 12,\n+\t[4132] = 13,\n+\t[4134] = 14,\n+\t[4170] = 15,\n+\t[4172] = 16,\n+\t[4174] = 17,\n+\t[4176] = 18,\n+\t[4190] = 19,\n+\t[4191] = 20,\n+\t[4192] = 21,\n+\t[4193] = 22,\n \t[4224] = 0,\n \t[4225] = 1,\n-\t[4226] = 2,\n-\t[4228] = 3,\n-\t[4230] = 4,\n-\t[4244] = 5,\n-\t[4246] = 6,\n-\t[4248] = 7,\n-\t[4250] = 8,\n-\t[4252] = 9,\n-\t[4254] = 10,\n-\t[4256] = 11,\n-\t[4258] = 12,\n-\t[4260] = 13,\n-\t[4262] = 14,\n+\t[4227] = 20,\n+\t[4229] = 21,\n+\t[4231] = 22,\n+\t[4244] = 2,\n+\t[4245] = 23,\n+\t[4246] = 3,\n+\t[4247] = 24,\n+\t[4248] = 4,\n+\t[4249] = 25,\n+\t[4250] = 5,\n+\t[4251] = 26,\n+\t[4252] = 6,\n+\t[4253] = 27,\n+\t[4254] = 7,\n+\t[4255] = 28,\n+\t[4256] = 8,\n+\t[4257] = 29,\n+\t[4258] = 9,\n+\t[4259] = 30,\n+\t[4260] = 10,\n+\t[4261] = 31,\n+\t[4262] = 11,\n+\t[4263] = 32,\n+\t[4298] = 12,\n+\t[4300] = 13,\n+\t[4302] = 14,\n+\t[4304] = 15,\n+\t[4318] = 16,\n+\t[4319] = 17,\n+\t[4320] = 18,\n+\t[4321] = 19,\n \t[4352] = 0,\n \t[4353] = 1,\n-\t[4354] = 2,\n-\t[4356] = 3,\n-\t[4358] = 4,\n-\t[4392] = 8,\n-\t[4394] = 9,\n-\t[4396] = 10,\n-\t[4398] = 11,\n-\t[4400] = 12,\n-\t[4402] = 13,\n-\t[4404] = 14,\n-\t[4406] = 15,\n-\t[4434] = 5,\n-\t[4438] = 6,\n-\t[4442] = 7,\n+\t[4355] = 20,\n+\t[4357] = 21,\n+\t[4359] = 22,\n+\t[4372] = 2,\n+\t[4373] = 23,\n+\t[4374] = 3,\n+\t[4375] = 24,\n+\t[4376] = 4,\n+\t[4377] = 25,\n+\t[4378] = 5,\n+\t[4379] = 26,\n+\t[4380] = 6,\n+\t[4381] = 27,\n+\t[4382] = 7,\n+\t[4383] = 28,\n+\t[4384] = 8,\n+\t[4385] = 29,\n+\t[4386] = 9,\n+\t[4387] = 30,\n+\t[4388] = 10,\n+\t[4389] = 31,\n+\t[4390] = 11,\n+\t[4391] = 32,\n+\t[4409] = 33,\n+\t[4411] = 34,\n+\t[4413] = 35,\n+\t[4415] = 36,\n+\t[4417] = 37,\n+\t[4419] = 38,\n+\t[4421] = 39,\n+\t[4423] = 40,\n+\t[4425] = 41,\n+\t[4426] = 12,\n+\t[4428] = 13,\n+\t[4430] = 14,\n+\t[4432] = 15,\n+\t[4446] = 16,\n+\t[4447] = 17,\n+\t[4448] = 18,\n+\t[4449] = 19,\n \t[4480] = 0,\n \t[4481] = 1,\n-\t[4482] = 2,\n-\t[4484] = 3,\n-\t[4486] = 4,\n-\t[4500] = 8,\n-\t[4502] = 9,\n-\t[4504] = 10,\n-\t[4506] = 11,\n-\t[4508] = 12,\n-\t[4510] = 13,\n-\t[4512] = 14,\n-\t[4514] = 15,\n-\t[4516] = 16,\n-\t[4518] = 17,\n-\t[4562] = 5,\n-\t[4566] = 6,\n-\t[4570] = 7,\n+\t[4483] = 20,\n+\t[4485] = 21,\n+\t[4487] = 22,\n+\t[4500] = 2,\n+\t[4501] = 23,\n+\t[4502] = 3,\n+\t[4503] = 24,\n+\t[4504] = 4,\n+\t[4505] = 25,\n+\t[4506] = 5,\n+\t[4507] = 26,\n+\t[4508] = 6,\n+\t[4509] = 27,\n+\t[4510] = 7,\n+\t[4511] = 28,\n+\t[4512] = 8,\n+\t[4513] = 29,\n+\t[4514] = 9,\n+\t[4515] = 30,\n+\t[4516] = 10,\n+\t[4517] = 31,\n+\t[4518] = 11,\n+\t[4519] = 32,\n+\t[4554] = 12,\n+\t[4555] = 33,\n+\t[4556] = 13,\n+\t[4557] = 34,\n+\t[4558] = 14,\n+\t[4559] = 35,\n+\t[4560] = 15,\n+\t[4561] = 36,\n+\t[4574] = 16,\n+\t[4575] = 17,\n+\t[4576] = 18,\n+\t[4577] = 19,\n \t[4608] = 0,\n \t[4609] = 1,\n-\t[4610] = 2,\n-\t[4612] = 3,\n-\t[4614] = 4,\n-\t[4648] = 5,\n-\t[4650] = 6,\n-\t[4652] = 7,\n-\t[4654] = 8,\n-\t[4656] = 9,\n-\t[4658] = 10,\n-\t[4660] = 11,\n-\t[4662] = 12,\n-\t[4664] = 13,\n-\t[4666] = 14,\n-\t[4668] = 15,\n-\t[4670] = 16,\n-\t[4672] = 17,\n-\t[4674] = 18,\n-\t[4676] = 19,\n-\t[4678] = 20,\n-\t[4680] = 21,\n-\t[4736] = 0,\n-\t[4737] = 1,\n-\t[4738] = 2,\n-\t[4740] = 3,\n-\t[4742] = 4,\n-\t[4756] = 5,\n-\t[4758] = 6,\n-\t[4760] = 7,\n-\t[4762] = 8,\n-\t[4764] = 9,\n-\t[4766] = 10,\n-\t[4768] = 11,\n-\t[4770] = 12,\n-\t[4772] = 13,\n-\t[4774] = 14,\n-\t[4792] = 15,\n-\t[4794] = 16,\n-\t[4796] = 17,\n-\t[4798] = 18,\n-\t[4800] = 19,\n-\t[4802] = 20,\n-\t[4804] = 21,\n-\t[4806] = 22,\n-\t[4808] = 23,\n-\t[4864] = 0,\n-\t[4865] = 1,\n-\t[4866] = 2,\n-\t[4868] = 3,\n-\t[4870] = 4,\n-\t[4904] = 5,\n-\t[4906] = 6,\n-\t[4908] = 7,\n-\t[4910] = 8,\n-\t[4912] = 9,\n-\t[4914] = 10,\n-\t[4916] = 11,\n-\t[4918] = 12,\n-\t[4938] = 13,\n-\t[4940] = 14,\n-\t[4942] = 15,\n-\t[4944] = 16,\n-\t[4992] = 0,\n-\t[4993] = 1,\n-\t[4994] = 2,\n-\t[4996] = 3,\n-\t[4998] = 4,\n-\t[5012] = 5,\n-\t[5014] = 6,\n-\t[5016] = 7,\n-\t[5018] = 8,\n-\t[5020] = 9,\n-\t[5022] = 10,\n-\t[5024] = 11,\n-\t[5026] = 12,\n-\t[5028] = 13,\n-\t[5030] = 14,\n-\t[5066] = 15,\n-\t[5068] = 16,\n-\t[5070] = 17,\n-\t[5072] = 18,\n-\t[5120] = 0,\n-\t[5121] = 1,\n-\t[5122] = 2,\n-\t[5124] = 3,\n-\t[5126] = 4,\n-\t[5160] = 8,\n-\t[5162] = 9,\n-\t[5164] = 10,\n-\t[5166] = 11,\n-\t[5168] = 12,\n-\t[5170] = 13,\n-\t[5172] = 14,\n-\t[5174] = 15,\n-\t[5176] = 16,\n-\t[5178] = 17,\n-\t[5180] = 18,\n-\t[5182] = 19,\n-\t[5184] = 20,\n-\t[5186] = 21,\n-\t[5188] = 22,\n-\t[5190] = 23,\n-\t[5192] = 24,\n-\t[5202] = 5,\n-\t[5206] = 6,\n-\t[5210] = 7,\n-\t[5248] = 0,\n-\t[5249] = 1,\n-\t[5250] = 2,\n-\t[5252] = 3,\n-\t[5254] = 4,\n-\t[5268] = 8,\n-\t[5270] = 9,\n-\t[5272] = 10,\n-\t[5274] = 11,\n-\t[5276] = 12,\n-\t[5278] = 13,\n-\t[5280] = 14,\n-\t[5282] = 15,\n-\t[5284] = 16,\n-\t[5286] = 17,\n-\t[5304] = 18,\n-\t[5306] = 19,\n-\t[5308] = 20,\n-\t[5310] = 21,\n-\t[5312] = 22,\n-\t[5314] = 23,\n-\t[5316] = 24,\n-\t[5318] = 25,\n-\t[5320] = 26,\n-\t[5330] = 5,\n-\t[5334] = 6,\n-\t[5338] = 7,\n-\t[5376] = 0,\n-\t[5377] = 1,\n-\t[5378] = 2,\n-\t[5380] = 3,\n-\t[5382] = 4,\n-\t[5416] = 8,\n-\t[5418] = 9,\n-\t[5420] = 10,\n-\t[5422] = 11,\n-\t[5424] = 12,\n-\t[5426] = 13,\n-\t[5428] = 14,\n-\t[5430] = 15,\n-\t[5450] = 16,\n-\t[5452] = 17,\n-\t[5454] = 18,\n-\t[5456] = 19,\n-\t[5458] = 5,\n-\t[5462] = 6,\n-\t[5466] = 7,\n-\t[5504] = 0,\n-\t[5505] = 1,\n-\t[5506] = 2,\n-\t[5508] = 3,\n-\t[5510] = 4,\n-\t[5524] = 8,\n-\t[5526] = 9,\n-\t[5528] = 10,\n-\t[5530] = 11,\n-\t[5532] = 12,\n-\t[5534] = 13,\n-\t[5536] = 14,\n-\t[5538] = 15,\n-\t[5540] = 16,\n-\t[5542] = 17,\n-\t[5578] = 18,\n-\t[5580] = 19,\n-\t[5582] = 20,\n-\t[5584] = 21,\n-\t[5586] = 5,\n-\t[5590] = 6,\n-\t[5594] = 7\n+\t[4611] = 20,\n+\t[4613] = 21,\n+\t[4615] = 22,\n+\t[4619] = 33,\n+\t[4621] = 34,\n+\t[4623] = 35,\n+\t[4625] = 36,\n+\t[4627] = 37,\n+\t[4628] = 2,\n+\t[4629] = 23,\n+\t[4630] = 3,\n+\t[4631] = 24,\n+\t[4632] = 4,\n+\t[4633] = 25,\n+\t[4634] = 5,\n+\t[4635] = 26,\n+\t[4636] = 6,\n+\t[4637] = 27,\n+\t[4638] = 7,\n+\t[4639] = 28,\n+\t[4640] = 8,\n+\t[4641] = 29,\n+\t[4642] = 9,\n+\t[4643] = 30,\n+\t[4644] = 10,\n+\t[4645] = 31,\n+\t[4646] = 11,\n+\t[4647] = 32,\n+\t[4682] = 12,\n+\t[4684] = 13,\n+\t[4686] = 14,\n+\t[4688] = 15,\n+\t[4702] = 16,\n+\t[4703] = 17,\n+\t[4704] = 18,\n+\t[4705] = 19,\n+\t[6144] = 0,\n+\t[6145] = 1,\n+\t[6146] = 2,\n+\t[6148] = 3,\n+\t[6150] = 4,\n+\t[6184] = 5,\n+\t[6186] = 6,\n+\t[6188] = 7,\n+\t[6190] = 8,\n+\t[6192] = 9,\n+\t[6194] = 10,\n+\t[6196] = 11,\n+\t[6198] = 12,\n+\t[6272] = 0,\n+\t[6273] = 1,\n+\t[6274] = 2,\n+\t[6276] = 3,\n+\t[6278] = 4,\n+\t[6292] = 5,\n+\t[6294] = 6,\n+\t[6296] = 7,\n+\t[6298] = 8,\n+\t[6300] = 9,\n+\t[6302] = 10,\n+\t[6304] = 11,\n+\t[6306] = 12,\n+\t[6308] = 13,\n+\t[6310] = 14,\n+\t[6400] = 0,\n+\t[6401] = 1,\n+\t[6402] = 2,\n+\t[6404] = 3,\n+\t[6406] = 4,\n+\t[6440] = 8,\n+\t[6442] = 9,\n+\t[6444] = 10,\n+\t[6446] = 11,\n+\t[6448] = 12,\n+\t[6450] = 13,\n+\t[6452] = 14,\n+\t[6454] = 15,\n+\t[6482] = 5,\n+\t[6486] = 6,\n+\t[6490] = 7,\n+\t[6528] = 0,\n+\t[6529] = 1,\n+\t[6530] = 2,\n+\t[6532] = 3,\n+\t[6534] = 4,\n+\t[6548] = 8,\n+\t[6550] = 9,\n+\t[6552] = 10,\n+\t[6554] = 11,\n+\t[6556] = 12,\n+\t[6558] = 13,\n+\t[6560] = 14,\n+\t[6562] = 15,\n+\t[6564] = 16,\n+\t[6566] = 17,\n+\t[6610] = 5,\n+\t[6614] = 6,\n+\t[6618] = 7,\n+\t[6656] = 0,\n+\t[6657] = 1,\n+\t[6658] = 2,\n+\t[6660] = 3,\n+\t[6662] = 4,\n+\t[6696] = 5,\n+\t[6698] = 6,\n+\t[6700] = 7,\n+\t[6702] = 8,\n+\t[6704] = 9,\n+\t[6706] = 10,\n+\t[6708] = 11,\n+\t[6710] = 12,\n+\t[6712] = 13,\n+\t[6714] = 14,\n+\t[6716] = 15,\n+\t[6718] = 16,\n+\t[6720] = 17,\n+\t[6722] = 18,\n+\t[6724] = 19,\n+\t[6726] = 20,\n+\t[6728] = 21,\n+\t[6784] = 0,\n+\t[6785] = 1,\n+\t[6786] = 2,\n+\t[6788] = 3,\n+\t[6790] = 4,\n+\t[6804] = 5,\n+\t[6806] = 6,\n+\t[6808] = 7,\n+\t[6810] = 8,\n+\t[6812] = 9,\n+\t[6814] = 10,\n+\t[6816] = 11,\n+\t[6818] = 12,\n+\t[6820] = 13,\n+\t[6822] = 14,\n+\t[6840] = 15,\n+\t[6842] = 16,\n+\t[6844] = 17,\n+\t[6846] = 18,\n+\t[6848] = 19,\n+\t[6850] = 20,\n+\t[6852] = 21,\n+\t[6854] = 22,\n+\t[6856] = 23,\n+\t[6912] = 0,\n+\t[6913] = 1,\n+\t[6914] = 2,\n+\t[6916] = 3,\n+\t[6918] = 4,\n+\t[6952] = 5,\n+\t[6954] = 6,\n+\t[6956] = 7,\n+\t[6958] = 8,\n+\t[6960] = 9,\n+\t[6962] = 10,\n+\t[6964] = 11,\n+\t[6966] = 12,\n+\t[6986] = 13,\n+\t[6988] = 14,\n+\t[6990] = 15,\n+\t[6992] = 16,\n+\t[7040] = 0,\n+\t[7041] = 1,\n+\t[7042] = 2,\n+\t[7044] = 3,\n+\t[7046] = 4,\n+\t[7060] = 5,\n+\t[7062] = 6,\n+\t[7064] = 7,\n+\t[7066] = 8,\n+\t[7068] = 9,\n+\t[7070] = 10,\n+\t[7072] = 11,\n+\t[7074] = 12,\n+\t[7076] = 13,\n+\t[7078] = 14,\n+\t[7114] = 15,\n+\t[7116] = 16,\n+\t[7118] = 17,\n+\t[7120] = 18,\n+\t[7168] = 0,\n+\t[7169] = 1,\n+\t[7170] = 2,\n+\t[7172] = 3,\n+\t[7174] = 4,\n+\t[7208] = 8,\n+\t[7210] = 9,\n+\t[7212] = 10,\n+\t[7214] = 11,\n+\t[7216] = 12,\n+\t[7218] = 13,\n+\t[7220] = 14,\n+\t[7222] = 15,\n+\t[7224] = 16,\n+\t[7226] = 17,\n+\t[7228] = 18,\n+\t[7230] = 19,\n+\t[7232] = 20,\n+\t[7234] = 21,\n+\t[7236] = 22,\n+\t[7238] = 23,\n+\t[7240] = 24,\n+\t[7250] = 5,\n+\t[7254] = 6,\n+\t[7258] = 7,\n+\t[7296] = 0,\n+\t[7297] = 1,\n+\t[7298] = 2,\n+\t[7300] = 3,\n+\t[7302] = 4,\n+\t[7316] = 8,\n+\t[7318] = 9,\n+\t[7320] = 10,\n+\t[7322] = 11,\n+\t[7324] = 12,\n+\t[7326] = 13,\n+\t[7328] = 14,\n+\t[7330] = 15,\n+\t[7332] = 16,\n+\t[7334] = 17,\n+\t[7352] = 18,\n+\t[7354] = 19,\n+\t[7356] = 20,\n+\t[7358] = 21,\n+\t[7360] = 22,\n+\t[7362] = 23,\n+\t[7364] = 24,\n+\t[7366] = 25,\n+\t[7368] = 26,\n+\t[7378] = 5,\n+\t[7382] = 6,\n+\t[7386] = 7,\n+\t[7424] = 0,\n+\t[7425] = 1,\n+\t[7426] = 2,\n+\t[7428] = 3,\n+\t[7430] = 4,\n+\t[7464] = 8,\n+\t[7466] = 9,\n+\t[7468] = 10,\n+\t[7470] = 11,\n+\t[7472] = 12,\n+\t[7474] = 13,\n+\t[7476] = 14,\n+\t[7478] = 15,\n+\t[7498] = 16,\n+\t[7500] = 17,\n+\t[7502] = 18,\n+\t[7504] = 19,\n+\t[7506] = 5,\n+\t[7510] = 6,\n+\t[7514] = 7,\n+\t[7552] = 0,\n+\t[7553] = 1,\n+\t[7554] = 2,\n+\t[7556] = 3,\n+\t[7558] = 4,\n+\t[7572] = 8,\n+\t[7574] = 9,\n+\t[7576] = 10,\n+\t[7578] = 11,\n+\t[7580] = 12,\n+\t[7582] = 13,\n+\t[7584] = 14,\n+\t[7586] = 15,\n+\t[7588] = 16,\n+\t[7590] = 17,\n+\t[7626] = 18,\n+\t[7628] = 19,\n+\t[7630] = 20,\n+\t[7632] = 21,\n+\t[7634] = 5,\n+\t[7638] = 6,\n+\t[7642] = 7\n };\n \ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c\nindex e342f340d9..d20c4197fa 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu May 13 18:15:56 2021 */\n+/* date: Thu May 20 11:56:39 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {\n \t\t.cond_start_idx = 0,\n \t\t.cond_nums = 4 }\n \t},\n-\t/* class_tid: 3, ingress */\n-\t[3] = {\n+\t/* class_tid: 4, ingress */\n+\t[4] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n \t.num_tbls = 15,\n \t.start_tbl_idx = 12,\n@@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {\n \t\t.cond_start_idx = 8,\n \t\t.cond_nums = 1 }\n \t},\n-\t/* class_tid: 4, egress */\n-\t[4] = {\n+\t/* class_tid: 5, egress */\n+\t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_THOR,\n \t.num_tbls = 6,\n \t.start_tbl_idx = 27,\n@@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 38,\n \t.result_num_fields = 5\n \t},\n-\t{ /* class_tid: 3, , table: int_full_act_record.0 */\n+\t{ /* class_tid: 4, , table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n@@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 128,\n \t.result_num_fields = 17\n \t},\n-\t{ /* class_tid: 3, , table: port_table.wr_0 */\n+\t{ /* class_tid: 4, , table: port_table.wr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,\n@@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 152,\n \t.result_num_fields = 5\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n@@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.ident_start_idx = 6,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 3, , table: control.ing_0 */\n+\t{ /* class_tid: 4, , table: control.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n@@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_RX,\n@@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.ident_start_idx = 6,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n@@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */\n+\t{ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n@@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */\n+\t{ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n@@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 3, , table: control.egr_0 */\n+\t{ /* class_tid: 4, , table: control.egr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n@@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 3, , table: int_full_act_record.egr_0 */\n+\t{ /* class_tid: 4, , table: int_full_act_record.egr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n@@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_num_fields = 17,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n@@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.ident_start_idx = 7,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 3, , table: control.egr_1 */\n+\t{ /* class_tid: 4, , table: control.egr_1 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n@@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n@@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.ident_start_idx = 7,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */\n+\t{ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n@@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */\n+\t{ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n@@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 4, , table: int_full_act_record.loopback */\n+\t{ /* class_tid: 5, , table: int_full_act_record.loopback */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n@@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_num_fields = 17,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */\n+\t{ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n@@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */\n+\t{ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n@@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 4, , table: int_full_act_record.vf_ing */\n+\t{ /* class_tid: 5, , table: int_full_act_record.vf_ing */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n@@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_num_fields = 17,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */\n+\t{ /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n \t.resource_sub_type =\n@@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {\n \t.result_num_fields = 0,\n \t.encap_num_fields = 11\n \t},\n-\t{ /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */\n+\t{ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n@@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_O_L4\n \t},\n-\t/* cond_reject: thor, class_tid: 3 */\n+\t/* cond_reject: thor, class_tid: 4 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n-\t/* cond_execute: class_tid: 3, control.ing_0 */\n+\t/* cond_execute: class_tid: 4, control.ing_0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 3, control.egr_0 */\n+\t/* cond_execute: class_tid: 4, control.egr_0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n-\t/* cond_execute: class_tid: 3, control.egr_1 */\n+\t/* cond_execute: class_tid: 4, control.egr_1 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_reject: thor, class_tid: 4 */\n+\t/* cond_reject: thor, class_tid: 5 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n@@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SKIP\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: port_table.wr_0 */\n+\t/* class_tid: 4, , table: port_table.wr_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"dev.port_id\",\n@@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n@@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"etype\",\n@@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n@@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n@@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {\n \t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"etype\",\n@@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 3, , table: int_full_act_record.0 */\n+\t/* class_tid: 4, , table: int_full_act_record.0 */\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n@@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 3, , table: port_table.wr_0 */\n+\t/* class_tid: 4, , table: port_table.wr_0 */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n@@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n \tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */\n+\t/* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */\n+\t/* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: int_full_act_record.egr_0 */\n+\t/* class_tid: 4, , table: int_full_act_record.egr_0 */\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n@@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n@@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n \tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n-\t/* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */\n+\t/* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */\n+\t/* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, , table: int_full_act_record.loopback */\n+\t/* class_tid: 5, , table: int_full_act_record.loopback */\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n@@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */\n+\t/* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */\n+\t/* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, , table: int_full_act_record.vf_ing */\n+\t/* class_tid: 5, , table: int_full_act_record.vf_ing */\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n@@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */\n+\t/* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n@@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {\n \t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,\n \tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}\n \t},\n-\t/* class_tid: 4, , table: int_full_act_record.vfr_egr0 */\n+\t/* class_tid: 5, , table: int_full_act_record.vfr_egr0 */\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n@@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 29\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 29\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c\nindex b6d2afd55b..de924fe81a 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Thu May 13 18:15:56 2021 */\n+/* date: Mon May 17 15:54:03 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\ndiff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c\nindex 85b8950e49..7b6ee03a4b 100644\n--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c\n+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Fri May 14 10:26:31 2021 */\n+/* date: Mon May 17 15:54:03 2021 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t\t.cond_start_idx = 0,\n \t\t.cond_nums = 1 }\n \t},\n-\t/* class_tid: 2, egress */\n+\t/* class_tid: 2, ingress */\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 15,\n@@ -32,24 +32,34 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t\t.cond_start_idx = 24,\n \t\t.cond_nums = 1 }\n \t},\n-\t/* class_tid: 3, ingress */\n+\t/* class_tid: 3, egress */\n \t[3] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 22,\n+\t.num_tbls = 15,\n \t.start_tbl_idx = 33,\n+\t.reject_info = {\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 30,\n+\t\t.cond_nums = 1 }\n+\t},\n+\t/* class_tid: 4, ingress */\n+\t[4] = {\n+\t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.num_tbls = 22,\n+\t.start_tbl_idx = 48,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 35,\n+\t\t.cond_start_idx = 41,\n \t\t.cond_nums = 0 }\n \t},\n-\t/* class_tid: 4, egress */\n-\t[4] = {\n+\t/* class_tid: 5, egress */\n+\t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 19,\n-\t.start_tbl_idx = 55,\n+\t.start_tbl_idx = 70,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 41,\n+\t\t.cond_start_idx = 47,\n \t\t.cond_nums = 0 }\n \t}\n };\n@@ -455,58 +465,133 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.result_bit_size = 64,\n \t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */\n+\t{ /* class_tid: 2, , table: tunnel_cache.rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 5,\n+\t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 25,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n \t.key_start_idx = 223,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n+\t.blob_key_bit_size = 16,\n+\t.key_bit_size = 16,\n+\t.key_num_fields = 2,\n \t.ident_start_idx = 9,\n \t.ident_nums = 1\n \t},\n+\t{ /* class_tid: 2, , table: control.tunnel_cache_check */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 25,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t{ /* class_tid: 2, , table: l2_cntxt_tcam.1 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 26,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 225,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 127,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 10,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* class_tid: 2, , table: tunnel_cache.wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 26,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 238,\n+\t.blob_key_bit_size = 16,\n+\t.key_bit_size = 16,\n+\t.key_num_fields = 2,\n+\t.result_start_idx = 140,\n+\t.result_bit_size = 52,\n+\t.result_num_fields = 3\n+\t},\n+\t{ /* class_tid: 2, , table: control.flow_type_check */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 5,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 26,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n \t{ /* class_tid: 2, , table: mac_addr_cache.rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 26,\n+\t\t.cond_start_idx = 27,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 224,\n+\t.key_start_idx = 240,\n \t.blob_key_bit_size = 73,\n \t.key_bit_size = 73,\n \t.key_num_fields = 5,\n-\t.ident_start_idx = 10,\n+\t.ident_start_idx = 11,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 2, , table: control.0 */\n+\t{ /* class_tid: 2, , table: control.mac_addr_cache_check */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 3,\n+\t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 26,\n+\t\t.cond_start_idx = 27,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n@@ -515,12 +600,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 27,\n+\t\t.cond_start_idx = 28,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -529,323 +614,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 229,\n+\t.key_start_idx = 245,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 127,\n+\t.result_start_idx = 143,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 11,\n-\t.ident_nums = 1\n+\t.ident_start_idx = 12,\n+\t.ident_nums = 0\n \t},\n \t{ /* class_tid: 2, , table: mac_addr_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n+\t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 27,\n+\t\t.cond_start_idx = 28,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 242,\n+\t.key_start_idx = 258,\n \t.blob_key_bit_size = 73,\n \t.key_bit_size = 73,\n \t.key_num_fields = 5,\n-\t.result_start_idx = 140,\n+\t.result_start_idx = 156,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 2, , table: profile_tcam_cache.rd */\n+\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 27,\n+\t\t.cond_start_idx = 28,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 247,\n+\t.key_start_idx = 263,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n \t.ident_start_idx = 12,\n \t.ident_nums = 3\n \t},\n-\t{ /* class_tid: 2, , table: control.gen_tbl_miss */\n+\t{ /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 2,\n-\t\t.cond_false_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 27,\n+\t\t.cond_start_idx = 28,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 2, , table: control.conflict_check */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 4,\n-\t\t.cond_false_goto = 1023,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 28,\n-\t\t.cond_nums = 1 },\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n-\t.func_info = {\n-\t\t.func_opc = BNXT_ULP_FUNC_OPC_EQ,\n-\t\t.func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,\n-\t\t.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n-\t\t.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,\n-\t\t.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,\n-\t\t.func_dst_opr = BNXT_ULP_RF_IDX_CC },\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n-\t},\n-\t{ /* class_tid: 2, , table: profile_tcam.ipv4 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 2,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 29,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 250,\n-\t.blob_key_bit_size = 81,\n-\t.key_bit_size = 81,\n-\t.key_num_fields = 43,\n-\t.result_start_idx = 144,\n-\t.result_bit_size = 38,\n-\t.result_num_fields = 17,\n-\t.ident_start_idx = 15,\n-\t.ident_nums = 1\n-\t},\n-\t{ /* class_tid: 2, , table: profile_tcam.ipv6 */\n+\t{ /* class_tid: 2, , table: profile_tcam.f2 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 30,\n+\t\t.cond_start_idx = 29,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 1,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 293,\n+\t.key_start_idx = 266,\n \t.blob_key_bit_size = 81,\n \t.key_bit_size = 81,\n \t.key_num_fields = 43,\n-\t.result_start_idx = 161,\n+\t.result_start_idx = 160,\n \t.result_bit_size = 38,\n-\t.result_num_fields = 17,\n-\t.ident_start_idx = 16,\n-\t.ident_nums = 1\n+\t.result_num_fields = 17\n \t},\n-\t{ /* class_tid: 2, , table: profile_tcam_cache.wr */\n+\t{ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 30,\n+\t\t.cond_start_idx = 29,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 336,\n+\t.key_start_idx = 309,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.result_start_idx = 178,\n+\t.result_start_idx = 177,\n \t.result_bit_size = 122,\n \t.result_num_fields = 5\n \t},\n-\t{ /* class_tid: 2, , table: em.ipv4 */\n+\t{ /* class_tid: 2, , table: em.tun */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type = TF_MEM_INTERNAL,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 30,\n-\t\t.cond_nums = 2 },\n+\t\t.cond_start_idx = 29,\n+\t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 339,\n-\t.blob_key_bit_size = 176,\n-\t.key_bit_size = 176,\n-\t.key_num_fields = 10,\n-\t.result_start_idx = 183,\n+\t.key_start_idx = 312,\n+\t.blob_key_bit_size = 112,\n+\t.key_bit_size = 112,\n+\t.key_num_fields = 8,\n+\t.result_start_idx = 182,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 2, , table: eem.ipv4 */\n+\t{ /* class_tid: 2, , table: eem.tun */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n \t.resource_type = TF_MEM_EXTERNAL,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 0,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 32,\n-\t\t.cond_nums = 2 },\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 30,\n+\t\t.cond_nums = 0 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 349,\n+\t.key_start_idx = 320,\n \t.blob_key_bit_size = 448,\n \t.key_bit_size = 448,\n-\t.key_num_fields = 10,\n-\t.result_start_idx = 192,\n+\t.key_num_fields = 8,\n+\t.result_start_idx = 191,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 2, , table: em.ipv6 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n-\t.resource_type = TF_MEM_INTERNAL,\n+\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 0,\n+\t\t.cond_true_goto  = 5,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 34,\n+\t\t.cond_start_idx = 31,\n \t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 359,\n-\t.blob_key_bit_size = 416,\n-\t.key_bit_size = 416,\n-\t.key_num_fields = 11,\n-\t.result_start_idx = 201,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 9\n+\t.key_start_idx = 328,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 15,\n+\t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 2, , table: eem.ipv6 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n-\t.resource_type = TF_MEM_EXTERNAL,\n+\t{ /* class_tid: 3, , table: mac_addr_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 0,\n-\t\t.cond_false_goto = 0,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 35,\n+\t\t.cond_start_idx = 32,\n \t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 370,\n-\t.blob_key_bit_size = 448,\n-\t.key_bit_size = 448,\n-\t.key_num_fields = 11,\n-\t.result_start_idx = 210,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 9\n+\t.key_start_idx = 329,\n+\t.blob_key_bit_size = 73,\n+\t.key_bit_size = 73,\n+\t.key_num_fields = 5,\n+\t.ident_start_idx = 16,\n+\t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, , table: int_full_act_record.ing_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 35,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 219,\n-\t.result_bit_size = 128,\n-\t.result_num_fields = 26\n-\t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 35,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 381,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 17,\n-\t.ident_nums = 0\n-\t},\n-\t{ /* class_tid: 3, , table: control.ing_0 */\n+\t{ /* class_tid: 3, , table: control.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_RX,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 3,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 35,\n+\t\t.cond_start_idx = 32,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n+\t{ /* class_tid: 3, , table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.direction = TF_DIR_RX,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 36,\n+\t\t.cond_start_idx = 33,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -853,361 +851,240 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 382,\n+\t.key_start_idx = 334,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 245,\n+\t.result_start_idx = 200,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.ident_start_idx = 17,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */\n+\t{ /* class_tid: 3, , table: mac_addr_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_RX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 36,\n+\t\t.cond_start_idx = 33,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 395,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.result_start_idx = 258,\n+\t.key_start_idx = 347,\n+\t.blob_key_bit_size = 73,\n+\t.key_bit_size = 73,\n+\t.key_num_fields = 5,\n+\t.result_start_idx = 213,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 36,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 262,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n-\t},\n-\t{ /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_RX,\n+\t{ /* class_tid: 3, , table: profile_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 36,\n+\t\t.cond_start_idx = 33,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 263,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.key_start_idx = 352,\n+\t.blob_key_bit_size = 14,\n+\t.key_bit_size = 14,\n+\t.key_num_fields = 3,\n+\t.ident_start_idx = 18,\n+\t.ident_nums = 3\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n-\t.direction = TF_DIR_RX,\n+\t{ /* class_tid: 3, , table: control.gen_tbl_miss */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n+\t\t.cond_true_goto  = 2,\n \t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 36,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 264,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 33,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 3, , table: control.egr_0 */\n+\t{ /* class_tid: 3, , table: control.conflict_check */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_RX,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 6,\n+\t\t.cond_true_goto  = 4,\n+\t\t.cond_false_goto = 1023,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 36,\n+\t\t.cond_start_idx = 34,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.func_info = {\n+\t\t.func_opc = BNXT_ULP_FUNC_OPC_EQ,\n+\t\t.func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,\n+\t\t.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n+\t\t.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,\n+\t\t.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,\n+\t\t.func_dst_opr = BNXT_ULP_RF_IDX_CC },\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 3, , table: int_full_act_record.egr_vfr */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 37,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 265,\n-\t.result_bit_size = 128,\n-\t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n-\t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t{ /* class_tid: 3, , table: profile_tcam.ipv4 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n+\t\t.cond_true_goto  = 2,\n \t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 37,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 396,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 18,\n-\t.ident_nums = 0\n-\t},\n-\t{ /* class_tid: 3, , table: control.egr_1 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 37,\n+\t\t.cond_start_idx = 35,\n \t\t.cond_nums = 1 },\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 355,\n+\t.blob_key_bit_size = 81,\n+\t.key_bit_size = 81,\n+\t.key_num_fields = 43,\n+\t.result_start_idx = 217,\n+\t.result_bit_size = 38,\n+\t.result_num_fields = 17,\n+\t.ident_start_idx = 21,\n+\t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */\n+\t{ /* class_tid: 3, , table: profile_tcam.ipv6 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 38,\n+\t\t.cond_start_idx = 36,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 397,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 291,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 18,\n-\t.ident_nums = 0\n+\t.key_start_idx = 398,\n+\t.blob_key_bit_size = 81,\n+\t.key_bit_size = 81,\n+\t.key_num_fields = 43,\n+\t.result_start_idx = 234,\n+\t.result_bit_size = 38,\n+\t.result_num_fields = 17,\n+\t.ident_start_idx = 22,\n+\t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */\n+\t{ /* class_tid: 3, , table: profile_tcam_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 0,\n+\t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 38,\n+\t\t.cond_start_idx = 36,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 410,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.result_start_idx = 304,\n-\t.result_bit_size = 62,\n-\t.result_num_fields = 4\n+\t.key_start_idx = 441,\n+\t.blob_key_bit_size = 14,\n+\t.key_bit_size = 14,\n+\t.key_num_fields = 3,\n+\t.result_start_idx = 251,\n+\t.result_bit_size = 122,\n+\t.result_num_fields = 5\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t{ /* class_tid: 3, , table: em.ipv4 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n+\t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 38,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 36,\n+\t\t.cond_nums = 2 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 411,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 18,\n-\t.ident_nums = 0\n-\t},\n-\t{ /* class_tid: 3, , table: control.egr_2 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 3,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 38,\n-\t\t.cond_nums = 1 },\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n-\t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 39,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 412,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 308,\n+\t.key_start_idx = 444,\n+\t.blob_key_bit_size = 176,\n+\t.key_bit_size = 176,\n+\t.key_num_fields = 10,\n+\t.result_start_idx = 256,\n \t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 18,\n-\t.ident_nums = 1\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t{ /* class_tid: 3, , table: eem.ipv4 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n+\t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 39,\n+\t\t.cond_start_idx = 38,\n \t\t.cond_nums = 2 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 425,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.result_start_idx = 321,\n-\t.result_bit_size = 62,\n-\t.result_num_fields = 4\n-\t},\n-\t{ /* class_tid: 3, , table: int_full_act_record.egr_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 41,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 325,\n-\t.result_bit_size = 128,\n-\t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n-\t},\n-\t{ /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 41,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 351,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.key_start_idx = 454,\n+\t.blob_key_bit_size = 448,\n+\t.key_bit_size = 448,\n+\t.key_num_fields = 10,\n+\t.result_start_idx = 265,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n+\t{ /* class_tid: 3, , table: em.ipv6 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n+\t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 41,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 40,\n+\t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 352,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.key_start_idx = 464,\n+\t.blob_key_bit_size = 416,\n+\t.key_bit_size = 416,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 274,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n+\t{ /* class_tid: 3, , table: eem.ipv6 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,\n+\t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 0,\n@@ -1215,41 +1092,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 41,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 353,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.key_start_idx = 475,\n+\t.blob_key_bit_size = 448,\n+\t.key_bit_size = 448,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 283,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 4, , table: int_full_act_record.loopback */\n+\t{ /* class_tid: 4, , table: int_full_act_record.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n-\t.direction = TF_DIR_TX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 41,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,\n-\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 354,\n+\t.result_start_idx = 292,\n \t.result_bit_size = 128,\n-\t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n+\t.result_num_fields = 26\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n@@ -1260,16 +1140,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 426,\n+\t.key_start_idx = 486,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.ident_start_idx = 19,\n+\t.ident_start_idx = 23,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 4, , table: control.vf_0 */\n+\t{ /* class_tid: 4, , table: control.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 3,\n@@ -1280,10 +1160,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n@@ -1296,22 +1176,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 427,\n+\t.key_start_idx = 487,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 380,\n+\t.result_start_idx = 318,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 19,\n+\t.ident_start_idx = 23,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n@@ -1322,119 +1204,103 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 440,\n+\t.key_start_idx = 500,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 393,\n+\t.result_start_idx = 331,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */\n+\t{ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 42,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n-\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 397,\n+\t.result_start_idx = 335,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */\n+\t{ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 42,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n-\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 398,\n+\t.result_start_idx = 336,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */\n+\t{ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 42,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n-\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 399,\n+\t.result_start_idx = 337,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 4, , table: int_full_act_record.vf_ing */\n+\t{ /* class_tid: 4, , table: control.egr_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 6,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 42,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t{ /* class_tid: 4, , table: int_full_act_record.egr_vfr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n-\t.direction = TF_DIR_RX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 400,\n+\t.result_start_idx = 338,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 441,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 426,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 20,\n-\t.ident_nums = 0\n-\t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n@@ -1443,33 +1309,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 454,\n+\t.key_start_idx = 501,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.ident_start_idx = 20,\n+\t.ident_start_idx = 24,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 4, , table: control.vfr_0 */\n+\t{ /* class_tid: 4, , table: control.egr_1 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n-\t\t.cond_false_goto = 3,\n+\t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 42,\n+\t\t.cond_start_idx = 43,\n \t\t.cond_nums = 1 },\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n@@ -1477,7 +1343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 43,\n+\t\t.cond_start_idx = 44,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -1486,140 +1352,392 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 455,\n+\t.key_start_idx = 502,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 439,\n+\t.result_start_idx = 364,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 20,\n+\t.ident_start_idx = 24,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 1,\n+\t\t.cond_true_goto  = 0,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 43,\n+\t\t.cond_start_idx = 44,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 468,\n+\t.key_start_idx = 515,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 452,\n+\t.result_start_idx = 377,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 43,\n+\t\t.cond_start_idx = 44,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 456,\n-\t.result_bit_size = 0,\n-\t.result_num_fields = 0,\n-\t.encap_num_fields = 12\n+\t.key_start_idx = 516,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 24,\n+\t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n+\t{ /* class_tid: 4, , table: control.egr_2 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 44,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 43,\n+\t\t.cond_start_idx = 45,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 517,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 381,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 24,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 45,\n+\t\t.cond_nums = 2 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 530,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 394,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n+\t},\n+\t{ /* class_tid: 4, , table: int_full_act_record.egr_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 47,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 468,\n+\t.result_start_idx = 398,\n \t.result_bit_size = 128,\n-\t.result_num_fields = 26\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 0\n+\t},\n+\t{ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 47,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 424,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 47,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 425,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 47,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 426,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */\n+\t{ /* class_tid: 5, , table: int_full_act_record.loopback */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n-\t.direction = TF_DIR_RX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 43,\n+\t\t.cond_start_idx = 47,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,\n+\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.result_start_idx = 494,\n+\t.result_start_idx = 427,\n \t.result_bit_size = 128,\n-\t.result_num_fields = 26\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 0\n+\t},\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 47,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 531,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 25,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 5, , table: control.vf_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 47,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.direction = TF_DIR_RX,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n \t\t.cond_true_goto  = 1,\n \t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 43,\n+\t\t.cond_start_idx = 48,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 469,\n+\t.key_start_idx = 532,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 520,\n+\t.result_start_idx = 453,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 20,\n-\t.ident_nums = 0\n+\t.ident_start_idx = 25,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 48,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 545,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 466,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n+\t},\n+\t{ /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 48,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n+\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 470,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 48,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n+\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 471,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 48,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n+\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 472,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 5, , table: int_full_act_record.vf_ing */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 48,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 473,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_true_goto  = 0,\n-\t\t.cond_false_goto = 0,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 43,\n+\t\t.cond_start_idx = 48,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -1629,19 +1747,224 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n \t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n-\t.key_start_idx = 482,\n+\t.key_start_idx = 546,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 533,\n+\t.result_start_idx = 499,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 20,\n+\t.ident_start_idx = 26,\n \t.ident_nums = 0\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n+\t},\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 48,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 559,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 26,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 5, , table: control.vfr_0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 48,\n+\t\t.cond_nums = 1 },\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE\n+\t},\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 49,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 560,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 512,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 26,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 49,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 573,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 525,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n+\t},\n+\t{ /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 49,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 529,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 12\n+\t},\n+\t{ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 49,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 541,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n+\t},\n+\t{ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 49,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.result_start_idx = 567,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n+\t},\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 49,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 574,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 593,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 26,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 49,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.byte_order = BNXT_ULP_BYTE_ORDER_LE,\n+\t.key_start_idx = 587,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 606,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 26,\n+\t.ident_nums = 0\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t/* cond_reject: wh_plus, class_tid: 1 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n@@ -1751,32 +2074,61 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_WC_MATCH\n \t},\n-\t/* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */\n+\t/* cond_execute: class_tid: 2, control.tunnel_cache_check */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n+\t},\n+\t/* cond_execute: class_tid: 2, control.flow_type_check */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_F1\n+\t},\n+\t/* cond_execute: class_tid: 2, control.mac_addr_cache_check */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n+\t},\n+\t/* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n+\t},\n+\t/* cond_execute: class_tid: 2, em.tun */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,\n+\t},\n+\t/* cond_reject: wh_plus, class_tid: 3 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n+\t.cond_operand = BNXT_ULP_CF_IDX_WC_MATCH\n+\t},\n+\t/* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,\n \t.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC\n \t},\n-\t/* cond_execute: class_tid: 2, control.0 */\n+\t/* cond_execute: class_tid: 3, control.0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 2, control.gen_tbl_miss */\n+\t/* cond_execute: class_tid: 3, control.gen_tbl_miss */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 2, control.conflict_check */\n+\t/* cond_execute: class_tid: 3, control.conflict_check */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_CC\n \t},\n-\t/* cond_execute: class_tid: 2, profile_tcam.ipv4 */\n+\t/* cond_execute: class_tid: 3, profile_tcam.ipv4 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n \t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n-\t/* cond_execute: class_tid: 2, em.ipv4 */\n+\t/* cond_execute: class_tid: 3, em.ipv4 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,\n \t},\n@@ -1784,7 +2136,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n \t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n-\t/* cond_execute: class_tid: 2, eem.ipv4 */\n+\t/* cond_execute: class_tid: 3, eem.ipv4 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,\n \t},\n@@ -1792,31 +2144,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n \t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n-\t/* cond_execute: class_tid: 2, em.ipv6 */\n+\t/* cond_execute: class_tid: 3, em.ipv6 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,\n \t},\n-\t/* cond_execute: class_tid: 3, control.ing_0 */\n+\t/* cond_execute: class_tid: 4, control.ing_0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 3, control.egr_0 */\n+\t/* cond_execute: class_tid: 4, control.egr_0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n-\t/* cond_execute: class_tid: 3, control.egr_1 */\n+\t/* cond_execute: class_tid: 4, control.egr_1 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 3, control.egr_2 */\n+\t/* cond_execute: class_tid: 4, control.egr_2 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */\n+\t/* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n@@ -1825,12 +2177,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 4, control.vf_0 */\n+\t/* cond_execute: class_tid: 5, control.vf_0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n \t},\n-\t/* cond_execute: class_tid: 4, control.vfr_0 */\n+\t/* cond_execute: class_tid: 5, control.vfr_0 */\n \t{\n \t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS\n@@ -5669,7 +6021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 2, , table: tunnel_cache.rd */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n@@ -5690,181 +6042,52 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: mac_addr_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"tunnel_id\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"tunnel_id\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: l2_cntxt_tcam.1 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"one_tag\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"one_tag\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, , table: l2_cntxt_tcam.0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -5872,19 +6095,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -5892,19 +6109,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -5968,18 +6179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -6046,7 +6252,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: mac_addr_cache.wr */\n+\t/* class_tid: 2, , table: tunnel_cache.wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tunnel_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tunnel_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, , table: mac_addr_cache.rd */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n@@ -6072,17 +6318,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.description = \"tun_hdr\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -6090,60 +6334,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.description = \"one_tag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"one_tag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -6153,8 +6364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac_addr\",\n@@ -6162,204 +6373,166 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: profile_tcam_cache.rd */\n+\t/* class_tid: 2, , table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: profile_tcam.ipv4 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_type\",\n+\t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_type\",\n+\t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr3 = {\n-\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_type\",\n+\t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n@@ -6367,7 +6540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_type\",\n+\t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6375,162 +6548,200 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_valid\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t1}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_valid\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: mac_addr_cache.wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_vtag_present\",\n+\t\t.description = \"one_tag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_vtag_present\",\n+\t\t.description = \"one_tag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr1 = {\n-\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, , table: profile_tcam.f2 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n+\t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n+\t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6538,13 +6749,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_err\",\n+\t\t.description = \"l4_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_err\",\n+\t\t.description = \"l4_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6552,15 +6763,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_valid\",\n+\t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_valid\",\n+\t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6568,13 +6777,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6582,27 +6791,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_error\",\n+\t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_error\",\n+\t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6610,29 +6819,44 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV4},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr3 = {\n+\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.description = \"l3_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.description = \"l3_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6640,27 +6864,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.description = \"l2_two_vtags\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.description = \"l2_two_vtags\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6668,57 +6896,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_two_vtags\",\n+\t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_two_vtags\",\n+\t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6726,13 +6952,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_vtag_present\",\n+\t\t.description = \"l2_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_vtag_present\",\n+\t\t.description = \"l2_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6740,35 +6966,37 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_valid\",\n+\t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n@@ -6776,7 +7004,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_valid\",\n+\t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6784,68 +7012,65 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hrec_next\",\n+\t\t.description = \"tun_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hrec_next\",\n+\t\t.description = \"tun_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_WP_SYM_TUN_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\tULP_WP_SYM_TL4_HDR_TYPE_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"agg_error\",\n+\t\t.description = \"tl4_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"agg_error\",\n+\t\t.description = \"tl4_hdr_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -6853,159 +7078,137 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_WP_SYM_TL4_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n+\t\t.description = \"tl3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n+\t\t.description = \"tl3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: profile_tcam.ipv6 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n-\t\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr3 = {\n-\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_error\",\n+\t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_error\",\n+\t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_WP_SYM_TL3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_valid\",\n+\t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_valid\",\n+\t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -7013,61 +7216,61 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n+\t\tULP_WP_SYM_TL2_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_error\",\n+\t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_error\",\n+\t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -7075,68 +7278,60 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_vtag_present\",\n+\t\t.description = \"agg_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_vtag_present\",\n+\t\t.description = \"agg_error\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -7144,15 +7339,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_type\",\n+\t\t.description = \"pkt_type_0\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_type\",\n+\t\t.description = \"pkt_type_0\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -7160,1487 +7353,1459 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_valid\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t1}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_valid\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: em.tun */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_id\",\n+\t\t.field_bit_size = 24,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_id\",\n+\t\t.field_bit_size = 24,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 2, , table: eem.tun */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 339,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 339,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_id\",\n+\t\t.field_bit_size = 24,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_id\",\n+\t\t.field_bit_size = 24,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: mac_addr_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"tun_hdr\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.description = \"tun_hdr\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"agg_error\",\n+\t\t.description = \"one_tag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"agg_error\",\n+\t\t.description = \"one_tag\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: profile_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr3 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: em.ipv4 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t1}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: mac_addr_cache.wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"tun_hdr\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"tun_hdr\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"one_tag\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"one_tag\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: eem.ipv4 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"mac_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"mac_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: profile_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr3 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: profile_tcam.ipv4 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr3 = {\n+\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: em.ipv6 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 128,\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 128,\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 128,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 128,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n \t\t}\n \t},\n-\t/* class_tid: 2, , table: eem.ipv6 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 35,\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 35,\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4.dst\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4.src\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.prot\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n-\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3.dst\",\n-\t\t.field_bit_size = 128,\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 128,\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3.src\",\n-\t\t.field_bit_size = 128,\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2.dmac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n+\t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n+\t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -8648,491 +8813,511 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n-\t\t}\n-\t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr3 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t1}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: profile_tcam.ipv6 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,\n+\t\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr3 = {\n+\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n+\t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n+\t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n+\t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n+\t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n+\t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n+\t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -9140,203 +9325,171 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n+\t\t.description = \"tl4_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n+\t\t.description = \"tl4_hdr_valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n+\t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n+\t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -9344,280 +9497,294 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr3 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t1}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: profile_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr3 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: em.ipv4 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n@@ -9625,211 +9792,305 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n+\t\t.description = \"l2.dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n+\t\t.description = \"l2.dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n+\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: eem.ipv4 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 275,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 275,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3.prot\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l3.prot\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 32,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n@@ -9837,34 +10098,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */\n+\t/* class_tid: 3, , table: em.ipv6 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n@@ -9872,32 +10147,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n@@ -9905,154 +10196,314 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n+\t\t.description = \"l3.prot\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 128,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l2.smac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l2.smac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n+\t\t.description = \"l2.dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n+\t\t.description = \"l2.dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n+\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t\t.field_opr1 = {\n-\t\t2}\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, , table: eem.ipv6 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l4.dst\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n-\t\t1}\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4.src\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l3.prot\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.prot\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},\n+\t\t.field_src3 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n \t\t.field_opr1 = {\n@@ -10060,13 +10511,67 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -10112,8 +10617,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n@@ -10177,17 +10682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t1}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n@@ -10249,529 +10750,2581 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t.field_opr1 = {\n \t\t1}\n \t\t}\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n-\t/* class_tid: 1, , table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */\n \t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n+\t\t}\n \t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */\n \t{\n-\t.description = \"l2_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t2}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t1}\n+\t\t}\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n+\t/* class_tid: 1, , table: l2_cntxt_tcam.0 */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t},\n+\t{\n+\t.description = \"allowed_pri\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"default_pri\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"allowed_tpid\",\n+\t.field_bit_size = 6,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"default_tpid\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"bd_act_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"byp_sp_lkup\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"pri_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tpid_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: mac_addr_cache.wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"src_property_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: profile_tcam.ipv4 */\n+\t{\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.0\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.2\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.3\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr3 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr3 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.8\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.9\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t3}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: profile_tcam.ipv6 */\n+\t{\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.0\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.2\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.3\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t},\n \t{\n-\t.description = \"parif\",\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr3 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},\n+\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr3 = {\n+\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.8\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.9\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t7}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: profile_tcam.ipv4_vxlan */\n+\t{\n+\t.description = \"wc_key_id\",\n \t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.0\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.2\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.3\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.8\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.9\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t20}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n+\t},\n+\t{\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, , table: profile_tcam_cache.wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"profile_tcam_index\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_sig_id\",\n+\t.field_bit_size = 64,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n+\t/* class_tid: 1, , table: em.ipv4 */\n \t{\n-\t.description = \"allowed_pri\",\n-\t.field_bit_size = 8,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"default_pri\",\n-\t.field_bit_size = 3,\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"allowed_tpid\",\n-\t.field_bit_size = 6,\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"default_tpid\",\n-\t.field_bit_size = 3,\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"bd_act_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"sp_rec_ptr\",\n-\t.field_bit_size = 16,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"byp_sp_lkup\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t1}\n+\t3}\n \t},\n \t{\n-\t.description = \"pri_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tpid_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n-\t/* class_tid: 1, , table: mac_addr_cache.wr */\n+\t/* class_tid: 1, , table: eem.ipv4 */\n \t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"l2_cntxt_tcam_index\",\n-\t.field_bit_size = 10,\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n-\t.description = \"src_property_ptr\",\n-\t.field_bit_size = 10,\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t(173 >> 8) & 0xff,\n+\t173 & 0xff}\n \t},\n-\t/* class_tid: 1, , table: profile_tcam.ipv4 */\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 4,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t3}\n \t},\n \t{\n-\t.description = \"wc_search_en\",\n+\t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.0\",\n+\t.description = \"valid\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* class_tid: 1, , table: em.ipv6 */\n \t{\n-\t.description = \"em_key_mask.1\",\n-\t.field_bit_size = 1,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"em_key_mask.2\",\n+\t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.3\",\n+\t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.4\",\n-\t.field_bit_size = 1,\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}\n+\t3}\n \t},\n \t{\n-\t.description = \"em_key_mask.5\",\n+\t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr3 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.6\",\n+\t.description = \"valid\",\n \t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr3 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}\n+\t1}\n \t},\n+\t/* class_tid: 1, , table: eem.ipv6 */\n \t{\n-\t.description = \"em_key_mask.7\",\n-\t.field_bit_size = 1,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"em_key_mask.8\",\n+\t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.9\",\n+\t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n+\t.description = \"act_rec_size\",\n \t.field_bit_size = 5,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t3}\n+\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t(413 >> 8) & 0xff,\n+\t413 & 0xff}\n \t},\n \t{\n-\t.description = \"em_search_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t1}\n+\t3}\n \t},\n \t{\n-\t.description = \"pl_byp_lkup_en\",\n+\t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: profile_tcam.ipv6 */\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 4,\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n+\t/* class_tid: 1, , table: em.vxlan */\n \t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"wc_search_en\",\n+\t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.0\",\n+\t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.1\",\n-\t.field_bit_size = 1,\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.2\",\n-\t.field_bit_size = 1,\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.3\",\n-\t.field_bit_size = 1,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.4\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t3}\n \t},\n \t{\n-\t.description = \"em_key_mask.5\",\n+\t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.6\",\n+\t.description = \"valid\",\n \t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr3 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}\n+\t1}\n \t},\n+\t/* class_tid: 1, , table: eem.vxlan */\n \t{\n-\t.description = \"em_key_mask.7\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr2 = {\n-\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},\n-\t.field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n-\t.field_opr3 = {\n-\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}\n+\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.description = \"em_key_mask.8\",\n+\t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.9\",\n+\t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n+\t.description = \"act_rec_size\",\n \t.field_bit_size = 5,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t7}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n-\t.description = \"em_search_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t1}\n-\t},\n-\t{\n-\t.description = \"pl_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t(197 >> 8) & 0xff,\n+\t197 & 0xff}\n \t},\n-\t/* class_tid: 1, , table: profile_tcam.ipv4_vxlan */\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 4,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t3}\n \t},\n \t{\n-\t.description = \"wc_search_en\",\n+\t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.0\",\n+\t.description = \"valid\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n+\t/* class_tid: 2, , table: l2_cntxt_tcam.1 */\n \t{\n-\t.description = \"em_key_mask.1\",\n-\t.field_bit_size = 1,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.2\",\n-\t.field_bit_size = 1,\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.3\",\n+\t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.4\",\n-\t.field_bit_size = 1,\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.5\",\n-\t.field_bit_size = 1,\n+\t.description = \"allowed_pri\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.6\",\n-\t.field_bit_size = 1,\n+\t.description = \"default_pri\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.7\",\n-\t.field_bit_size = 1,\n+\t.description = \"allowed_tpid\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.8\",\n-\t.field_bit_size = 1,\n+\t.description = \"default_tpid\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask.9\",\n+\t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 5,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t20}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_search_en\",\n+\t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -10779,12 +13332,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t1}\n \t},\n \t{\n-\t.description = \"pl_byp_lkup_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"pri_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, , table: profile_tcam_cache.wr */\n+\t{\n+\t.description = \"tpid_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 2, , table: tunnel_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -10795,299 +13354,303 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.description = \"profile_tcam_index\",\n+\t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n+\t/* class_tid: 2, , table: l2_cntxt_tcam.0 */\n \t{\n-\t.description = \"flow_sig_id\",\n-\t.field_bit_size = 64,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n-\t/* class_tid: 1, , table: em.ipv4 */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t(BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,\n+\tBNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n-\t.description = \"ext_flow_cntr\",\n+\t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t},\n+\t{\n+\t.description = \"allowed_pri\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n+\t.description = \"default_pri\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n+\t.description = \"allowed_tpid\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n+\t.description = \"default_tpid\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"bd_act_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"valid\",\n+\t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 1, , table: eem.ipv4 */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n+\t.description = \"pri_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n+\t.description = \"tpid_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, , table: mac_addr_cache.wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n \t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n+\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n+\t.description = \"src_property_ptr\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t(173 >> 8) & 0xff,\n-\t173 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, , table: profile_tcam.f2 */\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l1_cacheable\",\n+\t.description = \"wc_search_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"valid\",\n+\t.description = \"em_key_mask.0\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 1, , table: em.ipv6 */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t1}\n \t},\n \t{\n-\t.description = \"ext_flow_cntr\",\n+\t.description = \"em_key_mask.2\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_int\",\n+\t.description = \"em_key_mask.3\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l1_cacheable\",\n+\t.description = \"em_key_mask.8\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"valid\",\n+\t.description = \"em_key_mask.9\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t1}\n+\t8}\n \t},\n-\t/* class_tid: 1, , table: eem.ipv6 */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"ext_flow_cntr\",\n+\t.description = \"em_search_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t1}\n \t},\n \t{\n-\t.description = \"act_rec_int\",\n+\t.description = \"pl_byp_lkup_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_wr */\n \t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n+\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n+\t.description = \"profile_tcam_index\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t(413 >> 8) & 0xff,\n-\t413 & 0xff}\n-\t},\n-\t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t3}\n+\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"valid\",\n-\t.field_bit_size = 1,\n+\t.description = \"flow_sig_id\",\n+\t.field_bit_size = 64,\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t.field_opr1 = {\n-\t1}\n+\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n+\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n-\t/* class_tid: 1, , table: em.vxlan */\n+\t/* class_tid: 2, , table: em.tun */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -11149,7 +13712,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 1, , table: eem.vxlan */\n+\t/* class_tid: 2, , table: eem.tun */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -11186,8 +13749,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t(197 >> 8) & 0xff,\n-\t197 & 0xff}\n+\t(109 >> 8) & 0xff,\n+\t109 & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n@@ -11217,7 +13780,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 2, , table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, , table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n@@ -11317,7 +13880,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, , table: mac_addr_cache.wr */\n+\t/* class_tid: 3, , table: mac_addr_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -11351,7 +13914,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, , table: profile_tcam.ipv4 */\n+\t/* class_tid: 3, , table: profile_tcam.ipv4 */\n \t{\n \t.description = \"wc_key_id\",\n \t.field_bit_size = 4,\n@@ -11497,7 +14060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, , table: profile_tcam.ipv6 */\n+\t/* class_tid: 3, , table: profile_tcam.ipv6 */\n \t{\n \t.description = \"wc_key_id\",\n \t.field_bit_size = 4,\n@@ -11643,7 +14206,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, , table: profile_tcam_cache.wr */\n+\t/* class_tid: 3, , table: profile_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -11686,7 +14249,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n \tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n-\t/* class_tid: 2, , table: em.ipv4 */\n+\t/* class_tid: 3, , table: em.ipv4 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -11748,7 +14311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 2, , table: eem.ipv4 */\n+\t/* class_tid: 3, , table: eem.ipv4 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -11816,7 +14379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 2, , table: em.ipv6 */\n+\t/* class_tid: 3, , table: em.ipv6 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -11878,7 +14441,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 2, , table: eem.ipv6 */\n+\t/* class_tid: 3, , table: eem.ipv6 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n@@ -11946,7 +14509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t1}\n \t},\n-\t/* class_tid: 3, , table: int_full_act_record.ing_0 */\n+\t/* class_tid: 4, , table: int_full_act_record.ing_0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -12106,7 +14669,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n@@ -12196,7 +14759,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -12230,7 +14793,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */\n+\t/* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -12240,7 +14803,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */\n+\t/* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -12250,7 +14813,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */\n+\t/* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -12260,7 +14823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: int_full_act_record.egr_vfr */\n+\t/* class_tid: 4, , table: int_full_act_record.egr_vfr */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -12420,7 +14983,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -12508,7 +15071,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -12539,7 +15102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n@@ -12629,7 +15192,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -12663,7 +15226,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: int_full_act_record.egr_0 */\n+\t/* class_tid: 4, , table: int_full_act_record.egr_0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -12823,7 +15386,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */\n+\t/* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -12833,7 +15396,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */\n+\t/* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -12843,7 +15406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */\n+\t/* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -12853,7 +15416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, , table: int_full_act_record.loopback */\n+\t/* class_tid: 5, , table: int_full_act_record.loopback */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -13013,7 +15576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n@@ -13102,7 +15665,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -13136,7 +15699,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */\n+\t/* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -13146,7 +15709,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */\n+\t/* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -13156,7 +15719,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */\n+\t/* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -13166,7 +15729,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, , table: int_full_act_record.vf_ing */\n+\t/* class_tid: 5, , table: int_full_act_record.vf_ing */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -13326,7 +15889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -13412,7 +15975,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -13497,7 +16060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -13528,7 +16091,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */\n+\t/* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n@@ -13611,7 +16174,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: int_full_act_record.vfr_egr0 */\n+\t/* class_tid: 5, , table: int_full_act_record.vfr_egr0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -13774,7 +16337,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: int_full_act_record.vfr_ing0 */\n+\t/* class_tid: 5, , table: int_full_act_record.vfr_ing0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -13936,7 +16499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -14022,7 +16585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opc = BNXT_ULP_FIELD_OPC_SRC1,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -14180,13 +16743,22 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 28\n \t},\n-\t/* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 2, , table: tunnel_cache.rd */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 42\n \t},\n+\t/* class_tid: 2, , table: l2_cntxt_tcam.1 */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 0\n+\t},\n \t/* class_tid: 2, , table: mac_addr_cache.rd */\n \t{\n \t.description = \"l2_cntxt_id\",\n@@ -14194,7 +16766,40 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 42\n \t},\n-\t/* class_tid: 2, , table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 2, , table: profile_tcam_cache.f2_rd */\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 42\n+\t},\n+\t{\n+\t.description = \"flow_sig_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n+\t.ident_bit_size = 64,\n+\t.ident_bit_pos = 58\n+\t},\n+\t{\n+\t.description = \"profile_tcam_index\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 32\n+\t},\n+\t/* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 42\n+\t},\n+\t/* class_tid: 3, , table: mac_addr_cache.rd */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 42\n+\t},\n+\t/* class_tid: 3, , table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -14203,7 +16808,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 2, , table: profile_tcam_cache.rd */\n+\t/* class_tid: 3, , table: profile_tcam_cache.rd */\n \t{\n \t.description = \"em_profile_id\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n@@ -14222,7 +16827,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 32\n \t},\n-\t/* class_tid: 2, , table: profile_tcam.ipv4 */\n+\t/* class_tid: 3, , table: profile_tcam.ipv4 */\n \t{\n \t.description = \"em_profile_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -14231,7 +16836,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 28\n \t},\n-\t/* class_tid: 2, , table: profile_tcam.ipv6 */\n+\t/* class_tid: 3, , table: profile_tcam.ipv6 */\n \t{\n \t.description = \"em_profile_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -14240,7 +16845,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 28\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -14249,7 +16854,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */\n+\t/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -14258,7 +16863,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */\n+\t/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c\nindex 22c51976ac..d6b4f93d31 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c\n@@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,\n \t}\n \n \t/* Update the parent counters if it is child flow */\n-\tif (sw_acc_tbl_entry->parent_flow_id) {\n+\tif (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) {\n+\t\tuint32_t pc_idx;\n+\n \t\t/* Update the parent counters */\n \t\tt_sw = sw_acc_tbl_entry;\n-\t\tif (ulp_flow_db_parent_flow_count_update(ctxt,\n-\t\t\t\t\t\t\t t_sw->parent_flow_id,\n+\t\tpc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID;\n+\t\tif (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx,\n \t\t\t\t\t\t\t t_sw->pkt_count,\n \t\t\t\t\t\t\t t_sw->byte_count)) {\n \t\t\tPMD_DRV_LOG(ERR, \"Error updating parent counters\\n\");\n@@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,\n \tulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;\n \tulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;\n \tulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;\n+\tulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;\n \tulp_fc_info->num_entries--;\n \tpthread_mutex_unlock(&ulp_fc_info->fc_lock);\n \n@@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,\n \tuint32_t hw_cntr_id = 0, sw_cntr_idx = 0;\n \tstruct sw_acc_counter *sw_acc_tbl_entry;\n \tbool found_cntr_resource = false;\n+\tbool found_parent_flow = false;\n+\tuint32_t pc_idx = 0;\n \n \tulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);\n \tif (!ulp_fc_info)\n@@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,\n \t\t     (params.resource_sub_type ==\n \t\t      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT ||\n \t\t      params.resource_sub_type ==\n-\t\t      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT ||\n-\t\t      params.resource_sub_type ==\n-\t\t      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) {\n+\t\t      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) {\n \t\t\tfound_cntr_resource = true;\n \t\t\tbreak;\n \t\t}\n+\t\tif (params.resource_func ==\n+\t\t    BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {\n+\t\t\tfound_parent_flow = true;\n+\t\t\tpc_idx = params.resource_hndl;\n+\t\t}\n+\n \t} while (!rc && nxt_resource_index);\n \n \tbnxt_ulp_cntxt_release_fdb_lock(ctxt);\n@@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,\n \n \tdir = params.direction;\n \thw_cntr_id = params.resource_hndl;\n-\tif (params.resource_sub_type ==\n+\tif (!found_parent_flow &&\n+\t    params.resource_sub_type ==\n \t\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {\n \t\tif (!ulp_fc_info->num_counters)\n \t\t\treturn ulp_fc_tf_flow_stat_get(ctxt, &params, count);\n@@ -745,14 +755,17 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,\n \t\t\tsw_acc_tbl_entry->byte_count = 0;\n \t\t}\n \t\tpthread_mutex_unlock(&ulp_fc_info->fc_lock);\n-\t} else if (params.resource_sub_type ==\n-\t\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) {\n+\t} else if (found_parent_flow &&\n+\t\t   params.resource_sub_type ==\n+\t\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {\n \t\t/* Get stats from the parent child table */\n-\t\tulp_flow_db_parent_flow_count_get(ctxt, flow_id,\n+\t\tulp_flow_db_parent_flow_count_get(ctxt, pc_idx,\n \t\t\t\t\t\t  &count->hits, &count->bytes,\n \t\t\t\t\t\t  count->reset);\n-\t\tcount->hits_set = 1;\n-\t\tcount->bytes_set = 1;\n+\t\tif (count->hits)\n+\t\t\tcount->hits_set = 1;\n+\t\tif (count->bytes)\n+\t\t\tcount->bytes_set = 1;\n \t} else {\n \t\t/* TBD: Handle External counters */\n \t\trc = -EINVAL;\n@@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,\n  *\n  * hw_cntr_id [in] The HW flow counter ID\n  *\n- * fid [in] parent flow id\n+ * pc_idx [in] parent child db index\n  *\n  */\n int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,\n \t\t\t\t\tenum tf_dir dir,\n \t\t\t\t\tuint32_t hw_cntr_id,\n-\t\t\t\t\tuint32_t fid)\n+\t\t\t\t\tuint32_t pc_idx)\n {\n \tstruct bnxt_ulp_fc_info *ulp_fc_info;\n \tuint32_t sw_cntr_idx;\n@@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,\n \tpthread_mutex_lock(&ulp_fc_info->fc_lock);\n \tsw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;\n \tif (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {\n-\t\tulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;\n+\t\tpc_idx |= FLOW_CNTR_PC_FLOW_VALID;\n+\t\tulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx;\n \t} else {\n \t\tBNXT_TF_DBG(ERR, \"Failed to set parent flow id %x:%x\\n\",\n-\t\t\t    hw_cntr_id, fid);\n+\t\t\t    hw_cntr_id, pc_idx);\n \t\trc = -ENOENT;\n \t}\n \tpthread_mutex_unlock(&ulp_fc_info->fc_lock);\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h\nindex 448d05c118..9825ed2a27 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h\n@@ -21,12 +21,14 @@\n #define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \\\n \t\t(d)->byte_count_shift)\n \n+#define FLOW_CNTR_PC_FLOW_VALID\t0x1000000\n+\n struct sw_acc_counter {\n \tuint64_t pkt_count;\n \tuint64_t byte_count;\n \tbool\tvalid;\n \tuint32_t hw_cntr_id;\n-\tuint32_t parent_flow_id;\n+\tuint32_t pc_flow_idx;\n };\n \n struct hw_fc_mem_info {\n@@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,\n  *\n  * hw_cntr_id [in] The HW flow counter ID\n  *\n- * fid [in] parent flow id\n+ * pc_idx [in] parent child db index\n  *\n  */\n int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,\n \t\t\t\t\tenum tf_dir dir,\n \t\t\t\t\tuint32_t hw_cntr_id,\n-\t\t\t\t\tuint32_t fid);\n+\t\t\t\t\tuint32_t pc_idx);\n \n #endif /* _ULP_FC_MGR_H_ */\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c\nindex 747a360aa0..039c9c2a6b 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c\n@@ -386,101 +386,6 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db)\n \t}\n }\n \n-/* internal validation function for parent flow tbl */\n-static struct bnxt_ulp_flow_db *\n-ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t  uint32_t fid)\n-{\n-\tstruct bnxt_ulp_flow_db *flow_db;\n-\n-\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n-\tif (!flow_db) {\n-\t\tBNXT_TF_DBG(ERR, \"Invalid Arguments\\n\");\n-\t\treturn NULL;\n-\t}\n-\n-\t/* check for max flows */\n-\tif (fid >= flow_db->flow_tbl.num_flows || !fid) {\n-\t\tBNXT_TF_DBG(ERR, \"Invalid flow index\\n\");\n-\t\treturn NULL;\n-\t}\n-\n-\t/* No support for parent child db then just exit */\n-\tif (!flow_db->parent_child_db.entries_count) {\n-\t\tBNXT_TF_DBG(ERR, \"parent child db not supported\\n\");\n-\t\treturn NULL;\n-\t}\n-\n-\treturn flow_db;\n-}\n-\n-/*\n- * Set the tunnel index in the parent flow\n- *\n- * ulp_ctxt [in] Ptr to ulp_context\n- * parent_idx [in] The parent index of the parent flow entry\n- *\n- * returns index on success and negative on failure.\n- */\n-static int32_t\n-ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t       uint32_t parent_idx, uint8_t tun_idx)\n-{\n-\tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\n-\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n-\tif (!flow_db) {\n-\t\tBNXT_TF_DBG(ERR, \"Invalid Arguments\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* check for parent idx validity */\n-\tp_pdb = &flow_db->parent_child_db;\n-\tif (parent_idx >= p_pdb->entries_count ||\n-\t    !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {\n-\t\tBNXT_TF_DBG(ERR, \"Invalid parent flow index %x\\n\", parent_idx);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tp_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx;\n-\treturn 0;\n-}\n-\n-/*\n- * Get the tunnel index from the parent flow\n- *\n- * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n- *\n- * returns 0 if counter accum is set else -1.\n- */\n-static int32_t\n-ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t       uint32_t parent_fid, uint8_t *tun_idx)\n-{\n-\tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\tuint32_t idx;\n-\n-\t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);\n-\tif (!flow_db) {\n-\t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tp_pdb = &flow_db->parent_child_db;\n-\tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {\n-\t\t\t*tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx;\n-\t\t\treturn 0;\n-\t\t}\n-\t}\n-\n-\treturn -EINVAL;\n-}\n-\n /*\n  * Initialize the flow database. Memory is allocated in this\n  * call and assigned to the flow database.\n@@ -783,9 +688,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,\n \tstruct bnxt_ulp_flow_tbl *flow_tbl;\n \tstruct ulp_fdb_resource_info *nxt_resource, *fid_resource;\n \tuint32_t nxt_idx = 0;\n-\tstruct bnxt_tun_cache_entry *tun_tbl;\n-\tuint8_t tun_idx = 0;\n-\tint rc;\n \n \tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n \tif (!flow_db) {\n@@ -862,18 +764,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,\n \t\t\t\t      params->resource_hndl);\n \t}\n \n-\tif (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {\n-\t\ttun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);\n-\t\tif (!tun_tbl)\n-\t\t\treturn -EINVAL;\n-\n-\t\trc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\tulp_clear_tun_entry(tun_tbl, tun_idx);\n-\t}\n-\n \t/* all good, return success */\n \treturn 0;\n }\n@@ -892,7 +782,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,\n \t\t     enum bnxt_ulp_fdb_type flow_type,\n \t\t     uint32_t fid)\n {\n-\tstruct bnxt_tun_cache_entry *tun_tbl;\n \tstruct bnxt_ulp_flow_tbl *flow_tbl;\n \tstruct bnxt_ulp_flow_db *flow_db;\n \n@@ -934,12 +823,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,\n \tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)\n \t\tulp_flow_db_func_id_set(flow_db, fid, 0);\n \n-\ttun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);\n-\tif (!tun_tbl)\n-\t\treturn -EINVAL;\n-\n-\tulp_clear_tun_inner_entry(tun_tbl, fid);\n-\n #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG\n \tBNXT_TF_DBG(ERR, \"flow_id = %u:%u freed\\n\", flow_type, fid);\n #endif\n@@ -1307,24 +1190,84 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,\n \treturn 0;\n }\n \n+/* internal validation function for parent flow tbl */\n+static struct ulp_fdb_parent_info *\n+ulp_flow_db_pc_db_entry_get(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t    uint32_t pc_idx)\n+{\n+\tstruct bnxt_ulp_flow_db *flow_db;\n+\n+\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n+\tif (!flow_db) {\n+\t\tBNXT_TF_DBG(ERR, \"Invalid Arguments\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\t/* check for max flows */\n+\tif (pc_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {\n+\t\tBNXT_TF_DBG(ERR, \"Invalid tunnel index\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\t/* No support for parent child db then just exit */\n+\tif (!flow_db->parent_child_db.entries_count) {\n+\t\tBNXT_TF_DBG(ERR, \"parent child db not supported\\n\");\n+\t\treturn NULL;\n+\t}\n+\tif (!flow_db->parent_child_db.parent_flow_tbl[pc_idx].valid) {\n+\t\tBNXT_TF_DBG(ERR, \"Not a valid tunnel index\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\treturn &flow_db->parent_child_db.parent_flow_tbl[pc_idx];\n+}\n+\n+/* internal validation function for parent flow tbl */\n+static struct bnxt_ulp_flow_db *\n+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t\t  uint32_t tun_idx)\n+{\n+\tstruct bnxt_ulp_flow_db *flow_db;\n+\n+\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n+\tif (!flow_db) {\n+\t\tBNXT_TF_DBG(ERR, \"Invalid Arguments\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\t/* check for max flows */\n+\tif (tun_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {\n+\t\tBNXT_TF_DBG(ERR, \"Invalid tunnel index\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\t/* No support for parent child db then just exit */\n+\tif (!flow_db->parent_child_db.entries_count) {\n+\t\tBNXT_TF_DBG(ERR, \"parent child db not supported\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\treturn flow_db;\n+}\n+\n /*\n  * Allocate the entry in the parent-child database\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * fid [in] The flow id to the flow entry\n+ * tun_idx [in] The tunnel index of the flow entry\n  *\n  * returns index on success and negative on failure.\n  */\n-int32_t\n-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t      uint32_t fid)\n+static int32_t\n+ulp_flow_db_pc_db_idx_alloc(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t    uint32_t tun_idx)\n {\n \tstruct bnxt_ulp_flow_db *flow_db;\n \tstruct ulp_fdb_parent_child_db *p_pdb;\n \tuint32_t idx, free_idx = 0;\n \n \t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);\n+\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, tun_idx);\n \tif (!flow_db) {\n \t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n \t\treturn -EINVAL;\n@@ -1332,11 +1275,11 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,\n \n \tp_pdb = &flow_db->parent_child_db;\n \tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {\n-\t\t\tBNXT_TF_DBG(ERR, \"fid is already allocated\\n\");\n-\t\t\treturn -EINVAL;\n+\t\tif (p_pdb->parent_flow_tbl[idx].valid &&\n+\t\t    p_pdb->parent_flow_tbl[idx].tun_idx == tun_idx) {\n+\t\t\treturn idx;\n \t\t}\n-\t\tif (!p_pdb->parent_flow_tbl[idx].parent_fid && !free_idx)\n+\t\tif (!p_pdb->parent_flow_tbl[idx].valid && !free_idx)\n \t\t\tfree_idx = idx + 1;\n \t}\n \t/* no free slots */\n@@ -1347,132 +1290,148 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,\n \n \tfree_idx -= 1;\n \t/* set the Fid in the parent child */\n-\tp_pdb->parent_flow_tbl[free_idx].parent_fid = fid;\n+\tp_pdb->parent_flow_tbl[free_idx].tun_idx = tun_idx;\n+\tp_pdb->parent_flow_tbl[free_idx].valid = 1;\n \treturn free_idx;\n }\n \n /*\n  * Free the entry in the parent-child database\n  *\n- * ulp_ctxt [in] Ptr to ulp_context\n- * fid [in] The flow id to the flow entry\n+ * pc_entry [in] Ptr to parent child db entry\n  *\n- * returns 0 on success and negative on failure.\n+ * returns none.\n  */\n-int32_t\n-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t     uint32_t fid)\n+static void\n+ulp_flow_db_pc_db_entry_free(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t     struct ulp_fdb_parent_info *pc_entry)\n {\n+\tstruct bnxt_tun_cache_entry *tun_tbl;\n \tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\tuint32_t idx;\n+\tuint64_t *tmp_bitset;\n \n-\t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);\n-\tif (!flow_db) {\n-\t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n-\t\treturn -EINVAL;\n-\t}\n+\t/* free the tunnel entry */\n+\ttun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);\n+\tif (tun_tbl)\n+\t\tulp_tunnel_offload_entry_clear(tun_tbl, pc_entry->tun_idx);\n \n-\tp_pdb = &flow_db->parent_child_db;\n-\tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {\n-\t\t\t/* free the contents */\n-\t\t\tp_pdb->parent_flow_tbl[idx].parent_fid = 0;\n-\t\t\tmemset(p_pdb->parent_flow_tbl[idx].child_fid_bitset,\n-\t\t\t       0, p_pdb->child_bitset_size);\n-\t\t\treturn 0;\n-\t\t}\n-\t}\n-\tBNXT_TF_DBG(ERR, \"parent entry not found = %x\\n\", fid);\n-\treturn -EINVAL;\n+\t/* free the child bitset*/\n+\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n+\tif (flow_db)\n+\t\tmemset(pc_entry->child_fid_bitset, 0,\n+\t\t       flow_db->parent_child_db.child_bitset_size);\n+\n+\t/* free the contents */\n+\ttmp_bitset = pc_entry->child_fid_bitset;\n+\tmemset(pc_entry, 0, sizeof(struct ulp_fdb_parent_info));\n+\tpc_entry->child_fid_bitset = tmp_bitset;\n }\n \n /*\n- * Set or reset the child flow in the parent-child database\n+ * Set or reset the parent flow in the parent-child database\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n+ * pc_idx [in] The index to parent child db\n  * parent_fid [in] The flow id of the parent flow entry\n- * child_fid [in] The flow id of the child flow entry\n  * set_flag [in] Use 1 for setting child, 0 to reset\n  *\n  * returns zero on success and negative on failure.\n  */\n int32_t\n-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,\n+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t\t  uint32_t pc_idx,\n \t\t\t\t  uint32_t parent_fid,\n-\t\t\t\t  uint32_t child_fid,\n \t\t\t\t  uint32_t set_flag)\n {\n+\tstruct ulp_fdb_parent_info *pc_entry;\n \tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\tuint32_t idx, a_idx;\n-\tuint64_t *t;\n \n-\t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);\n+\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n \tif (!flow_db) {\n \t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n \t\treturn -EINVAL;\n \t}\n \n \t/* check for fid validity */\n-\tif (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {\n-\t\tBNXT_TF_DBG(ERR, \"Invalid child flow index %x\\n\", child_fid);\n+\tif (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {\n+\t\tBNXT_TF_DBG(ERR, \"Invalid parent flow index %x\\n\", parent_fid);\n \t\treturn -EINVAL;\n \t}\n \n-\tp_pdb = &flow_db->parent_child_db;\n-\ta_idx = child_fid / ULP_INDEX_BITMAP_SIZE;\n-\tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {\n-\t\t\tt = p_pdb->parent_flow_tbl[idx].child_fid_bitset;\n-\t\t\tif (set_flag)\n-\t\t\t\tULP_INDEX_BITMAP_SET(t[a_idx], child_fid);\n-\t\t\telse\n-\t\t\t\tULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);\n-\t\t\treturn 0;\n-\t\t}\n+\t/* validate the arguments and parent child entry */\n+\tpc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);\n+\tif (!pc_entry) {\n+\t\tBNXT_TF_DBG(ERR, \"failed to get the parent child entry\\n\");\n+\t\treturn -EINVAL;\n \t}\n-\tBNXT_TF_DBG(ERR, \"Unable to set the parent-child flow %x:%x\\n\",\n-\t\t    parent_fid, child_fid);\n-\treturn -1;\n+\n+\tif (set_flag) {\n+\t\tpc_entry->parent_fid = parent_fid;\n+\t} else {\n+\t\tif (pc_entry->parent_fid != parent_fid)\n+\t\t\tBNXT_TF_DBG(ERR, \"Panic: invalid parent id\\n\");\n+\t\tpc_entry->parent_fid = 0;\n+\n+\t\t/* Free the parent child db entry if no user present */\n+\t\tif (!pc_entry->f2_cnt)\n+\t\t\tulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);\n+\t}\n+\treturn 0;\n }\n \n /*\n- * Get the parent index from the parent-child database\n+ * Set or reset the child flow in the parent-child database\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n- * parent_idx [out] The parent index of parent flow entry\n+ * pc_idx [in] The index to parent child db\n+ * child_fid [in] The flow id of the child flow entry\n+ * set_flag [in] Use 1 for setting child, 0 to reset\n  *\n  * returns zero on success and negative on failure.\n  */\n int32_t\n-ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\tuint32_t parent_fid,\n-\t\t\t\tuint32_t *parent_idx)\n+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t\t uint32_t pc_idx,\n+\t\t\t\t uint32_t child_fid,\n+\t\t\t\t uint32_t set_flag)\n {\n+\tstruct ulp_fdb_parent_info *pc_entry;\n \tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\tuint32_t idx;\n+\tuint32_t a_idx;\n+\tuint64_t *t;\n \n-\t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);\n+\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n \tif (!flow_db) {\n \t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n \t\treturn -EINVAL;\n \t}\n \n-\tp_pdb = &flow_db->parent_child_db;\n-\tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {\n-\t\t\t*parent_idx = idx;\n-\t\t\treturn 0;\n-\t\t}\n+\t/* check for fid validity */\n+\tif (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {\n+\t\tBNXT_TF_DBG(ERR, \"Invalid child flow index %x\\n\", child_fid);\n+\t\treturn -EINVAL;\n \t}\n-\tBNXT_TF_DBG(ERR, \"Unable to get the parent flow %x\\n\", parent_fid);\n-\treturn -1;\n+\n+\t/* validate the arguments and parent child entry */\n+\tpc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);\n+\tif (!pc_entry) {\n+\t\tBNXT_TF_DBG(ERR, \"failed to get the parent child entry\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ta_idx = child_fid / ULP_INDEX_BITMAP_SIZE;\n+\tt = pc_entry->child_fid_bitset;\n+\tif (set_flag) {\n+\t\tULP_INDEX_BITMAP_SET(t[a_idx], child_fid);\n+\t\tpc_entry->f2_cnt++;\n+\t} else {\n+\t\tULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);\n+\t\tif (pc_entry->f2_cnt)\n+\t\t\tpc_entry->f2_cnt--;\n+\t\tif (!pc_entry->f2_cnt && !pc_entry->parent_fid)\n+\t\t\tulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);\n+\t}\n+\treturn 0;\n }\n \n /*\n@@ -1541,13 +1500,13 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,\n  * Set the counter accumulation in the parent flow\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * parent_idx [in] The parent index of the parent flow entry\n+ * pc_idx [in] The parent child index of the parent flow entry\n  *\n  * returns index on success and negative on failure.\n  */\n static int32_t\n ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t\tuint32_t parent_idx)\n+\t\t\t\t\tuint32_t pc_idx)\n {\n \tstruct bnxt_ulp_flow_db *flow_db;\n \tstruct ulp_fdb_parent_child_db *p_pdb;\n@@ -1560,50 +1519,16 @@ ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,\n \n \t/* check for parent idx validity */\n \tp_pdb = &flow_db->parent_child_db;\n-\tif (parent_idx >= p_pdb->entries_count ||\n-\t    !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {\n-\t\tBNXT_TF_DBG(ERR, \"Invalid parent flow index %x\\n\", parent_idx);\n+\tif (pc_idx >= p_pdb->entries_count ||\n+\t    !p_pdb->parent_flow_tbl[pc_idx].parent_fid) {\n+\t\tBNXT_TF_DBG(ERR, \"Invalid parent child index %x\\n\", pc_idx);\n \t\treturn -EINVAL;\n \t}\n \n-\tp_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;\n+\tp_pdb->parent_flow_tbl[pc_idx].counter_acc = 1;\n \treturn 0;\n }\n \n-/*\n- * Get the counter accumulation in the parent flow\n- *\n- * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n- *\n- * returns 0 if counter accum is set else -1.\n- */\n-static int32_t\n-ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t\tuint32_t parent_fid)\n-{\n-\tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\tuint32_t idx;\n-\n-\t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);\n-\tif (!flow_db) {\n-\t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tp_pdb = &flow_db->parent_child_db;\n-\tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {\n-\t\t\tif (p_pdb->parent_flow_tbl[idx].counter_acc)\n-\t\t\t\treturn 0;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn -1;\n-}\n-\n /*\n  * Orphan the child flow entry\n  * This is called only for child flows that have\n@@ -1677,22 +1602,30 @@ int32_t\n ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)\n {\n \tstruct ulp_flow_db_res_params fid_parms;\n-\tuint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC;\n+\tuint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;\n \tstruct ulp_flow_db_res_params res_params;\n-\tint32_t fid_idx, rc;\n+\tint32_t pc_idx;\n \n-\t/* create the child flow entry in parent flow table */\n-\tfid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid);\n-\tif (fid_idx < 0) {\n-\t\tBNXT_TF_DBG(ERR, \"Error in creating parent flow fid %x\\n\",\n-\t\t\t    parms->fid);\n-\t\treturn -1;\n+\t/* create or get the parent child database */\n+\tpc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);\n+\tif (pc_idx < 0) {\n+\t\tBNXT_TF_DBG(ERR, \"Error in getting parent child db %x\\n\",\n+\t\t\t    parms->tun_idx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Update the parent fid */\n+\tif (ulp_flow_db_pc_db_parent_flow_set(parms->ulp_ctx, pc_idx,\n+\t\t\t\t\t      parms->fid, 1)) {\n+\t\tBNXT_TF_DBG(ERR, \"Error in setting parent fid %x\\n\",\n+\t\t\t    parms->tun_idx);\n+\t\treturn -EINVAL;\n \t}\n \n \t/* Add the parent details in the resource list of the flow */\n \tmemset(&fid_parms, 0, sizeof(fid_parms));\n \tfid_parms.resource_func\t= BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW;\n-\tfid_parms.resource_hndl\t= fid_idx;\n+\tfid_parms.resource_hndl\t= pc_idx;\n \tfid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;\n \tif (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,\n \t\t\t\t     parms->fid, &fid_parms)) {\n@@ -1710,20 +1643,13 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)\n \t\t\t\t\t     &res_params)) {\n \t\t/* Enable the counter accumulation in parent entry */\n \t\tif (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,\n-\t\t\t\t\t\t\t    fid_idx)) {\n+\t\t\t\t\t\t\t    pc_idx)) {\n \t\t\tBNXT_TF_DBG(ERR, \"Error in setting counter acc %x\\n\",\n \t\t\t\t    parms->fid);\n \t\t\treturn -1;\n \t\t}\n \t}\n \n-\trc  = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx,\n-\t\t\t\t\t     parms->tun_idx);\n-\tif (rc) {\n-\t\tBNXT_TF_DBG(ERR, \"Error setting tun_idx in the parent flow\\n\");\n-\t\treturn rc;\n-\t}\n-\n \treturn 0;\n }\n \n@@ -1741,13 +1667,19 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)\n \tuint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;\n \tenum bnxt_ulp_resource_func res_fun;\n \tstruct ulp_flow_db_res_params res_p;\n-\tuint32_t parent_fid = parms->parent_fid;\n-\tint32_t rc;\n+\tint32_t rc, pc_idx;\n+\n+\t/* create or get the parent child database */\n+\tpc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);\n+\tif (pc_idx < 0) {\n+\t\tBNXT_TF_DBG(ERR, \"Error in getting parent child db %x\\n\",\n+\t\t\t    parms->tun_idx);\n+\t\treturn -1;\n+\t}\n \n \t/* create the parent flow entry in parent flow table */\n-\trc = ulp_flow_db_parent_child_flow_set(parms->ulp_ctx,\n-\t\t\t\t\t       parms->parent_fid,\n-\t\t\t\t\t       parms->fid, 1);\n+\trc = ulp_flow_db_pc_db_child_flow_set(parms->ulp_ctx, pc_idx,\n+\t\t\t\t\t      parms->fid, 1);\n \tif (rc) {\n \t\tBNXT_TF_DBG(ERR, \"Error in setting child fid %x\\n\", parms->fid);\n \t\treturn rc;\n@@ -1756,7 +1688,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)\n \t/* Add the parent details in the resource list of the flow */\n \tmemset(&fid_parms, 0, sizeof(fid_parms));\n \tfid_parms.resource_func\t= BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;\n-\tfid_parms.resource_hndl\t= parms->parent_fid;\n+\tfid_parms.resource_hndl\t= pc_idx;\n \tfid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;\n \trc  = ulp_flow_db_resource_add(parms->ulp_ctx,\n \t\t\t\t       BNXT_ULP_FDB_TYPE_REGULAR,\n@@ -1767,30 +1699,26 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)\n \t\treturn rc;\n \t}\n \n-\t/* check if accumulation count is set for parent flow */\n-\trc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,\n-\t\t\t\t\t\t     parms->parent_fid);\n+\t/* check if internal count action included for this flow.*/\n+\tres_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;\n+\trc = ulp_flow_db_resource_params_get(parms->ulp_ctx,\n+\t\t\t\t\t     BNXT_ULP_FDB_TYPE_REGULAR,\n+\t\t\t\t\t     parms->fid,\n+\t\t\t\t\t     res_fun,\n+\t\t\t\t\t     sub_type,\n+\t\t\t\t\t     &res_p);\n \tif (!rc) {\n-\t\t/* check if internal count action included for this flow.*/\n-\t\tres_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;\n-\t\trc = ulp_flow_db_resource_params_get(parms->ulp_ctx,\n-\t\t\t\t\t\t     BNXT_ULP_FDB_TYPE_REGULAR,\n-\t\t\t\t\t\t     parms->fid,\n-\t\t\t\t\t\t     res_fun,\n-\t\t\t\t\t\t     sub_type,\n-\t\t\t\t\t\t     &res_p);\n-\t\tif (!rc) {\n-\t\t\t/* update the counter manager to include parent fid */\n-\t\t\tif (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,\n-\t\t\t\t\t\t\t    res_p.direction,\n-\t\t\t\t\t\t\t    res_p.resource_hndl,\n-\t\t\t\t\t\t\t    parent_fid)) {\n-\t\t\t\tBNXT_TF_DBG(ERR, \"Error in setting child %x\\n\",\n-\t\t\t\t\t    parms->fid);\n-\t\t\t\treturn -1;\n-\t\t\t}\n+\t\t/* update the counter manager to include parent fid */\n+\t\tif (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,\n+\t\t\t\t\t\t    res_p.direction,\n+\t\t\t\t\t\t    res_p.resource_hndl,\n+\t\t\t\t\t\t    pc_idx)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"Error in setting child %x\\n\",\n+\t\t\t\t    parms->fid);\n+\t\t\treturn -1;\n \t\t}\n \t}\n+\n \t/* return success */\n \treturn 0;\n }\n@@ -1799,7 +1727,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)\n  * Update the parent counters\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n+ * pc_idx [in] The parent flow entry idx\n  * packet_count [in] - packet count\n  * byte_count [in] - byte count\n  *\n@@ -1807,41 +1735,31 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)\n  */\n int32_t\n ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t     uint32_t parent_fid,\n+\t\t\t\t     uint32_t pc_idx,\n \t\t\t\t     uint64_t packet_count,\n \t\t\t\t     uint64_t byte_count)\n {\n-\tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\tuint32_t idx;\n+\tstruct ulp_fdb_parent_info *pc_entry;\n \n-\t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);\n-\tif (!flow_db) {\n-\t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n+\t/* validate the arguments and get parent child entry */\n+\tpc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);\n+\tif (!pc_entry) {\n+\t\tBNXT_TF_DBG(ERR, \"failed to get the parent child entry\\n\");\n \t\treturn -EINVAL;\n \t}\n \n-\tp_pdb = &flow_db->parent_child_db;\n-\tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {\n-\t\t\tif (p_pdb->parent_flow_tbl[idx].counter_acc) {\n-\t\t\t\tp_pdb->parent_flow_tbl[idx].pkt_count +=\n-\t\t\t\t\tpacket_count;\n-\t\t\t\tp_pdb->parent_flow_tbl[idx].byte_count +=\n-\t\t\t\t\tbyte_count;\n-\t\t\t}\n-\t\t\treturn 0;\n-\t\t}\n+\tif (pc_entry->counter_acc) {\n+\t\tpc_entry->pkt_count += packet_count;\n+\t\tpc_entry->byte_count += byte_count;\n \t}\n-\treturn -ENOENT;\n+\treturn 0;\n }\n \n /*\n  * Get the parent accumulation counters\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n+ * pc_idx [in] The parent flow entry idx\n  * packet_count [out] - packet count\n  * byte_count [out] - byte count\n  *\n@@ -1849,37 +1767,27 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,\n  */\n int32_t\n ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t  uint32_t parent_fid, uint64_t *packet_count,\n+\t\t\t\t  uint32_t pc_idx, uint64_t *packet_count,\n \t\t\t\t  uint64_t *byte_count, uint8_t count_reset)\n {\n-\tstruct bnxt_ulp_flow_db *flow_db;\n-\tstruct ulp_fdb_parent_child_db *p_pdb;\n-\tuint32_t idx;\n+\tstruct ulp_fdb_parent_info *pc_entry;\n \n-\t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);\n-\tif (!flow_db) {\n-\t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n+\t/* validate the arguments and get parent child entry */\n+\tpc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);\n+\tif (!pc_entry) {\n+\t\tBNXT_TF_DBG(ERR, \"failed to get the parent child entry\\n\");\n \t\treturn -EINVAL;\n \t}\n \n-\tp_pdb = &flow_db->parent_child_db;\n-\tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {\n-\t\t\tif (p_pdb->parent_flow_tbl[idx].counter_acc) {\n-\t\t\t\t*packet_count =\n-\t\t\t\t\tp_pdb->parent_flow_tbl[idx].pkt_count;\n-\t\t\t\t*byte_count =\n-\t\t\t\t\tp_pdb->parent_flow_tbl[idx].byte_count;\n-\t\t\t\tif (count_reset) {\n-\t\t\t\t\tp_pdb->parent_flow_tbl[idx].pkt_count = 0;\n-\t\t\t\t\tp_pdb->parent_flow_tbl[idx].byte_count = 0;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\treturn 0;\n+\tif (pc_entry->counter_acc) {\n+\t\t*packet_count = pc_entry->pkt_count;\n+\t\t*byte_count = pc_entry->byte_count;\n+\t\tif (count_reset) {\n+\t\t\tpc_entry->pkt_count = 0;\n+\t\t\tpc_entry->byte_count = 0;\n \t\t}\n \t}\n-\treturn -ENOENT;\n+\treturn 0;\n }\n \n /*\n@@ -1897,7 +1805,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)\n \tuint32_t idx;\n \n \t/* validate the arguments */\n-\tflow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);\n+\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);\n \tif (!flow_db) {\n \t\tBNXT_TF_DBG(ERR, \"parent child db validation failed\\n\");\n \t\treturn;\n@@ -1905,7 +1813,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)\n \n \tp_pdb = &flow_db->parent_child_db;\n \tfor (idx = 0; idx < p_pdb->entries_count; idx++) {\n-\t\tif (p_pdb->parent_flow_tbl[idx].parent_fid &&\n+\t\tif (p_pdb->parent_flow_tbl[idx].valid &&\n \t\t    p_pdb->parent_flow_tbl[idx].counter_acc) {\n \t\t\tp_pdb->parent_flow_tbl[idx].pkt_count = 0;\n \t\t\tp_pdb->parent_flow_tbl[idx].byte_count = 0;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h\nindex 0ddfa6f66d..8680ee8f65 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h\n@@ -58,6 +58,7 @@ struct bnxt_ulp_flow_tbl {\n \n /* Structure to maintain parent-child flow relationships */\n struct ulp_fdb_parent_info {\n+\tuint32_t\tvalid;\n \tuint32_t\tparent_fid;\n \tuint32_t\tcounter_acc;\n \tuint64_t\tpkt_count;\n@@ -259,45 +260,38 @@ int32_t\n ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,\n \t\t\t\t   uint32_t flow_id,\n \t\t\t\t   uint16_t *cfa_action);\n-/*\n- * Allocate the entry in the parent-child database\n- *\n- * ulp_ctxt [in] Ptr to ulp_context\n- * fid [in] The flow id to the flow entry\n- *\n- * returns index on success and negative on failure.\n- */\n-int32_t\n-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t      uint32_t fid);\n \n /*\n- * Free the entry in the parent-child database\n+ * Set or reset the parent flow in the parent-child database\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * fid [in] The flow id to the flow entry\n+ * pc_idx [in] The index to parent child db\n+ * parent_fid [in] The flow id of the parent flow entry\n+ * set_flag [in] Use 1 for setting child, 0 to reset\n  *\n- * returns 0 on success and negative on failure.\n+ * returns zero on success and negative on failure.\n  */\n int32_t\n-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t     uint32_t fid);\n+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t\t  uint32_t pc_idx,\n+\t\t\t\t  uint32_t parent_fid,\n+\t\t\t\t  uint32_t set_flag);\n \n /*\n  * Set or reset the child flow in the parent-child database\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n+ * pc_idx [in] The index to parent child db\n  * child_fid [in] The flow id of the child flow entry\n  * set_flag [in] Use 1 for setting child, 0 to reset\n  *\n  * returns zero on success and negative on failure.\n  */\n int32_t\n-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t  uint32_t parent_fid,\n-\t\t\t\t  uint32_t child_fid,\n-\t\t\t\t  uint32_t set_flag);\n+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,\n+\t\t\t\t uint32_t pc_idx,\n+\t\t\t\t uint32_t child_fid,\n+\t\t\t\t uint32_t set_flag);\n \n /*\n  * Get the parent index from the parent-child database\n@@ -368,7 +362,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);\n  * Update the parent counters\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n+ * pc_idx [in] The parent flow entry idx\n  * packet_count [in] - packet count\n  * byte_count [in] - byte count\n  *\n@@ -376,14 +370,14 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);\n  */\n int32_t\n ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t     uint32_t parent_fid,\n+\t\t\t\t     uint32_t pc_idx,\n \t\t\t\t     uint64_t packet_count,\n \t\t\t\t     uint64_t byte_count);\n /*\n  * Get the parent accumulation counters\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n- * parent_fid [in] The flow id of the parent flow entry\n+ * pc_idx [in] The parent flow entry idx\n  * packet_count [out] - packet count\n  * byte_count [out] - byte count\n  *\n@@ -391,7 +385,7 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,\n  */\n int32_t\n ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,\n-\t\t\t\t  uint32_t parent_fid,\n+\t\t\t\t  uint32_t pc_idx,\n \t\t\t\t  uint64_t *packet_count,\n \t\t\t\t  uint64_t *byte_count,\n \t\t\t\t  uint8_t count_reset);\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\nindex 7fc3767b33..6d804c7ef9 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n@@ -544,34 +544,14 @@ ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp,\n \t\t\t    uint32_t parent_fid,\n \t\t\t    struct ulp_flow_db_res_params *res)\n {\n-\tuint32_t idx, child_fid = 0, parent_idx;\n-\tstruct bnxt_ulp_flow_db *flow_db;\n+\tuint32_t pc_idx;\n \n-\tparent_idx = (uint32_t)res->resource_hndl;\n+\tpc_idx = (uint32_t)res->resource_hndl;\n \n-\t/* check the validity of the parent fid */\n-\tif (ulp_flow_db_parent_flow_idx_get(ulp, parent_fid, &idx) ||\n-\t    idx != parent_idx) {\n-\t\tBNXT_TF_DBG(ERR, \"invalid parent flow id %x\\n\", parent_fid);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Clear all the child flows parent index */\n-\tflow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp);\n-\twhile (!ulp_flow_db_parent_child_flow_next_entry_get(flow_db, idx,\n-\t\t\t\t\t\t\t     &child_fid)) {\n-\t\t/* update the child flows resource handle */\n-\t\tif (ulp_flow_db_child_flow_reset(ulp, BNXT_ULP_FDB_TYPE_REGULAR,\n-\t\t\t\t\t\t child_fid)) {\n-\t\t\tBNXT_TF_DBG(ERR, \"failed to reset child flow %x\\n\",\n-\t\t\t\t    child_fid);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/* free the parent entry in the parent table flow */\n-\tif (ulp_flow_db_parent_flow_free(ulp, parent_fid)) {\n-\t\tBNXT_TF_DBG(ERR, \"failed to free parent flow %x\\n\", parent_fid);\n+\t/* reset the child flow bitset*/\n+\tif (ulp_flow_db_pc_db_parent_flow_set(ulp, pc_idx, parent_fid, 0)) {\n+\t\tBNXT_TF_DBG(ERR, \"error in reset parent flow bitset %x:%x\\n\",\n+\t\t\t    pc_idx, parent_fid);\n \t\treturn -EINVAL;\n \t}\n \treturn 0;\n@@ -582,16 +562,14 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp,\n \t\t\t   uint32_t child_fid,\n \t\t\t   struct ulp_flow_db_res_params *res)\n {\n-\tuint32_t parent_fid;\n+\tuint32_t pc_idx;\n \n-\tparent_fid = (uint32_t)res->resource_hndl;\n-\tif (!parent_fid)\n-\t\treturn 0; /* Already freed - orphan child*/\n+\tpc_idx = (uint32_t)res->resource_hndl;\n \n \t/* reset the child flow bitset*/\n-\tif (ulp_flow_db_parent_child_flow_set(ulp, parent_fid, child_fid, 0)) {\n+\tif (ulp_flow_db_pc_db_child_flow_set(ulp, pc_idx, child_fid, 0)) {\n \t\tBNXT_TF_DBG(ERR, \"error in resetting child flow bitset %x:%x\\n\",\n-\t\t\t    parent_fid, child_fid);\n+\t\t\t    pc_idx, child_fid);\n \t\treturn -EINVAL;\n \t}\n \treturn 0;\n@@ -1944,6 +1922,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \t\treturn -EINVAL;\n \t}\n \n+\t/* If only allocation of identifier then perform and exit */\n+\tif (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT) {\n+\t\trc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl);\n+\t\treturn rc;\n+\t}\n+\n \tkflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds);\n \tif (!kflds || !num_kflds) {\n \t\tBNXT_TF_DBG(ERR, \"Failed to get key fields\\n\");\n@@ -3889,7 +3873,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,\n \tparms.class_tid = cparms->class_tid;\n \tparms.flow_type = cparms->flow_type;\n \tparms.parent_flow = cparms->parent_flow;\n-\tparms.parent_fid = cparms->parent_fid;\n+\tparms.child_flow = cparms->child_flow;\n \tparms.fid = cparms->flow_id;\n \tparms.tun_idx = cparms->tun_idx;\n \tparms.app_priority = cparms->app_priority;\n@@ -3954,7 +3938,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,\n \t\trc = ulp_flow_db_parent_flow_create(&parms);\n \t\tif (rc)\n \t\t\tgoto flow_error;\n-\t} else if (parms.parent_fid) {\n+\t} else if (parms.child_flow) {\n \t\t/* create a child flow details */\n \t\trc = ulp_flow_db_child_flow_create(&parms);\n \t\tif (rc)\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h\nindex 004e89ac2b..d4d6969bb5 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h\n@@ -53,7 +53,7 @@ struct bnxt_ulp_mapper_parms {\n \tenum bnxt_ulp_fdb_type\t\t\tflow_type;\n \tstruct bnxt_ulp_mapper_data\t\t*mapper_data;\n \tstruct bnxt_ulp_device_params\t\t*device_params;\n-\tuint32_t\t\t\t\tparent_fid;\n+\tuint32_t\t\t\t\tchild_flow;\n \tuint32_t\t\t\t\tparent_flow;\n \tuint8_t\t\t\t\t\ttun_idx;\n \tuint32_t\t\t\t\tapp_priority;\n@@ -79,8 +79,8 @@ struct bnxt_ulp_mapper_create_parms {\n \tenum bnxt_ulp_fdb_type\t\tflow_type;\n \n \tuint32_t\t\t\tflow_id;\n-\t/* if set then create it as a child flow with parent as parent_fid */\n-\tuint32_t\t\t\tparent_fid;\n+\t/* if set then create it as a child flow */\n+\tuint32_t\t\t\tchild_flow;\n \t/* if set then create a parent flow */\n \tuint32_t\t\t\tparent_flow;\n \tuint8_t\t\t\t\ttun_idx;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c\nindex 35e9858727..9b165c12b5 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c\n@@ -215,6 +215,21 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {\n \t}\n };\n \n+struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {\n+\t[BNXT_RTE_FLOW_ACTION_TYPE_END - BNXT_RTE_FLOW_ACTION_TYPE_END] = {\n+\t.act_type                = BNXT_ULP_ACT_TYPE_END,\n+\t.proto_act_func          = NULL\n+\t},\n+\t[BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ACTION_TYPE_END] = {\n+\t.act_type                = BNXT_ULP_ACT_TYPE_SUPPORTED,\n+\t.proto_act_func          = ulp_vendor_vxlan_decap_act_handler\n+\t},\n+\t[BNXT_RTE_FLOW_ACTION_TYPE_LAST - BNXT_RTE_FLOW_ACTION_TYPE_END] = {\n+\t.act_type                = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,\n+\t.proto_act_func          = NULL\n+\t}\n+};\n+\n /*\n  * This table has to be indexed based on the rte_flow_item_type that is part of\n  * DPDK. The below array is list of parsing functions for each of the flow items\n@@ -414,3 +429,19 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {\n \t.proto_hdr_func          = NULL\n \t}\n };\n+\n+struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[] = {\n+\t[BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = {\n+\t.hdr_type                = BNXT_ULP_HDR_TYPE_END,\n+\t.proto_hdr_func          = NULL\n+\t},\n+\t[BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = {\n+\t.hdr_type                = BNXT_ULP_HDR_TYPE_SUPPORTED,\n+\t.proto_hdr_func          = ulp_rte_vendor_vxlan_decap_hdr_handler\n+\t},\n+\t[BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = {\n+\t.hdr_type                = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,\n+\t.proto_hdr_func          = NULL\n+\t},\n+\n+};\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\nindex 79b9957781..fadcd3873c 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n@@ -125,13 +125,21 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],\n \n \t/* Parse all the items in the pattern */\n \twhile (item && item->type != RTE_FLOW_ITEM_TYPE_END) {\n-\t\t/* get the header information from the flow_hdr_info table */\n-\t\thdr_info = &ulp_hdr_info[item->type];\n+\t\tif (item->type >= (uint32_t)\n+\t\t    BNXT_RTE_FLOW_ITEM_TYPE_END) {\n+\t\t\tif (item->type >=\n+\t\t\t    (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST)\n+\t\t\t\tgoto hdr_parser_error;\n+\t\t\t/* get the header information */\n+\t\t\thdr_info = &ulp_vendor_hdr_info[item->type -\n+\t\t\t\tBNXT_RTE_FLOW_ITEM_TYPE_END];\n+\t\t} else {\n+\t\t\tif (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)\n+\t\t\t\tgoto hdr_parser_error;\n+\t\t\thdr_info = &ulp_hdr_info[item->type];\n+\t\t}\n \t\tif (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_NOT_SUPPORTED) {\n-\t\t\tBNXT_TF_DBG(ERR,\n-\t\t\t\t    \"Truflow parser does not support type %d\\n\",\n-\t\t\t\t    item->type);\n-\t\t\treturn BNXT_TF_RC_PARSE_ERR;\n+\t\t\tgoto hdr_parser_error;\n \t\t} else if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_SUPPORTED) {\n \t\t\t/* call the registered callback handler */\n \t\t\tif (hdr_info->proto_hdr_func) {\n@@ -145,6 +153,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],\n \t}\n \t/* update the implied SVIF */\n \treturn ulp_rte_parser_implicit_match_port_process(params);\n+\n+hdr_parser_error:\n+\tBNXT_TF_DBG(ERR, \"Truflow parser does not support type %d\\n\",\n+\t\t    item->type);\n+\treturn BNXT_TF_RC_PARSE_ERR;\n }\n \n /*\n@@ -160,16 +173,23 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],\n \n \t/* Parse all the items in the pattern */\n \twhile (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {\n-\t\t/* get the header information from the flow_hdr_info table */\n-\t\thdr_info = &ulp_act_info[action_item->type];\n-\t\tif (hdr_info->act_type ==\n-\t\t    BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {\n-\t\t\tBNXT_TF_DBG(ERR,\n-\t\t\t\t    \"Truflow parser does not support act %u\\n\",\n-\t\t\t\t    action_item->type);\n-\t\t\treturn BNXT_TF_RC_ERROR;\n-\t\t} else if (hdr_info->act_type ==\n-\t\t    BNXT_ULP_ACT_TYPE_SUPPORTED) {\n+\t\tif (action_item->type >=\n+\t\t    (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) {\n+\t\t\tif (action_item->type >=\n+\t\t\t    (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST)\n+\t\t\t\tgoto act_parser_error;\n+\t\t\t/* get the header information from bnxt actinfo table */\n+\t\t\thdr_info = &ulp_vendor_act_info[action_item->type -\n+\t\t\t\tBNXT_RTE_FLOW_ACTION_TYPE_END];\n+\t\t} else {\n+\t\t\tif (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)\n+\t\t\t\tgoto act_parser_error;\n+\t\t\t/* get the header information from the act info table */\n+\t\t\thdr_info = &ulp_act_info[action_item->type];\n+\t\t}\n+\t\tif (hdr_info->act_type == BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {\n+\t\t\tgoto act_parser_error;\n+\t\t} else if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_SUPPORTED) {\n \t\t\t/* call the registered callback handler */\n \t\t\tif (hdr_info->proto_act_func) {\n \t\t\t\tif (hdr_info->proto_act_func(action_item,\n@@ -184,6 +204,11 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],\n \t/* update the implied port details */\n \tulp_rte_parser_implicit_act_port_process(params);\n \treturn BNXT_TF_RC_SUCCESS;\n+\n+act_parser_error:\n+\tBNXT_TF_DBG(ERR, \"Truflow parser does not support act %u\\n\",\n+\t\t    action_item->type);\n+\treturn BNXT_TF_RC_ERROR;\n }\n \n /*\n@@ -325,11 +350,10 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)\n /*\n  * Function to handle the post processing of the parsing details\n  */\n-int32_t\n+void\n bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)\n {\n \tulp_post_process_normal_flow(params);\n-\treturn ulp_post_process_tun_flow(params);\n }\n \n /*\n@@ -660,7 +684,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,\n {\n \tconst struct rte_flow_item_eth *eth_spec = item->spec;\n \tconst struct rte_flow_item_eth *eth_mask = item->mask;\n-\tuint32_t idx = 0;\n+\tuint32_t idx = 0, dmac_idx = 0;\n \tuint32_t size;\n \tuint16_t eth_type = 0;\n \tuint32_t inner_flag = 0;\n@@ -686,6 +710,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,\n \t * Copy the rte_flow_item for eth into hdr_field using ethernet\n \t * header fields\n \t */\n+\tdmac_idx = idx;\n \tsize = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes);\n \tulp_rte_prsr_fld_mask(params, &idx, size,\n \t\t\t      ulp_deference_struct(eth_spec, dst.addr_bytes),\n@@ -719,6 +744,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,\n \t\tinner_flag = 1;\n \t} else {\n \t\tULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID,\n+\t\t\t\t    dmac_idx);\n \t}\n \t/* Update the field protocol hdr bitmap */\n \tulp_rte_l2_proto_type_update(params, eth_type, inner_flag);\n@@ -926,7 +953,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,\n \tconst struct rte_flow_item_ipv4 *ipv4_spec = item->spec;\n \tconst struct rte_flow_item_ipv4 *ipv4_mask = item->mask;\n \tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n-\tuint32_t idx = 0;\n+\tuint32_t idx = 0, dip_idx = 0;\n \tuint32_t size;\n \tuint8_t proto = 0;\n \tuint32_t inner_flag = 0;\n@@ -939,22 +966,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,\n \t\treturn BNXT_TF_RC_ERROR;\n \t}\n \n-\tif (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n-\t\t\t      BNXT_ULP_HDR_BIT_O_ETH) &&\n-\t    !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n-\t\t\t      BNXT_ULP_HDR_BIT_I_ETH)) {\n-\t\t/* Since F2 flow does not include eth item, when parser detects\n-\t\t * IPv4/IPv6 item list and it belongs to the outer header; i.e.,\n-\t\t * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,\n-\t\t * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.\n-\t\t * This will allow the parser post processor to update the\n-\t\t * t_dmac in hdr_field[o_eth.dmac]\n-\t\t */\n-\t\tidx += (BNXT_ULP_PROTO_HDR_ETH_NUM +\n-\t\t\tBNXT_ULP_PROTO_HDR_VLAN_NUM);\n-\t\tparams->field_idx = idx;\n-\t}\n-\n \tif (ulp_rte_prsr_fld_size_validate(params, &idx,\n \t\t\t\t\t   BNXT_ULP_PROTO_HDR_IPV4_NUM)) {\n \t\tBNXT_TF_DBG(ERR, \"Error parsing protocol header\\n\");\n@@ -1033,6 +1044,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,\n \t\t\t      ulp_deference_struct(ipv4_mask, hdr.src_addr),\n \t\t\t      ULP_PRSR_ACT_DEFAULT);\n \n+\tdip_idx = idx;\n \tsize = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr);\n \tulp_rte_prsr_fld_mask(params, &idx, size,\n \t\t\t      ulp_deference_struct(ipv4_spec, hdr.dst_addr),\n@@ -1048,6 +1060,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,\n \t} else {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);\n \t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);\n+\t\t/* Update the tunnel offload dest ip offset */\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,\n+\t\t\t\t    dip_idx);\n \t}\n \n \t/* Some of the PMD applications may set the protocol field\n@@ -1071,7 +1086,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,\n \tconst struct rte_flow_item_ipv6\t*ipv6_spec = item->spec;\n \tconst struct rte_flow_item_ipv6\t*ipv6_mask = item->mask;\n \tstruct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;\n-\tuint32_t idx = 0;\n+\tuint32_t idx = 0, dip_idx = 0;\n \tuint32_t size;\n \tuint32_t ver_spec = 0, ver_mask = 0;\n \tuint32_t tc_spec = 0, tc_mask = 0;\n@@ -1087,22 +1102,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,\n \t\treturn BNXT_TF_RC_ERROR;\n \t}\n \n-\tif (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n-\t\t\t      BNXT_ULP_HDR_BIT_O_ETH) &&\n-\t    !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n-\t\t\t      BNXT_ULP_HDR_BIT_I_ETH)) {\n-\t\t/* Since F2 flow does not include eth item, when parser detects\n-\t\t * IPv4/IPv6 item list and it belongs to the outer header; i.e.,\n-\t\t * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,\n-\t\t * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.\n-\t\t * This will allow the parser post processor to update the\n-\t\t * t_dmac in hdr_field[o_eth.dmac]\n-\t\t */\n-\t\tidx += (BNXT_ULP_PROTO_HDR_ETH_NUM +\n-\t\t\tBNXT_ULP_PROTO_HDR_VLAN_NUM);\n-\t\tparams->field_idx = idx;\n-\t}\n-\n \tif (ulp_rte_prsr_fld_size_validate(params, &idx,\n \t\t\t\t\t   BNXT_ULP_PROTO_HDR_IPV6_NUM)) {\n \t\tBNXT_TF_DBG(ERR, \"Error parsing protocol header\\n\");\n@@ -1171,6 +1170,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,\n \t\t\t      ulp_deference_struct(ipv6_mask, hdr.src_addr),\n \t\t\t      ULP_PRSR_ACT_DEFAULT);\n \n+\tdip_idx =  idx;\n \tsize = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr);\n \tulp_rte_prsr_fld_mask(params, &idx, size,\n \t\t\t      ulp_deference_struct(ipv6_spec, hdr.dst_addr),\n@@ -1186,6 +1186,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,\n \t} else {\n \t\tULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);\n \t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);\n+\t\t/* Update the tunnel offload dest ip offset */\n+\t\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,\n+\t\t\t\t    dip_idx);\n \t}\n \n \t/* Update the field protocol hdr bitmap */\n@@ -1200,9 +1203,11 @@ static void\n ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,\n \t\t\t     uint16_t dst_port)\n {\n-\tif (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))\n+\tif (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {\n \t\tULP_BITMAP_SET(param->hdr_fp_bit.bits,\n \t\t\t       BNXT_ULP_HDR_BIT_T_VXLAN);\n+\t\tULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);\n+\t}\n \n \tif (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,\n \t\t\t     BNXT_ULP_HDR_BIT_T_VXLAN) ||\n@@ -2484,3 +2489,24 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,\n \n \treturn ret;\n }\n+\n+/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */\n+int32_t\n+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,\n+\t\t\t\t   struct ulp_rte_parser_params *params)\n+{\n+\t/* Set the F1 flow header bit */\n+\tULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);\n+\treturn ulp_rte_vxlan_decap_act_handler(action_item, params);\n+}\n+\n+/* Function to handle the parsing of bnxt vendor Flow item vxlan Header. */\n+int32_t\n+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,\n+\t\t\t\t       struct ulp_rte_parser_params *params)\n+{\n+\tRTE_SET_USED(item);\n+\t/* Set the F2 flow header bit */\n+\tULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);\n+\treturn ulp_rte_vxlan_decap_act_handler(NULL, params);\n+}\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h\nindex 4431f1bbd0..673172c811 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h\n@@ -75,7 +75,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],\n /*\n  * Function to handle the post processing of the parsing details\n  */\n-int32_t\n+void\n bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);\n \n /* Function to handle the parsing of RTE Flow item PF Header. */\n@@ -270,4 +270,12 @@ int32_t\n ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,\n \t\t\t   struct ulp_rte_parser_params *params);\n \n+int32_t\n+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,\n+\t\t\t\t   struct ulp_rte_parser_params *params);\n+\n+int32_t\n+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,\n+\t\t\t\t       struct ulp_rte_parser_params *params);\n+\n #endif /* _ULP_RTE_PARSER_H_ */\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\nindex 0cbac66237..2685e63432 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n@@ -78,17 +78,19 @@ struct ulp_rte_parser_params {\n \tuint32_t\t\t\tpriority;\n \tuint32_t\t\t\tfid;\n \tuint32_t\t\t\tparent_flow;\n-\tuint32_t\t\t\tparent_fid;\n+\tuint32_t\t\t\tchild_flow;\n \tuint16_t\t\t\tfunc_id;\n \tuint16_t\t\t\tport_id;\n \tuint32_t\t\t\tclass_id;\n \tuint32_t\t\t\tact_tmpl;\n \tstruct bnxt_ulp_context\t\t*ulp_ctx;\n \tuint32_t\t\t\thdr_sig_id;\n-\tuint32_t\t\t\tflow_sig_id;\n+\tuint64_t\t\t\tflow_sig_id;\n \tuint32_t\t\t\tflow_pattern_id;\n \tuint32_t\t\t\tact_pattern_id;\n \tuint8_t\t\t\t\tapp_id;\n+\tuint8_t\t\t\t\ttun_idx;\n+\n };\n \n /* Flow Parser Header Information Structure */\n@@ -101,6 +103,7 @@ struct bnxt_ulp_rte_hdr_info {\n \n /* Flow Parser Header Information Structure Array defined in template source*/\n extern struct bnxt_ulp_rte_hdr_info\tulp_hdr_info[];\n+extern struct bnxt_ulp_rte_hdr_info\tulp_vendor_hdr_info[];\n \n /* Flow Parser Action Information Structure */\n struct bnxt_ulp_rte_act_info {\n@@ -113,6 +116,7 @@ struct bnxt_ulp_rte_act_info {\n \n /* Flow Parser Action Information Structure Array defined in template source*/\n extern struct bnxt_ulp_rte_act_info\tulp_act_info[];\n+extern struct bnxt_ulp_rte_act_info\tulp_vendor_act_info[];\n \n /* Flow Matcher structures */\n struct bnxt_ulp_header_match_info {\n@@ -136,7 +140,7 @@ struct bnxt_ulp_class_match_info {\n \tuint8_t\t\t\twc_pri;\n \tuint8_t\t\t\tapp_sig;\n \tuint32_t\t\thdr_sig_id;\n-\tuint32_t\t\tflow_sig_id;\n+\tuint64_t\t\tflow_sig_id;\n \tuint32_t\t\tflow_pattern_id;\n };\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c\nindex a1dd5b902c..7ce6740633 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c\n@@ -3,225 +3,111 @@\n  * All rights reserved.\n  */\n \n-#include <sys/queue.h>\n-\n-#include <rte_malloc.h>\n-\n+#include \"bnxt.h\"\n+#include \"bnxt_ulp.h\"\n #include \"ulp_tun.h\"\n-#include \"ulp_rte_parser.h\"\n-#include \"ulp_template_db_enum.h\"\n-#include \"ulp_template_struct.h\"\n-#include \"ulp_matcher.h\"\n-#include \"ulp_mapper.h\"\n-#include \"ulp_flow_db.h\"\n+#include \"ulp_utils.h\"\n \n-/* This function programs the outer tunnel flow in the hardware. */\n-static int32_t\n-ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,\n-\t\t\t   struct bnxt_tun_cache_entry *tun_entry,\n-\t\t\t   uint16_t tun_idx)\n+/* returns negative on error, 1 if new entry is allocated or zero if old */\n+int32_t\n+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,\n+\t\t\t struct rte_flow_tunnel *app_tunnel,\n+\t\t\t struct bnxt_flow_app_tun_ent **tun_entry)\n {\n-\tstruct bnxt_ulp_mapper_create_parms mparms = { 0 };\n-\tint ret;\n-\n-\t/* Reset the JUMP action bit in the action bitmap as we don't\n-\t * offload this action.\n-\t */\n-\tULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);\n-\n-\tULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);\n-\n-#ifdef\tRTE_LIBRTE_BNXT_TRUFLOW_DEBUG\n-#ifdef\tRTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER\n-\t/* Dump the rte flow pattern */\n-\tulp_parser_hdr_info_dump(params);\n-\t/* Dump the rte flow action */\n-\tulp_parser_act_info_dump(params);\n-#endif\n-#endif\n-\n-\tret = ulp_matcher_pattern_match(params, &params->class_id);\n-\tif (ret != BNXT_TF_RC_SUCCESS)\n-\t\tgoto err;\n+\tstruct bnxt_flow_app_tun_ent *tun_ent_list;\n+\tint32_t i, rc = 0, free_entry = -1;\n \n-\tret = ulp_matcher_action_match(params, &params->act_tmpl);\n-\tif (ret != BNXT_TF_RC_SUCCESS)\n-\t\tgoto err;\n-\n-\tparams->parent_flow = true;\n-\tbnxt_ulp_init_mapper_params(&mparms, params,\n-\t\t\t\t    BNXT_ULP_FDB_TYPE_REGULAR);\n-\tmparms.tun_idx = tun_idx;\n-\n-\t/* Call the ulp mapper to create the flow in the hardware. */\n-\tret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);\n-\tif (ret)\n-\t\tgoto err;\n-\n-\t/* Store the tunnel dmac in the tunnel cache table and use it while\n-\t * programming tunnel inner flow.\n-\t */\n-\tmemcpy(tun_entry->t_dmac,\n-\t       &params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,\n-\t       RTE_ETHER_ADDR_LEN);\n-\n-\ttun_entry->tun_flow_info[params->port_id].state =\n-\t\t\t\tBNXT_ULP_FLOW_STATE_TUN_O_OFFLD;\n-\ttun_entry->outer_tun_flow_id = params->fid;\n-\n-\t/* Tunnel outer flow  and it's related inner flows are correlated\n-\t * based on Tunnel Destination IP Address.\n-\t */\n-\tif (tun_entry->t_dst_ip_valid)\n-\t\tgoto done;\n-\tif (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))\n-\t\tmemcpy(&tun_entry->t_dst_ip,\n-\t\t       &params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,\n-\t\t       sizeof(rte_be32_t));\n-\telse\n-\t\tmemcpy(tun_entry->t_dst_ip6,\n-\t\t       &params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,\n-\t\t       sizeof(tun_entry->t_dst_ip6));\n-\ttun_entry->t_dst_ip_valid = true;\n+\ttun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);\n+\tif (!tun_ent_list) {\n+\t\tBNXT_TF_DBG(ERR, \"unable to get the app tunnel list\\n\");\n+\t\treturn -EINVAL;\n+\t}\n \n-done:\n-\treturn BNXT_TF_RC_FID;\n+\tfor (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {\n+\t\tif (!tun_ent_list[i].ref_cnt) {\n+\t\t\tif (free_entry < 0)\n+\t\t\t\tfree_entry = i;\n+\t\t} else {\n+\t\t\tif (!memcmp(&tun_ent_list[i].app_tunnel,\n+\t\t\t\t    app_tunnel,\n+\t\t\t\t    sizeof(struct rte_flow_tunnel))) {\n+\t\t\t\t*tun_entry =  &tun_ent_list[i];\n+\t\t\t\ttun_ent_list[free_entry].ref_cnt++;\n+\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif (free_entry >= 0) {\n+\t\t*tun_entry =  &tun_ent_list[free_entry];\n+\t\tmemcpy(&tun_ent_list[free_entry].app_tunnel, app_tunnel,\n+\t\t       sizeof(struct rte_flow_tunnel));\n+\t\ttun_ent_list[free_entry].ref_cnt = 1;\n+\t\trc = 1;\n+\t} else {\n+\t\tBNXT_TF_DBG(ERR, \"ulp app tunnel list is full\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n \n-err:\n-\tmemset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry));\n-\treturn BNXT_TF_RC_ERROR;\n+\treturn rc;\n }\n \n-/* This function programs the inner tunnel flow in the hardware. */\n-static void\n-ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry,\n-\t\t\t   struct ulp_rte_parser_params *tun_o_params)\n+void\n+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry)\n {\n-\tstruct bnxt_ulp_mapper_create_parms mparms = { 0 };\n-\tstruct ulp_per_port_flow_info *flow_info;\n-\tstruct ulp_rte_parser_params *inner_params;\n-\tint ret;\n-\n-\t/* Tunnel inner flow doesn't have tunnel dmac, use the tunnel\n-\t * dmac that was stored during F1 programming.\n-\t */\n-\tflow_info = &tun_entry->tun_flow_info[tun_o_params->port_id];\n-\tSTAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) {\n-\t\tmemcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],\n-\t\t       tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);\n-\t\tinner_params->parent_fid = tun_entry->outer_tun_flow_id;\n-\n-\t\tbnxt_ulp_init_mapper_params(&mparms, inner_params,\n-\t\t\t\t\t    BNXT_ULP_FDB_TYPE_REGULAR);\n-\n-\t\tret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms);\n-\t\tif (ret)\n-\t\t\tPMD_DRV_LOG(ERR,\n-\t\t\t\t    \"Failed to create inner tun flow, FID:%u.\",\n-\t\t\t\t    inner_params->fid);\n+\tif (tun_entry) {\n+\t\tif (tun_entry->ref_cnt) {\n+\t\t\ttun_entry->ref_cnt--;\n+\t\t\tif (!tun_entry->ref_cnt)\n+\t\t\t\tmemset(tun_entry, 0,\n+\t\t\t\t       sizeof(struct bnxt_flow_app_tun_ent));\n+\t\t}\n \t}\n }\n \n-/* This function either install outer tunnel flow & inner tunnel flow\n- * or just the outer tunnel flow based on the flow state.\n- */\n-static int32_t\n-ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,\n-\t\t\t     struct bnxt_tun_cache_entry *tun_entry,\n-\t\t\t     uint16_t tun_idx)\n+int32_t\n+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry)\n {\n-\tint ret;\n-\n-\tret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);\n-\tif (ret == BNXT_TF_RC_ERROR) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to create outer tunnel flow.\");\n-\t\treturn ret;\n-\t}\n+\tif (!tun_entry)\n+\t\treturn -EINVAL;\n \n-\t/* Install any cached tunnel inner flows that came before tunnel\n-\t * outer flow.\n-\t */\n-\tulp_install_inner_tun_flow(tun_entry, params);\n-\n-\treturn BNXT_TF_RC_FID;\n+\ttun_entry->action.type = (typeof(tun_entry->action.type))\n+\t\t\t      BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP;\n+\ttun_entry->action.conf = tun_entry;\n+\treturn 0;\n }\n \n-/* This function will be called if inner tunnel flow request comes before\n- * outer tunnel flow request.\n- */\n-static int32_t\n-ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,\n-\t\t\t\t      struct bnxt_tun_cache_entry *tun_entry)\n+int32_t\n+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry)\n {\n-\tstruct ulp_rte_parser_params *inner_tun_params;\n-\tstruct ulp_per_port_flow_info *flow_info;\n-\tint ret;\n-\n-#ifdef\tRTE_LIBRTE_BNXT_TRUFLOW_DEBUG\n-#ifdef\tRTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER\n-\t/* Dump the rte flow pattern */\n-\tulp_parser_hdr_info_dump(params);\n-\t/* Dump the rte flow action */\n-\tulp_parser_act_info_dump(params);\n-#endif\n-#endif\n-\n-\tret = ulp_matcher_pattern_match(params, &params->class_id);\n-\tif (ret != BNXT_TF_RC_SUCCESS)\n-\t\treturn BNXT_TF_RC_ERROR;\n-\n-\tret = ulp_matcher_action_match(params, &params->act_tmpl);\n-\tif (ret != BNXT_TF_RC_SUCCESS)\n-\t\treturn BNXT_TF_RC_ERROR;\n-\n-\t/* If Tunnel inner flow comes first then we can't install it in the\n-\t * hardware, because, Tunnel inner flow will not have L2 context\n-\t * information. So, just cache the Tunnel inner flow information\n-\t * and program it in the context of F1 flow installation.\n-\t */\n-\tflow_info = &tun_entry->tun_flow_info[params->port_id];\n-\tinner_tun_params = rte_zmalloc(\"ulp_inner_tun_params\",\n-\t\t\t\t       sizeof(struct ulp_rte_parser_params), 0);\n-\tif (!inner_tun_params)\n-\t\treturn BNXT_TF_RC_ERROR;\n-\tmemcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params));\n-\tSTAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params,\n-\t\t\t   next);\n-\tflow_info->tun_i_cnt++;\n-\n-\t/* F1 and it's related Tunnel inner flows are correlated based on\n-\t * Tunnel Destination IP Address. It could be already set, if\n-\t * the inner flow got offloaded first.\n-\t */\n-\tif (tun_entry->t_dst_ip_valid)\n-\t\tgoto done;\n-\tif (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))\n-\t\tmemcpy(&tun_entry->t_dst_ip,\n-\t\t       &params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,\n-\t\t       sizeof(rte_be32_t));\n-\telse\n-\t\tmemcpy(tun_entry->t_dst_ip6,\n-\t\t       &params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,\n-\t\t       sizeof(tun_entry->t_dst_ip6));\n-\ttun_entry->t_dst_ip_valid = true;\n-\n-done:\n-\treturn BNXT_TF_RC_FID;\n+\tif (!tun_entry)\n+\t\treturn -EINVAL;\n+\n+\ttun_entry->item.type = (typeof(tun_entry->item.type))\n+\t\t\t      BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP;\n+\ttun_entry->item.spec = tun_entry;\n+\ttun_entry->item.last = NULL;\n+\ttun_entry->item.mask = NULL;\n+\treturn 0;\n }\n \n-/* This function will be called if inner tunnel flow request comes after\n- * the outer tunnel flow request.\n- */\n-static int32_t\n-ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params,\n-\t\t\t\tstruct bnxt_tun_cache_entry *tun_entry)\n+struct bnxt_flow_app_tun_ent *\n+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx,\n+\t\t\tconst void *ctx)\n {\n-\tmemcpy(&params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],\n-\t       tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);\n+\tstruct bnxt_flow_app_tun_ent *tun_ent_list;\n+\tint32_t i;\n \n-\tparams->parent_fid = tun_entry->outer_tun_flow_id;\n+\ttun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);\n+\tif (!tun_ent_list) {\n+\t\tBNXT_TF_DBG(ERR, \"unable to get the app tunnel list\\n\");\n+\t\treturn NULL;\n+\t}\n \n-\treturn BNXT_TF_RC_NORMAL;\n+\tfor (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {\n+\t\tif (&tun_ent_list[i] == ctx)\n+\t\t\treturn &tun_ent_list[i];\n+\t}\n+\treturn NULL;\n }\n \n static int32_t\n@@ -229,203 +115,116 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params,\n \t\t  struct bnxt_tun_cache_entry **tun_entry,\n \t\t  uint16_t *tun_idx)\n {\n-\tint i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;\n+\tint32_t i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;\n \tstruct bnxt_tun_cache_entry *tun_tbl;\n-\tbool tun_entry_found = false, free_entry_found = false;\n+\tuint32_t dip_idx, dmac_idx, use_ipv4 = 0;\n \n \ttun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx);\n-\tif (!tun_tbl)\n+\tif (!tun_tbl) {\n+\t\tBNXT_TF_DBG(ERR, \"Error: could not get Tunnel table\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n+\t}\n+\n+\t/* get the outer destination ip field index */\n+\tdip_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID);\n+\tdmac_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID);\n+\tif (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))\n+\t\tuse_ipv4 = 1;\n \n \tfor (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {\n-\t\tif (!memcmp(&tun_tbl[i].t_dst_ip,\n-\t\t\t    &params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,\n-\t\t\t    sizeof(rte_be32_t)) ||\n-\t\t    !memcmp(&tun_tbl[i].t_dst_ip6,\n-\t\t\t    &params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,\n-\t\t\t    16)) {\n-\t\t\ttun_entry_found = true;\n-\t\t\tbreak;\n+\t\tif (!tun_tbl[i].t_dst_ip_valid) {\n+\t\t\tif (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)\n+\t\t\t\tfirst_free_entry = i;\n+\t\t\tcontinue;\n \t\t}\n-\n-\t\tif (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) {\n-\t\t\tfirst_free_entry = i;\n-\t\t\tfree_entry_found = true;\n+\t\t/* match on the destination ip of the tunnel */\n+\t\tif ((use_ipv4 && !memcmp(&tun_tbl[i].t_dst_ip,\n+\t\t\t\t\t params->hdr_field[dip_idx].spec,\n+\t\t\t\t\t sizeof(rte_be32_t))) ||\n+\t\t    (!use_ipv4 &&\n+\t\t     !memcmp(tun_tbl[i].t_dst_ip6,\n+\t\t\t     params->hdr_field[dip_idx].spec,\n+\t\t\t     sizeof(((struct bnxt_tun_cache_entry *)\n+\t\t\t\t     NULL)->t_dst_ip6)))) {\n+\t\t\t*tun_entry = &tun_tbl[i];\n+\t\t\t*tun_idx = i;\n+\t\t\treturn 0;\n \t\t}\n \t}\n-\n-\tif (tun_entry_found) {\n-\t\t*tun_entry = &tun_tbl[i];\n-\t\t*tun_idx = i;\n-\t} else {\n-\t\tif (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)\n-\t\t\treturn BNXT_TF_RC_ERROR;\n-\t\t*tun_entry = &tun_tbl[first_free_entry];\n-\t\t*tun_idx = first_free_entry;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int32_t\n-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)\n-{\n-\tbool inner_tun_sig, cache_inner_tun_flow;\n-\tbool outer_tun_reject, outer_tun_flow, inner_tun_flow;\n-\tenum bnxt_ulp_tun_flow_state flow_state;\n-\tstruct bnxt_tun_cache_entry *tun_entry;\n-\tuint32_t l3_tun, l3_tun_decap;\n-\tuint16_t tun_idx;\n-\tint rc;\n-\n-\t/* Computational fields that indicate it's a TUNNEL DECAP flow */\n-\tl3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN);\n-\tl3_tun_decap = ULP_COMP_FLD_IDX_RD(params,\n-\t\t\t\t\t   BNXT_ULP_CF_IDX_L3_TUN_DECAP);\n-\tif (!l3_tun)\n-\t\treturn BNXT_TF_RC_NORMAL;\n-\n-\trc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);\n-\tif (rc == BNXT_TF_RC_ERROR)\n-\t\treturn rc;\n-\n-\tif (params->port_id >= RTE_MAX_ETHPORTS)\n+\tif (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) {\n+\t\tBNXT_TF_DBG(ERR, \"Error: No entry available in tunnel table\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n-\tflow_state = tun_entry->tun_flow_info[params->port_id].state;\n-\t/* Outer tunnel flow validation */\n-\touter_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params);\n-\touter_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,\n-\t\t\t\t\t\t      outer_tun_flow);\n-\n-\t/* Inner tunnel flow validation */\n-\tinner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);\n-\tcache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state,\n-\t\t\t\t\t\t\t inner_tun_sig);\n-\tinner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);\n-\n-\tif (outer_tun_reject) {\n-\t\ttun_entry->outer_tun_rej_cnt++;\n-\t\tBNXT_TF_DBG(ERR,\n-\t\t\t    \"Tunnel F1 flow rejected, COUNT: %d\\n\",\n-\t\t\t    tun_entry->outer_tun_rej_cnt);\n \t}\n \n-\tif (outer_tun_reject)\n-\t\treturn BNXT_TF_RC_ERROR;\n-\telse if (cache_inner_tun_flow)\n-\t\treturn ulp_post_process_cache_inner_tun_flow(params, tun_entry);\n-\telse if (outer_tun_flow)\n-\t\treturn ulp_post_process_outer_tun_flow(params, tun_entry,\n-\t\t\t\t\t\t       tun_idx);\n-\telse if (inner_tun_flow)\n-\t\treturn ulp_post_process_inner_tun_flow(params, tun_entry);\n-\telse\n-\t\treturn BNXT_TF_RC_NORMAL;\n-}\n+\t*tun_idx = first_free_entry;\n+\t*tun_entry = &tun_tbl[first_free_entry];\n+\ttun_tbl[first_free_entry].t_dst_ip_valid = true;\n \n-void\n-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl)\n-{\n-\tstruct ulp_per_port_flow_info *flow_info;\n-\tint i, j;\n+\t/* Update the destination ip and mac */\n+\tif (use_ipv4)\n+\t\tmemcpy(&tun_tbl[first_free_entry].t_dst_ip,\n+\t\t       params->hdr_field[dip_idx].spec, sizeof(rte_be32_t));\n+\telse\n+\t\tmemcpy(tun_tbl[first_free_entry].t_dst_ip6,\n+\t\t       params->hdr_field[dip_idx].spec,\n+\t\t       sizeof(((struct bnxt_tun_cache_entry *)\n+\t\t\t\t     NULL)->t_dst_ip6));\n+\tmemcpy(tun_tbl[first_free_entry].t_dmac,\n+\t       params->hdr_field[dmac_idx].spec, RTE_ETHER_ADDR_LEN);\n \n-\tfor (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {\n-\t\tfor (j = 0; j < RTE_MAX_ETHPORTS; j++) {\n-\t\t\tflow_info = &tun_tbl[i].tun_flow_info[j];\n-\t\t\tSTAILQ_INIT(&flow_info->tun_i_prms_list);\n-\t\t}\n-\t}\n+\treturn 0;\n }\n \n+/* Tunnel API to delete the tunnel entry */\n void\n-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)\n+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,\n+\t\t\t       uint8_t tun_idx)\n {\n-\tstruct ulp_rte_parser_params *inner_params;\n-\tstruct ulp_per_port_flow_info *flow_info;\n-\tint j;\n-\n-\tfor (j = 0; j < RTE_MAX_ETHPORTS; j++) {\n-\t\tflow_info = &tun_tbl[tun_idx].tun_flow_info[j];\n-\t\tSTAILQ_FOREACH(inner_params,\n-\t\t\t       &flow_info->tun_i_prms_list,\n-\t\t\t       next) {\n-\t\t\tSTAILQ_REMOVE(&flow_info->tun_i_prms_list,\n-\t\t\t\t      inner_params,\n-\t\t\t\t      ulp_rte_parser_params, next);\n-\t\t\trte_free(inner_params);\n-\t\t}\n-\t}\n-\n-\tmemset(&tun_tbl[tun_idx], 0,\n-\t\t\tsizeof(struct bnxt_tun_cache_entry));\n-\n-\tfor (j = 0; j < RTE_MAX_ETHPORTS; j++) {\n-\t\tflow_info = &tun_tbl[tun_idx].tun_flow_info[j];\n-\t\tSTAILQ_INIT(&flow_info->tun_i_prms_list);\n-\t}\n+\tmemset(&tun_tbl[tun_idx], 0, sizeof(struct bnxt_tun_cache_entry));\n }\n \n-static bool\n-ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry,\n-\t\t\t   struct ulp_per_port_flow_info *flow_info,\n-\t\t\t   uint32_t fid)\n+/* Tunnel API to perform tunnel offload process when there is F1/F2 flows */\n+int32_t\n+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params)\n {\n-\tstruct ulp_rte_parser_params *inner_params;\n-\tint j;\n-\n-\tSTAILQ_FOREACH(inner_params,\n-\t\t       &flow_info->tun_i_prms_list,\n-\t\t       next) {\n-\t\tif (inner_params->fid == fid) {\n-\t\t\tSTAILQ_REMOVE(&flow_info->tun_i_prms_list,\n-\t\t\t\t      inner_params,\n-\t\t\t\t      ulp_rte_parser_params,\n-\t\t\t\t      next);\n-\t\t\trte_free(inner_params);\n-\t\t\tflow_info->tun_i_cnt--;\n-\t\t\t/* When a dpdk application offloads a duplicate\n-\t\t\t * tunnel inner flow on a port that it is not\n-\t\t\t * destined to, there won't be a tunnel outer flow\n-\t\t\t * associated with these duplicate tunnel inner flows.\n-\t\t\t * So, when the last tunnel inner flow ages out, the\n-\t\t\t * driver has to clear the tunnel entry, otherwise\n-\t\t\t * the tunnel entry cannot be reused.\n-\t\t\t */\n-\t\t\tif (!flow_info->tun_i_cnt &&\n-\t\t\t    flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) {\n-\t\t\t\tmemset(tun_entry, 0,\n-\t\t\t\t       sizeof(struct bnxt_tun_cache_entry));\n-\t\t\t\tfor (j = 0; j < RTE_MAX_ETHPORTS; j++)\n-\t\t\t\t\tSTAILQ_INIT(&flow_info->tun_i_prms_list);\n-\t\t\t}\n-\t\t\treturn true;\n-\t\t}\n-\t}\n+\tstruct bnxt_tun_cache_entry *tun_entry;\n+\tuint16_t tun_idx;\n+\tint32_t rc = BNXT_TF_RC_SUCCESS;\n \n-\treturn false;\n-}\n+\t/* Perform the tunnel offload only for F1 and F2 flows */\n+\tif (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n+\t\t\t      BNXT_ULP_HDR_BIT_F1) &&\n+\t    !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n+\t\t\t      BNXT_ULP_HDR_BIT_F2))\n+\t\treturn rc;\n \n-/* When a dpdk application offloads the same tunnel inner flow\n- * on all the uplink ports, a tunnel inner flow entry is cached\n- * even if it is not for the right uplink port. Such tunnel\n- * inner flows will eventually get aged out as there won't be\n- * any traffic on these ports. When such a flow destroy is\n- * called, cleanup the tunnel inner flow entry.\n- */\n-void\n-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid)\n-{\n-\tstruct ulp_per_port_flow_info *flow_info;\n-\tint i, j;\n+\t/* search for the tunnel entry if not found create one */\n+\trc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);\n+\tif (rc == BNXT_TF_RC_ERROR)\n+\t\treturn rc;\n \n-\tfor (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {\n-\t\tif (!tun_tbl[i].t_dst_ip_valid)\n-\t\t\tcontinue;\n-\t\tfor (j = 0; j < RTE_MAX_ETHPORTS; j++) {\n-\t\t\tflow_info = &tun_tbl[i].tun_flow_info[j];\n-\t\t\tif (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i],\n-\t\t\t\t\t\t       flow_info, fid) == true)\n-\t\t\t\treturn;\n-\t\t}\n+\t/* Tunnel offload for the outer Tunnel flow */\n+\tif (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n+\t\t\t     BNXT_ULP_HDR_BIT_F1)) {\n+\t\t/* Reset the JUMP action bit in the action bitmap as we don't\n+\t\t * offload this action.\n+\t\t */\n+\t\tULP_BITMAP_RESET(params->act_bitmap.bits,\n+\t\t\t\t BNXT_ULP_ACT_BIT_JUMP);\n+\t\tparams->parent_flow = true;\n+\t\tparams->tun_idx = tun_idx;\n+\t\ttun_entry->outer_tun_flow_id = params->fid;\n+\t} else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n+\t\t\t     BNXT_ULP_HDR_BIT_F2)) {\n+\t\tULP_BITMAP_RESET(params->hdr_bitmap.bits,\n+\t\t\t\t BNXT_ULP_HDR_BIT_F2);\n+\t\t/* add the vxlan decap action for F2 flows */\n+\t\tULP_BITMAP_SET(params->act_bitmap.bits,\n+\t\t\t       BNXT_ULP_ACT_BIT_VXLAN_DECAP);\n+\t\tparams->child_flow = true;\n+\t\tparams->tun_idx = tun_idx;\n+\t\tparams->parent_flow = false;\n \t}\n+\tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUNNEL_ID, tun_idx);\n+\treturn rc;\n }\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h\nindex 898071bfe7..0fc2ac39d1 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h\n@@ -8,7 +8,6 @@\n \n #include <inttypes.h>\n #include <stdbool.h>\n-#include <sys/queue.h>\n \n #include \"rte_version.h\"\n #include \"rte_ethdev.h\"\n@@ -16,60 +15,6 @@\n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_struct.h\"\n \n-#define\tBNXT_OUTER_TUN_FLOW(l3_tun, params)\t\t\\\n-\t((l3_tun) &&\t\t\t\t\t\\\n-\t ULP_BITMAP_ISSET((params)->act_bitmap.bits,\t\\\n-\t\t\t  BNXT_ULP_ACT_BIT_JUMP))\n-#define\tBNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params)\t\t\\\n-\t((l3_tun) && (l3_tun_decap) &&\t\t\t\t\t\\\n-\t !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits,\t\t\t\\\n-\t\t\t   BNXT_ULP_HDR_BIT_O_ETH))\n-\n-#define\tBNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig)\t\\\n-\t((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))\n-#define\tBNXT_INNER_TUN_FLOW(state, inner_tun_sig)\t\t\\\n-\t((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))\n-\n-/* It is invalid to get another outer flow offload request\n- * for the same tunnel, while the outer flow is already offloaded.\n- */\n-#define\tBNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig)\t\\\n-\t((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))\n-\n-#define\tULP_TUN_O_DMAC_HDR_FIELD_INDEX\t1\n-#define\tULP_TUN_O_IPV4_DIP_INDEX\t19\n-#define\tULP_TUN_O_IPV6_DIP_INDEX\t17\n-\n-/* When a flow offload request comes the following state transitions\n- * happen based on the order in which the outer & inner flow offload\n- * requests arrive.\n- *\n- * If inner tunnel flow offload request arrives first then the flow\n- * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state.\n- * The following outer tunnel flow offload request will change the\n- * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from\n- * BNXT_ULP_FLOW_STATE_NORMAL.\n- *\n- * If outer tunnel flow offload request arrives first then the flow state\n- * will change from BNXT_ULP_FLOW_STATE_NORMAL to\n- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD.\n- *\n- * Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner\n- * tunnel flow offload requests after that point will be treated as a\n- * normal flow and the tunnel flow state remains in\n- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD\n- */\n-enum bnxt_ulp_tun_flow_state {\n-\tBNXT_ULP_FLOW_STATE_NORMAL = 0,\n-\tBNXT_ULP_FLOW_STATE_TUN_O_OFFLD,\n-};\n-\n-struct ulp_per_port_flow_info {\n-\tenum bnxt_ulp_tun_flow_state\t\tstate;\n-\tuint32_t\t\t\t\ttun_i_cnt;\n-\tSTAILQ_HEAD(, ulp_rte_parser_params)\ttun_i_prms_list;\n-};\n-\n struct bnxt_tun_cache_entry {\n \tbool\t\t\t\tt_dst_ip_valid;\n \tuint8_t\t\t\t\tt_dmac[RTE_ETHER_ADDR_LEN];\n@@ -78,17 +23,39 @@ struct bnxt_tun_cache_entry {\n \t\tuint8_t\t\t\tt_dst_ip6[16];\n \t};\n \tuint32_t\t\t\touter_tun_flow_id;\n-\tuint16_t\t\t\touter_tun_rej_cnt;\n-\tstruct ulp_per_port_flow_info\ttun_flow_info[RTE_MAX_ETHPORTS];\n };\n \n-void\n-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl);\n+struct bnxt_flow_app_tun_ent {\n+\tstruct rte_flow_tunnel\t\t\tapp_tunnel;\n+\tuint32_t\t\t\t\ttun_id;\n+\tuint32_t\t\t\t\tref_cnt;\n+\tstruct rte_flow_action\t\t\taction;\n+\tstruct rte_flow_item\t\t\titem;\n+};\n+\n+int32_t\n+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,\n+\t\t\t struct rte_flow_tunnel *app_tunnel,\n+\t\t\t struct bnxt_flow_app_tun_ent **tun_entry);\n \n void\n-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);\n+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry);\n \n+int32_t\n+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry);\n+\n+int32_t\n+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry);\n+\n+struct bnxt_flow_app_tun_ent *\n+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, const void *ctx);\n+\n+/* Tunnel API to delete the tunnel entry */\n void\n-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid);\n+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,\n+\t\t\t       uint8_t tun_idx);\n+\n+int32_t\n+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);\n \n #endif\n",
    "prefixes": [
        "v3",
        "06/13"
    ]
}