Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/987/?format=api
{ "id": 987, "url": "http://patches.dpdk.org/api/patches/987/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1414500657-23774-9-git-send-email-david.marchand@6wind.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1414500657-23774-9-git-send-email-david.marchand@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1414500657-23774-9-git-send-email-david.marchand@6wind.com", "date": "2014-10-28T12:50:55", "name": "[dpdk-dev,v3,08/10] eal: split CPU flags operations to architecture specific", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "eae9f84173126b8592d068e38dc1774bd21bd9bc", "submitter": { "id": 3, "url": "http://patches.dpdk.org/api/people/3/?format=api", "name": "David Marchand", "email": "david.marchand@6wind.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1414500657-23774-9-git-send-email-david.marchand@6wind.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/987/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/987/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5CC477F28;\n\tTue, 28 Oct 2014 13:42:43 +0100 (CET)", "from mail-wi0-f171.google.com (mail-wi0-f171.google.com\n\t[209.85.212.171]) by dpdk.org (Postfix) with ESMTP id F22D57F1C\n\tfor <dev@dpdk.org>; Tue, 28 Oct 2014 13:42:29 +0100 (CET)", "by mail-wi0-f171.google.com with SMTP id hi2so5637874wib.4\n\tfor <dev@dpdk.org>; Tue, 28 Oct 2014 05:51:17 -0700 (PDT)", "from alcyon.dev.6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by mx.google.com with ESMTPSA id\n\tht9sm15314425wib.8.2014.10.28.05.51.15 for <multiple recipients>\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 28 Oct 2014 05:51:16 -0700 (PDT)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=ZgysmC9fNStNSt16O/Vn6mlIzGEba2tI2doE3a7+Zn0=;\n\tb=mbbl/wNwurzWeMT1ZJmv+lxEk6+Ad1knH1+6ewLPhYpYnbKxWN4erShpvuFxfWjuqp\n\tYFqRjPetHWh15PtVSzOL8V8d4+W9JCKET0wycLsA39lURGVVlP0+vZs5wvHgkdhw/CPQ\n\tJpKJKWKhe39zg4TQwQxDAmUt1biPpghaXgCoQe+loFtHSmxEwVr0/e+YGDov7eAZ9yCs\n\tQtPSzDwGQqtvtL4kdLzkf/I5HpxYwQpPTpUvVgLNld60jkopKEnCIpRxhfRlnJrTBf3u\n\t8+A/dWeFx4pwYzMPZNaWDY2Mr9hBacEjSRLNkoUD+ykYU1yhrFjm+QZSlkcxOzqXY7ik\n\t3Mvg==", "X-Gm-Message-State": "ALoCoQmDjPplULlH6NSzI+GCymOVDG/VdPi2FptTPpLEZTyJKywMKXJpRBUUHlJAejBUtJ6C3Vzj", "X-Received": "by 10.180.221.129 with SMTP id qe1mr4576779wic.21.1414500677113; \n\tTue, 28 Oct 2014 05:51:17 -0700 (PDT)", "From": "David Marchand <david.marchand@6wind.com>", "To": "dev@dpdk.org", "Date": "Tue, 28 Oct 2014 13:50:55 +0100", "Message-Id": "<1414500657-23774-9-git-send-email-david.marchand@6wind.com>", "X-Mailer": "git-send-email 1.7.10.4", "In-Reply-To": "<1414500657-23774-1-git-send-email-david.marchand@6wind.com>", "References": "<1414500657-23774-1-git-send-email-david.marchand@6wind.com>", "Cc": "bjzhuc@cn.ibm.com", "Subject": "[dpdk-dev] [PATCH v3 08/10] eal: split CPU flags operations to\n\tarchitecture specific", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Chao Zhu <bjzhuc@cn.ibm.com>\n\nThis patch splits CPU flags related operations from DPDK and push them\nto architecture specific arch directories, so that other processor\narchitecture can implement its own CPU flag functions to support DPDK.\n\nSigned-off-by: Chao Zhu <bjzhuc@cn.ibm.com>\nSigned-off-by: David Marchand <david.marchand@6wind.com>\n---\n lib/librte_eal/common/Makefile | 4 +-\n lib/librte_eal/common/eal_common_cpuflags.c | 190 ------------\n .../common/include/arch/i686/rte_cpuflags.h | 310 ++++++++++++++++++++\n .../common/include/arch/x86_64/rte_cpuflags.h | 310 ++++++++++++++++++++\n .../common/include/generic/rte_cpuflags.h | 110 +++++++\n lib/librte_eal/common/include/rte_cpuflags.h | 182 ------------\n 6 files changed, 732 insertions(+), 374 deletions(-)\n create mode 100644 lib/librte_eal/common/include/arch/i686/rte_cpuflags.h\n create mode 100644 lib/librte_eal/common/include/arch/x86_64/rte_cpuflags.h\n create mode 100644 lib/librte_eal/common/include/generic/rte_cpuflags.h\n delete mode 100644 lib/librte_eal/common/include/rte_cpuflags.h", "diff": "diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex f9f98dc..ddf8b48 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -36,7 +36,7 @@ INC += rte_debug.h rte_eal.h rte_errno.h rte_launch.h rte_lcore.h\n INC += rte_log.h rte_memory.h rte_memzone.h rte_pci.h\n INC += rte_pci_dev_ids.h rte_per_lcore.h rte_random.h\n INC += rte_rwlock.h rte_tailq.h rte_interrupts.h rte_alarm.h\n-INC += rte_string_fns.h rte_cpuflags.h rte_version.h rte_tailq_elem.h\n+INC += rte_string_fns.h rte_version.h rte_tailq_elem.h\n INC += rte_eal_memconfig.h rte_malloc_heap.h\n INC += rte_hexdump.h rte_devargs.h rte_dev.h\n INC += rte_common_vect.h\n@@ -47,7 +47,7 @@ INC += rte_warnings.h\n endif\n \n GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\n-GENERIC_INC += rte_spinlock.h rte_memcpy.h\n+GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h\n ARCH_INC := $(GENERIC_INC)\n \n SYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include := $(addprefix include/,$(INC))\ndiff --git a/lib/librte_eal/common/eal_common_cpuflags.c b/lib/librte_eal/common/eal_common_cpuflags.c\nindex 9e79179..6fd360c 100644\n--- a/lib/librte_eal/common/eal_common_cpuflags.c\n+++ b/lib/librte_eal/common/eal_common_cpuflags.c\n@@ -30,10 +30,6 @@\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n-#include <stdlib.h>\n-#include <stdio.h>\n-#include <errno.h>\n-#include <stdint.h>\n #include <rte_cpuflags.h>\n \n /*\n@@ -50,192 +46,6 @@\n #endif\n \n /**\n- * Enumeration of CPU registers\n- */\n-enum cpu_register_t {\n-\tREG_EAX = 0,\n-\tREG_EBX,\n-\tREG_ECX,\n-\tREG_EDX,\n-};\n-\n-typedef uint32_t cpuid_registers_t[4];\n-\n-#define CPU_FLAG_NAME_MAX_LEN 64\n-\n-/**\n- * Struct to hold a processor feature entry\n- */\n-struct feature_entry {\n-\tuint32_t leaf;\t\t\t\t/**< cpuid leaf */\n-\tuint32_t subleaf;\t\t\t/**< cpuid subleaf */\n-\tuint32_t reg;\t\t\t\t/**< cpuid register */\n-\tuint32_t bit;\t\t\t\t/**< cpuid register bit */\n-\tchar name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */\n-};\n-\n-#define FEAT_DEF(name, leaf, subleaf, reg, bit) \\\n-\t[RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },\n-\n-/**\n- * An array that holds feature entries\n- */\n-static const struct feature_entry cpu_feature_table[] = {\n-\tFEAT_DEF(SSE3, 0x00000001, 0, REG_ECX, 0)\n-\tFEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX, 1)\n-\tFEAT_DEF(DTES64, 0x00000001, 0, REG_ECX, 2)\n-\tFEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX, 3)\n-\tFEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX, 4)\n-\tFEAT_DEF(VMX, 0x00000001, 0, REG_ECX, 5)\n-\tFEAT_DEF(SMX, 0x00000001, 0, REG_ECX, 6)\n-\tFEAT_DEF(EIST, 0x00000001, 0, REG_ECX, 7)\n-\tFEAT_DEF(TM2, 0x00000001, 0, REG_ECX, 8)\n-\tFEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX, 9)\n-\tFEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)\n-\tFEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)\n-\tFEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)\n-\tFEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)\n-\tFEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)\n-\tFEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)\n-\tFEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)\n-\tFEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)\n-\tFEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)\n-\tFEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)\n-\tFEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)\n-\tFEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)\n-\tFEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)\n-\tFEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)\n-\tFEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)\n-\tFEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)\n-\tFEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)\n-\tFEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)\n-\tFEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)\n-\n-\tFEAT_DEF(FPU, 0x00000001, 0, REG_EDX, 0)\n-\tFEAT_DEF(VME, 0x00000001, 0, REG_EDX, 1)\n-\tFEAT_DEF(DE, 0x00000001, 0, REG_EDX, 2)\n-\tFEAT_DEF(PSE, 0x00000001, 0, REG_EDX, 3)\n-\tFEAT_DEF(TSC, 0x00000001, 0, REG_EDX, 4)\n-\tFEAT_DEF(MSR, 0x00000001, 0, REG_EDX, 5)\n-\tFEAT_DEF(PAE, 0x00000001, 0, REG_EDX, 6)\n-\tFEAT_DEF(MCE, 0x00000001, 0, REG_EDX, 7)\n-\tFEAT_DEF(CX8, 0x00000001, 0, REG_EDX, 8)\n-\tFEAT_DEF(APIC, 0x00000001, 0, REG_EDX, 9)\n-\tFEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)\n-\tFEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)\n-\tFEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)\n-\tFEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)\n-\tFEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)\n-\tFEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)\n-\tFEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)\n-\tFEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)\n-\tFEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)\n-\tFEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)\n-\tFEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)\n-\tFEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)\n-\tFEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)\n-\tFEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)\n-\tFEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)\n-\tFEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)\n-\tFEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)\n-\tFEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)\n-\tFEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)\n-\n-\tFEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX, 0)\n-\tFEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX, 1)\n-\tFEAT_DEF(ARAT, 0x00000006, 0, REG_EAX, 2)\n-\tFEAT_DEF(PLN, 0x00000006, 0, REG_EAX, 4)\n-\tFEAT_DEF(ECMD, 0x00000006, 0, REG_EAX, 5)\n-\tFEAT_DEF(PTM, 0x00000006, 0, REG_EAX, 6)\n-\n-\tFEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX, 0)\n-\tFEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX, 1)\n-\tFEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX, 3)\n-\n-\tFEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX, 0)\n-\tFEAT_DEF(BMI1, 0x00000007, 0, REG_EBX, 2)\n-\tFEAT_DEF(HLE, 0x00000007, 0, REG_EBX, 4)\n-\tFEAT_DEF(AVX2, 0x00000007, 0, REG_EBX, 5)\n-\tFEAT_DEF(SMEP, 0x00000007, 0, REG_EBX, 6)\n-\tFEAT_DEF(BMI2, 0x00000007, 0, REG_EBX, 7)\n-\tFEAT_DEF(ERMS, 0x00000007, 0, REG_EBX, 8)\n-\tFEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)\n-\tFEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)\n-\n-\tFEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX, 0)\n-\tFEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX, 4)\n-\n-\tFEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)\n-\tFEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)\n-\tFEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)\n-\tFEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)\n-\tFEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)\n-\n-\tFEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX, 8)\n-};\n-\n-/*\n- * Execute CPUID instruction and get contents of a specific register\n- *\n- * This function, when compiled with GCC, will generate architecture-neutral\n- * code, as per GCC manual.\n- */\n-static inline void\n-rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)\n-{\n-#if defined(__i386__) && defined(__PIC__)\n- /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */\n- asm volatile(\"movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0\"\n-\t\t : \"=r\" (out[REG_EBX]),\n-\t\t \"=a\" (out[REG_EAX]),\n-\t\t \"=c\" (out[REG_ECX]),\n-\t\t \"=d\" (out[REG_EDX])\n-\t\t : \"a\" (leaf), \"c\" (subleaf));\n-#else\n-\n- asm volatile(\"cpuid\"\n-\t\t : \"=a\" (out[REG_EAX]),\n-\t\t \"=b\" (out[REG_EBX]),\n-\t\t \"=c\" (out[REG_ECX]),\n-\t\t \"=d\" (out[REG_EDX])\n-\t\t : \"a\" (leaf), \"c\" (subleaf));\n-\n-#endif\n-}\n-\n-/*\n- * Checks if a particular flag is available on current machine.\n- */\n-int\n-rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n-{\n-\tconst struct feature_entry *feat;\n-\tcpuid_registers_t regs;\n-\n-\n-\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n-\t\t/* Flag does not match anything in the feature tables */\n-\t\treturn -ENOENT;\n-\n-\tfeat = &cpu_feature_table[feature];\n-\n-\tif (!feat->leaf)\n-\t\t/* This entry in the table wasn't filled out! */\n-\t\treturn -EFAULT;\n-\n-\trte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);\n-\tif (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||\n-\t regs[REG_EAX] < feat->leaf)\n-\t\treturn 0;\n-\n-\t/* get the cpuid leaf containing the desired feature */\n-\trte_cpu_get_features(feat->leaf, feat->subleaf, regs);\n-\n-\t/* check if the feature is enabled */\n-\treturn (regs[feat->reg] >> feat->bit) & 1;\n-}\n-\n-/**\n * Checks if the machine is adequate for running the binary. If it is not, the\n * program exits with status 1.\n * The function attribute forces this function to be called before main(). But\ndiff --git a/lib/librte_eal/common/include/arch/i686/rte_cpuflags.h b/lib/librte_eal/common/include/arch/i686/rte_cpuflags.h\nnew file mode 100644\nindex 0000000..fd27e8f\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/i686/rte_cpuflags.h\n@@ -0,0 +1,310 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_CPUFLAGS_I686_H_\n+#define _RTE_CPUFLAGS_I686_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include <stdint.h>\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+enum rte_cpu_flag_t {\n+\t/* (EAX 01h) ECX features*/\n+\tRTE_CPUFLAG_SSE3 = 0, /**< SSE3 */\n+\tRTE_CPUFLAG_PCLMULQDQ, /**< PCLMULQDQ */\n+\tRTE_CPUFLAG_DTES64, /**< DTES64 */\n+\tRTE_CPUFLAG_MONITOR, /**< MONITOR */\n+\tRTE_CPUFLAG_DS_CPL, /**< DS_CPL */\n+\tRTE_CPUFLAG_VMX, /**< VMX */\n+\tRTE_CPUFLAG_SMX, /**< SMX */\n+\tRTE_CPUFLAG_EIST, /**< EIST */\n+\tRTE_CPUFLAG_TM2, /**< TM2 */\n+\tRTE_CPUFLAG_SSSE3, /**< SSSE3 */\n+\tRTE_CPUFLAG_CNXT_ID, /**< CNXT_ID */\n+\tRTE_CPUFLAG_FMA, /**< FMA */\n+\tRTE_CPUFLAG_CMPXCHG16B, /**< CMPXCHG16B */\n+\tRTE_CPUFLAG_XTPR, /**< XTPR */\n+\tRTE_CPUFLAG_PDCM, /**< PDCM */\n+\tRTE_CPUFLAG_PCID, /**< PCID */\n+\tRTE_CPUFLAG_DCA, /**< DCA */\n+\tRTE_CPUFLAG_SSE4_1, /**< SSE4_1 */\n+\tRTE_CPUFLAG_SSE4_2, /**< SSE4_2 */\n+\tRTE_CPUFLAG_X2APIC, /**< X2APIC */\n+\tRTE_CPUFLAG_MOVBE, /**< MOVBE */\n+\tRTE_CPUFLAG_POPCNT, /**< POPCNT */\n+\tRTE_CPUFLAG_TSC_DEADLINE, /**< TSC_DEADLINE */\n+\tRTE_CPUFLAG_AES, /**< AES */\n+\tRTE_CPUFLAG_XSAVE, /**< XSAVE */\n+\tRTE_CPUFLAG_OSXSAVE, /**< OSXSAVE */\n+\tRTE_CPUFLAG_AVX, /**< AVX */\n+\tRTE_CPUFLAG_F16C, /**< F16C */\n+\tRTE_CPUFLAG_RDRAND, /**< RDRAND */\n+\n+\t/* (EAX 01h) EDX features */\n+\tRTE_CPUFLAG_FPU, /**< FPU */\n+\tRTE_CPUFLAG_VME, /**< VME */\n+\tRTE_CPUFLAG_DE, /**< DE */\n+\tRTE_CPUFLAG_PSE, /**< PSE */\n+\tRTE_CPUFLAG_TSC, /**< TSC */\n+\tRTE_CPUFLAG_MSR, /**< MSR */\n+\tRTE_CPUFLAG_PAE, /**< PAE */\n+\tRTE_CPUFLAG_MCE, /**< MCE */\n+\tRTE_CPUFLAG_CX8, /**< CX8 */\n+\tRTE_CPUFLAG_APIC, /**< APIC */\n+\tRTE_CPUFLAG_SEP, /**< SEP */\n+\tRTE_CPUFLAG_MTRR, /**< MTRR */\n+\tRTE_CPUFLAG_PGE, /**< PGE */\n+\tRTE_CPUFLAG_MCA, /**< MCA */\n+\tRTE_CPUFLAG_CMOV, /**< CMOV */\n+\tRTE_CPUFLAG_PAT, /**< PAT */\n+\tRTE_CPUFLAG_PSE36, /**< PSE36 */\n+\tRTE_CPUFLAG_PSN, /**< PSN */\n+\tRTE_CPUFLAG_CLFSH, /**< CLFSH */\n+\tRTE_CPUFLAG_DS, /**< DS */\n+\tRTE_CPUFLAG_ACPI, /**< ACPI */\n+\tRTE_CPUFLAG_MMX, /**< MMX */\n+\tRTE_CPUFLAG_FXSR, /**< FXSR */\n+\tRTE_CPUFLAG_SSE, /**< SSE */\n+\tRTE_CPUFLAG_SSE2, /**< SSE2 */\n+\tRTE_CPUFLAG_SS, /**< SS */\n+\tRTE_CPUFLAG_HTT, /**< HTT */\n+\tRTE_CPUFLAG_TM, /**< TM */\n+\tRTE_CPUFLAG_PBE, /**< PBE */\n+\n+\t/* (EAX 06h) EAX features */\n+\tRTE_CPUFLAG_DIGTEMP, /**< DIGTEMP */\n+\tRTE_CPUFLAG_TRBOBST, /**< TRBOBST */\n+\tRTE_CPUFLAG_ARAT, /**< ARAT */\n+\tRTE_CPUFLAG_PLN, /**< PLN */\n+\tRTE_CPUFLAG_ECMD, /**< ECMD */\n+\tRTE_CPUFLAG_PTM, /**< PTM */\n+\n+\t/* (EAX 06h) ECX features */\n+\tRTE_CPUFLAG_MPERF_APERF_MSR, /**< MPERF_APERF_MSR */\n+\tRTE_CPUFLAG_ACNT2, /**< ACNT2 */\n+\tRTE_CPUFLAG_ENERGY_EFF, /**< ENERGY_EFF */\n+\n+\t/* (EAX 07h, ECX 0h) EBX features */\n+\tRTE_CPUFLAG_FSGSBASE, /**< FSGSBASE */\n+\tRTE_CPUFLAG_BMI1, /**< BMI1 */\n+\tRTE_CPUFLAG_HLE, /**< Hardware Lock elision */\n+\tRTE_CPUFLAG_AVX2, /**< AVX2 */\n+\tRTE_CPUFLAG_SMEP, /**< SMEP */\n+\tRTE_CPUFLAG_BMI2, /**< BMI2 */\n+\tRTE_CPUFLAG_ERMS, /**< ERMS */\n+\tRTE_CPUFLAG_INVPCID, /**< INVPCID */\n+\tRTE_CPUFLAG_RTM, /**< Transactional memory */\n+\n+\t/* (EAX 80000001h) ECX features */\n+\tRTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */\n+\tRTE_CPUFLAG_LZCNT, /**< LZCNT */\n+\n+\t/* (EAX 80000001h) EDX features */\n+\tRTE_CPUFLAG_SYSCALL, /**< SYSCALL */\n+\tRTE_CPUFLAG_XD, /**< XD */\n+\tRTE_CPUFLAG_1GB_PG, /**< 1GB_PG */\n+\tRTE_CPUFLAG_RDTSCP, /**< RDTSCP */\n+\tRTE_CPUFLAG_EM64T, /**< EM64T */\n+\n+\t/* (EAX 80000007h) EDX features */\n+\tRTE_CPUFLAG_INVTSC, /**< INVTSC */\n+\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */\n+};\n+\n+enum cpu_register_t {\n+\tREG_EAX = 0,\n+\tREG_EBX,\n+\tREG_ECX,\n+\tREG_EDX,\n+};\n+\n+static const struct feature_entry cpu_feature_table[] = {\n+\tFEAT_DEF(SSE3, 0x00000001, 0, REG_ECX, 0)\n+\tFEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX, 1)\n+\tFEAT_DEF(DTES64, 0x00000001, 0, REG_ECX, 2)\n+\tFEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX, 3)\n+\tFEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX, 4)\n+\tFEAT_DEF(VMX, 0x00000001, 0, REG_ECX, 5)\n+\tFEAT_DEF(SMX, 0x00000001, 0, REG_ECX, 6)\n+\tFEAT_DEF(EIST, 0x00000001, 0, REG_ECX, 7)\n+\tFEAT_DEF(TM2, 0x00000001, 0, REG_ECX, 8)\n+\tFEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX, 9)\n+\tFEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)\n+\tFEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)\n+\tFEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)\n+\tFEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)\n+\tFEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)\n+\tFEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)\n+\tFEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)\n+\tFEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)\n+\tFEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)\n+\tFEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)\n+\tFEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)\n+\tFEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)\n+\tFEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)\n+\tFEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)\n+\tFEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)\n+\tFEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)\n+\tFEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)\n+\tFEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)\n+\tFEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)\n+\n+\tFEAT_DEF(FPU, 0x00000001, 0, REG_EDX, 0)\n+\tFEAT_DEF(VME, 0x00000001, 0, REG_EDX, 1)\n+\tFEAT_DEF(DE, 0x00000001, 0, REG_EDX, 2)\n+\tFEAT_DEF(PSE, 0x00000001, 0, REG_EDX, 3)\n+\tFEAT_DEF(TSC, 0x00000001, 0, REG_EDX, 4)\n+\tFEAT_DEF(MSR, 0x00000001, 0, REG_EDX, 5)\n+\tFEAT_DEF(PAE, 0x00000001, 0, REG_EDX, 6)\n+\tFEAT_DEF(MCE, 0x00000001, 0, REG_EDX, 7)\n+\tFEAT_DEF(CX8, 0x00000001, 0, REG_EDX, 8)\n+\tFEAT_DEF(APIC, 0x00000001, 0, REG_EDX, 9)\n+\tFEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)\n+\tFEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)\n+\tFEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)\n+\tFEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)\n+\tFEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)\n+\tFEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)\n+\tFEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)\n+\tFEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)\n+\tFEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)\n+\tFEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)\n+\tFEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)\n+\tFEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)\n+\tFEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)\n+\tFEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)\n+\tFEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)\n+\tFEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)\n+\tFEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)\n+\tFEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)\n+\tFEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)\n+\n+\tFEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX, 0)\n+\tFEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX, 1)\n+\tFEAT_DEF(ARAT, 0x00000006, 0, REG_EAX, 2)\n+\tFEAT_DEF(PLN, 0x00000006, 0, REG_EAX, 4)\n+\tFEAT_DEF(ECMD, 0x00000006, 0, REG_EAX, 5)\n+\tFEAT_DEF(PTM, 0x00000006, 0, REG_EAX, 6)\n+\n+\tFEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX, 0)\n+\tFEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX, 1)\n+\tFEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX, 3)\n+\n+\tFEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX, 0)\n+\tFEAT_DEF(BMI1, 0x00000007, 0, REG_EBX, 2)\n+\tFEAT_DEF(HLE, 0x00000007, 0, REG_EBX, 4)\n+\tFEAT_DEF(AVX2, 0x00000007, 0, REG_EBX, 5)\n+\tFEAT_DEF(SMEP, 0x00000007, 0, REG_EBX, 6)\n+\tFEAT_DEF(BMI2, 0x00000007, 0, REG_EBX, 7)\n+\tFEAT_DEF(ERMS, 0x00000007, 0, REG_EBX, 8)\n+\tFEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)\n+\tFEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)\n+\n+\tFEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX, 0)\n+\tFEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX, 4)\n+\n+\tFEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)\n+\tFEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)\n+\tFEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)\n+\tFEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)\n+\tFEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)\n+\n+\tFEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX, 8)\n+};\n+\n+static inline void\n+rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)\n+{\n+#if defined(__i386__) && defined(__PIC__)\n+ /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */\n+ asm volatile(\"movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0\"\n+\t\t : \"=r\" (out[REG_EBX]),\n+\t\t \"=a\" (out[REG_EAX]),\n+\t\t \"=c\" (out[REG_ECX]),\n+\t\t \"=d\" (out[REG_EDX])\n+\t\t : \"a\" (leaf), \"c\" (subleaf));\n+#else\n+\n+ asm volatile(\"cpuid\"\n+\t\t : \"=a\" (out[REG_EAX]),\n+\t\t \"=b\" (out[REG_EBX]),\n+\t\t \"=c\" (out[REG_ECX]),\n+\t\t \"=d\" (out[REG_EDX])\n+\t\t : \"a\" (leaf), \"c\" (subleaf));\n+\n+#endif\n+}\n+\n+static inline int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n+{\n+\tconst struct feature_entry *feat;\n+\tcpuid_registers_t regs;\n+\n+\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\t/* Flag does not match anything in the feature tables */\n+\t\treturn -ENOENT;\n+\n+\tfeat = &cpu_feature_table[feature];\n+\n+\tif (!feat->leaf)\n+\t\t/* This entry in the table wasn't filled out! */\n+\t\treturn -EFAULT;\n+\n+\trte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);\n+\tif (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||\n+\t regs[REG_EAX] < feat->leaf)\n+\t\treturn 0;\n+\n+\t/* get the cpuid leaf containing the desired feature */\n+\trte_cpu_get_features(feat->leaf, feat->subleaf, regs);\n+\n+\t/* check if the feature is enabled */\n+\treturn (regs[feat->reg] >> feat->bit) & 1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CPUFLAGS_I686_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/x86_64/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86_64/rte_cpuflags.h\nnew file mode 100644\nindex 0000000..98906c8\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/x86_64/rte_cpuflags.h\n@@ -0,0 +1,310 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+ \n+#ifndef _RTE_CPUFLAGS_X86_64_H_\n+#define _RTE_CPUFLAGS_X86_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include <stdint.h>\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+enum rte_cpu_flag_t {\n+\t/* (EAX 01h) ECX features*/\n+\tRTE_CPUFLAG_SSE3 = 0, /**< SSE3 */\n+\tRTE_CPUFLAG_PCLMULQDQ, /**< PCLMULQDQ */\n+\tRTE_CPUFLAG_DTES64, /**< DTES64 */\n+\tRTE_CPUFLAG_MONITOR, /**< MONITOR */\n+\tRTE_CPUFLAG_DS_CPL, /**< DS_CPL */\n+\tRTE_CPUFLAG_VMX, /**< VMX */\n+\tRTE_CPUFLAG_SMX, /**< SMX */\n+\tRTE_CPUFLAG_EIST, /**< EIST */\n+\tRTE_CPUFLAG_TM2, /**< TM2 */\n+\tRTE_CPUFLAG_SSSE3, /**< SSSE3 */\n+\tRTE_CPUFLAG_CNXT_ID, /**< CNXT_ID */\n+\tRTE_CPUFLAG_FMA, /**< FMA */\n+\tRTE_CPUFLAG_CMPXCHG16B, /**< CMPXCHG16B */\n+\tRTE_CPUFLAG_XTPR, /**< XTPR */\n+\tRTE_CPUFLAG_PDCM, /**< PDCM */\n+\tRTE_CPUFLAG_PCID, /**< PCID */\n+\tRTE_CPUFLAG_DCA, /**< DCA */\n+\tRTE_CPUFLAG_SSE4_1, /**< SSE4_1 */\n+\tRTE_CPUFLAG_SSE4_2, /**< SSE4_2 */\n+\tRTE_CPUFLAG_X2APIC, /**< X2APIC */\n+\tRTE_CPUFLAG_MOVBE, /**< MOVBE */\n+\tRTE_CPUFLAG_POPCNT, /**< POPCNT */\n+\tRTE_CPUFLAG_TSC_DEADLINE, /**< TSC_DEADLINE */\n+\tRTE_CPUFLAG_AES, /**< AES */\n+\tRTE_CPUFLAG_XSAVE, /**< XSAVE */\n+\tRTE_CPUFLAG_OSXSAVE, /**< OSXSAVE */\n+\tRTE_CPUFLAG_AVX, /**< AVX */\n+\tRTE_CPUFLAG_F16C, /**< F16C */\n+\tRTE_CPUFLAG_RDRAND, /**< RDRAND */\n+\n+\t/* (EAX 01h) EDX features */\n+\tRTE_CPUFLAG_FPU, /**< FPU */\n+\tRTE_CPUFLAG_VME, /**< VME */\n+\tRTE_CPUFLAG_DE, /**< DE */\n+\tRTE_CPUFLAG_PSE, /**< PSE */\n+\tRTE_CPUFLAG_TSC, /**< TSC */\n+\tRTE_CPUFLAG_MSR, /**< MSR */\n+\tRTE_CPUFLAG_PAE, /**< PAE */\n+\tRTE_CPUFLAG_MCE, /**< MCE */\n+\tRTE_CPUFLAG_CX8, /**< CX8 */\n+\tRTE_CPUFLAG_APIC, /**< APIC */\n+\tRTE_CPUFLAG_SEP, /**< SEP */\n+\tRTE_CPUFLAG_MTRR, /**< MTRR */\n+\tRTE_CPUFLAG_PGE, /**< PGE */\n+\tRTE_CPUFLAG_MCA, /**< MCA */\n+\tRTE_CPUFLAG_CMOV, /**< CMOV */\n+\tRTE_CPUFLAG_PAT, /**< PAT */\n+\tRTE_CPUFLAG_PSE36, /**< PSE36 */\n+\tRTE_CPUFLAG_PSN, /**< PSN */\n+\tRTE_CPUFLAG_CLFSH, /**< CLFSH */\n+\tRTE_CPUFLAG_DS, /**< DS */\n+\tRTE_CPUFLAG_ACPI, /**< ACPI */\n+\tRTE_CPUFLAG_MMX, /**< MMX */\n+\tRTE_CPUFLAG_FXSR, /**< FXSR */\n+\tRTE_CPUFLAG_SSE, /**< SSE */\n+\tRTE_CPUFLAG_SSE2, /**< SSE2 */\n+\tRTE_CPUFLAG_SS, /**< SS */\n+\tRTE_CPUFLAG_HTT, /**< HTT */\n+\tRTE_CPUFLAG_TM, /**< TM */\n+\tRTE_CPUFLAG_PBE, /**< PBE */\n+\n+\t/* (EAX 06h) EAX features */\n+\tRTE_CPUFLAG_DIGTEMP, /**< DIGTEMP */\n+\tRTE_CPUFLAG_TRBOBST, /**< TRBOBST */\n+\tRTE_CPUFLAG_ARAT, /**< ARAT */\n+\tRTE_CPUFLAG_PLN, /**< PLN */\n+\tRTE_CPUFLAG_ECMD, /**< ECMD */\n+\tRTE_CPUFLAG_PTM, /**< PTM */\n+\n+\t/* (EAX 06h) ECX features */\n+\tRTE_CPUFLAG_MPERF_APERF_MSR, /**< MPERF_APERF_MSR */\n+\tRTE_CPUFLAG_ACNT2, /**< ACNT2 */\n+\tRTE_CPUFLAG_ENERGY_EFF, /**< ENERGY_EFF */\n+\n+\t/* (EAX 07h, ECX 0h) EBX features */\n+\tRTE_CPUFLAG_FSGSBASE, /**< FSGSBASE */\n+\tRTE_CPUFLAG_BMI1, /**< BMI1 */\n+\tRTE_CPUFLAG_HLE, /**< Hardware Lock elision */\n+\tRTE_CPUFLAG_AVX2, /**< AVX2 */\n+\tRTE_CPUFLAG_SMEP, /**< SMEP */\n+\tRTE_CPUFLAG_BMI2, /**< BMI2 */\n+\tRTE_CPUFLAG_ERMS, /**< ERMS */\n+\tRTE_CPUFLAG_INVPCID, /**< INVPCID */\n+\tRTE_CPUFLAG_RTM, /**< Transactional memory */\n+\n+\t/* (EAX 80000001h) ECX features */\n+\tRTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */\n+\tRTE_CPUFLAG_LZCNT, /**< LZCNT */\n+\n+\t/* (EAX 80000001h) EDX features */\n+\tRTE_CPUFLAG_SYSCALL, /**< SYSCALL */\n+\tRTE_CPUFLAG_XD, /**< XD */\n+\tRTE_CPUFLAG_1GB_PG, /**< 1GB_PG */\n+\tRTE_CPUFLAG_RDTSCP, /**< RDTSCP */\n+\tRTE_CPUFLAG_EM64T, /**< EM64T */\n+\n+\t/* (EAX 80000007h) EDX features */\n+\tRTE_CPUFLAG_INVTSC, /**< INVTSC */\n+\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */\n+};\n+\n+enum cpu_register_t {\n+\tREG_EAX = 0,\n+\tREG_EBX,\n+\tREG_ECX,\n+\tREG_EDX,\n+};\n+\n+static const struct feature_entry cpu_feature_table[] = {\n+\tFEAT_DEF(SSE3, 0x00000001, 0, REG_ECX, 0)\n+\tFEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX, 1)\n+\tFEAT_DEF(DTES64, 0x00000001, 0, REG_ECX, 2)\n+\tFEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX, 3)\n+\tFEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX, 4)\n+\tFEAT_DEF(VMX, 0x00000001, 0, REG_ECX, 5)\n+\tFEAT_DEF(SMX, 0x00000001, 0, REG_ECX, 6)\n+\tFEAT_DEF(EIST, 0x00000001, 0, REG_ECX, 7)\n+\tFEAT_DEF(TM2, 0x00000001, 0, REG_ECX, 8)\n+\tFEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX, 9)\n+\tFEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)\n+\tFEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)\n+\tFEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)\n+\tFEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)\n+\tFEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)\n+\tFEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)\n+\tFEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)\n+\tFEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)\n+\tFEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)\n+\tFEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)\n+\tFEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)\n+\tFEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)\n+\tFEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)\n+\tFEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)\n+\tFEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)\n+\tFEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)\n+\tFEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)\n+\tFEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)\n+\tFEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)\n+\n+\tFEAT_DEF(FPU, 0x00000001, 0, REG_EDX, 0)\n+\tFEAT_DEF(VME, 0x00000001, 0, REG_EDX, 1)\n+\tFEAT_DEF(DE, 0x00000001, 0, REG_EDX, 2)\n+\tFEAT_DEF(PSE, 0x00000001, 0, REG_EDX, 3)\n+\tFEAT_DEF(TSC, 0x00000001, 0, REG_EDX, 4)\n+\tFEAT_DEF(MSR, 0x00000001, 0, REG_EDX, 5)\n+\tFEAT_DEF(PAE, 0x00000001, 0, REG_EDX, 6)\n+\tFEAT_DEF(MCE, 0x00000001, 0, REG_EDX, 7)\n+\tFEAT_DEF(CX8, 0x00000001, 0, REG_EDX, 8)\n+\tFEAT_DEF(APIC, 0x00000001, 0, REG_EDX, 9)\n+\tFEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)\n+\tFEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)\n+\tFEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)\n+\tFEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)\n+\tFEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)\n+\tFEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)\n+\tFEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)\n+\tFEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)\n+\tFEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)\n+\tFEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)\n+\tFEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)\n+\tFEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)\n+\tFEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)\n+\tFEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)\n+\tFEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)\n+\tFEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)\n+\tFEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)\n+\tFEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)\n+\tFEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)\n+\n+\tFEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX, 0)\n+\tFEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX, 1)\n+\tFEAT_DEF(ARAT, 0x00000006, 0, REG_EAX, 2)\n+\tFEAT_DEF(PLN, 0x00000006, 0, REG_EAX, 4)\n+\tFEAT_DEF(ECMD, 0x00000006, 0, REG_EAX, 5)\n+\tFEAT_DEF(PTM, 0x00000006, 0, REG_EAX, 6)\n+\n+\tFEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX, 0)\n+\tFEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX, 1)\n+\tFEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX, 3)\n+\n+\tFEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX, 0)\n+\tFEAT_DEF(BMI1, 0x00000007, 0, REG_EBX, 2)\n+\tFEAT_DEF(HLE, 0x00000007, 0, REG_EBX, 4)\n+\tFEAT_DEF(AVX2, 0x00000007, 0, REG_EBX, 5)\n+\tFEAT_DEF(SMEP, 0x00000007, 0, REG_EBX, 6)\n+\tFEAT_DEF(BMI2, 0x00000007, 0, REG_EBX, 7)\n+\tFEAT_DEF(ERMS, 0x00000007, 0, REG_EBX, 8)\n+\tFEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)\n+\tFEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)\n+\n+\tFEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX, 0)\n+\tFEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX, 4)\n+\n+\tFEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)\n+\tFEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)\n+\tFEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)\n+\tFEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)\n+\tFEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)\n+\n+\tFEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX, 8)\n+};\n+\n+static inline void\n+rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)\n+{\n+#if defined(__i386__) && defined(__PIC__)\n+ /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */\n+ asm volatile(\"movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0\"\n+\t\t : \"=r\" (out[REG_EBX]),\n+\t\t \"=a\" (out[REG_EAX]),\n+\t\t \"=c\" (out[REG_ECX]),\n+\t\t \"=d\" (out[REG_EDX])\n+\t\t : \"a\" (leaf), \"c\" (subleaf));\n+#else\n+\n+ asm volatile(\"cpuid\"\n+\t\t : \"=a\" (out[REG_EAX]),\n+\t\t \"=b\" (out[REG_EBX]),\n+\t\t \"=c\" (out[REG_ECX]),\n+\t\t \"=d\" (out[REG_EDX])\n+\t\t : \"a\" (leaf), \"c\" (subleaf));\n+\n+#endif\n+}\n+\n+static inline int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n+{\n+\tconst struct feature_entry *feat;\n+\tcpuid_registers_t regs;\n+\n+\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\t/* Flag does not match anything in the feature tables */\n+\t\treturn -ENOENT;\n+\n+\tfeat = &cpu_feature_table[feature];\n+\n+\tif (!feat->leaf)\n+\t\t/* This entry in the table wasn't filled out! */\n+\t\treturn -EFAULT;\n+\n+\trte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);\n+\tif (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||\n+\t regs[REG_EAX] < feat->leaf)\n+\t\treturn 0;\n+\n+\t/* get the cpuid leaf containing the desired feature */\n+\trte_cpu_get_features(feat->leaf, feat->subleaf, regs);\n+\n+\t/* check if the feature is enabled */\n+\treturn (regs[feat->reg] >> feat->bit) & 1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CPUFLAGS_X86_64_H_ */\ndiff --git a/lib/librte_eal/common/include/generic/rte_cpuflags.h b/lib/librte_eal/common/include/generic/rte_cpuflags.h\nnew file mode 100644\nindex 0000000..7f04838\n--- /dev/null\n+++ b/lib/librte_eal/common/include/generic/rte_cpuflags.h\n@@ -0,0 +1,110 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_CPUFLAGS_H_\n+#define _RTE_CPUFLAGS_H_\n+\n+/**\n+ * @file\n+ * Architecture specific API to determine available CPU features at runtime.\n+ */\n+\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include <stdint.h>\n+\n+/**\n+ * Enumeration of all CPU features supported\n+ */\n+enum rte_cpu_flag_t;\n+\n+/**\n+ * Enumeration of CPU registers\n+ */\n+enum cpu_register_t;\n+\n+typedef uint32_t cpuid_registers_t[4];\n+\n+#define CPU_FLAG_NAME_MAX_LEN 64\n+\n+/**\n+ * Struct to hold a processor feature entry\n+ */\n+struct feature_entry {\n+\tuint32_t leaf;\t\t\t\t/**< cpuid leaf */\n+\tuint32_t subleaf;\t\t\t/**< cpuid subleaf */\n+\tuint32_t reg;\t\t\t\t/**< cpuid register */\n+\tuint32_t bit;\t\t\t\t/**< cpuid register bit */\n+\tchar name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */\n+};\n+\n+#define FEAT_DEF(name, leaf, subleaf, reg, bit) \\\n+\t[RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },\n+\n+/**\n+ * An array that holds feature entries\n+ */\n+static const struct feature_entry cpu_feature_table[];\n+\n+/**\n+ * Execute CPUID instruction and get contents of a specific register\n+ *\n+ * This function, when compiled with GCC, will generate architecture-neutral\n+ * code, as per GCC manual.\n+ */\n+static inline void\n+rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out);\n+\n+/**\n+ * Function for checking a CPU flag availability\n+ *\n+ * @param flag\n+ * CPU flag to query CPU for\n+ * @return\n+ * 1 if flag is available\n+ * 0 if flag is not available\n+ * -ENOENT if flag is invalid\n+ */\n+static inline int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature);\n+\n+/**\n+ * This function checks that the currently used CPU supports the CPU features\n+ * that were specified at compile time. It is called automatically within the\n+ * EAL, so does not need to be used by applications.\n+ */\n+void\n+rte_cpu_check_supported(void);\n+\n+#endif /* _RTE_CPUFLAGS_H_ */\ndiff --git a/lib/librte_eal/common/include/rte_cpuflags.h b/lib/librte_eal/common/include/rte_cpuflags.h\ndeleted file mode 100644\nindex 5fa96db..0000000\n--- a/lib/librte_eal/common/include/rte_cpuflags.h\n+++ /dev/null\n@@ -1,182 +0,0 @@\n-/*-\n- * BSD LICENSE\n- *\n- * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n- * All rights reserved.\n- *\n- * Redistribution and use in source and binary forms, with or without\n- * modification, are permitted provided that the following conditions\n- * are met:\n- *\n- * * Redistributions of source code must retain the above copyright\n- * notice, this list of conditions and the following disclaimer.\n- * * Redistributions in binary form must reproduce the above copyright\n- * notice, this list of conditions and the following disclaimer in\n- * the documentation and/or other materials provided with the\n- * distribution.\n- * * Neither the name of Intel Corporation nor the names of its\n- * contributors may be used to endorse or promote products derived\n- * from this software without specific prior written permission.\n- *\n- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- */\n-\n-#ifndef _RTE_CPUFLAGS_H_\n-#define _RTE_CPUFLAGS_H_\n-\n-/**\n- * @file\n- * Simple API to determine available CPU features at runtime.\n- */\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-\n-/**\n- * Enumeration of all CPU features supported\n- */\n-enum rte_cpu_flag_t {\n-\t/* (EAX 01h) ECX features*/\n-\tRTE_CPUFLAG_SSE3 = 0, /**< SSE3 */\n-\tRTE_CPUFLAG_PCLMULQDQ, /**< PCLMULQDQ */\n-\tRTE_CPUFLAG_DTES64, /**< DTES64 */\n-\tRTE_CPUFLAG_MONITOR, /**< MONITOR */\n-\tRTE_CPUFLAG_DS_CPL, /**< DS_CPL */\n-\tRTE_CPUFLAG_VMX, /**< VMX */\n-\tRTE_CPUFLAG_SMX, /**< SMX */\n-\tRTE_CPUFLAG_EIST, /**< EIST */\n-\tRTE_CPUFLAG_TM2, /**< TM2 */\n-\tRTE_CPUFLAG_SSSE3, /**< SSSE3 */\n-\tRTE_CPUFLAG_CNXT_ID, /**< CNXT_ID */\n-\tRTE_CPUFLAG_FMA, /**< FMA */\n-\tRTE_CPUFLAG_CMPXCHG16B, /**< CMPXCHG16B */\n-\tRTE_CPUFLAG_XTPR, /**< XTPR */\n-\tRTE_CPUFLAG_PDCM, /**< PDCM */\n-\tRTE_CPUFLAG_PCID, /**< PCID */\n-\tRTE_CPUFLAG_DCA, /**< DCA */\n-\tRTE_CPUFLAG_SSE4_1, /**< SSE4_1 */\n-\tRTE_CPUFLAG_SSE4_2, /**< SSE4_2 */\n-\tRTE_CPUFLAG_X2APIC, /**< X2APIC */\n-\tRTE_CPUFLAG_MOVBE, /**< MOVBE */\n-\tRTE_CPUFLAG_POPCNT, /**< POPCNT */\n-\tRTE_CPUFLAG_TSC_DEADLINE, /**< TSC_DEADLINE */\n-\tRTE_CPUFLAG_AES, /**< AES */\n-\tRTE_CPUFLAG_XSAVE, /**< XSAVE */\n-\tRTE_CPUFLAG_OSXSAVE, /**< OSXSAVE */\n-\tRTE_CPUFLAG_AVX, /**< AVX */\n-\tRTE_CPUFLAG_F16C, /**< F16C */\n-\tRTE_CPUFLAG_RDRAND, /**< RDRAND */\n-\n-\t/* (EAX 01h) EDX features */\n-\tRTE_CPUFLAG_FPU, /**< FPU */\n-\tRTE_CPUFLAG_VME, /**< VME */\n-\tRTE_CPUFLAG_DE, /**< DE */\n-\tRTE_CPUFLAG_PSE, /**< PSE */\n-\tRTE_CPUFLAG_TSC, /**< TSC */\n-\tRTE_CPUFLAG_MSR, /**< MSR */\n-\tRTE_CPUFLAG_PAE, /**< PAE */\n-\tRTE_CPUFLAG_MCE, /**< MCE */\n-\tRTE_CPUFLAG_CX8, /**< CX8 */\n-\tRTE_CPUFLAG_APIC, /**< APIC */\n-\tRTE_CPUFLAG_SEP, /**< SEP */\n-\tRTE_CPUFLAG_MTRR, /**< MTRR */\n-\tRTE_CPUFLAG_PGE, /**< PGE */\n-\tRTE_CPUFLAG_MCA, /**< MCA */\n-\tRTE_CPUFLAG_CMOV, /**< CMOV */\n-\tRTE_CPUFLAG_PAT, /**< PAT */\n-\tRTE_CPUFLAG_PSE36, /**< PSE36 */\n-\tRTE_CPUFLAG_PSN, /**< PSN */\n-\tRTE_CPUFLAG_CLFSH, /**< CLFSH */\n-\tRTE_CPUFLAG_DS, /**< DS */\n-\tRTE_CPUFLAG_ACPI, /**< ACPI */\n-\tRTE_CPUFLAG_MMX, /**< MMX */\n-\tRTE_CPUFLAG_FXSR, /**< FXSR */\n-\tRTE_CPUFLAG_SSE, /**< SSE */\n-\tRTE_CPUFLAG_SSE2, /**< SSE2 */\n-\tRTE_CPUFLAG_SS, /**< SS */\n-\tRTE_CPUFLAG_HTT, /**< HTT */\n-\tRTE_CPUFLAG_TM, /**< TM */\n-\tRTE_CPUFLAG_PBE, /**< PBE */\n-\n-\t/* (EAX 06h) EAX features */\n-\tRTE_CPUFLAG_DIGTEMP, /**< DIGTEMP */\n-\tRTE_CPUFLAG_TRBOBST, /**< TRBOBST */\n-\tRTE_CPUFLAG_ARAT, /**< ARAT */\n-\tRTE_CPUFLAG_PLN, /**< PLN */\n-\tRTE_CPUFLAG_ECMD, /**< ECMD */\n-\tRTE_CPUFLAG_PTM, /**< PTM */\n-\n-\t/* (EAX 06h) ECX features */\n-\tRTE_CPUFLAG_MPERF_APERF_MSR, /**< MPERF_APERF_MSR */\n-\tRTE_CPUFLAG_ACNT2, /**< ACNT2 */\n-\tRTE_CPUFLAG_ENERGY_EFF, /**< ENERGY_EFF */\n-\n-\t/* (EAX 07h, ECX 0h) EBX features */\n-\tRTE_CPUFLAG_FSGSBASE, /**< FSGSBASE */\n-\tRTE_CPUFLAG_BMI1, /**< BMI1 */\n-\tRTE_CPUFLAG_HLE, /**< Hardware Lock elision */\n-\tRTE_CPUFLAG_AVX2, /**< AVX2 */\n-\tRTE_CPUFLAG_SMEP, /**< SMEP */\n-\tRTE_CPUFLAG_BMI2, /**< BMI2 */\n-\tRTE_CPUFLAG_ERMS, /**< ERMS */\n-\tRTE_CPUFLAG_INVPCID, /**< INVPCID */\n-\tRTE_CPUFLAG_RTM, /**< Transactional memory */\n-\n-\t/* (EAX 80000001h) ECX features */\n-\tRTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */\n-\tRTE_CPUFLAG_LZCNT, /**< LZCNT */\n-\n-\t/* (EAX 80000001h) EDX features */\n-\tRTE_CPUFLAG_SYSCALL, /**< SYSCALL */\n-\tRTE_CPUFLAG_XD, /**< XD */\n-\tRTE_CPUFLAG_1GB_PG, /**< 1GB_PG */\n-\tRTE_CPUFLAG_RDTSCP, /**< RDTSCP */\n-\tRTE_CPUFLAG_EM64T, /**< EM64T */\n-\n-\t/* (EAX 80000007h) EDX features */\n-\tRTE_CPUFLAG_INVTSC, /**< INVTSC */\n-\n-\t/* The last item */\n-\tRTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */\n-};\n-\n-\n-/**\n- * Function for checking a CPU flag availability\n- *\n- * @param flag\n- * CPU flag to query CPU for\n- * @return\n- * 1 if flag is available\n- * 0 if flag is not available\n- * -ENOENT if flag is invalid\n- */\n-int\n-rte_cpu_get_flag_enabled(enum rte_cpu_flag_t flag);\n-\n-/**\n- * This function checks that the currently used CPU supports the CPU features\n- * that were specified at compile time. It is called automatically within the\n- * EAL, so does not need to be used by applications.\n- */\n-void\n-rte_cpu_check_supported(void);\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-\n-#endif /* _RTE_CPUFLAGS_H_ */\n", "prefixes": [ "dpdk-dev", "v3", "08/10" ] }