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{
    "id": 98608,
    "url": "http://patches.dpdk.org/api/patches/98608/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210910123003.85448-12-cristian.dumitrescu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210910123003.85448-12-cristian.dumitrescu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210910123003.85448-12-cristian.dumitrescu@intel.com",
    "date": "2021-09-10T12:29:51",
    "name": "[12/24] pipeline: create inline functions for ALU instructions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0434b410311e40bb6d72aa6859297e5ab990742d",
    "submitter": {
        "id": 19,
        "url": "http://patches.dpdk.org/api/people/19/?format=api",
        "name": "Cristian Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210910123003.85448-12-cristian.dumitrescu@intel.com/mbox/",
    "series": [
        {
            "id": 18838,
            "url": "http://patches.dpdk.org/api/series/18838/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18838",
            "date": "2021-09-10T12:29:44",
            "name": "[01/24] pipeline: move data structures to internal header file",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/18838/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/98608/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/98608/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10102\"; a=\"243386287\"",
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            "E=Sophos;i=\"5.85,282,1624345200\"; d=\"scan'208\";a=\"514279755\""
        ],
        "X-ExtLoop1": "1",
        "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Fri, 10 Sep 2021 13:29:51 +0100",
        "Message-Id": "<20210910123003.85448-12-cristian.dumitrescu@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210910123003.85448-1-cristian.dumitrescu@intel.com>",
        "References": "<20210910123003.85448-1-cristian.dumitrescu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 12/24] pipeline: create inline functions for ALU\n instructions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/pipeline/rte_swx_pipeline.c          | 348 ++-----------\n lib/pipeline/rte_swx_pipeline_internal.h | 616 +++++++++++++++++++++++\n 2 files changed, 660 insertions(+), 304 deletions(-)",
    "diff": "diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c\nindex a06dc8d348..8956b6de27 100644\n--- a/lib/pipeline/rte_swx_pipeline.c\n+++ b/lib/pipeline/rte_swx_pipeline.c\n@@ -3044,10 +3044,8 @@ instr_alu_add_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] add\\n\", p->thread_id);\n-\n-\t/* Structs. */\n-\tALU(t, ip, +);\n+\t/* Structs */\n+\t__instr_alu_add_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3059,10 +3057,8 @@ instr_alu_add_mh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] add (mh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MH(t, ip, +);\n+\t__instr_alu_add_mh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3074,10 +3070,8 @@ instr_alu_add_hm_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] add (hm)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HM(t, ip, +);\n+\t__instr_alu_add_hm_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3089,10 +3083,8 @@ instr_alu_add_hh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] add (hh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HH(t, ip, +);\n+\t__instr_alu_add_hh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3104,10 +3096,8 @@ instr_alu_add_mi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] add (mi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MI(t, ip, +);\n+\t__instr_alu_add_mi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3119,10 +3109,8 @@ instr_alu_add_hi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] add (hi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HI(t, ip, +);\n+\t__instr_alu_add_hi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3134,10 +3122,8 @@ instr_alu_sub_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] sub\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU(t, ip, -);\n+\t__instr_alu_sub_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3149,10 +3135,8 @@ instr_alu_sub_mh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] sub (mh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MH(t, ip, -);\n+\t__instr_alu_sub_mh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3164,10 +3148,8 @@ instr_alu_sub_hm_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] sub (hm)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HM(t, ip, -);\n+\t__instr_alu_sub_hm_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3179,10 +3161,8 @@ instr_alu_sub_hh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] sub (hh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HH(t, ip, -);\n+\t__instr_alu_sub_hh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3194,10 +3174,8 @@ instr_alu_sub_mi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] sub (mi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MI(t, ip, -);\n+\t__instr_alu_sub_mi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3209,10 +3187,8 @@ instr_alu_sub_hi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] sub (hi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HI(t, ip, -);\n+\t__instr_alu_sub_hi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3224,10 +3200,8 @@ instr_alu_shl_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shl\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU(t, ip, <<);\n+\t__instr_alu_shl_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3239,10 +3213,8 @@ instr_alu_shl_mh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shl (mh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MH(t, ip, <<);\n+\t__instr_alu_shl_mh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3254,10 +3226,8 @@ instr_alu_shl_hm_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shl (hm)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HM(t, ip, <<);\n+\t__instr_alu_shl_hm_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3269,10 +3239,8 @@ instr_alu_shl_hh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shl (hh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HH(t, ip, <<);\n+\t__instr_alu_shl_hh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3284,10 +3252,8 @@ instr_alu_shl_mi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shl (mi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MI(t, ip, <<);\n+\t__instr_alu_shl_mi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3299,10 +3265,8 @@ instr_alu_shl_hi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shl (hi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HI(t, ip, <<);\n+\t__instr_alu_shl_hi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3314,10 +3278,8 @@ instr_alu_shr_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shr\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU(t, ip, >>);\n+\t__instr_alu_shr_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3329,10 +3291,8 @@ instr_alu_shr_mh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shr (mh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MH(t, ip, >>);\n+\t__instr_alu_shr_mh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3344,10 +3304,8 @@ instr_alu_shr_hm_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shr (hm)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HM(t, ip, >>);\n+\t__instr_alu_shr_hm_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3359,10 +3317,8 @@ instr_alu_shr_hh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shr (hh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HH(t, ip, >>);\n+\t__instr_alu_shr_hh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3374,10 +3330,8 @@ instr_alu_shr_mi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shr (mi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MI(t, ip, >>);\n+\t__instr_alu_shr_mi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3389,10 +3343,8 @@ instr_alu_shr_hi_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] shr (hi)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HI(t, ip, >>);\n+\t__instr_alu_shr_hi_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3404,10 +3356,8 @@ instr_alu_and_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] and\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU(t, ip, &);\n+\t__instr_alu_and_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3419,10 +3369,8 @@ instr_alu_and_mh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] and (mh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MH(t, ip, &);\n+\t__instr_alu_and_mh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3434,10 +3382,8 @@ instr_alu_and_hm_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] and (hm)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HM_FAST(t, ip, &);\n+\t__instr_alu_and_hm_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3449,10 +3395,8 @@ instr_alu_and_hh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] and (hh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HH_FAST(t, ip, &);\n+\t__instr_alu_and_hh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3464,10 +3408,8 @@ instr_alu_and_i_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] and (i)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_I(t, ip, &);\n+\t__instr_alu_and_i_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3479,10 +3421,8 @@ instr_alu_or_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] or\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU(t, ip, |);\n+\t__instr_alu_or_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3494,10 +3434,8 @@ instr_alu_or_mh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] or (mh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MH(t, ip, |);\n+\t__instr_alu_or_mh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3509,10 +3447,8 @@ instr_alu_or_hm_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] or (hm)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HM_FAST(t, ip, |);\n+\t__instr_alu_or_hm_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3524,10 +3460,8 @@ instr_alu_or_hh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] or (hh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HH_FAST(t, ip, |);\n+\t__instr_alu_or_hh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3539,10 +3473,8 @@ instr_alu_or_i_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] or (i)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_I(t, ip, |);\n+\t__instr_alu_or_i_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3554,10 +3486,8 @@ instr_alu_xor_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] xor\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU(t, ip, ^);\n+\t__instr_alu_xor_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3569,10 +3499,8 @@ instr_alu_xor_mh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] xor (mh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_MH(t, ip, ^);\n+\t__instr_alu_xor_mh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3584,10 +3512,8 @@ instr_alu_xor_hm_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] xor (hm)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HM_FAST(t, ip, ^);\n+\t__instr_alu_xor_hm_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3599,10 +3525,8 @@ instr_alu_xor_hh_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] xor (hh)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_HH_FAST(t, ip, ^);\n+\t__instr_alu_xor_hh_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3614,10 +3538,8 @@ instr_alu_xor_i_exec(struct rte_swx_pipeline *p)\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n \n-\tTRACE(\"[Thread %2u] xor (i)\\n\", p->thread_id);\n-\n \t/* Structs. */\n-\tALU_I(t, ip, ^);\n+\t__instr_alu_xor_i_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3628,55 +3550,9 @@ instr_alu_ckadd_field_exec(struct rte_swx_pipeline *p)\n {\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n-\tuint8_t *dst_struct, *src_struct;\n-\tuint16_t *dst16_ptr, dst;\n-\tuint64_t *src64_ptr, src64, src64_mask, src;\n-\tuint64_t r;\n-\n-\tTRACE(\"[Thread %2u] ckadd (field)\\n\", p->thread_id);\n \n \t/* Structs. */\n-\tdst_struct = t->structs[ip->alu.dst.struct_id];\n-\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n-\tdst = *dst16_ptr;\n-\n-\tsrc_struct = t->structs[ip->alu.src.struct_id];\n-\tsrc64_ptr = (uint64_t *)&src_struct[ip->alu.src.offset];\n-\tsrc64 = *src64_ptr;\n-\tsrc64_mask = UINT64_MAX >> (64 - ip->alu.src.n_bits);\n-\tsrc = src64 & src64_mask;\n-\n-\tr = dst;\n-\tr = ~r & 0xFFFF;\n-\n-\t/* The first input (r) is a 16-bit number. The second and the third\n-\t * inputs are 32-bit numbers. In the worst case scenario, the sum of the\n-\t * three numbers (output r) is a 34-bit number.\n-\t */\n-\tr += (src >> 32) + (src & 0xFFFFFFFF);\n-\n-\t/* The first input is a 16-bit number. The second input is an 18-bit\n-\t * number. In the worst case scenario, the sum of the two numbers is a\n-\t * 19-bit number.\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n-\t * a 3-bit number (0 .. 7). Their sum is a 17-bit number (0 .. 0x10006).\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n-\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n-\t * 0x10006), the output r is (0 .. 7). So no carry bit can be generated,\n-\t * therefore the output r is always a 16-bit number.\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\tr = ~r & 0xFFFF;\n-\tr = r ? r : 0xFFFF;\n-\n-\t*dst16_ptr = (uint16_t)r;\n+\t__instr_alu_ckadd_field_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3687,67 +3563,9 @@ instr_alu_cksub_field_exec(struct rte_swx_pipeline *p)\n {\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n-\tuint8_t *dst_struct, *src_struct;\n-\tuint16_t *dst16_ptr, dst;\n-\tuint64_t *src64_ptr, src64, src64_mask, src;\n-\tuint64_t r;\n-\n-\tTRACE(\"[Thread %2u] cksub (field)\\n\", p->thread_id);\n \n \t/* Structs. */\n-\tdst_struct = t->structs[ip->alu.dst.struct_id];\n-\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n-\tdst = *dst16_ptr;\n-\n-\tsrc_struct = t->structs[ip->alu.src.struct_id];\n-\tsrc64_ptr = (uint64_t *)&src_struct[ip->alu.src.offset];\n-\tsrc64 = *src64_ptr;\n-\tsrc64_mask = UINT64_MAX >> (64 - ip->alu.src.n_bits);\n-\tsrc = src64 & src64_mask;\n-\n-\tr = dst;\n-\tr = ~r & 0xFFFF;\n-\n-\t/* Subtraction in 1's complement arithmetic (i.e. a '- b) is the same as\n-\t * the following sequence of operations in 2's complement arithmetic:\n-\t *    a '- b = (a - b) % 0xFFFF.\n-\t *\n-\t * In order to prevent an underflow for the below subtraction, in which\n-\t * a 33-bit number (the subtrahend) is taken out of a 16-bit number (the\n-\t * minuend), we first add a multiple of the 0xFFFF modulus to the\n-\t * minuend. The number we add to the minuend needs to be a 34-bit number\n-\t * or higher, so for readability reasons we picked the 36-bit multiple.\n-\t * We are effectively turning the 16-bit minuend into a 36-bit number:\n-\t *    (a - b) % 0xFFFF = (a + 0xFFFF00000 - b) % 0xFFFF.\n-\t */\n-\tr += 0xFFFF00000ULL; /* The output r is a 36-bit number. */\n-\n-\t/* A 33-bit number is subtracted from a 36-bit number (the input r). The\n-\t * result (the output r) is a 36-bit number.\n-\t */\n-\tr -= (src >> 32) + (src & 0xFFFFFFFF);\n-\n-\t/* The first input is a 16-bit number. The second input is a 20-bit\n-\t * number. Their sum is a 21-bit number.\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n-\t * a 5-bit number (0 .. 31). The sum is a 17-bit number (0 .. 0x1001E).\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n-\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n-\t * 0x1001E), the output r is (0 .. 31). So no carry bit can be\n-\t * generated, therefore the output r is always a 16-bit number.\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\tr = ~r & 0xFFFF;\n-\tr = r ? r : 0xFFFF;\n-\n-\t*dst16_ptr = (uint16_t)r;\n+\t__instr_alu_cksub_field_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3758,47 +3576,9 @@ instr_alu_ckadd_struct20_exec(struct rte_swx_pipeline *p)\n {\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n-\tuint8_t *dst_struct, *src_struct;\n-\tuint16_t *dst16_ptr;\n-\tuint32_t *src32_ptr;\n-\tuint64_t r0, r1;\n-\n-\tTRACE(\"[Thread %2u] ckadd (struct of 20 bytes)\\n\", p->thread_id);\n \n \t/* Structs. */\n-\tdst_struct = t->structs[ip->alu.dst.struct_id];\n-\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n-\n-\tsrc_struct = t->structs[ip->alu.src.struct_id];\n-\tsrc32_ptr = (uint32_t *)&src_struct[0];\n-\n-\tr0 = src32_ptr[0]; /* r0 is a 32-bit number. */\n-\tr1 = src32_ptr[1]; /* r1 is a 32-bit number. */\n-\tr0 += src32_ptr[2]; /* The output r0 is a 33-bit number. */\n-\tr1 += src32_ptr[3]; /* The output r1 is a 33-bit number. */\n-\tr0 += r1 + src32_ptr[4]; /* The output r0 is a 35-bit number. */\n-\n-\t/* The first input is a 16-bit number. The second input is a 19-bit\n-\t * number. Their sum is a 20-bit number.\n-\t */\n-\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n-\n-\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n-\t * a 4-bit number (0 .. 15). The sum is a 17-bit number (0 .. 0x1000E).\n-\t */\n-\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n-\n-\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n-\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n-\t * 0x1000E), the output r is (0 .. 15). So no carry bit can be\n-\t * generated, therefore the output r is always a 16-bit number.\n-\t */\n-\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n-\n-\tr0 = ~r0 & 0xFFFF;\n-\tr0 = r0 ? r0 : 0xFFFF;\n-\n-\t*dst16_ptr = (uint16_t)r0;\n+\t__instr_alu_ckadd_struct20_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\n@@ -3809,49 +3589,9 @@ instr_alu_ckadd_struct_exec(struct rte_swx_pipeline *p)\n {\n \tstruct thread *t = &p->threads[p->thread_id];\n \tstruct instruction *ip = t->ip;\n-\tuint8_t *dst_struct, *src_struct;\n-\tuint16_t *dst16_ptr;\n-\tuint32_t *src32_ptr;\n-\tuint64_t r = 0;\n-\tuint32_t i;\n-\n-\tTRACE(\"[Thread %2u] ckadd (struct)\\n\", p->thread_id);\n \n \t/* Structs. */\n-\tdst_struct = t->structs[ip->alu.dst.struct_id];\n-\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n-\n-\tsrc_struct = t->structs[ip->alu.src.struct_id];\n-\tsrc32_ptr = (uint32_t *)&src_struct[0];\n-\n-\t/* The max number of 32-bit words in a 256-byte header is 8 = 2^3.\n-\t * Therefore, in the worst case scenario, a 35-bit number is added to a\n-\t * 16-bit number (the input r), so the output r is 36-bit number.\n-\t */\n-\tfor (i = 0; i < ip->alu.src.n_bits / 32; i++, src32_ptr++)\n-\t\tr += *src32_ptr;\n-\n-\t/* The first input is a 16-bit number. The second input is a 20-bit\n-\t * number. Their sum is a 21-bit number.\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n-\t * a 5-bit number (0 .. 31). The sum is a 17-bit number (0 .. 0x1000E).\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n-\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n-\t * 0x1001E), the output r is (0 .. 31). So no carry bit can be\n-\t * generated, therefore the output r is always a 16-bit number.\n-\t */\n-\tr = (r & 0xFFFF) + (r >> 16);\n-\n-\tr = ~r & 0xFFFF;\n-\tr = r ? r : 0xFFFF;\n-\n-\t*dst16_ptr = (uint16_t)r;\n+\t__instr_alu_ckadd_struct_exec(p, t, ip);\n \n \t/* Thread. */\n \tthread_ip_inc(p);\ndiff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h\nindex ec8e342a5d..7c4a2c05ef 100644\n--- a/lib/pipeline/rte_swx_pipeline_internal.h\n+++ b/lib/pipeline/rte_swx_pipeline_internal.h\n@@ -2211,4 +2211,620 @@ __instr_dma_ht8_exec(struct rte_swx_pipeline *p, struct thread *t, const struct\n \t__instr_dma_ht_many_exec(p, t, ip, 8);\n }\n \n+/*\n+ * alu.\n+ */\n+static inline void\n+__instr_alu_add_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t     struct thread *t,\n+\t\t     const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] add\\n\", p->thread_id);\n+\n+\tALU(t, ip, +);\n+}\n+\n+static inline void\n+__instr_alu_add_mh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] add (mh)\\n\", p->thread_id);\n+\n+\tALU_MH(t, ip, +);\n+}\n+\n+static inline void\n+__instr_alu_add_hm_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] add (hm)\\n\", p->thread_id);\n+\n+\tALU_HM(t, ip, +);\n+}\n+\n+static inline void\n+__instr_alu_add_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] add (hh)\\n\", p->thread_id);\n+\n+\tALU_HH(t, ip, +);\n+}\n+\n+static inline void\n+__instr_alu_add_mi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] add (mi)\\n\", p->thread_id);\n+\n+\tALU_MI(t, ip, +);\n+}\n+\n+static inline void\n+__instr_alu_add_hi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] add (hi)\\n\", p->thread_id);\n+\n+\tALU_HI(t, ip, +);\n+}\n+\n+static inline void\n+__instr_alu_sub_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t     struct thread *t,\n+\t\t     const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] sub\\n\", p->thread_id);\n+\n+\tALU(t, ip, -);\n+}\n+\n+static inline void\n+__instr_alu_sub_mh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] sub (mh)\\n\", p->thread_id);\n+\n+\tALU_MH(t, ip, -);\n+}\n+\n+static inline void\n+__instr_alu_sub_hm_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] sub (hm)\\n\", p->thread_id);\n+\n+\tALU_HM(t, ip, -);\n+}\n+\n+static inline void\n+__instr_alu_sub_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] sub (hh)\\n\", p->thread_id);\n+\n+\tALU_HH(t, ip, -);\n+}\n+\n+static inline void\n+__instr_alu_sub_mi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] sub (mi)\\n\", p->thread_id);\n+\n+\tALU_MI(t, ip, -);\n+}\n+\n+static inline void\n+__instr_alu_sub_hi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] sub (hi)\\n\", p->thread_id);\n+\n+\tALU_HI(t, ip, -);\n+}\n+\n+static inline void\n+__instr_alu_shl_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t     struct thread *t,\n+\t\t     const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shl\\n\", p->thread_id);\n+\n+\tALU(t, ip, <<);\n+}\n+\n+static inline void\n+__instr_alu_shl_mh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shl (mh)\\n\", p->thread_id);\n+\n+\tALU_MH(t, ip, <<);\n+}\n+\n+static inline void\n+__instr_alu_shl_hm_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shl (hm)\\n\", p->thread_id);\n+\n+\tALU_HM(t, ip, <<);\n+}\n+\n+static inline void\n+__instr_alu_shl_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shl (hh)\\n\", p->thread_id);\n+\n+\tALU_HH(t, ip, <<);\n+}\n+\n+static inline void\n+__instr_alu_shl_mi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shl (mi)\\n\", p->thread_id);\n+\n+\tALU_MI(t, ip, <<);\n+}\n+\n+static inline void\n+__instr_alu_shl_hi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shl (hi)\\n\", p->thread_id);\n+\n+\tALU_HI(t, ip, <<);\n+}\n+\n+static inline void\n+__instr_alu_shr_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t     struct thread *t,\n+\t\t     const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shr\\n\", p->thread_id);\n+\n+\tALU(t, ip, >>);\n+}\n+\n+static inline void\n+__instr_alu_shr_mh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shr (mh)\\n\", p->thread_id);\n+\n+\tALU_MH(t, ip, >>);\n+}\n+\n+static inline void\n+__instr_alu_shr_hm_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shr (hm)\\n\", p->thread_id);\n+\n+\tALU_HM(t, ip, >>);\n+}\n+\n+static inline void\n+__instr_alu_shr_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shr (hh)\\n\", p->thread_id);\n+\n+\tALU_HH(t, ip, >>);\n+}\n+\n+static inline void\n+__instr_alu_shr_mi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shr (mi)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_MI(t, ip, >>);\n+}\n+\n+static inline void\n+__instr_alu_shr_hi_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] shr (hi)\\n\", p->thread_id);\n+\n+\tALU_HI(t, ip, >>);\n+}\n+\n+static inline void\n+__instr_alu_and_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t     struct thread *t,\n+\t\t     const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] and\\n\", p->thread_id);\n+\n+\tALU(t, ip, &);\n+}\n+\n+static inline void\n+__instr_alu_and_mh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] and (mh)\\n\", p->thread_id);\n+\n+\tALU_MH(t, ip, &);\n+}\n+\n+static inline void\n+__instr_alu_and_hm_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] and (hm)\\n\", p->thread_id);\n+\n+\tALU_HM_FAST(t, ip, &);\n+}\n+\n+static inline void\n+__instr_alu_and_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] and (hh)\\n\", p->thread_id);\n+\n+\tALU_HH_FAST(t, ip, &);\n+}\n+\n+static inline void\n+__instr_alu_and_i_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t       struct thread *t,\n+\t\t       const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] and (i)\\n\", p->thread_id);\n+\n+\tALU_I(t, ip, &);\n+}\n+\n+static inline void\n+__instr_alu_or_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t    struct thread *t,\n+\t\t    const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] or\\n\", p->thread_id);\n+\n+\tALU(t, ip, |);\n+}\n+\n+static inline void\n+__instr_alu_or_mh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t       struct thread *t,\n+\t\t       const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] or (mh)\\n\", p->thread_id);\n+\n+\tALU_MH(t, ip, |);\n+}\n+\n+static inline void\n+__instr_alu_or_hm_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t       struct thread *t,\n+\t\t       const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] or (hm)\\n\", p->thread_id);\n+\n+\tALU_HM_FAST(t, ip, |);\n+}\n+\n+static inline void\n+__instr_alu_or_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t       struct thread *t,\n+\t\t       const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] or (hh)\\n\", p->thread_id);\n+\n+\tALU_HH_FAST(t, ip, |);\n+}\n+\n+static inline void\n+__instr_alu_or_i_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t      struct thread *t,\n+\t\t      const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] or (i)\\n\", p->thread_id);\n+\n+\tALU_I(t, ip, |);\n+}\n+\n+static inline void\n+__instr_alu_xor_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t     struct thread *t,\n+\t\t     const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] xor\\n\", p->thread_id);\n+\n+\tALU(t, ip, ^);\n+}\n+\n+static inline void\n+__instr_alu_xor_mh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] xor (mh)\\n\", p->thread_id);\n+\n+\tALU_MH(t, ip, ^);\n+}\n+\n+static inline void\n+__instr_alu_xor_hm_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] xor (hm)\\n\", p->thread_id);\n+\n+\tALU_HM_FAST(t, ip, ^);\n+}\n+\n+static inline void\n+__instr_alu_xor_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] xor (hh)\\n\", p->thread_id);\n+\n+\tALU_HH_FAST(t, ip, ^);\n+}\n+\n+static inline void\n+__instr_alu_xor_i_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t       struct thread *t,\n+\t\t       const struct instruction *ip)\n+{\n+\tTRACE(\"[Thread %2u] xor (i)\\n\", p->thread_id);\n+\n+\tALU_I(t, ip, ^);\n+}\n+\n+static inline void\n+__instr_alu_ckadd_field_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\t     struct thread *t,\n+\t\t\t     const struct instruction *ip)\n+{\n+\tuint8_t *dst_struct, *src_struct;\n+\tuint16_t *dst16_ptr, dst;\n+\tuint64_t *src64_ptr, src64, src64_mask, src;\n+\tuint64_t r;\n+\n+\tTRACE(\"[Thread %2u] ckadd (field)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tdst_struct = t->structs[ip->alu.dst.struct_id];\n+\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n+\tdst = *dst16_ptr;\n+\n+\tsrc_struct = t->structs[ip->alu.src.struct_id];\n+\tsrc64_ptr = (uint64_t *)&src_struct[ip->alu.src.offset];\n+\tsrc64 = *src64_ptr;\n+\tsrc64_mask = UINT64_MAX >> (64 - ip->alu.src.n_bits);\n+\tsrc = src64 & src64_mask;\n+\n+\tr = dst;\n+\tr = ~r & 0xFFFF;\n+\n+\t/* The first input (r) is a 16-bit number. The second and the third\n+\t * inputs are 32-bit numbers. In the worst case scenario, the sum of the\n+\t * three numbers (output r) is a 34-bit number.\n+\t */\n+\tr += (src >> 32) + (src & 0xFFFFFFFF);\n+\n+\t/* The first input is a 16-bit number. The second input is an 18-bit\n+\t * number. In the worst case scenario, the sum of the two numbers is a\n+\t * 19-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n+\t * a 3-bit number (0 .. 7). Their sum is a 17-bit number (0 .. 0x10006).\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n+\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n+\t * 0x10006), the output r is (0 .. 7). So no carry bit can be generated,\n+\t * therefore the output r is always a 16-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\tr = ~r & 0xFFFF;\n+\tr = r ? r : 0xFFFF;\n+\n+\t*dst16_ptr = (uint16_t)r;\n+}\n+\n+static inline void\n+__instr_alu_cksub_field_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\t     struct thread *t,\n+\t\t\t     const struct instruction *ip)\n+{\n+\tuint8_t *dst_struct, *src_struct;\n+\tuint16_t *dst16_ptr, dst;\n+\tuint64_t *src64_ptr, src64, src64_mask, src;\n+\tuint64_t r;\n+\n+\tTRACE(\"[Thread %2u] cksub (field)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tdst_struct = t->structs[ip->alu.dst.struct_id];\n+\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n+\tdst = *dst16_ptr;\n+\n+\tsrc_struct = t->structs[ip->alu.src.struct_id];\n+\tsrc64_ptr = (uint64_t *)&src_struct[ip->alu.src.offset];\n+\tsrc64 = *src64_ptr;\n+\tsrc64_mask = UINT64_MAX >> (64 - ip->alu.src.n_bits);\n+\tsrc = src64 & src64_mask;\n+\n+\tr = dst;\n+\tr = ~r & 0xFFFF;\n+\n+\t/* Subtraction in 1's complement arithmetic (i.e. a '- b) is the same as\n+\t * the following sequence of operations in 2's complement arithmetic:\n+\t *    a '- b = (a - b) % 0xFFFF.\n+\t *\n+\t * In order to prevent an underflow for the below subtraction, in which\n+\t * a 33-bit number (the subtrahend) is taken out of a 16-bit number (the\n+\t * minuend), we first add a multiple of the 0xFFFF modulus to the\n+\t * minuend. The number we add to the minuend needs to be a 34-bit number\n+\t * or higher, so for readability reasons we picked the 36-bit multiple.\n+\t * We are effectively turning the 16-bit minuend into a 36-bit number:\n+\t *    (a - b) % 0xFFFF = (a + 0xFFFF00000 - b) % 0xFFFF.\n+\t */\n+\tr += 0xFFFF00000ULL; /* The output r is a 36-bit number. */\n+\n+\t/* A 33-bit number is subtracted from a 36-bit number (the input r). The\n+\t * result (the output r) is a 36-bit number.\n+\t */\n+\tr -= (src >> 32) + (src & 0xFFFFFFFF);\n+\n+\t/* The first input is a 16-bit number. The second input is a 20-bit\n+\t * number. Their sum is a 21-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n+\t * a 5-bit number (0 .. 31). The sum is a 17-bit number (0 .. 0x1001E).\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n+\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n+\t * 0x1001E), the output r is (0 .. 31). So no carry bit can be\n+\t * generated, therefore the output r is always a 16-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\tr = ~r & 0xFFFF;\n+\tr = r ? r : 0xFFFF;\n+\n+\t*dst16_ptr = (uint16_t)r;\n+}\n+\n+static inline void\n+__instr_alu_ckadd_struct20_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\t\tstruct thread *t,\n+\t\t\t\tconst struct instruction *ip)\n+{\n+\tuint8_t *dst_struct, *src_struct;\n+\tuint16_t *dst16_ptr;\n+\tuint32_t *src32_ptr;\n+\tuint64_t r0, r1;\n+\n+\tTRACE(\"[Thread %2u] ckadd (struct of 20 bytes)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tdst_struct = t->structs[ip->alu.dst.struct_id];\n+\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n+\n+\tsrc_struct = t->structs[ip->alu.src.struct_id];\n+\tsrc32_ptr = (uint32_t *)&src_struct[0];\n+\n+\tr0 = src32_ptr[0]; /* r0 is a 32-bit number. */\n+\tr1 = src32_ptr[1]; /* r1 is a 32-bit number. */\n+\tr0 += src32_ptr[2]; /* The output r0 is a 33-bit number. */\n+\tr1 += src32_ptr[3]; /* The output r1 is a 33-bit number. */\n+\tr0 += r1 + src32_ptr[4]; /* The output r0 is a 35-bit number. */\n+\n+\t/* The first input is a 16-bit number. The second input is a 19-bit\n+\t * number. Their sum is a 20-bit number.\n+\t */\n+\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n+\n+\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n+\t * a 4-bit number (0 .. 15). The sum is a 17-bit number (0 .. 0x1000E).\n+\t */\n+\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n+\n+\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n+\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n+\t * 0x1000E), the output r is (0 .. 15). So no carry bit can be\n+\t * generated, therefore the output r is always a 16-bit number.\n+\t */\n+\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n+\n+\tr0 = ~r0 & 0xFFFF;\n+\tr0 = r0 ? r0 : 0xFFFF;\n+\n+\t*dst16_ptr = (uint16_t)r0;\n+}\n+\n+static inline void\n+__instr_alu_ckadd_struct_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\t      struct thread *t,\n+\t\t\t      const struct instruction *ip)\n+{\n+\tuint8_t *dst_struct, *src_struct;\n+\tuint16_t *dst16_ptr;\n+\tuint32_t *src32_ptr;\n+\tuint64_t r = 0;\n+\tuint32_t i;\n+\n+\tTRACE(\"[Thread %2u] ckadd (struct)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tdst_struct = t->structs[ip->alu.dst.struct_id];\n+\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n+\n+\tsrc_struct = t->structs[ip->alu.src.struct_id];\n+\tsrc32_ptr = (uint32_t *)&src_struct[0];\n+\n+\t/* The max number of 32-bit words in a 256-byte header is 8 = 2^3.\n+\t * Therefore, in the worst case scenario, a 35-bit number is added to a\n+\t * 16-bit number (the input r), so the output r is 36-bit number.\n+\t */\n+\tfor (i = 0; i < ip->alu.src.n_bits / 32; i++, src32_ptr++)\n+\t\tr += *src32_ptr;\n+\n+\t/* The first input is a 16-bit number. The second input is a 20-bit\n+\t * number. Their sum is a 21-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n+\t * a 5-bit number (0 .. 31). The sum is a 17-bit number (0 .. 0x1000E).\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n+\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n+\t * 0x1001E), the output r is (0 .. 31). So no carry bit can be\n+\t * generated, therefore the output r is always a 16-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\tr = ~r & 0xFFFF;\n+\tr = r ? r : 0xFFFF;\n+\n+\t*dst16_ptr = (uint16_t)r;\n+}\n+\n #endif\n",
    "prefixes": [
        "12/24"
    ]
}