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GET /api/patches/9841/?format=api
{ "id": 9841, "url": "http://patches.dpdk.org/api/patches/9841/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1452735516-4527-6-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1452735516-4527-6-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1452735516-4527-6-git-send-email-wenzhuo.lu@intel.com", "date": "2016-01-14T01:38:35", "name": "[dpdk-dev,v2,5/6] ixgbe: support VxLAN & NVGRE TX checksum off-load", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d831a181b5a94d290e44a118dd08a698eab59443", "submitter": { "id": 258, "url": "http://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 10, "url": "http://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1452735516-4527-6-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/9841/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/9841/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0A9E28E99;\n\tThu, 14 Jan 2016 02:39:15 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 65AA48E87\n\tfor <dev@dpdk.org>; Thu, 14 Jan 2016 02:39:11 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP; 13 Jan 2016 17:38:54 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 13 Jan 2016 17:38:53 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u0E1cqCZ032225;\n\tThu, 14 Jan 2016 09:38:52 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u0E1cnsD004603; Thu, 14 Jan 2016 09:38:51 +0800", "(from wenzhuol@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u0E1cnwb004599; \n\tThu, 14 Jan 2016 09:38:49 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,292,1449561600\"; d=\"scan'208\";a=\"860101916\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 14 Jan 2016 09:38:35 +0800", "Message-Id": "<1452735516-4527-6-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1452735516-4527-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1452496044-17524-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1452735516-4527-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 5/6] ixgbe: support VxLAN & NVGRE TX checksum\n\toff-load", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The patch add VxLAN & NVGRE TX checksum off-load. When the flag of\nouter IP header checksum offload is set, we'll set the context\ndescriptor to enable this checksum off-load.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/ixgbe/ixgbe_rxtx.c | 52 ++++++++++++++++++++++++++++++++++--------\n drivers/net/ixgbe/ixgbe_rxtx.h | 6 ++++-\n lib/librte_mbuf/rte_mbuf.h | 2 ++\n 3 files changed, 49 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex 512ac3a..fea2495 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -85,7 +85,8 @@\n \t\tPKT_TX_VLAN_PKT |\t\t \\\n \t\tPKT_TX_IP_CKSUM |\t\t \\\n \t\tPKT_TX_L4_MASK |\t\t \\\n-\t\tPKT_TX_TCP_SEG)\n+\t\tPKT_TX_TCP_SEG |\t\t \\\n+\t\tPKT_TX_OUTER_IP_CKSUM)\n \n static inline struct rte_mbuf *\n rte_rxmbuf_alloc(struct rte_mempool *mp)\n@@ -364,9 +365,11 @@ ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,\n \tuint32_t ctx_idx;\n \tuint32_t vlan_macip_lens;\n \tunion ixgbe_tx_offload tx_offload_mask;\n+\tuint32_t seqnum_seed = 0;\n \n \tctx_idx = txq->ctx_curr;\n-\ttx_offload_mask.data = 0;\n+\ttx_offload_mask.data[0] = 0;\n+\ttx_offload_mask.data[1] = 0;\n \ttype_tucmd_mlhl = 0;\n \n \t/* Specify which HW CTX to upload. */\n@@ -430,9 +433,20 @@ ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,\n \t\t}\n \t}\n \n+\tif (ol_flags & PKT_TX_OUTER_IP_CKSUM) {\n+\t\ttx_offload_mask.outer_l3_len |= ~0;\n+\t\ttx_offload_mask.outer_l2_len |= ~0;\n+\t\tseqnum_seed |= tx_offload.outer_l3_len\n+\t\t\t << IXGBE_ADVTXD_OUTER_IPLEN;\n+\t\tseqnum_seed |= tx_offload.outer_l2_len\n+\t\t\t << IXGBE_ADVTXD_TUNNEL_LEN;\n+\t}\n+\n \ttxq->ctx_cache[ctx_idx].flags = ol_flags;\n-\ttxq->ctx_cache[ctx_idx].tx_offload.data =\n-\t\ttx_offload_mask.data & tx_offload.data;\n+\ttxq->ctx_cache[ctx_idx].tx_offload.data[0] =\n+\t\ttx_offload_mask.data[0] & tx_offload.data[0];\n+\ttxq->ctx_cache[ctx_idx].tx_offload.data[1] =\n+\t\ttx_offload_mask.data[1] & tx_offload.data[1];\n \ttxq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;\n \n \tctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);\n@@ -441,7 +455,7 @@ ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,\n \tvlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);\n \tctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);\n \tctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);\n-\tctx_txd->seqnum_seed = 0;\n+\tctx_txd->seqnum_seed = seqnum_seed;\n }\n \n /*\n@@ -454,16 +468,24 @@ what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,\n {\n \t/* If match with the current used context */\n \tif (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&\n-\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data ==\n-\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]\n+\t\t & tx_offload.data[0])) &&\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]\n+\t\t & tx_offload.data[1])))) {\n \t\t\treturn txq->ctx_curr;\n \t}\n \n \t/* What if match with the next context */\n \ttxq->ctx_curr ^= 1;\n \tif (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&\n-\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data ==\n-\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]\n+\t\t & tx_offload.data[0])) &&\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==\n+\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]\n+\t\t & tx_offload.data[1])))) {\n \t\t\treturn txq->ctx_curr;\n \t}\n \n@@ -492,6 +514,12 @@ tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)\n \t\tcmdtype |= IXGBE_ADVTXD_DCMD_VLE;\n \tif (ol_flags & PKT_TX_TCP_SEG)\n \t\tcmdtype |= IXGBE_ADVTXD_DCMD_TSE;\n+\tif (ol_flags & PKT_TX_OUTER_IP_CKSUM)\n+\t\tcmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);\n+\tif (ol_flags & PKT_TX_VXLAN_PKT)\n+\t\tcmdtype &= ~(1 << IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE);\n+\telse\n+\t\tcmdtype |= (1 << IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE);\n \treturn cmdtype;\n }\n \n@@ -588,8 +616,10 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint64_t tx_ol_req;\n \tuint32_t ctx = 0;\n \tuint32_t new_ctx;\n-\tunion ixgbe_tx_offload tx_offload = {0};\n+\tunion ixgbe_tx_offload tx_offload;\n \n+\ttx_offload.data[0] = 0;\n+\ttx_offload.data[1] = 0;\n \ttxq = tx_queue;\n \tsw_ring = txq->sw_ring;\n \ttxr = txq->tx_ring;\n@@ -623,6 +653,8 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\ttx_offload.l4_len = tx_pkt->l4_len;\n \t\t\ttx_offload.vlan_tci = tx_pkt->vlan_tci;\n \t\t\ttx_offload.tso_segsz = tx_pkt->tso_segsz;\n+\t\t\ttx_offload.outer_l2_len = tx_pkt->outer_l2_len;\n+\t\t\ttx_offload.outer_l3_len = tx_pkt->outer_l3_len;\n \n \t\t\t/* If new context need be built or reuse the exist ctx. */\n \t\t\tctx = what_advctx_update(txq, tx_ol_req,\ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h\nindex 475a800..c15f9fa 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.h\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.h\n@@ -163,7 +163,7 @@ enum ixgbe_advctx_num {\n \n /** Offload features */\n union ixgbe_tx_offload {\n-\tuint64_t data;\n+\tuint64_t data[2];\n \tstruct {\n \t\tuint64_t l2_len:7; /**< L2 (MAC) Header Length. */\n \t\tuint64_t l3_len:9; /**< L3 (IP) Header Length. */\n@@ -171,6 +171,10 @@ union ixgbe_tx_offload {\n \t\tuint64_t tso_segsz:16; /**< TCP TSO segment size */\n \t\tuint64_t vlan_tci:16;\n \t\t/**< VLAN Tag Control Identifier (CPU order). */\n+\n+\t\t/* fields for TX offloading of tunnels */\n+\t\tuint64_t outer_l3_len:8; /**< Outer L3 (IP) Hdr Length. */\n+\t\tuint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */\n \t};\n };\n \ndiff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h\nindex 5ad5e59..1bda00e 100644\n--- a/lib/librte_mbuf/rte_mbuf.h\n+++ b/lib/librte_mbuf/rte_mbuf.h\n@@ -103,6 +103,8 @@ extern \"C\" {\n \n /* add new TX flags here */\n \n+#define PKT_TX_VXLAN_PKT (1ULL << 48) /**< TX packet is a VxLAN packet. */\n+\n /**\n * Second VLAN insertion (QinQ) flag.\n */\n", "prefixes": [ "dpdk-dev", "v2", "5/6" ] }