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GET /api/patches/98289/?format=api
{ "id": 98289, "url": "http://patches.dpdk.org/api/patches/98289/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210908083758.312055-9-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210908083758.312055-9-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210908083758.312055-9-jiawenwu@trustnetic.com", "date": "2021-09-08T08:37:34", "name": "[08/32] net/ngbe: support basic statistics", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "d0ca83a764b731b9ce6c6957d75daf887f8018ae", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210908083758.312055-9-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 18760, "url": "http://patches.dpdk.org/api/series/18760/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18760", "date": "2021-09-08T08:37:26", "name": "net/ngbe: add many features", "version": 1, "mbox": "http://patches.dpdk.org/series/18760/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/98289/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/98289/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ABC43A0C56;\n\tWed, 8 Sep 2021 10:37:22 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 38617411A0;\n\tWed, 8 Sep 2021 10:36:42 +0200 (CEST)", "from smtpbg506.qq.com (smtpbg506.qq.com [203.205.250.33])\n by mails.dpdk.org (Postfix) with ESMTP id 3119D411A0\n for <dev@dpdk.org>; Wed, 8 Sep 2021 10:36:38 +0200 (CEST)", "from wxdbg.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Wed, 08 Sep 2021 16:36:33 +0800 (CST)" ], "X-QQ-mid": "bizesmtp47t1631090194tcw5lffv", "X-QQ-SSF": "01400000002000E0G000B00A0000000", "X-QQ-FEAT": "NC3V4KDEm0GNS7HtLA5n+4BPNGuSW5rO0xqv/czdpNXkevC9vdnsi2Pmg64YU\n bXkFvTXdsytF9hM7Fi7hOCr0ijrYeM43ntKE3Dm5HESSQvqtchX9LXYlRtezFP7C3qDGzOh\n 3LuvXLKpLkNCgixpTVzQi7LYnb4bIlEjfsB46My2DEOjGbnqq7faZD0672kj82XDtOhguUK\n 0cp5rVl54LHKqidjSdfqXz6LTsSBdbrSgdYKROtX+Av24yixE0f0fnr4S+8+LyznN2pP9Da\n R+SFuqXA9bntIZ1EyE86WI2gIkteZmz9n6HLBEtoIIU3WkaDWviYpwmP3SxlUBgCaHdQ3Hc\n uh9zDpGdVeKlvYMsN65/f4APJgbw//AI7JqKIgb", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Wed, 8 Sep 2021 16:37:34 +0800", "Message-Id": "<20210908083758.312055-9-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210908083758.312055-1-jiawenwu@trustnetic.com>", "References": "<20210908083758.312055-1-jiawenwu@trustnetic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign2", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH 08/32] net/ngbe: support basic statistics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Support to read and clear basic statistics, and configure per-queue\nstats counter mapping.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/ngbe.ini | 2 +\n doc/guides/nics/ngbe.rst | 1 +\n drivers/net/ngbe/base/ngbe_dummy.h | 5 +\n drivers/net/ngbe/base/ngbe_hw.c | 101 ++++++++++\n drivers/net/ngbe/base/ngbe_hw.h | 1 +\n drivers/net/ngbe/base/ngbe_type.h | 134 +++++++++++++\n drivers/net/ngbe/ngbe_ethdev.c | 300 +++++++++++++++++++++++++++++\n drivers/net/ngbe/ngbe_ethdev.h | 19 ++\n 8 files changed, 563 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/ngbe.ini b/doc/guides/nics/features/ngbe.ini\nindex 4ae2d66d15..f310fb102a 100644\n--- a/doc/guides/nics/features/ngbe.ini\n+++ b/doc/guides/nics/features/ngbe.ini\n@@ -19,6 +19,8 @@ L4 checksum offload = P\n Inner L3 checksum = P\n Inner L4 checksum = P\n Packet type parsing = Y\n+Basic stats = Y\n+Stats per queue = Y\n Multiprocess aware = Y\n Linux = Y\n ARMv8 = Y\ndiff --git a/doc/guides/nics/ngbe.rst b/doc/guides/nics/ngbe.rst\nindex 9518a59443..64c07e4741 100644\n--- a/doc/guides/nics/ngbe.rst\n+++ b/doc/guides/nics/ngbe.rst\n@@ -15,6 +15,7 @@ Features\n - Checksum offload\n - VLAN/QinQ stripping and inserting\n - TSO offload\n+- Port hardware statistics\n - Jumbo frames\n - Link state information\n - Scattered and gather for TX and RX\ndiff --git a/drivers/net/ngbe/base/ngbe_dummy.h b/drivers/net/ngbe/base/ngbe_dummy.h\nindex 8863acef0d..0def116c53 100644\n--- a/drivers/net/ngbe/base/ngbe_dummy.h\n+++ b/drivers/net/ngbe/base/ngbe_dummy.h\n@@ -55,6 +55,10 @@ static inline s32 ngbe_mac_stop_hw_dummy(struct ngbe_hw *TUP0)\n {\n \treturn NGBE_ERR_OPS_DUMMY;\n }\n+static inline s32 ngbe_mac_clear_hw_cntrs_dummy(struct ngbe_hw *TUP0)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n static inline s32 ngbe_mac_get_mac_addr_dummy(struct ngbe_hw *TUP0, u8 *TUP1)\n {\n \treturn NGBE_ERR_OPS_DUMMY;\n@@ -178,6 +182,7 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw)\n \thw->mac.reset_hw = ngbe_mac_reset_hw_dummy;\n \thw->mac.start_hw = ngbe_mac_start_hw_dummy;\n \thw->mac.stop_hw = ngbe_mac_stop_hw_dummy;\n+\thw->mac.clear_hw_cntrs = ngbe_mac_clear_hw_cntrs_dummy;\n \thw->mac.get_mac_addr = ngbe_mac_get_mac_addr_dummy;\n \thw->mac.enable_rx_dma = ngbe_mac_enable_rx_dma_dummy;\n \thw->mac.disable_sec_rx_path = ngbe_mac_disable_sec_rx_path_dummy;\ndiff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c\nindex 6b575fc67b..f302df5d9d 100644\n--- a/drivers/net/ngbe/base/ngbe_hw.c\n+++ b/drivers/net/ngbe/base/ngbe_hw.c\n@@ -19,6 +19,9 @@ s32 ngbe_start_hw(struct ngbe_hw *hw)\n {\n \tDEBUGFUNC(\"ngbe_start_hw\");\n \n+\t/* Clear statistics registers */\n+\thw->mac.clear_hw_cntrs(hw);\n+\n \t/* Clear adapter stopped flag */\n \thw->adapter_stopped = false;\n \n@@ -159,6 +162,7 @@ s32 ngbe_reset_hw_em(struct ngbe_hw *hw)\n \tmsec_delay(50);\n \n \tngbe_reset_misc_em(hw);\n+\thw->mac.clear_hw_cntrs(hw);\n \n \tmsec_delay(50);\n \n@@ -175,6 +179,102 @@ s32 ngbe_reset_hw_em(struct ngbe_hw *hw)\n \treturn status;\n }\n \n+/**\n+ * ngbe_clear_hw_cntrs - Generic clear hardware counters\n+ * @hw: pointer to hardware structure\n+ *\n+ * Clears all hardware statistics counters by reading them from the hardware\n+ * Statistics counters are clear on read.\n+ **/\n+s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)\n+{\n+\tu16 i = 0;\n+\n+\tDEBUGFUNC(\"ngbe_clear_hw_cntrs\");\n+\n+\t/* QP Stats */\n+\t/* don't write clear queue stats */\n+\tfor (i = 0; i < NGBE_MAX_QP; i++) {\n+\t\thw->qp_last[i].rx_qp_packets = 0;\n+\t\thw->qp_last[i].tx_qp_packets = 0;\n+\t\thw->qp_last[i].rx_qp_bytes = 0;\n+\t\thw->qp_last[i].tx_qp_bytes = 0;\n+\t\thw->qp_last[i].rx_qp_mc_packets = 0;\n+\t\thw->qp_last[i].tx_qp_mc_packets = 0;\n+\t\thw->qp_last[i].rx_qp_bc_packets = 0;\n+\t\thw->qp_last[i].tx_qp_bc_packets = 0;\n+\t}\n+\n+\t/* PB Stats */\n+\trd32(hw, NGBE_PBRXLNKXON);\n+\trd32(hw, NGBE_PBRXLNKXOFF);\n+\trd32(hw, NGBE_PBTXLNKXON);\n+\trd32(hw, NGBE_PBTXLNKXOFF);\n+\n+\t/* DMA Stats */\n+\trd32(hw, NGBE_DMARXPKT);\n+\trd32(hw, NGBE_DMATXPKT);\n+\n+\trd64(hw, NGBE_DMARXOCTL);\n+\trd64(hw, NGBE_DMATXOCTL);\n+\n+\t/* MAC Stats */\n+\trd64(hw, NGBE_MACRXERRCRCL);\n+\trd64(hw, NGBE_MACRXMPKTL);\n+\trd64(hw, NGBE_MACTXMPKTL);\n+\n+\trd64(hw, NGBE_MACRXPKTL);\n+\trd64(hw, NGBE_MACTXPKTL);\n+\trd64(hw, NGBE_MACRXGBOCTL);\n+\n+\trd64(hw, NGBE_MACRXOCTL);\n+\trd32(hw, NGBE_MACTXOCTL);\n+\n+\trd64(hw, NGBE_MACRX1TO64L);\n+\trd64(hw, NGBE_MACRX65TO127L);\n+\trd64(hw, NGBE_MACRX128TO255L);\n+\trd64(hw, NGBE_MACRX256TO511L);\n+\trd64(hw, NGBE_MACRX512TO1023L);\n+\trd64(hw, NGBE_MACRX1024TOMAXL);\n+\trd64(hw, NGBE_MACTX1TO64L);\n+\trd64(hw, NGBE_MACTX65TO127L);\n+\trd64(hw, NGBE_MACTX128TO255L);\n+\trd64(hw, NGBE_MACTX256TO511L);\n+\trd64(hw, NGBE_MACTX512TO1023L);\n+\trd64(hw, NGBE_MACTX1024TOMAXL);\n+\n+\trd64(hw, NGBE_MACRXERRLENL);\n+\trd32(hw, NGBE_MACRXOVERSIZE);\n+\trd32(hw, NGBE_MACRXJABBER);\n+\n+\t/* MACsec Stats */\n+\trd32(hw, NGBE_LSECTX_UTPKT);\n+\trd32(hw, NGBE_LSECTX_ENCPKT);\n+\trd32(hw, NGBE_LSECTX_PROTPKT);\n+\trd32(hw, NGBE_LSECTX_ENCOCT);\n+\trd32(hw, NGBE_LSECTX_PROTOCT);\n+\trd32(hw, NGBE_LSECRX_UTPKT);\n+\trd32(hw, NGBE_LSECRX_BTPKT);\n+\trd32(hw, NGBE_LSECRX_NOSCIPKT);\n+\trd32(hw, NGBE_LSECRX_UNSCIPKT);\n+\trd32(hw, NGBE_LSECRX_DECOCT);\n+\trd32(hw, NGBE_LSECRX_VLDOCT);\n+\trd32(hw, NGBE_LSECRX_UNCHKPKT);\n+\trd32(hw, NGBE_LSECRX_DLYPKT);\n+\trd32(hw, NGBE_LSECRX_LATEPKT);\n+\tfor (i = 0; i < 2; i++) {\n+\t\trd32(hw, NGBE_LSECRX_OKPKT(i));\n+\t\trd32(hw, NGBE_LSECRX_INVPKT(i));\n+\t\trd32(hw, NGBE_LSECRX_BADPKT(i));\n+\t}\n+\tfor (i = 0; i < 4; i++) {\n+\t\trd32(hw, NGBE_LSECRX_INVSAPKT(i));\n+\t\trd32(hw, NGBE_LSECRX_BADSAPKT(i));\n+\t}\n+\n+\treturn 0;\n+}\n+\n /**\n * ngbe_get_mac_addr - Generic get MAC address\n * @hw: pointer to hardware structure\n@@ -988,6 +1088,7 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw)\n \tmac->init_hw = ngbe_init_hw;\n \tmac->reset_hw = ngbe_reset_hw_em;\n \tmac->start_hw = ngbe_start_hw;\n+\tmac->clear_hw_cntrs = ngbe_clear_hw_cntrs;\n \tmac->enable_rx_dma = ngbe_enable_rx_dma;\n \tmac->get_mac_addr = ngbe_get_mac_addr;\n \tmac->stop_hw = ngbe_stop_hw;\ndiff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h\nindex 17a0a03c88..6a08c02bee 100644\n--- a/drivers/net/ngbe/base/ngbe_hw.h\n+++ b/drivers/net/ngbe/base/ngbe_hw.h\n@@ -17,6 +17,7 @@ s32 ngbe_init_hw(struct ngbe_hw *hw);\n s32 ngbe_start_hw(struct ngbe_hw *hw);\n s32 ngbe_reset_hw_em(struct ngbe_hw *hw);\n s32 ngbe_stop_hw(struct ngbe_hw *hw);\n+s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw);\n s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr);\n \n void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw);\ndiff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h\nindex 28540e4ba0..c13f0208fd 100644\n--- a/drivers/net/ngbe/base/ngbe_type.h\n+++ b/drivers/net/ngbe/base/ngbe_type.h\n@@ -9,6 +9,7 @@\n #define NGBE_LINK_UP_TIME\t90 /* 9.0 Seconds */\n \n #define NGBE_FRAME_SIZE_DFT (1522) /* Default frame size, +FCS */\n+#define NGBE_MAX_QP (8)\n \n #define NGBE_ALIGN\t\t128 /* as intel did */\n #define NGBE_ISB_SIZE\t\t16\n@@ -77,6 +78,127 @@ struct ngbe_bus_info {\n \tu8 lan_id;\n };\n \n+/* Statistics counters collected by the MAC */\n+/* PB[] RxTx */\n+struct ngbe_pb_stats {\n+\tu64 tx_pb_xon_packets;\n+\tu64 rx_pb_xon_packets;\n+\tu64 tx_pb_xoff_packets;\n+\tu64 rx_pb_xoff_packets;\n+\tu64 rx_pb_dropped;\n+\tu64 rx_pb_mbuf_alloc_errors;\n+\tu64 tx_pb_xon2off_packets;\n+};\n+\n+/* QP[] RxTx */\n+struct ngbe_qp_stats {\n+\tu64 rx_qp_packets;\n+\tu64 tx_qp_packets;\n+\tu64 rx_qp_bytes;\n+\tu64 tx_qp_bytes;\n+\tu64 rx_qp_mc_packets;\n+};\n+\n+struct ngbe_hw_stats {\n+\t/* MNG RxTx */\n+\tu64 mng_bmc2host_packets;\n+\tu64 mng_host2bmc_packets;\n+\t/* Basix RxTx */\n+\tu64 rx_drop_packets;\n+\tu64 tx_drop_packets;\n+\tu64 rx_dma_drop;\n+\tu64 tx_secdrp_packets;\n+\tu64 rx_packets;\n+\tu64 tx_packets;\n+\tu64 rx_bytes;\n+\tu64 tx_bytes;\n+\tu64 rx_total_bytes;\n+\tu64 rx_total_packets;\n+\tu64 tx_total_packets;\n+\tu64 rx_total_missed_packets;\n+\tu64 rx_broadcast_packets;\n+\tu64 tx_broadcast_packets;\n+\tu64 rx_multicast_packets;\n+\tu64 tx_multicast_packets;\n+\tu64 rx_management_packets;\n+\tu64 tx_management_packets;\n+\tu64 rx_management_dropped;\n+\n+\t/* Basic Error */\n+\tu64 rx_crc_errors;\n+\tu64 rx_illegal_byte_errors;\n+\tu64 rx_error_bytes;\n+\tu64 rx_mac_short_packet_dropped;\n+\tu64 rx_length_errors;\n+\tu64 rx_undersize_errors;\n+\tu64 rx_fragment_errors;\n+\tu64 rx_oversize_errors;\n+\tu64 rx_jabber_errors;\n+\tu64 rx_l3_l4_xsum_error;\n+\tu64 mac_local_errors;\n+\tu64 mac_remote_errors;\n+\n+\t/* MACSEC */\n+\tu64 tx_macsec_pkts_untagged;\n+\tu64 tx_macsec_pkts_encrypted;\n+\tu64 tx_macsec_pkts_protected;\n+\tu64 tx_macsec_octets_encrypted;\n+\tu64 tx_macsec_octets_protected;\n+\tu64 rx_macsec_pkts_untagged;\n+\tu64 rx_macsec_pkts_badtag;\n+\tu64 rx_macsec_pkts_nosci;\n+\tu64 rx_macsec_pkts_unknownsci;\n+\tu64 rx_macsec_octets_decrypted;\n+\tu64 rx_macsec_octets_validated;\n+\tu64 rx_macsec_sc_pkts_unchecked;\n+\tu64 rx_macsec_sc_pkts_delayed;\n+\tu64 rx_macsec_sc_pkts_late;\n+\tu64 rx_macsec_sa_pkts_ok;\n+\tu64 rx_macsec_sa_pkts_invalid;\n+\tu64 rx_macsec_sa_pkts_notvalid;\n+\tu64 rx_macsec_sa_pkts_unusedsa;\n+\tu64 rx_macsec_sa_pkts_notusingsa;\n+\n+\t/* MAC RxTx */\n+\tu64 rx_size_64_packets;\n+\tu64 rx_size_65_to_127_packets;\n+\tu64 rx_size_128_to_255_packets;\n+\tu64 rx_size_256_to_511_packets;\n+\tu64 rx_size_512_to_1023_packets;\n+\tu64 rx_size_1024_to_max_packets;\n+\tu64 tx_size_64_packets;\n+\tu64 tx_size_65_to_127_packets;\n+\tu64 tx_size_128_to_255_packets;\n+\tu64 tx_size_256_to_511_packets;\n+\tu64 tx_size_512_to_1023_packets;\n+\tu64 tx_size_1024_to_max_packets;\n+\n+\t/* Flow Control */\n+\tu64 tx_xon_packets;\n+\tu64 rx_xon_packets;\n+\tu64 tx_xoff_packets;\n+\tu64 rx_xoff_packets;\n+\n+\tu64 rx_up_dropped;\n+\n+\tu64 rdb_pkt_cnt;\n+\tu64 rdb_repli_cnt;\n+\tu64 rdb_drp_cnt;\n+\n+\t/* QP[] RxTx */\n+\tstruct {\n+\t\tu64 rx_qp_packets;\n+\t\tu64 tx_qp_packets;\n+\t\tu64 rx_qp_bytes;\n+\t\tu64 tx_qp_bytes;\n+\t\tu64 rx_qp_mc_packets;\n+\t\tu64 tx_qp_mc_packets;\n+\t\tu64 rx_qp_bc_packets;\n+\t\tu64 tx_qp_bc_packets;\n+\t} qp[NGBE_MAX_QP];\n+\n+};\n+\n struct ngbe_rom_info {\n \ts32 (*init_params)(struct ngbe_hw *hw);\n \ts32 (*validate_checksum)(struct ngbe_hw *hw, u16 *checksum_val);\n@@ -96,6 +218,7 @@ struct ngbe_mac_info {\n \ts32 (*reset_hw)(struct ngbe_hw *hw);\n \ts32 (*start_hw)(struct ngbe_hw *hw);\n \ts32 (*stop_hw)(struct ngbe_hw *hw);\n+\ts32 (*clear_hw_cntrs)(struct ngbe_hw *hw);\n \ts32 (*get_mac_addr)(struct ngbe_hw *hw, u8 *mac_addr);\n \ts32 (*enable_rx_dma)(struct ngbe_hw *hw, u32 regval);\n \ts32 (*disable_sec_rx_path)(struct ngbe_hw *hw);\n@@ -195,7 +318,18 @@ struct ngbe_hw {\n \n \tu32 q_rx_regs[8 * 4];\n \tu32 q_tx_regs[8 * 4];\n+\tbool offset_loaded;\n \tbool is_pf;\n+\tstruct {\n+\t\tu64 rx_qp_packets;\n+\t\tu64 tx_qp_packets;\n+\t\tu64 rx_qp_bytes;\n+\t\tu64 tx_qp_bytes;\n+\t\tu64 rx_qp_mc_packets;\n+\t\tu64 tx_qp_mc_packets;\n+\t\tu64 rx_qp_bc_packets;\n+\t\tu64 tx_qp_bc_packets;\n+\t} qp_last[NGBE_MAX_QP];\n };\n \n #include \"ngbe_regs.h\"\ndiff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c\nindex 3903eb0a2c..3d459718b1 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.c\n+++ b/drivers/net/ngbe/ngbe_ethdev.c\n@@ -17,6 +17,7 @@\n static int ngbe_dev_close(struct rte_eth_dev *dev);\n static int ngbe_dev_link_update(struct rte_eth_dev *dev,\n \t\t\t\tint wait_to_complete);\n+static int ngbe_dev_stats_reset(struct rte_eth_dev *dev);\n static void ngbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);\n static void ngbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,\n \t\t\t\t\tuint16_t queue);\n@@ -122,6 +123,56 @@ ngbe_disable_intr(struct ngbe_hw *hw)\n \tngbe_flush(hw);\n }\n \n+static int\n+ngbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,\n+\t\t\t\t uint16_t queue_id,\n+\t\t\t\t uint8_t stat_idx,\n+\t\t\t\t uint8_t is_rx)\n+{\n+\tstruct ngbe_stat_mappings *stat_mappings =\n+\t\tNGBE_DEV_STAT_MAPPINGS(eth_dev);\n+\tuint32_t qsmr_mask = 0;\n+\tuint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;\n+\tuint32_t q_map;\n+\tuint8_t n, offset;\n+\n+\tif (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)\n+\t\treturn -EIO;\n+\n+\tPMD_INIT_LOG(DEBUG, \"Setting port %d, %s queue_id %d to stat index %d\",\n+\t\t (int)(eth_dev->data->port_id), is_rx ? \"RX\" : \"TX\",\n+\t\t queue_id, stat_idx);\n+\n+\tn = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);\n+\tif (n >= NGBE_NB_STAT_MAPPING) {\n+\t\tPMD_INIT_LOG(ERR, \"Nb of stat mapping registers exceeded\");\n+\t\treturn -EIO;\n+\t}\n+\toffset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);\n+\n+\t/* Now clear any previous stat_idx set */\n+\tclearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);\n+\tif (!is_rx)\n+\t\tstat_mappings->tqsm[n] &= ~clearing_mask;\n+\telse\n+\t\tstat_mappings->rqsm[n] &= ~clearing_mask;\n+\n+\tq_map = (uint32_t)stat_idx;\n+\tq_map &= QMAP_FIELD_RESERVED_BITS_MASK;\n+\tqsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);\n+\tif (!is_rx)\n+\t\tstat_mappings->tqsm[n] |= qsmr_mask;\n+\telse\n+\t\tstat_mappings->rqsm[n] |= qsmr_mask;\n+\n+\tPMD_INIT_LOG(DEBUG, \"Set port %d, %s queue_id %d to stat index %d\",\n+\t\t (int)(eth_dev->data->port_id), is_rx ? \"RX\" : \"TX\",\n+\t\t queue_id, stat_idx);\n+\tPMD_INIT_LOG(DEBUG, \"%s[%d] = 0x%08x\", is_rx ? \"RQSMR\" : \"TQSM\", n,\n+\t\t is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);\n+\treturn 0;\n+}\n+\n /*\n * Ensure that all locks are released before first NVM or PHY access\n */\n@@ -236,6 +287,9 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n \t\treturn -EIO;\n \t}\n \n+\t/* Reset the hw statistics */\n+\tngbe_dev_stats_reset(eth_dev);\n+\n \t/* disable interrupt */\n \tngbe_disable_intr(hw);\n \n@@ -616,6 +670,7 @@ static int\n ngbe_dev_start(struct rte_eth_dev *dev)\n {\n \tstruct ngbe_hw *hw = ngbe_dev_hw(dev);\n+\tstruct ngbe_hw_stats *hw_stats = NGBE_DEV_STATS(dev);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tuint32_t intr_vector = 0;\n@@ -780,6 +835,9 @@ ngbe_dev_start(struct rte_eth_dev *dev)\n \t */\n \tngbe_dev_link_update(dev, 0);\n \n+\tngbe_read_stats_registers(hw, hw_stats);\n+\thw->offset_loaded = 1;\n+\n \treturn 0;\n \n error:\n@@ -916,6 +974,245 @@ ngbe_dev_reset(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+#define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \\\n+\t{ \\\n+\t\tuint32_t current_counter = rd32(hw, reg); \\\n+\t\tif (current_counter < last_counter) \\\n+\t\t\tcurrent_counter += 0x100000000LL; \\\n+\t\tif (!hw->offset_loaded) \\\n+\t\t\tlast_counter = current_counter; \\\n+\t\tcounter = current_counter - last_counter; \\\n+\t\tcounter &= 0xFFFFFFFFLL; \\\n+\t}\n+\n+#define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \\\n+\t{ \\\n+\t\tuint64_t current_counter_lsb = rd32(hw, reg_lsb); \\\n+\t\tuint64_t current_counter_msb = rd32(hw, reg_msb); \\\n+\t\tuint64_t current_counter = (current_counter_msb << 32) | \\\n+\t\t\tcurrent_counter_lsb; \\\n+\t\tif (current_counter < last_counter) \\\n+\t\t\tcurrent_counter += 0x1000000000LL; \\\n+\t\tif (!hw->offset_loaded) \\\n+\t\t\tlast_counter = current_counter; \\\n+\t\tcounter = current_counter - last_counter; \\\n+\t\tcounter &= 0xFFFFFFFFFLL; \\\n+\t}\n+\n+void\n+ngbe_read_stats_registers(struct ngbe_hw *hw,\n+\t\t\t struct ngbe_hw_stats *hw_stats)\n+{\n+\tunsigned int i;\n+\n+\t/* QP Stats */\n+\tfor (i = 0; i < hw->nb_rx_queues; i++) {\n+\t\tUPDATE_QP_COUNTER_32bit(NGBE_QPRXPKT(i),\n+\t\t\thw->qp_last[i].rx_qp_packets,\n+\t\t\thw_stats->qp[i].rx_qp_packets);\n+\t\tUPDATE_QP_COUNTER_36bit(NGBE_QPRXOCTL(i), NGBE_QPRXOCTH(i),\n+\t\t\thw->qp_last[i].rx_qp_bytes,\n+\t\t\thw_stats->qp[i].rx_qp_bytes);\n+\t\tUPDATE_QP_COUNTER_32bit(NGBE_QPRXMPKT(i),\n+\t\t\thw->qp_last[i].rx_qp_mc_packets,\n+\t\t\thw_stats->qp[i].rx_qp_mc_packets);\n+\t\tUPDATE_QP_COUNTER_32bit(NGBE_QPRXBPKT(i),\n+\t\t\thw->qp_last[i].rx_qp_bc_packets,\n+\t\t\thw_stats->qp[i].rx_qp_bc_packets);\n+\t}\n+\n+\tfor (i = 0; i < hw->nb_tx_queues; i++) {\n+\t\tUPDATE_QP_COUNTER_32bit(NGBE_QPTXPKT(i),\n+\t\t\thw->qp_last[i].tx_qp_packets,\n+\t\t\thw_stats->qp[i].tx_qp_packets);\n+\t\tUPDATE_QP_COUNTER_36bit(NGBE_QPTXOCTL(i), NGBE_QPTXOCTH(i),\n+\t\t\thw->qp_last[i].tx_qp_bytes,\n+\t\t\thw_stats->qp[i].tx_qp_bytes);\n+\t\tUPDATE_QP_COUNTER_32bit(NGBE_QPTXMPKT(i),\n+\t\t\thw->qp_last[i].tx_qp_mc_packets,\n+\t\t\thw_stats->qp[i].tx_qp_mc_packets);\n+\t\tUPDATE_QP_COUNTER_32bit(NGBE_QPTXBPKT(i),\n+\t\t\thw->qp_last[i].tx_qp_bc_packets,\n+\t\t\thw_stats->qp[i].tx_qp_bc_packets);\n+\t}\n+\n+\t/* PB Stats */\n+\thw_stats->rx_up_dropped += rd32(hw, NGBE_PBRXMISS);\n+\thw_stats->rdb_pkt_cnt += rd32(hw, NGBE_PBRXPKT);\n+\thw_stats->rdb_repli_cnt += rd32(hw, NGBE_PBRXREP);\n+\thw_stats->rdb_drp_cnt += rd32(hw, NGBE_PBRXDROP);\n+\thw_stats->tx_xoff_packets += rd32(hw, NGBE_PBTXLNKXOFF);\n+\thw_stats->tx_xon_packets += rd32(hw, NGBE_PBTXLNKXON);\n+\n+\thw_stats->rx_xon_packets += rd32(hw, NGBE_PBRXLNKXON);\n+\thw_stats->rx_xoff_packets += rd32(hw, NGBE_PBRXLNKXOFF);\n+\n+\t/* DMA Stats */\n+\thw_stats->rx_drop_packets += rd32(hw, NGBE_DMARXDROP);\n+\thw_stats->tx_drop_packets += rd32(hw, NGBE_DMATXDROP);\n+\thw_stats->rx_dma_drop += rd32(hw, NGBE_DMARXDROP);\n+\thw_stats->tx_secdrp_packets += rd32(hw, NGBE_DMATXSECDROP);\n+\thw_stats->rx_packets += rd32(hw, NGBE_DMARXPKT);\n+\thw_stats->tx_packets += rd32(hw, NGBE_DMATXPKT);\n+\thw_stats->rx_bytes += rd64(hw, NGBE_DMARXOCTL);\n+\thw_stats->tx_bytes += rd64(hw, NGBE_DMATXOCTL);\n+\n+\t/* MAC Stats */\n+\thw_stats->rx_crc_errors += rd64(hw, NGBE_MACRXERRCRCL);\n+\thw_stats->rx_multicast_packets += rd64(hw, NGBE_MACRXMPKTL);\n+\thw_stats->tx_multicast_packets += rd64(hw, NGBE_MACTXMPKTL);\n+\n+\thw_stats->rx_total_packets += rd64(hw, NGBE_MACRXPKTL);\n+\thw_stats->tx_total_packets += rd64(hw, NGBE_MACTXPKTL);\n+\thw_stats->rx_total_bytes += rd64(hw, NGBE_MACRXGBOCTL);\n+\n+\thw_stats->rx_broadcast_packets += rd64(hw, NGBE_MACRXOCTL);\n+\thw_stats->tx_broadcast_packets += rd32(hw, NGBE_MACTXOCTL);\n+\n+\thw_stats->rx_size_64_packets += rd64(hw, NGBE_MACRX1TO64L);\n+\thw_stats->rx_size_65_to_127_packets += rd64(hw, NGBE_MACRX65TO127L);\n+\thw_stats->rx_size_128_to_255_packets += rd64(hw, NGBE_MACRX128TO255L);\n+\thw_stats->rx_size_256_to_511_packets += rd64(hw, NGBE_MACRX256TO511L);\n+\thw_stats->rx_size_512_to_1023_packets +=\n+\t\t\trd64(hw, NGBE_MACRX512TO1023L);\n+\thw_stats->rx_size_1024_to_max_packets +=\n+\t\t\trd64(hw, NGBE_MACRX1024TOMAXL);\n+\thw_stats->tx_size_64_packets += rd64(hw, NGBE_MACTX1TO64L);\n+\thw_stats->tx_size_65_to_127_packets += rd64(hw, NGBE_MACTX65TO127L);\n+\thw_stats->tx_size_128_to_255_packets += rd64(hw, NGBE_MACTX128TO255L);\n+\thw_stats->tx_size_256_to_511_packets += rd64(hw, NGBE_MACTX256TO511L);\n+\thw_stats->tx_size_512_to_1023_packets +=\n+\t\t\trd64(hw, NGBE_MACTX512TO1023L);\n+\thw_stats->tx_size_1024_to_max_packets +=\n+\t\t\trd64(hw, NGBE_MACTX1024TOMAXL);\n+\n+\thw_stats->rx_undersize_errors += rd64(hw, NGBE_MACRXERRLENL);\n+\thw_stats->rx_oversize_errors += rd32(hw, NGBE_MACRXOVERSIZE);\n+\thw_stats->rx_jabber_errors += rd32(hw, NGBE_MACRXJABBER);\n+\n+\t/* MNG Stats */\n+\thw_stats->mng_bmc2host_packets = rd32(hw, NGBE_MNGBMC2OS);\n+\thw_stats->mng_host2bmc_packets = rd32(hw, NGBE_MNGOS2BMC);\n+\thw_stats->rx_management_packets = rd32(hw, NGBE_DMARXMNG);\n+\thw_stats->tx_management_packets = rd32(hw, NGBE_DMATXMNG);\n+\n+\t/* MACsec Stats */\n+\thw_stats->tx_macsec_pkts_untagged += rd32(hw, NGBE_LSECTX_UTPKT);\n+\thw_stats->tx_macsec_pkts_encrypted +=\n+\t\t\trd32(hw, NGBE_LSECTX_ENCPKT);\n+\thw_stats->tx_macsec_pkts_protected +=\n+\t\t\trd32(hw, NGBE_LSECTX_PROTPKT);\n+\thw_stats->tx_macsec_octets_encrypted +=\n+\t\t\trd32(hw, NGBE_LSECTX_ENCOCT);\n+\thw_stats->tx_macsec_octets_protected +=\n+\t\t\trd32(hw, NGBE_LSECTX_PROTOCT);\n+\thw_stats->rx_macsec_pkts_untagged += rd32(hw, NGBE_LSECRX_UTPKT);\n+\thw_stats->rx_macsec_pkts_badtag += rd32(hw, NGBE_LSECRX_BTPKT);\n+\thw_stats->rx_macsec_pkts_nosci += rd32(hw, NGBE_LSECRX_NOSCIPKT);\n+\thw_stats->rx_macsec_pkts_unknownsci += rd32(hw, NGBE_LSECRX_UNSCIPKT);\n+\thw_stats->rx_macsec_octets_decrypted += rd32(hw, NGBE_LSECRX_DECOCT);\n+\thw_stats->rx_macsec_octets_validated += rd32(hw, NGBE_LSECRX_VLDOCT);\n+\thw_stats->rx_macsec_sc_pkts_unchecked +=\n+\t\t\trd32(hw, NGBE_LSECRX_UNCHKPKT);\n+\thw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, NGBE_LSECRX_DLYPKT);\n+\thw_stats->rx_macsec_sc_pkts_late += rd32(hw, NGBE_LSECRX_LATEPKT);\n+\tfor (i = 0; i < 2; i++) {\n+\t\thw_stats->rx_macsec_sa_pkts_ok +=\n+\t\t\trd32(hw, NGBE_LSECRX_OKPKT(i));\n+\t\thw_stats->rx_macsec_sa_pkts_invalid +=\n+\t\t\trd32(hw, NGBE_LSECRX_INVPKT(i));\n+\t\thw_stats->rx_macsec_sa_pkts_notvalid +=\n+\t\t\trd32(hw, NGBE_LSECRX_BADPKT(i));\n+\t}\n+\tfor (i = 0; i < 4; i++) {\n+\t\thw_stats->rx_macsec_sa_pkts_unusedsa +=\n+\t\t\trd32(hw, NGBE_LSECRX_INVSAPKT(i));\n+\t\thw_stats->rx_macsec_sa_pkts_notusingsa +=\n+\t\t\trd32(hw, NGBE_LSECRX_BADSAPKT(i));\n+\t}\n+\thw_stats->rx_total_missed_packets =\n+\t\t\thw_stats->rx_up_dropped;\n+}\n+\n+static int\n+ngbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+{\n+\tstruct ngbe_hw *hw = ngbe_dev_hw(dev);\n+\tstruct ngbe_hw_stats *hw_stats = NGBE_DEV_STATS(dev);\n+\tstruct ngbe_stat_mappings *stat_mappings =\n+\t\t\tNGBE_DEV_STAT_MAPPINGS(dev);\n+\tuint32_t i, j;\n+\n+\tngbe_read_stats_registers(hw, hw_stats);\n+\n+\tif (stats == NULL)\n+\t\treturn -EINVAL;\n+\n+\t/* Fill out the rte_eth_stats statistics structure */\n+\tstats->ipackets = hw_stats->rx_packets;\n+\tstats->ibytes = hw_stats->rx_bytes;\n+\tstats->opackets = hw_stats->tx_packets;\n+\tstats->obytes = hw_stats->tx_bytes;\n+\n+\tmemset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));\n+\tmemset(&stats->q_opackets, 0, sizeof(stats->q_opackets));\n+\tmemset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));\n+\tmemset(&stats->q_obytes, 0, sizeof(stats->q_obytes));\n+\tmemset(&stats->q_errors, 0, sizeof(stats->q_errors));\n+\tfor (i = 0; i < NGBE_MAX_QP; i++) {\n+\t\tuint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;\n+\t\tuint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;\n+\t\tuint32_t q_map;\n+\n+\t\tq_map = (stat_mappings->rqsm[n] >> offset)\n+\t\t\t\t& QMAP_FIELD_RESERVED_BITS_MASK;\n+\t\tj = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS\n+\t\t ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);\n+\t\tstats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;\n+\t\tstats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;\n+\n+\t\tq_map = (stat_mappings->tqsm[n] >> offset)\n+\t\t\t\t& QMAP_FIELD_RESERVED_BITS_MASK;\n+\t\tj = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS\n+\t\t ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);\n+\t\tstats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;\n+\t\tstats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;\n+\t}\n+\n+\t/* Rx Errors */\n+\tstats->imissed = hw_stats->rx_total_missed_packets +\n+\t\t\t hw_stats->rx_dma_drop;\n+\tstats->ierrors = hw_stats->rx_crc_errors +\n+\t\t\t hw_stats->rx_mac_short_packet_dropped +\n+\t\t\t hw_stats->rx_length_errors +\n+\t\t\t hw_stats->rx_undersize_errors +\n+\t\t\t hw_stats->rx_oversize_errors +\n+\t\t\t hw_stats->rx_illegal_byte_errors +\n+\t\t\t hw_stats->rx_error_bytes +\n+\t\t\t hw_stats->rx_fragment_errors;\n+\n+\t/* Tx Errors */\n+\tstats->oerrors = 0;\n+\treturn 0;\n+}\n+\n+static int\n+ngbe_dev_stats_reset(struct rte_eth_dev *dev)\n+{\n+\tstruct ngbe_hw *hw = ngbe_dev_hw(dev);\n+\tstruct ngbe_hw_stats *hw_stats = NGBE_DEV_STATS(dev);\n+\n+\t/* HW registers are cleared on read */\n+\thw->offset_loaded = 0;\n+\tngbe_dev_stats_get(dev, NULL);\n+\thw->offset_loaded = 1;\n+\n+\t/* Reset software totals */\n+\tmemset(hw_stats, 0, sizeof(*hw_stats));\n+\n+\treturn 0;\n+}\n+\n static int\n ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n {\n@@ -1462,6 +1759,9 @@ static const struct eth_dev_ops ngbe_eth_dev_ops = {\n \t.dev_close = ngbe_dev_close,\n \t.dev_reset = ngbe_dev_reset,\n \t.link_update = ngbe_dev_link_update,\n+\t.stats_get = ngbe_dev_stats_get,\n+\t.stats_reset = ngbe_dev_stats_reset,\n+\t.queue_stats_mapping_set = ngbe_dev_queue_stats_mapping_set,\n \t.vlan_offload_set = ngbe_vlan_offload_set,\n \t.rx_queue_start\t = ngbe_dev_rx_queue_start,\n \t.rx_queue_stop = ngbe_dev_rx_queue_stop,\ndiff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h\nindex 8b3a1cdc3d..c0f1a50c66 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.h\n+++ b/drivers/net/ngbe/ngbe_ethdev.h\n@@ -40,6 +40,15 @@ struct ngbe_interrupt {\n \tuint64_t mask_orig; /* save mask during delayed handler */\n };\n \n+#define NGBE_NB_STAT_MAPPING 32\n+#define QSM_REG_NB_BITS_PER_QMAP_FIELD 8\n+#define NB_QMAP_FIELDS_PER_QSM_REG 4\n+#define QMAP_FIELD_RESERVED_BITS_MASK 0x0f\n+struct ngbe_stat_mappings {\n+\tuint32_t tqsm[NGBE_NB_STAT_MAPPING];\n+\tuint32_t rqsm[NGBE_NB_STAT_MAPPING];\n+};\n+\n struct ngbe_vfta {\n \tuint32_t vfta[NGBE_VFTA_SIZE];\n };\n@@ -53,7 +62,9 @@ struct ngbe_hwstrip {\n */\n struct ngbe_adapter {\n \tstruct ngbe_hw hw;\n+\tstruct ngbe_hw_stats stats;\n \tstruct ngbe_interrupt intr;\n+\tstruct ngbe_stat_mappings stat_mappings;\n \tstruct ngbe_vfta shadow_vfta;\n \tstruct ngbe_hwstrip hwstrip;\n \tbool rx_bulk_alloc_allowed;\n@@ -76,6 +87,9 @@ ngbe_dev_hw(struct rte_eth_dev *dev)\n \treturn hw;\n }\n \n+#define NGBE_DEV_STATS(dev) \\\n+\t(&((struct ngbe_adapter *)(dev)->data->dev_private)->stats)\n+\n static inline struct ngbe_interrupt *\n ngbe_dev_intr(struct rte_eth_dev *dev)\n {\n@@ -85,6 +99,9 @@ ngbe_dev_intr(struct rte_eth_dev *dev)\n \treturn intr;\n }\n \n+#define NGBE_DEV_STAT_MAPPINGS(dev) \\\n+\t(&((struct ngbe_adapter *)(dev)->data->dev_private)->stat_mappings)\n+\n #define NGBE_DEV_VFTA(dev) \\\n \t(&((struct ngbe_adapter *)(dev)->data->dev_private)->shadow_vfta)\n \n@@ -190,5 +207,7 @@ void ngbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,\n \t\tuint16_t queue, bool on);\n void ngbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,\n \t\t\t\t\t\t int mask);\n+void ngbe_read_stats_registers(struct ngbe_hw *hw,\n+\t\t\t struct ngbe_hw_stats *hw_stats);\n \n #endif /* _NGBE_ETHDEV_H_ */\n", "prefixes": [ "08/32" ] }