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GET /api/patches/98211/?format=api
{ "id": 98211, "url": "http://patches.dpdk.org/api/patches/98211/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210907164925.291904-9-bruce.richardson@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210907164925.291904-9-bruce.richardson@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210907164925.291904-9-bruce.richardson@intel.com", "date": "2021-09-07T16:49:25", "name": "[v3,8/8] app/test: add dmadev burst capacity API test", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e4d818087015f84ce9b8172b74b2249a54d69785", "submitter": { "id": 20, "url": "http://patches.dpdk.org/api/people/20/?format=api", "name": "Bruce Richardson", "email": "bruce.richardson@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210907164925.291904-9-bruce.richardson@intel.com/mbox/", "series": [ { "id": 18744, "url": "http://patches.dpdk.org/api/series/18744/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18744", "date": "2021-09-07T16:49:24", "name": "add test suite for DMA drivers", "version": 3, "mbox": "http://patches.dpdk.org/series/18744/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/98211/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/98211/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3B67FA0C47;\n\tTue, 7 Sep 2021 18:55:10 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1AEDE411A4;\n\tTue, 7 Sep 2021 18:55:06 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 9554A410EF\n for <dev@dpdk.org>; Tue, 7 Sep 2021 18:55:04 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Sep 2021 09:50:03 -0700", "from silpixa00399126.ir.intel.com ([10.237.223.29])\n by orsmga007.jf.intel.com with ESMTP; 07 Sep 2021 09:50:00 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10099\"; a=\"207374740\"", "E=Sophos;i=\"5.85,274,1624345200\"; d=\"scan'208\";a=\"207374740\"", "E=Sophos;i=\"5.85,274,1624345200\"; d=\"scan'208\";a=\"469268922\"" ], "X-ExtLoop1": "1", "From": "Bruce Richardson <bruce.richardson@intel.com>", "To": "dev@dpdk.org", "Cc": "conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com,\n jerinj@marvell.com, Bruce Richardson <bruce.richardson@intel.com>", "Date": "Tue, 7 Sep 2021 17:49:25 +0100", "Message-Id": "<20210907164925.291904-9-bruce.richardson@intel.com>", "X-Mailer": "git-send-email 2.30.2", "In-Reply-To": "<20210907164925.291904-1-bruce.richardson@intel.com>", "References": "<20210826183301.333442-1-bruce.richardson@intel.com>\n <20210907164925.291904-1-bruce.richardson@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 8/8] app/test: add dmadev burst capacity API\n test", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kevin Laatz <kevin.laatz@intel.com>\n\nAdd a test case to validate the functionality of drivers' burst capacity\nAPI implementations.\n\nSigned-off-by: Kevin Laatz <kevin.laatz@intel.com>\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n app/test/test_dmadev.c | 68 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 68 insertions(+)", "diff": "diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c\nindex 9ad865f249..98dddae6d6 100644\n--- a/app/test/test_dmadev.c\n+++ b/app/test/test_dmadev.c\n@@ -671,6 +671,69 @@ test_enqueue_fill(int dev_id, uint16_t vchan)\n \treturn 0;\n }\n \n+static int\n+test_burst_capacity(int dev_id, uint16_t vchan)\n+{\n+#define CAP_TEST_BURST_SIZE\t64\n+\tconst int ring_space = rte_dmadev_burst_capacity(dev_id, vchan);\n+\tstruct rte_mbuf *src, *dst;\n+\tint i, j, iter;\n+\tint cap, ret;\n+\tbool dma_err;\n+\n+\tsrc = rte_pktmbuf_alloc(pool);\n+\tdst = rte_pktmbuf_alloc(pool);\n+\n+\t/* to test capacity, we enqueue elements and check capacity is reduced\n+\t * by one each time - rebaselining the expected value after each burst\n+\t * as the capacity is only for a burst. We enqueue multiple bursts to\n+\t * fill up half the ring, before emptying it again. We do this twice to\n+\t * ensure that we get to test scenarios where we get ring wrap-around\n+\t */\n+\tfor (iter = 0; iter < 2; iter++) {\n+\t\tfor (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) {\n+\t\t\tcap = rte_dmadev_burst_capacity(dev_id, vchan);\n+\n+\t\t\tfor (j = 0; j < CAP_TEST_BURST_SIZE; j++) {\n+\t\t\t\tret = rte_dmadev_copy(dev_id, vchan, rte_pktmbuf_iova(src),\n+\t\t\t\t\t\trte_pktmbuf_iova(dst), COPY_LEN, 0);\n+\t\t\t\tif (ret < 0)\n+\t\t\t\t\tERR_RETURN(\"Error with rte_dmadev_copy\\n\");\n+\n+\t\t\t\tif (rte_dmadev_burst_capacity(dev_id, vchan) != cap - (j + 1))\n+\t\t\t\t\tERR_RETURN(\"Error, ring capacity did not change as expected\\n\");\n+\t\t\t}\n+\t\t\tif (rte_dmadev_submit(dev_id, vchan) < 0)\n+\t\t\t\tERR_RETURN(\"Error, failed to submit burst\\n\");\n+\n+\t\t\tif (cap < rte_dmadev_burst_capacity(dev_id, vchan))\n+\t\t\t\tERR_RETURN(\"Error, avail ring capacity has gone up, not down\\n\");\n+\t\t}\n+\t\tawait_hw(dev_id, vchan);\n+\n+\t\tfor (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) {\n+\t\t\tret = rte_dmadev_completed(dev_id, vchan,\n+\t\t\t\t\tCAP_TEST_BURST_SIZE, NULL, &dma_err);\n+\t\t\tif (ret != CAP_TEST_BURST_SIZE || dma_err) {\n+\t\t\t\tenum rte_dma_status_code status;\n+\n+\t\t\t\trte_dmadev_completed_status(dev_id, vchan, 1, NULL, &status);\n+\t\t\t\tERR_RETURN(\"Error with rte_dmadev_completed, %u [expected: %u], dma_err = %d, i = %u, iter = %u, status = %u\\n\",\n+\t\t\t\t\t\tret, CAP_TEST_BURST_SIZE, dma_err, i, iter, status);\n+\t\t\t}\n+\t\t}\n+\t\tcap = rte_dmadev_burst_capacity(dev_id, vchan);\n+\t\tif (cap != ring_space)\n+\t\t\tERR_RETURN(\"Error, ring capacity has not reset to original value, got %u, expected %u\\n\",\n+\t\t\t\t\tcap, ring_space);\n+\t}\n+\n+\trte_pktmbuf_free(src);\n+\trte_pktmbuf_free(dst);\n+\n+\treturn 0;\n+}\n+\n static int\n test_dmadev_instance(uint16_t dev_id)\n {\n@@ -741,6 +804,11 @@ test_dmadev_instance(uint16_t dev_id)\n \telse if (runtest(\"fill\", test_enqueue_fill, 1, dev_id, vchan, CHECK_ERRS) < 0)\n \t\tgoto err;\n \n+\tif (rte_dmadev_burst_capacity(dev_id, vchan) == -ENOTSUP)\n+\t\tprintf(\"DMA Dev %u: Burst capacity API not supported, skipping tests\\n\", dev_id);\n+\telse if (runtest(\"burst capacity\", test_burst_capacity, 1, dev_id, vchan, CHECK_ERRS) < 0)\n+\t\tgoto err;\n+\n \trte_mempool_free(pool);\n \trte_dmadev_stop(dev_id);\n \trte_dmadev_stats_reset(dev_id, vchan);\n", "prefixes": [ "v3", "8/8" ] }