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GET /api/patches/97761/?format=api
{ "id": 97761, "url": "http://patches.dpdk.org/api/patches/97761/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210902070034.1086-1-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210902070034.1086-1-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210902070034.1086-1-pbhagavatula@marvell.com", "date": "2021-09-02T07:00:32", "name": "[1/2] common/cnxk: add SSO XAQ pool create and free", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "80232f0546c24581cbdb48f188f5127efb40493b", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210902070034.1086-1-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 18614, "url": "http://patches.dpdk.org/api/series/18614/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18614", "date": "2021-09-02T07:00:33", "name": "[1/2] common/cnxk: add SSO XAQ pool create and free", "version": 1, "mbox": "http://patches.dpdk.org/series/18614/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/97761/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/97761/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7FC0FA0547;\n\tThu, 2 Sep 2021 09:00:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A3D3340DDE;\n\tThu, 2 Sep 2021 09:00:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 76F6E40142\n for <dev@dpdk.org>; Thu, 2 Sep 2021 09:00:50 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 1823lgrH027710;\n Thu, 2 Sep 2021 00:00:47 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3atdwqae6g-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 02 Sep 2021 00:00:46 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 2 Sep 2021 00:00:44 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 2 Sep 2021 00:00:44 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 525D23F7051;\n Thu, 2 Sep 2021 00:00:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=edI1ULTNqzsAEtAG8EyY0TSiuTDi/E3MRXq4mfaj7N4=;\n b=Nt2HtPjzTRwlUILNGQPdvcQJQnNeamisUuv7XAQjyUK/2BnlqqsNt33KzQcqDEDXhZTB\n 5oOCPqhxeUCWa9gUWBanS4BrujjMkTFH2t1j+Luh9/AnOrGuMoTAII88VWHjZe2KdF2S\n 5jqDYCWAy6KbqplUYGUEAXIEfXG9EZeZSzzLKckRR5Ok5kPHRAYtk1wZHq2foEERXzIP\n UH4hh9q5MtODx5z8JqfmSaCqHUTjGwukj2EKnH/Dl2UPb2Moo55tev8gQGoV1roMx6w3\n pEQcX8kieBRSftlhJUEs7wuDjqP1JhkGIUy0J97Te9cGDOiip+s1R0k2nLGf21KJrC7x 8w==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Thu, 2 Sep 2021 12:30:32 +0530", "Message-ID": "<20210902070034.1086-1-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "LZTp_Ov-dCvo5VGNmQfa3IEqovbrNCl3", "X-Proofpoint-GUID": "LZTp_Ov-dCvo5VGNmQfa3IEqovbrNCl3", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-02_02,2021-09-01_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 1/2] common/cnxk: add SSO XAQ pool create and free", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd common API to create and free SSO XAQ pool.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n Depends-on: series-18612 (\"net/cnxk: support for inline ipsec\")\n\n drivers/common/cnxk/roc_sso.c | 122 +++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_sso.h | 14 ++++\n drivers/common/cnxk/roc_sso_priv.h | 5 ++\n drivers/common/cnxk/version.map | 2 +\n 4 files changed, 143 insertions(+)\n\n--\n2.32.0", "diff": "diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex bdf973fc2a..31cae30c88 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -5,6 +5,8 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n\n+#define SSO_XAQ_CACHE_CNT (0x7)\n+\n /* Private functions. */\n int\n sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf,\n@@ -387,6 +389,126 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n \treturn mbox_process(dev->mbox);\n }\n\n+int\n+sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,\n+\t\t\tuint32_t nb_xae, uint32_t xae_waes,\n+\t\t\tuint32_t xaq_buf_size, uint16_t nb_hwgrp)\n+{\n+\tstruct npa_pool_s pool;\n+\tstruct npa_aura_s aura;\n+\tplt_iova_t iova;\n+\tuint32_t i;\n+\tint rc;\n+\n+\tif (xaq->mem != NULL) {\n+\t\trc = sso_hwgrp_release_xaq(dev, nb_hwgrp);\n+\t\tif (rc < 0) {\n+\t\t\tplt_err(\"Failed to release XAQ %d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t\troc_npa_pool_destroy(xaq->aura_handle);\n+\t\tplt_free(xaq->fc);\n+\t\tplt_free(xaq->mem);\n+\t\tmemset(xaq, 0, sizeof(struct roc_sso_xaq_data));\n+\t}\n+\n+\txaq->fc = plt_zmalloc(ROC_ALIGN, ROC_ALIGN);\n+\tif (xaq->fc == NULL) {\n+\t\tplt_err(\"Failed to allocate XAQ FC\");\n+\t\trc = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Taken from HRM 14.3.3(4) */\n+\tnb_xae += (xae_waes * SSO_XAQ_CACHE_CNT * nb_hwgrp);\n+\txaq->nb_xae = nb_xae;\n+\txaq->nb_xaq = xaq->nb_xae / xae_waes;\n+\n+\txaq->mem = plt_zmalloc(xaq_buf_size * xaq->nb_xaq, xaq_buf_size);\n+\tif (xaq->mem == NULL) {\n+\t\tplt_err(\"Failed to allocate XAQ mem\");\n+\t\trc = -ENOMEM;\n+\t\tgoto free_fc;\n+\t}\n+\n+\tmemset(&pool, 0, sizeof(struct npa_pool_s));\n+\tpool.nat_align = 1;\n+\n+\tmemset(&aura, 0, sizeof(aura));\n+\taura.fc_ena = 1;\n+\taura.fc_addr = (uint64_t)xaq->fc;\n+\taura.fc_hyst_bits = 0; /* Store count on all updates */\n+\trc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq,\n+\t\t\t\t &aura, &pool);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to create XAQ pool\");\n+\t\tgoto npa_fail;\n+\t}\n+\n+\tiova = (uint64_t)xaq->mem;\n+\tfor (i = 0; i < xaq->nb_xaq; i++) {\n+\t\troc_npa_aura_op_free(xaq->aura_handle, 0, iova);\n+\t\tiova += xaq_buf_size;\n+\t}\n+\troc_npa_aura_op_range_set(xaq->aura_handle, (uint64_t)xaq->mem, iova);\n+\n+\t/* When SW does addwork (enqueue) check if there is space in XAQ by\n+\t * comparing fc_addr above against the xaq_lmt calculated below.\n+\t * There should be a minimum headroom of one XAQ per HWGRP for SSO\n+\t * to request XAQ to cache them even before enqueue is called.\n+\t */\n+\txaq->xaq_lmt = xaq->nb_xaq - nb_hwgrp;\n+\treturn 0;\n+npa_fail:\n+\tplt_free(xaq->mem);\n+free_fc:\n+\tplt_free(xaq->fc);\n+fail:\n+\tmemset(xaq, 0, sizeof(struct roc_sso_xaq_data));\n+\treturn rc;\n+}\n+\n+int\n+roc_sso_hwgrp_init_xaq_aura(struct roc_sso *roc_sso, uint32_t nb_xae)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\n+\treturn sso_hwgrp_init_xaq_aura(dev, &roc_sso->xaq, nb_xae,\n+\t\t\t\t roc_sso->xae_waes, roc_sso->xaq_buf_size,\n+\t\t\t\t roc_sso->nb_hwgrp);\n+}\n+\n+int\n+sso_hwgrp_free_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,\n+\t\t\tuint16_t nb_hwgrp)\n+{\n+\tint rc;\n+\n+\tif (xaq->mem != NULL) {\n+\t\tif (nb_hwgrp) {\n+\t\t\trc = sso_hwgrp_release_xaq(dev, nb_hwgrp);\n+\t\t\tif (rc < 0) {\n+\t\t\t\tplt_err(\"Failed to release XAQ %d\", rc);\n+\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t}\n+\t\troc_npa_pool_destroy(xaq->aura_handle);\n+\t\tplt_free(xaq->fc);\n+\t\tplt_free(xaq->mem);\n+\t}\n+\tmemset(xaq, 0, sizeof(struct roc_sso_xaq_data));\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_sso_hwgrp_free_xaq_aura(struct roc_sso *roc_sso, uint16_t nb_hwgrp)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\n+\treturn sso_hwgrp_free_xaq_aura(dev, &roc_sso->xaq, nb_hwgrp);\n+}\n+\n int\n sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps)\n {\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex b28f6089cc..27d49c6c68 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -27,6 +27,15 @@ struct roc_sso_hwgrp_stats {\n \tuint64_t page_cnt;\n };\n\n+struct roc_sso_xaq_data {\n+\tuint32_t nb_xaq;\n+\tuint32_t nb_xae;\n+\tuint32_t xaq_lmt;\n+\tuint64_t aura_handle;\n+\tvoid *fc;\n+\tvoid *mem;\n+};\n+\n struct roc_sso {\n \tstruct plt_pci_device *pci_dev;\n \t/* Public data. */\n@@ -35,6 +44,7 @@ struct roc_sso {\n \tuint16_t nb_hwgrp;\n \tuint8_t nb_hws;\n \tuintptr_t lmt_base;\n+\tstruct roc_sso_xaq_data xaq;\n \t/* HW Const. */\n \tuint32_t xae_waes;\n \tuint32_t xaq_buf_size;\n@@ -95,6 +105,10 @@ int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso,\n uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws);\n uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso,\n \t\t\t\t\t uint16_t hwgrp);\n+int __roc_api roc_sso_hwgrp_init_xaq_aura(struct roc_sso *roc_sso,\n+\t\t\t\t\t uint32_t nb_xae);\n+int __roc_api roc_sso_hwgrp_free_xaq_aura(struct roc_sso *roc_sso,\n+\t\t\t\t\t uint16_t nb_hwgrp);\n\n /* Debug */\n void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws,\ndiff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h\nindex 8dffa3fbf4..2e1b025d1c 100644\n--- a/drivers/common/cnxk/roc_sso_priv.h\n+++ b/drivers/common/cnxk/roc_sso_priv.h\n@@ -47,6 +47,11 @@ void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n \t\t\t uint16_t hwgrp[], uint16_t n, uint16_t enable);\n int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps);\n int sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps);\n+int sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,\n+\t\t\t uint32_t nb_xae, uint32_t xae_waes,\n+\t\t\t uint32_t xaq_buf_size, uint16_t nb_hwgrp);\n+int sso_hwgrp_free_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,\n+\t\t\t uint16_t nb_hwgrp);\n\n /* SSO IRQ */\n int sso_register_irqs_priv(struct roc_sso *roc_sso,\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 9fcc677e34..153c45b910 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -280,7 +280,9 @@ INTERNAL {\n \troc_sso_dump;\n \troc_sso_hwgrp_alloc_xaq;\n \troc_sso_hwgrp_base_get;\n+\troc_sso_hwgrp_free_xaq_aura;\n \troc_sso_hwgrp_hws_link_status;\n+\troc_sso_hwgrp_init_xaq_aura;\n \troc_sso_hwgrp_qos_config;\n \troc_sso_hwgrp_release_xaq;\n \troc_sso_hwgrp_set_priority;\n", "prefixes": [ "1/2" ] }