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GET /api/patches/97745/?format=api
{ "id": 97745, "url": "http://patches.dpdk.org/api/patches/97745/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-20-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210902021505.17607-20-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210902021505.17607-20-ndabilpuram@marvell.com", "date": "2021-09-02T02:14:57", "name": "[19/27] net/cnxk: add cn10k Rx support for security offload", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "145cd22877ec3317db13a26000e699c45eb6ed07", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-20-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 18612, "url": "http://patches.dpdk.org/api/series/18612/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18612", "date": "2021-09-02T02:14:38", "name": "net/cnxk: support for inline ipsec", "version": 1, "mbox": "http://patches.dpdk.org/series/18612/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/97745/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/97745/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D77A2A0C4C;\n\tThu, 2 Sep 2021 04:18:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 90C4E41104;\n\tThu, 2 Sep 2021 04:17:46 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 95935410FE\n for <dev@dpdk.org>; Thu, 2 Sep 2021 04:17:44 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181HQ203011573\n for <dev@dpdk.org>; Wed, 1 Sep 2021 19:17:44 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9hu3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Sep 2021 19:17:43 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 1 Sep 2021 19:17:41 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 1 Sep 2021 19:17:41 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id B95753F7040;\n Wed, 1 Sep 2021 19:17:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=UuPtBQ4Jzvd3UK+/5CxFM8Ry3pLxW/oddD14A88c+Hs=;\n b=UNARFcr7N1RpEPKe6ch02TR6MLBCADiWINZWdS47qntUQIuLVZCJ16l/Q3MFPH2QEyeF\n CI7Xib/DmCUmieeg6cfVh9ocgsLGpbul2DeMkIdokSjgue3md1XjLGCRrIcAMHVK9N6w\n HsBf/ffD1hJX7VYPUumuDxKnAdVH8L4SUJ74gVTeQwAFo4jW2pw6BKqhbR/9ZlKOOohJ\n AaK6mtm+uCxSB6t59tpUkWSRPIL3U+OHNUzTRfk/DYaIz7mJjmnca509v3Smfu33MRxd\n jgYVlRjwkQs8YJtUG+Dm5FzGG3cqhC/mJGk1tC33vTG3WKAbL5agpqFSS9L9cMWRL1l4 1A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Pavan Nikhilesh <pbhagavatula@marvell.com>, Shijith Thotton\n <sthotton@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <schalla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 2 Sep 2021 07:44:57 +0530", "Message-ID": "<20210902021505.17607-20-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "iKLyED_EcZb5NX-PZklNP5D7S6EyHlic", "X-Proofpoint-GUID": "iKLyED_EcZb5NX-PZklNP5D7S6EyHlic", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 19/27] net/cnxk: add cn10k Rx support for\n security offload", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support to receive CPT processed packets on Rx via\nsecond pass.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 80 ++--\n drivers/event/cnxk/cn10k_worker.h | 73 +++-\n drivers/event/cnxk/cn10k_worker_deq.c | 2 +-\n drivers/event/cnxk/cn10k_worker_deq_burst.c | 2 +-\n drivers/event/cnxk/cn10k_worker_deq_ca.c | 2 +-\n drivers/event/cnxk/cn10k_worker_deq_tmo.c | 2 +-\n drivers/net/cnxk/cn10k_ethdev.h | 4 +\n drivers/net/cnxk/cn10k_rx.c | 31 +-\n drivers/net/cnxk/cn10k_rx.h | 648 +++++++++++++++++++++++-----\n drivers/net/cnxk/cn10k_rx_mseg.c | 2 +-\n drivers/net/cnxk/cn10k_rx_vec.c | 4 +-\n drivers/net/cnxk/cn10k_rx_vec_mseg.c | 4 +-\n drivers/net/cnxk/cn10k_tx.h | 3 -\n 13 files changed, 688 insertions(+), 169 deletions(-)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex bfb6f1a..2f2e7f8 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -7,7 +7,8 @@\n #include \"cnxk_worker.h\"\n \n #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \\\n-\tdeq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \\\n+\tdeq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)] \\\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \\\n \t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \\\n \t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \\\n \t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \\\n@@ -287,88 +288,91 @@ static void\n cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n-\tconst event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,\n+\tconst event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,\n+\tconst event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,\n+\tconst event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name,\n+\tconst event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_burst_t sso_hws_deq_ca_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name,\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_deq_ca_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,\n+\tconst event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_deq_seg_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,\n+\tconst event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n \tconst event_dequeue_burst_t\n-\t\tsso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,\n+\t\tsso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,\n \t\t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t\t};\n \n-\tconst event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name,\n+\tconst event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name,\n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n \tconst event_dequeue_burst_t\n-\t\tsso_hws_deq_ca_seg_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name,\n+\t\tsso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name,\n \t\t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n@@ -384,7 +388,7 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \n \tconst event_tx_adapter_enqueue\n \t\tsso_hws_tx_adptr_enq_seg[2][2][2][2][2][2] = {\n-#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \\\n+#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \\\n \t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,\n \t\t\tNIX_TX_FASTPATH_MODES\n #undef T\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex e5ed043..b79bd90 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -106,12 +106,17 @@ cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n \n static __rte_always_inline void\n cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n-\t\t void *lookup_mem, void *tstamp)\n+\t\t void *lookup_mem, void *tstamp, uintptr_t lbase)\n {\n \tuint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |\n \t\t\t (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);\n \tstruct rte_event_vector *vec;\n+\tuint64_t aura_handle, laddr;\n \tuint16_t nb_mbufs, non_vec;\n+\tuint16_t lmt_id, d_off;\n+\tstruct rte_mbuf *mbuf;\n+\tuint8_t loff = 0;\n+\tuint64_t sa_base;\n \tuint64_t **wqe;\n \n \tmbuf_init |= ((uint64_t)port_id) << 48;\n@@ -121,17 +126,41 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n \tnb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);\n \tnb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs,\n \t\t\t\t\t flags | NIX_RX_VWQE_F, lookup_mem,\n-\t\t\t\t\t tstamp);\n+\t\t\t\t\t tstamp, lbase);\n \twqe += nb_mbufs;\n \tnon_vec = vec->nb_elem - nb_mbufs;\n \n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {\n+\t\tmbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -\n+\t\t\t\t\t sizeof(struct rte_mbuf));\n+\t\t/* Pick first mbuf's aura handle assuming all\n+\t\t * mbufs are from a vec and are from same RQ.\n+\t\t */\n+\t\taura_handle = mbuf->pool->pool_id;\n+\t\tROC_LMT_BASE_ID_GET(lbase, lmt_id);\n+\t\tladdr = lbase;\n+\t\tladdr += 8;\n+\t\td_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);\n+\t\td_off += (mbuf_init & 0xFFFF);\n+\t\tsa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);\n+\t\tsa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);\n+\t}\n+\n \twhile (non_vec) {\n \t\tstruct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];\n-\t\tstruct rte_mbuf *mbuf;\n \t\tuint64_t tstamp_ptr;\n \n \t\tmbuf = (struct rte_mbuf *)((char *)cqe -\n \t\t\t\t\t sizeof(struct rte_mbuf));\n+\n+\t\t/* Translate meta to mbuf */\n+\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\tconst uint64_t cq_w1 = *((const uint64_t *)cqe + 1);\n+\n+\t\t\tmbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr,\n+\t\t\t\t\t\t &loff, mbuf, d_off);\n+\t\t}\n+\n \t\tcn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,\n \t\t\t\t mbuf_init, flags);\n \t\t/* Extracting tstamp, if PTP enabled*/\n@@ -145,6 +174,12 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n \t\tnon_vec--;\n \t\twqe++;\n \t}\n+\n+\t/* Free remaining meta buffers if any */\n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {\n+\t\tnix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);\n+\t\tplt_io_wmb();\n+\t}\n }\n \n static __rte_always_inline uint16_t\n@@ -188,6 +223,34 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\t\t RTE_EVENT_TYPE_ETHDEV) {\n \t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n \n+\t\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\t\tstruct rte_mbuf *m;\n+\t\t\t\tuintptr_t sa_base;\n+\t\t\t\tuint64_t iova = 0;\n+\t\t\t\tuint8_t loff = 0;\n+\t\t\t\tuint16_t d_off;\n+\t\t\t\tuint64_t cq_w1;\n+\n+\t\t\t\tm = (struct rte_mbuf *)mbuf;\n+\t\t\t\td_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;\n+\t\t\t\td_off += RTE_PKTMBUF_HEADROOM;\n+\n+\t\t\t\tcq_w1 = *(uint64_t *)(gw.u64[1] + 8);\n+\n+\t\t\t\tsa_base = cnxk_nix_sa_base_get(port,\n+\t\t\t\t\t\t\t lookup_mem);\n+\t\t\t\tsa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);\n+\n+\t\t\t\tmbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(cq_w1,\n+\t\t\t\t\t\tsa_base, (uintptr_t)&iova,\n+\t\t\t\t\t\t&loff, (struct rte_mbuf *)mbuf,\n+\t\t\t\t\t\td_off);\n+\t\t\t\tif (loff)\n+\t\t\t\t\troc_npa_aura_op_free(m->pool->pool_id,\n+\t\t\t\t\t\t\t 0, iova);\n+\n+\t\t\t}\n+\n \t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n \t\t\tcn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n \t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n@@ -212,7 +275,7 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\t\t\t ((uint64_t)port << 32);\n \t\t\t*(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;\n \t\t\tcn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,\n-\t\t\t\t\t ws->tstamp);\n+\t\t\t\t\t ws->tstamp, ws->lmt_base);\n \t\t}\n \t}\n \n@@ -290,7 +353,7 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,\n uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],\n \t\t\t\t\tuint16_t nb_events);\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \\\ndiff --git a/drivers/event/cnxk/cn10k_worker_deq.c b/drivers/event/cnxk/cn10k_worker_deq.c\nindex 36ec454..6083f69 100644\n--- a/drivers/event/cnxk/cn10k_worker_deq.c\n+++ b/drivers/event/cnxk/cn10k_worker_deq.c\n@@ -6,7 +6,7 @@\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_worker.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n \t{ \\\ndiff --git a/drivers/event/cnxk/cn10k_worker_deq_burst.c b/drivers/event/cnxk/cn10k_worker_deq_burst.c\nindex 29ecc55..8539d5d 100644\n--- a/drivers/event/cnxk/cn10k_worker_deq_burst.c\n+++ b/drivers/event/cnxk/cn10k_worker_deq_burst.c\n@@ -6,7 +6,7 @@\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_worker.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \\\n \t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n \t\tuint64_t timeout_ticks) \\\ndiff --git a/drivers/event/cnxk/cn10k_worker_deq_ca.c b/drivers/event/cnxk/cn10k_worker_deq_ca.c\nindex 508d30f..0d10fc8 100644\n--- a/drivers/event/cnxk/cn10k_worker_deq_ca.c\n+++ b/drivers/event/cnxk/cn10k_worker_deq_ca.c\n@@ -6,7 +6,7 @@\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_worker.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_ca_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n \t{ \\\ndiff --git a/drivers/event/cnxk/cn10k_worker_deq_tmo.c b/drivers/event/cnxk/cn10k_worker_deq_tmo.c\nindex c8524a2..537ae37 100644\n--- a/drivers/event/cnxk/cn10k_worker_deq_tmo.c\n+++ b/drivers/event/cnxk/cn10k_worker_deq_tmo.c\n@@ -6,7 +6,7 @@\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_worker.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n \t{ \\\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nindex a888364..200cd93 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.h\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -81,4 +81,8 @@ void cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev);\n /* Security context setup */\n void cn10k_eth_sec_ops_override(void);\n \n+#define LMT_OFF(lmt_addr, lmt_num, offset) \\\n+\t(void *)((uintptr_t)(lmt_addr) + \\\n+\t\t ((uint64_t)(lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset))\n+\n #endif /* __CN10K_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cn10k_rx.c b/drivers/net/cnxk/cn10k_rx.c\nindex 69e767a..d6af54b 100644\n--- a/drivers/net/cnxk/cn10k_rx.c\n+++ b/drivers/net/cnxk/cn10k_rx.c\n@@ -5,7 +5,7 @@\n #include \"cn10k_ethdev.h\"\n #include \"cn10k_rx.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n \tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name(\t \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n \t{ \\\n@@ -17,12 +17,13 @@ NIX_RX_FASTPATH_MODES\n \n static inline void\n pick_rx_func(struct rte_eth_dev *eth_dev,\n-\t const eth_rx_burst_t rx_burst[2][2][2][2][2][2])\n+\t const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2])\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n \n \t/* [VLAN] [TSP] [MARK] [CKSUM] [PTYPE] [RSS] */\n \teth_dev->rx_pkt_burst = rx_burst\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F)]\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n@@ -38,33 +39,33 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n \n-\tconst eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_##name,\n+\tconst eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_##name,\n \n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_mseg_##name,\n+\tconst eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_mseg_##name,\n \n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name,\n+\tconst eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name,\n \n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tconst eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2] = {\n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n-\t[f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name,\n+\tconst eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2][2] = {\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name,\n \n \t\tNIX_RX_FASTPATH_MODES\n #undef R\n@@ -73,7 +74,7 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n \t/* Copy multi seg version with no offload for tear down sequence */\n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n \t\tdev->rx_pkt_burst_no_offload =\n-\t\t\tnix_eth_rx_burst_mseg[0][0][0][0][0][0];\n+\t\t\tnix_eth_rx_burst_mseg[0][0][0][0][0][0][0];\n \n \tif (dev->scalar_ena) {\n \t\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex d27a231..fcc451a 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -65,6 +65,130 @@ nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)\n \treturn (struct rte_mbuf *)(buff - data_off);\n }\n \n+static __rte_always_inline void\n+nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff,\n+\t\t uintptr_t aura_handle)\n+{\n+\tuint64_t pa;\n+\n+\t/* laddr is pointing to first pointer */\n+\tladdr -= 8;\n+\n+\t/* Trigger free either on lmtline full or different aura handle */\n+\tpa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;\n+\n+\t/* Update aura handle */\n+\t*(uint64_t *)laddr = (((uint64_t)(loff & 0x1) << 32) |\n+\t\t\t roc_npa_aura_handle_to_aura(aura_handle));\n+\n+\tpa |= ((loff >> 1) << 4);\n+\troc_lmt_submit_steorl(lmt_id, pa);\n+}\n+\n+static __rte_always_inline struct rte_mbuf *\n+nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr,\n+\t\t\tuint8_t *loff, struct rte_mbuf *mbuf, uint16_t data_off)\n+{\n+\tconst void *__p = (void *)((uintptr_t)mbuf + (uint16_t)data_off);\n+\tconst struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)__p;\n+\tstruct cn10k_inb_priv_data *inb_priv;\n+\tstruct rte_mbuf *inner;\n+\tuint32_t sa_idx;\n+\tvoid *inb_sa;\n+\tuint64_t w0;\n+\n+\tif (cq_w1 & BIT(11)) {\n+\t\tinner = (struct rte_mbuf *)(rte_be_to_cpu_64(hdr->wqe_ptr) -\n+\t\t\t\t\t sizeof(struct rte_mbuf));\n+\n+\t\t/* Get SPI from CPT_PARSE_S's cookie(already swapped) */\n+\t\tw0 = hdr->w0.u64;\n+\t\tsa_idx = w0 >> 32;\n+\n+\t\tinb_sa = roc_nix_inl_ot_ipsec_inb_sa(sa_base, sa_idx);\n+\t\tinb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa);\n+\n+\t\t/* Update dynamic field with userdata */\n+\t\t*rte_security_dynfield(inner) = (uint64_t)inb_priv->userdata;\n+\n+\t\t/* Update l2 hdr length first */\n+\t\tinner->pkt_len = (hdr->w2.il3_off -\n+\t\t\t\t sizeof(struct cpt_parse_hdr_s) - (w0 & 0x7));\n+\n+\t\t/* Store meta in lmtline to free\n+\t\t * Assume all meta's from same aura.\n+\t\t */\n+\t\t*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;\n+\t\t*loff = *loff + 1;\n+\n+\t\treturn inner;\n+\t}\n+\treturn mbuf;\n+}\n+\n+#if defined(RTE_ARCH_ARM64)\n+\n+static __rte_always_inline struct rte_mbuf *\n+nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr,\n+\t\t uint8_t *loff, struct rte_mbuf *mbuf, uint16_t data_off,\n+\t\t uint8x16_t *rx_desc_field1, uint64_t *ol_flags)\n+{\n+\tconst void *__p = (void *)((uintptr_t)mbuf + (uint16_t)data_off);\n+\tconst struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)__p;\n+\tstruct cn10k_inb_priv_data *inb_priv;\n+\tstruct rte_mbuf *inner;\n+\tuint64_t *sg, res_w1;\n+\tuint32_t sa_idx;\n+\tvoid *inb_sa;\n+\tuint16_t len;\n+\tuint64_t w0;\n+\n+\tif (cq_w1 & BIT(11)) {\n+\t\tinner = (struct rte_mbuf *)(rte_be_to_cpu_64(hdr->wqe_ptr) -\n+\t\t\t\t\t sizeof(struct rte_mbuf));\n+\t\t/* Get SPI from CPT_PARSE_S's cookie(already swapped) */\n+\t\tw0 = hdr->w0.u64;\n+\t\tsa_idx = w0 >> 32;\n+\n+\t\tinb_sa = roc_nix_inl_ot_ipsec_inb_sa(sa_base, sa_idx);\n+\t\tinb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa);\n+\n+\t\t/* Update dynamic field with userdata */\n+\t\t*rte_security_dynfield(inner) = (uint64_t)inb_priv->userdata;\n+\n+\t\t/* CPT result(struct cpt_cn10k_res_s) is at\n+\t\t * after first IOVA in meta\n+\t\t */\n+\t\tsg = (uint64_t *)(inner + 1);\n+\t\tres_w1 = sg[10];\n+\n+\t\t/* Clear checksum flags and update security flag */\n+\t\t*ol_flags &= ~(PKT_RX_L4_CKSUM_MASK | PKT_RX_IP_CKSUM_MASK);\n+\t\t*ol_flags |= (((res_w1 & 0xFF) == CPT_COMP_WARN) ?\n+\t\t\t PKT_RX_SEC_OFFLOAD :\n+\t\t\t (PKT_RX_SEC_OFFLOAD | PKT_RX_SEC_OFFLOAD_FAILED));\n+\t\t/* Calculate inner packet length */\n+\t\tlen = ((res_w1 >> 16) & 0xFFFF) + hdr->w2.il3_off -\n+\t\t\tsizeof(struct cpt_parse_hdr_s) - (w0 & 0x7);\n+\t\t/* Update pkt_len and data_len */\n+\t\t*rx_desc_field1 = vsetq_lane_u16(len, *rx_desc_field1, 2);\n+\t\t*rx_desc_field1 = vsetq_lane_u16(len, *rx_desc_field1, 4);\n+\n+\t\t/* Store meta in lmtline to free\n+\t\t * Assume all meta's from same aura.\n+\t\t */\n+\t\t*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;\n+\t\t*loff = *loff + 1;\n+\n+\t\t/* Return inner mbuf */\n+\t\treturn inner;\n+\t}\n+\n+\t/* Return same mbuf as it is not a decrypted pkt */\n+\treturn mbuf;\n+}\n+#endif\n+\n static __rte_always_inline uint32_t\n nix_ptype_get(const void *const lookup_mem, const uint64_t in)\n {\n@@ -177,8 +301,8 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n {\n \tconst union nix_rx_parse_u *rx =\n \t\t(const union nix_rx_parse_u *)((const uint64_t *)cq + 1);\n-\tconst uint16_t len = rx->pkt_lenm1 + 1;\n \tconst uint64_t w1 = *(const uint64_t *)rx;\n+\tuint16_t len = rx->pkt_lenm1 + 1;\n \tuint64_t ol_flags = 0;\n \n \t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n@@ -194,8 +318,30 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t\tol_flags |= PKT_RX_RSS_HASH;\n \t}\n \n-\tif (flag & NIX_RX_OFFLOAD_CHECKSUM_F)\n-\t\tol_flags |= nix_rx_olflags_get(lookup_mem, w1);\n+\t/* Process Security packets */\n+\tif (flag & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\tif (w1 & BIT(11)) {\n+\t\t\t/* CPT result(struct cpt_cn10k_res_s) is at\n+\t\t\t * after first IOVA in meta\n+\t\t\t */\n+\t\t\tconst uint64_t *sg = (const uint64_t *)(mbuf + 1);\n+\t\t\tconst uint64_t res_w1 = sg[10];\n+\t\t\tconst uint16_t uc_cc = res_w1 & 0xFF;\n+\n+\t\t\t/* Rlen */\n+\t\t\tlen = ((res_w1 >> 16) & 0xFFFF) + mbuf->pkt_len;\n+\t\t\tol_flags |= ((uc_cc == CPT_COMP_WARN) ?\n+\t\t\t\t\t\t PKT_RX_SEC_OFFLOAD :\n+\t\t\t\t\t\t (PKT_RX_SEC_OFFLOAD |\n+\t\t\t\t\t PKT_RX_SEC_OFFLOAD_FAILED));\n+\t\t} else {\n+\t\t\tif (flag & NIX_RX_OFFLOAD_CHECKSUM_F)\n+\t\t\t\tol_flags |= nix_rx_olflags_get(lookup_mem, w1);\n+\t\t}\n+\t} else {\n+\t\tif (flag & NIX_RX_OFFLOAD_CHECKSUM_F)\n+\t\t\tol_flags |= nix_rx_olflags_get(lookup_mem, w1);\n+\t}\n \n \tif (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) {\n \t\tif (rx->vtag0_gone) {\n@@ -263,13 +409,28 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \tconst uintptr_t desc = rxq->desc;\n \tconst uint64_t wdata = rxq->wdata;\n \tconst uint32_t qmask = rxq->qmask;\n+\tuint64_t lbase = rxq->lmt_base;\n \tuint16_t packets = 0, nb_pkts;\n+\tuint8_t loff = 0, lnum = 0;\n \tuint32_t head = rxq->head;\n \tstruct nix_cqe_hdr_s *cq;\n \tstruct rte_mbuf *mbuf;\n+\tuint64_t aura_handle;\n+\tuint64_t sa_base;\n+\tuint16_t lmt_id;\n+\tuint64_t laddr;\n \n \tnb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n \n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\taura_handle = rxq->aura_handle;\n+\t\tsa_base = rxq->sa_base;\n+\t\tsa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);\n+\t\tROC_LMT_BASE_ID_GET(lbase, lmt_id);\n+\t\tladdr = lbase;\n+\t\tladdr += 8;\n+\t}\n+\n \twhile (packets < nb_pkts) {\n \t\t/* Prefetch N desc ahead */\n \t\trte_prefetch_non_temporal(\n@@ -278,6 +439,14 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \n \t\tmbuf = nix_get_mbuf_from_cqe(cq, data_off);\n \n+\t\t/* Translate meta to mbuf */\n+\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\tconst uint64_t cq_w1 = *((const uint64_t *)cq + 1);\n+\n+\t\t\tmbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr,\n+\t\t\t\t\t\t &loff, mbuf, data_off);\n+\t\t}\n+\n \t\tcn10k_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init,\n \t\t\t\t flags);\n \t\tcnxk_nix_mbuf_to_tstamp(mbuf, rxq->tstamp,\n@@ -289,6 +458,20 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \t\troc_prefetch_store_keep(mbuf);\n \t\thead++;\n \t\thead &= qmask;\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\t/* Flush when we don't have space for 4 meta */\n+\t\t\tif ((15 - loff) < 1) {\n+\t\t\t\tnix_sec_flush_meta(laddr, lmt_id + lnum, loff,\n+\t\t\t\t\t\t aura_handle);\n+\t\t\t\tlnum++;\n+\t\t\t\tlnum &= BIT_ULL(ROC_LMT_LINES_PER_CORE_LOG2) -\n+\t\t\t\t\t1;\n+\t\t\t\t/* First pointer starts at 8B offset */\n+\t\t\t\tladdr = (uintptr_t)LMT_OFF(lbase, lnum, 8);\n+\t\t\t\tloff = 0;\n+\t\t\t}\n+\t\t}\n \t}\n \n \trxq->head = head;\n@@ -297,6 +480,12 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \t/* Free all the CQs that we've processed */\n \tplt_write64((wdata | nb_pkts), rxq->cq_door);\n \n+\t/* Free remaining meta buffers if any */\n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {\n+\t\tnix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);\n+\t\tplt_io_wmb();\n+\t}\n+\n \treturn nb_pkts;\n }\n \n@@ -327,7 +516,8 @@ nix_qinq_update(const uint64_t w2, uint64_t ol_flags, struct rte_mbuf *mbuf)\n static __rte_always_inline uint16_t\n cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t const uint16_t flags, void *lookup_mem,\n-\t\t\t struct cnxk_timesync_info *tstamp)\n+\t\t\t struct cnxk_timesync_info *tstamp,\n+\t\t\t uintptr_t lmt_base)\n {\n \tstruct cn10k_eth_rxq *rxq = args;\n \tconst uint64_t mbuf_initializer = (flags & NIX_RX_VWQE_F) ?\n@@ -346,9 +536,13 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \tuint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);\n \tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n \tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n+\tuint64_t aura_handle, lbase, laddr;\n+\tuint8_t loff = 0, lnum = 0;\n \tuint8x16_t f0, f1, f2, f3;\n+\tuint16_t lmt_id, d_off;\n \tuint16_t packets = 0;\n \tuint16_t pkts_left;\n+\tuintptr_t sa_base;\n \tuint32_t head;\n \tuintptr_t cq0;\n \n@@ -366,6 +560,38 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\tRTE_SET_USED(head);\n \t}\n \n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\tif (flags & NIX_RX_VWQE_F) {\n+\t\t\tuint16_t port;\n+\n+\t\t\tmbuf0 = (struct rte_mbuf *)((uintptr_t)mbufs[0] -\n+\t\t\t\t\t\t sizeof(struct rte_mbuf));\n+\t\t\t/* Pick first mbuf's aura handle assuming all\n+\t\t\t * mbufs are from a vec and are from same RQ.\n+\t\t\t */\n+\t\t\taura_handle = mbuf0->pool->pool_id;\n+\t\t\t/* Calculate offset from mbuf to actual data area */\n+\t\t\td_off = ((uintptr_t)mbuf0->buf_addr - (uintptr_t)mbuf0);\n+\t\t\td_off += (mbuf_initializer & 0xFFFF);\n+\n+\t\t\t/* Get SA Base from lookup tbl using port_id */\n+\t\t\tport = mbuf_initializer >> 48;\n+\t\t\tsa_base = cnxk_nix_sa_base_get(port, lookup_mem);\n+\n+\t\t\tlbase = lmt_base;\n+\t\t} else {\n+\t\t\taura_handle = rxq->aura_handle;\n+\t\t\td_off = rxq->data_off;\n+\t\t\tsa_base = rxq->sa_base;\n+\t\t\tlbase = rxq->lmt_base;\n+\t\t}\n+\t\tsa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);\n+\t\tROC_LMT_BASE_ID_GET(lbase, lmt_id);\n+\t\tlnum = 0;\n+\t\tladdr = lbase;\n+\t\tladdr += 8;\n+\t}\n+\n \twhile (packets < pkts) {\n \t\tif (!(flags & NIX_RX_VWQE_F)) {\n \t\t\t/* Exit loop if head is about to wrap and become\n@@ -428,6 +654,14 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\tf2 = vqtbl1q_u8(cq2_w8, shuf_msk);\n \t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n \n+\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\t/* Prefetch probable CPT parse header area */\n+\t\t\trte_prefetch_non_temporal(RTE_PTR_ADD(mbuf0, d_off));\n+\t\t\trte_prefetch_non_temporal(RTE_PTR_ADD(mbuf1, d_off));\n+\t\t\trte_prefetch_non_temporal(RTE_PTR_ADD(mbuf2, d_off));\n+\t\t\trte_prefetch_non_temporal(RTE_PTR_ADD(mbuf3, d_off));\n+\t\t}\n+\n \t\t/* Load CQE word0 and word 1 */\n \t\tconst uint64_t cq0_w0 = *CQE_PTR_OFF(cq0, 0, 0, flags);\n \t\tconst uint64_t cq0_w1 = *CQE_PTR_OFF(cq0, 0, 8, flags);\n@@ -474,6 +708,30 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\tol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);\n \t\t}\n \n+\t\t/* Translate meta to mbuf */\n+\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\t/* Checksum ol_flags will be cleared if mbuf is meta */\n+\t\t\tmbuf0 = nix_sec_meta_to_mbuf(cq0_w1, sa_base, laddr,\n+\t\t\t\t\t\t &loff, mbuf0, d_off, &f0,\n+\t\t\t\t\t\t &ol_flags0);\n+\t\t\tmbuf01 = vsetq_lane_u64((uint64_t)mbuf0, mbuf01, 0);\n+\n+\t\t\tmbuf1 = nix_sec_meta_to_mbuf(cq1_w1, sa_base, laddr,\n+\t\t\t\t\t\t &loff, mbuf1, d_off, &f1,\n+\t\t\t\t\t\t &ol_flags1);\n+\t\t\tmbuf01 = vsetq_lane_u64((uint64_t)mbuf1, mbuf01, 1);\n+\n+\t\t\tmbuf2 = nix_sec_meta_to_mbuf(cq2_w1, sa_base, laddr,\n+\t\t\t\t\t\t &loff, mbuf2, d_off, &f2,\n+\t\t\t\t\t\t &ol_flags2);\n+\t\t\tmbuf23 = vsetq_lane_u64((uint64_t)mbuf2, mbuf23, 0);\n+\n+\t\t\tmbuf3 = nix_sec_meta_to_mbuf(cq3_w1, sa_base, laddr,\n+\t\t\t\t\t\t &loff, mbuf3, d_off, &f3,\n+\t\t\t\t\t\t &ol_flags3);\n+\t\t\tmbuf23 = vsetq_lane_u64((uint64_t)mbuf3, mbuf23, 1);\n+\t\t}\n+\n \t\tif (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) {\n \t\t\tuint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16);\n \t\t\tuint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16);\n@@ -659,6 +917,26 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\thead += NIX_DESCS_PER_LOOP;\n \t\t\thead &= qmask;\n \t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\t/* Flush when we don't have space for 4 meta */\n+\t\t\tif ((15 - loff) < 4) {\n+\t\t\t\tnix_sec_flush_meta(laddr, lmt_id + lnum, loff,\n+\t\t\t\t\t\t aura_handle);\n+\t\t\t\tlnum++;\n+\t\t\t\tlnum &= BIT_ULL(ROC_LMT_LINES_PER_CORE_LOG2) -\n+\t\t\t\t\t1;\n+\t\t\t\t/* First pointer starts at 8B offset */\n+\t\t\t\tladdr = (uintptr_t)LMT_OFF(lbase, lnum, 8);\n+\t\t\t\tloff = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {\n+\t\tnix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);\n+\t\tif (flags & NIX_RX_VWQE_F)\n+\t\t\tplt_io_wmb();\n \t}\n \n \tif (flags & NIX_RX_VWQE_F)\n@@ -681,16 +959,18 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n #else\n \n static inline uint16_t\n-cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n-\t\t\t uint16_t pkts, const uint16_t flags,\n-\t\t\t void *lookup_mem, void *tstamp)\n+cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n+\t\t\t const uint16_t flags, void *lookup_mem,\n+\t\t\t struct cnxk_timesync_info *tstamp,\n+\t\t\t uintptr_t lmt_base)\n {\n-\tRTE_SET_USED(lookup_mem);\n-\tRTE_SET_USED(rx_queue);\n-\tRTE_SET_USED(rx_pkts);\n+\tRTE_SET_USED(args);\n+\tRTE_SET_USED(mbufs);\n \tRTE_SET_USED(pkts);\n \tRTE_SET_USED(flags);\n+\tRTE_SET_USED(lookup_mem);\n \tRTE_SET_USED(tstamp);\n+\tRTE_SET_USED(lmt_base);\n \n \treturn 0;\n }\n@@ -704,98 +984,268 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n #define MARK_F\t NIX_RX_OFFLOAD_MARK_UPDATE_F\n #define TS_F NIX_RX_OFFLOAD_TSTAMP_F\n #define RX_VLAN_F NIX_RX_OFFLOAD_VLAN_STRIP_F\n+#define R_SEC_F NIX_RX_OFFLOAD_SECURITY_F\n \n-/* [RX_VLAN_F] [TS] [MARK] [CKSUM] [PTYPE] [RSS] */\n+/* [R_SEC_F] [RX_VLAN_F] [TS] [MARK] [CKSUM] [PTYPE] [RSS] */\n #define NIX_RX_FASTPATH_MODES\t\t\t\t\t\t \\\n-R(no_offload,\t\t\t0, 0, 0, 0, 0, 0, NIX_RX_OFFLOAD_NONE)\t \\\n-R(rss,\t\t\t\t0, 0, 0, 0, 0, 1, RSS_F)\t\t \\\n-R(ptype,\t\t\t0, 0, 0, 0, 1, 0, PTYPE_F)\t\t \\\n-R(ptype_rss,\t\t\t0, 0, 0, 0, 1, 1, PTYPE_F | RSS_F)\t \\\n-R(cksum,\t\t\t0, 0, 0, 1, 0, 0, CKSUM_F)\t\t \\\n-R(cksum_rss,\t\t\t0, 0, 0, 1, 0, 1, CKSUM_F | RSS_F)\t \\\n-R(cksum_ptype,\t\t\t0, 0, 0, 1, 1, 0, CKSUM_F | PTYPE_F)\t \\\n-R(cksum_ptype_rss,\t\t0, 0, 0, 1, 1, 1, CKSUM_F | PTYPE_F | RSS_F) \\\n-R(mark,\t\t\t\t0, 0, 1, 0, 0, 0, MARK_F)\t\t \\\n-R(mark_rss,\t\t\t0, 0, 1, 0, 0, 1, MARK_F | RSS_F)\t \\\n-R(mark_ptype,\t\t\t0, 0, 1, 0, 1, 0, MARK_F | PTYPE_F)\t \\\n-R(mark_ptype_rss,\t\t0, 0, 1, 0, 1, 1, MARK_F | PTYPE_F | RSS_F) \\\n-R(mark_cksum,\t\t\t0, 0, 1, 1, 0, 0, MARK_F | CKSUM_F)\t \\\n-R(mark_cksum_rss,\t\t0, 0, 1, 1, 0, 1, MARK_F | CKSUM_F | RSS_F) \\\n-R(mark_cksum_ptype,\t\t0, 0, 1, 1, 1, 0, MARK_F | CKSUM_F | PTYPE_F) \\\n-R(mark_cksum_ptype_rss,\t\t0, 0, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tMARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n-R(ts,\t\t\t\t0, 1, 0, 0, 0, 0, TS_F)\t\t\t \\\n-R(ts_rss,\t\t\t0, 1, 0, 0, 0, 1, TS_F | RSS_F)\t\t \\\n-R(ts_ptype,\t\t\t0, 1, 0, 0, 1, 0, TS_F | PTYPE_F)\t \\\n-R(ts_ptype_rss,\t\t\t0, 1, 0, 0, 1, 1, TS_F | PTYPE_F | RSS_F) \\\n-R(ts_cksum,\t\t\t0, 1, 0, 1, 0, 0, TS_F | CKSUM_F)\t \\\n-R(ts_cksum_rss,\t\t\t0, 1, 0, 1, 0, 1, TS_F | CKSUM_F | RSS_F) \\\n-R(ts_cksum_ptype,\t\t0, 1, 0, 1, 1, 0, TS_F | CKSUM_F | PTYPE_F) \\\n-R(ts_cksum_ptype_rss,\t\t0, 1, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tTS_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n-R(ts_mark,\t\t\t0, 1, 1, 0, 0, 0, TS_F | MARK_F)\t \\\n-R(ts_mark_rss,\t\t\t0, 1, 1, 0, 0, 1, TS_F | MARK_F | RSS_F) \\\n-R(ts_mark_ptype,\t\t0, 1, 1, 0, 1, 0, TS_F | MARK_F | PTYPE_F) \\\n-R(ts_mark_ptype_rss,\t\t0, 1, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | PTYPE_F | RSS_F)\t\t \\\n-R(ts_mark_cksum,\t\t0, 1, 1, 1, 0, 0, TS_F | MARK_F | CKSUM_F) \\\n-R(ts_mark_cksum_rss,\t\t0, 1, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | CKSUM_F | RSS_F)\t\t \\\n-R(ts_mark_cksum_ptype,\t\t0, 1, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F)\t\t \\\n-R(ts_mark_cksum_ptype_rss,\t0, 1, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(vlan,\t\t\t\t1, 0, 0, 0, 0, 0, RX_VLAN_F)\t\t \\\n-R(vlan_rss,\t\t\t1, 0, 0, 0, 0, 1, RX_VLAN_F | RSS_F)\t \\\n-R(vlan_ptype,\t\t\t1, 0, 0, 0, 1, 0, RX_VLAN_F | PTYPE_F)\t \\\n-R(vlan_ptype_rss,\t\t1, 0, 0, 0, 1, 1, RX_VLAN_F | PTYPE_F | RSS_F) \\\n-R(vlan_cksum,\t\t\t1, 0, 0, 1, 0, 0, RX_VLAN_F | CKSUM_F)\t \\\n-R(vlan_cksum_rss,\t\t1, 0, 0, 1, 0, 1, RX_VLAN_F | CKSUM_F | RSS_F) \\\n-R(vlan_cksum_ptype,\t\t1, 0, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_VLAN_F | CKSUM_F | PTYPE_F)\t\t\t \\\n-R(vlan_cksum_ptype_rss,\t\t1, 0, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n-R(vlan_mark,\t\t\t1, 0, 1, 0, 0, 0, RX_VLAN_F | MARK_F)\t \\\n-R(vlan_mark_rss,\t\t1, 0, 1, 0, 0, 1, RX_VLAN_F | MARK_F | RSS_F) \\\n-R(vlan_mark_ptype,\t\t1, 0, 1, 0, 1, 0, RX_VLAN_F | MARK_F | PTYPE_F)\\\n-R(vlan_mark_ptype_rss,\t\t1, 0, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | MARK_F | PTYPE_F | RSS_F)\t\t \\\n-R(vlan_mark_cksum,\t\t1, 0, 1, 1, 0, 0, RX_VLAN_F | MARK_F | CKSUM_F)\\\n-R(vlan_mark_cksum_rss,\t\t1, 0, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | MARK_F | CKSUM_F | RSS_F)\t\t \\\n-R(vlan_mark_cksum_ptype,\t1, 0, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F)\t\t \\\n-R(vlan_mark_cksum_ptype_rss,\t1, 0, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(vlan_ts,\t\t\t1, 1, 0, 0, 0, 0, RX_VLAN_F | TS_F)\t \\\n-R(vlan_ts_rss,\t\t\t1, 1, 0, 0, 0, 1, RX_VLAN_F | TS_F | RSS_F) \\\n-R(vlan_ts_ptype,\t\t1, 1, 0, 0, 1, 0, RX_VLAN_F | TS_F | PTYPE_F) \\\n-R(vlan_ts_ptype_rss,\t\t1, 1, 0, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | PTYPE_F | RSS_F)\t\t \\\n-R(vlan_ts_cksum,\t\t1, 1, 0, 1, 0, 0, RX_VLAN_F | TS_F | CKSUM_F) \\\n-R(vlan_ts_cksum_rss,\t\t1, 1, 0, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | CKSUM_F | RSS_F)\t\t \\\n-R(vlan_ts_cksum_ptype,\t\t1, 1, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | CKSUM_F | PTYPE_F)\t\t \\\n-R(vlan_ts_cksum_ptype_rss,\t1, 1, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(vlan_ts_mark,\t\t\t1, 1, 1, 0, 0, 0, RX_VLAN_F | TS_F | MARK_F) \\\n-R(vlan_ts_mark_rss,\t\t1, 1, 1, 0, 0, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | MARK_F | RSS_F)\t\t \\\n-R(vlan_ts_mark_ptype,\t\t1, 1, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | MARK_F | PTYPE_F)\t\t \\\n-R(vlan_ts_mark_ptype_rss,\t1, 1, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F)\t \\\n-R(vlan_ts_mark_cksum,\t\t1, 1, 1, 1, 0, 0,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F)\t\t \\\n-R(vlan_ts_mark_cksum_rss,\t1, 1, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F)\t \\\n-R(vlan_ts_mark_cksum_ptype,\t1, 1, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F)\t \\\n-R(vlan_ts_mark_cksum_ptype_rss,\t1, 1, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\n+R(no_offload,\t\t\t0, 0, 0, 0, 0, 0, 0,\t\t\t \\\n+\t\tNIX_RX_OFFLOAD_NONE)\t\t\t\t\t \\\n+R(rss,\t\t\t\t0, 0, 0, 0, 0, 0, 1,\t\t\t \\\n+\t\tRSS_F)\t\t\t\t\t\t\t \\\n+R(ptype,\t\t\t0, 0, 0, 0, 0, 1, 0,\t\t\t \\\n+\t\tPTYPE_F)\t\t\t\t\t\t \\\n+R(ptype_rss,\t\t\t0, 0, 0, 0, 0, 1, 1,\t\t\t \\\n+\t\tPTYPE_F | RSS_F)\t\t\t\t\t \\\n+R(cksum,\t\t\t0, 0, 0, 0, 1, 0, 0,\t\t\t \\\n+\t\tCKSUM_F)\t\t\t\t\t\t \\\n+R(cksum_rss,\t\t\t0, 0, 0, 0, 1, 0, 1,\t\t\t \\\n+\t\tCKSUM_F | RSS_F)\t\t\t\t\t \\\n+R(cksum_ptype,\t\t\t0, 0, 0, 0, 1, 1, 0,\t\t\t \\\n+\t\tCKSUM_F | PTYPE_F)\t\t\t\t\t \\\n+R(cksum_ptype_rss,\t\t0, 0, 0, 0, 1, 1, 1,\t\t\t \\\n+\t\tCKSUM_F | PTYPE_F | RSS_F)\t\t\t\t \\\n+R(mark,\t\t\t\t0, 0, 0, 1, 0, 0, 0,\t\t\t \\\n+\t\tMARK_F)\t\t\t\t\t\t\t \\\n+R(mark_rss,\t\t\t0, 0, 0, 1, 0, 0, 1,\t\t\t \\\n+\t\tMARK_F | RSS_F)\t\t\t\t\t\t \\\n+R(mark_ptype,\t\t\t0, 0, 0, 1, 0, 1, 0,\t\t\t \\\n+\t\tMARK_F | PTYPE_F)\t\t\t\t\t \\\n+R(mark_ptype_rss,\t\t0, 0, 0, 1, 0, 1, 1,\t\t\t \\\n+\t\tMARK_F | PTYPE_F | RSS_F)\t\t\t\t \\\n+R(mark_cksum,\t\t\t0, 0, 0, 1, 1, 0, 0,\t\t\t \\\n+\t\tMARK_F | CKSUM_F)\t\t\t\t\t \\\n+R(mark_cksum_rss,\t\t0, 0, 0, 1, 1, 0, 1,\t\t\t \\\n+\t\tMARK_F | CKSUM_F | RSS_F)\t\t\t\t \\\n+R(mark_cksum_ptype,\t\t0, 0, 0, 1, 1, 1, 0,\t\t\t \\\n+\t\tMARK_F | CKSUM_F | PTYPE_F)\t\t\t\t \\\n+R(mark_cksum_ptype_rss,\t\t0, 0, 0, 1, 1, 1, 1,\t\t\t \\\n+\t\tMARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(ts,\t\t\t\t0, 0, 1, 0, 0, 0, 0,\t\t\t \\\n+\t\tTS_F)\t\t\t\t\t\t\t \\\n+R(ts_rss,\t\t\t0, 0, 1, 0, 0, 0, 1,\t\t\t \\\n+\t\tTS_F | RSS_F)\t\t\t\t\t\t \\\n+R(ts_ptype,\t\t\t0, 0, 1, 0, 0, 1, 0,\t\t\t \\\n+\t\tTS_F | PTYPE_F)\t\t\t\t\t\t \\\n+R(ts_ptype_rss,\t\t\t0, 0, 1, 0, 0, 1, 1,\t\t\t \\\n+\t\tTS_F | PTYPE_F | RSS_F)\t\t\t\t\t \\\n+R(ts_cksum,\t\t\t0, 0, 1, 0, 1, 0, 0,\t\t\t \\\n+\t\tTS_F | CKSUM_F)\t\t\t\t\t\t \\\n+R(ts_cksum_rss,\t\t\t0, 0, 1, 0, 1, 0, 1,\t\t\t \\\n+\t\tTS_F | CKSUM_F | RSS_F)\t\t\t\t\t \\\n+R(ts_cksum_ptype,\t\t0, 0, 1, 0, 1, 1, 0,\t\t\t \\\n+\t\tTS_F | CKSUM_F | PTYPE_F)\t\t\t\t \\\n+R(ts_cksum_ptype_rss,\t\t0, 0, 1, 0, 1, 1, 1,\t\t\t \\\n+\t\tTS_F | CKSUM_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(ts_mark,\t\t\t0, 0, 1, 1, 0, 0, 0,\t\t\t \\\n+\t\tTS_F | MARK_F)\t\t\t\t\t\t \\\n+R(ts_mark_rss,\t\t\t0, 0, 1, 1, 0, 0, 1,\t\t\t \\\n+\t\tTS_F | MARK_F | RSS_F)\t\t\t\t\t \\\n+R(ts_mark_ptype,\t\t0, 0, 1, 1, 0, 1, 0,\t\t\t \\\n+\t\tTS_F | MARK_F | PTYPE_F)\t\t\t\t \\\n+R(ts_mark_ptype_rss,\t\t0, 0, 1, 1, 0, 1, 1,\t\t\t \\\n+\t\tTS_F | MARK_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(ts_mark_cksum,\t\t0, 0, 1, 1, 1, 0, 0,\t\t\t \\\n+\t\tTS_F | MARK_F | CKSUM_F)\t\t\t\t \\\n+R(ts_mark_cksum_rss,\t\t0, 0, 1, 1, 1, 0, 1,\t\t\t \\\n+\t\tTS_F | MARK_F | CKSUM_F | RSS_F)\t\t\t \\\n+R(ts_mark_cksum_ptype,\t\t0, 0, 1, 1, 1, 1, 0,\t\t\t \\\n+\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F)\t\t\t \\\n+R(ts_mark_cksum_ptype_rss,\t0, 0, 1, 1, 1, 1, 1,\t\t\t \\\n+\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n+R(vlan,\t\t\t\t0, 1, 0, 0, 0, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F)\t\t\t\t\t\t \\\n+R(vlan_rss,\t\t\t0, 1, 0, 0, 0, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | RSS_F)\t\t\t\t\t \\\n+R(vlan_ptype,\t\t\t0, 1, 0, 0, 0, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | PTYPE_F)\t\t\t\t\t \\\n+R(vlan_ptype_rss,\t\t0, 1, 0, 0, 0, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | PTYPE_F | RSS_F)\t\t\t\t \\\n+R(vlan_cksum,\t\t\t0, 1, 0, 0, 1, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F | CKSUM_F)\t\t\t\t\t \\\n+R(vlan_cksum_rss,\t\t0, 1, 0, 0, 1, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | CKSUM_F | RSS_F)\t\t\t\t \\\n+R(vlan_cksum_ptype,\t\t0, 1, 0, 0, 1, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | CKSUM_F | PTYPE_F)\t\t\t\t \\\n+R(vlan_cksum_ptype_rss,\t\t0, 1, 0, 0, 1, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(vlan_mark,\t\t\t0, 1, 0, 1, 0, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F)\t\t\t\t\t \\\n+R(vlan_mark_rss,\t\t0, 1, 0, 1, 0, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F | RSS_F)\t\t\t\t \\\n+R(vlan_mark_ptype,\t\t0, 1, 0, 1, 0, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F | PTYPE_F)\t\t\t\t \\\n+R(vlan_mark_ptype_rss,\t\t0, 1, 0, 1, 0, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(vlan_mark_cksum,\t\t0, 1, 0, 1, 1, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F | CKSUM_F)\t\t\t\t \\\n+R(vlan_mark_cksum_rss,\t\t0, 1, 0, 1, 1, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F | CKSUM_F | RSS_F)\t\t\t \\\n+R(vlan_mark_cksum_ptype,\t0, 1, 0, 1, 1, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F)\t\t\t \\\n+R(vlan_mark_cksum_ptype_rss,\t0, 1, 0, 1, 1, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n+R(vlan_ts,\t\t\t0, 1, 1, 0, 0, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F)\t\t\t\t\t \\\n+R(vlan_ts_rss,\t\t\t0, 1, 1, 0, 0, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | RSS_F)\t\t\t\t \\\n+R(vlan_ts_ptype,\t\t0, 1, 1, 0, 0, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | PTYPE_F)\t\t\t\t \\\n+R(vlan_ts_ptype_rss,\t\t0, 1, 1, 0, 0, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(vlan_ts_cksum,\t\t0, 1, 1, 0, 1, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | CKSUM_F)\t\t\t\t \\\n+R(vlan_ts_cksum_rss,\t\t0, 1, 1, 0, 1, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | CKSUM_F | RSS_F)\t\t\t \\\n+R(vlan_ts_cksum_ptype,\t\t0, 1, 1, 0, 1, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | CKSUM_F | PTYPE_F)\t\t\t \\\n+R(vlan_ts_cksum_ptype_rss,\t0, 1, 1, 0, 1, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n+R(vlan_ts_mark,\t\t\t0, 1, 1, 1, 0, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F)\t\t\t\t \\\n+R(vlan_ts_mark_rss,\t\t0, 1, 1, 1, 0, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F | RSS_F)\t\t\t \\\n+R(vlan_ts_mark_ptype,\t\t0, 1, 1, 1, 0, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F | PTYPE_F)\t\t\t \\\n+R(vlan_ts_mark_ptype_rss,\t0, 1, 1, 1, 0, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F)\t\t \\\n+R(vlan_ts_mark_cksum,\t\t0, 1, 1, 1, 1, 0, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F)\t\t\t \\\n+R(vlan_ts_mark_cksum_rss,\t0, 1, 1, 1, 1, 0, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F)\t\t \\\n+R(vlan_ts_mark_cksum_ptype,\t0, 1, 1, 1, 1, 1, 0,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F)\t\t \\\n+R(vlan_ts_mark_cksum_ptype_rss,\t0, 1, 1, 1, 1, 1, 1,\t\t\t \\\n+\t\tRX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n+R(sec,\t\t\t\t1, 0, 0, 0, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F)\t\t\t\t\t\t \\\n+R(sec_rss,\t\t\t1, 0, 0, 0, 0, 0, 1,\t\t\t \\\n+\t\tRSS_F)\t\t\t\t\t\t\t \\\n+R(sec_ptype,\t\t\t1, 0, 0, 0, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | PTYPE_F)\t\t\t\t\t \\\n+R(sec_ptype_rss,\t\t1, 0, 0, 0, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | PTYPE_F | RSS_F)\t\t\t\t \\\n+R(sec_cksum,\t\t\t1, 0, 0, 0, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | CKSUM_F)\t\t\t\t\t \\\n+R(sec_cksum_rss,\t\t1, 0, 0, 0, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | CKSUM_F | RSS_F)\t\t\t\t \\\n+R(sec_cksum_ptype,\t\t1, 0, 0, 0, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | CKSUM_F | PTYPE_F)\t\t\t\t \\\n+R(sec_cksum_ptype_rss,\t\t1, 0, 0, 0, 1, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | CKSUM_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(sec_mark,\t\t\t1, 0, 0, 1, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | MARK_F)\t\t\t\t\t \\\n+R(sec_mark_rss,\t\t\t1, 0, 0, 1, 0, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | MARK_F | RSS_F)\t\t\t\t \\\n+R(sec_mark_ptype,\t\t1, 0, 0, 1, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | MARK_F | PTYPE_F)\t\t\t\t \\\n+R(sec_mark_ptype_rss,\t\t1, 0, 0, 1, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | MARK_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(sec_mark_cksum,\t\t1, 0, 0, 1, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | MARK_F | CKSUM_F)\t\t\t\t \\\n+R(sec_mark_cksum_rss,\t\t1, 0, 0, 1, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | MARK_F | CKSUM_F | RSS_F)\t\t\t \\\n+R(sec_mark_cksum_ptype,\t\t1, 0, 0, 1, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | MARK_F | CKSUM_F | PTYPE_F)\t\t\t \\\n+R(sec_mark_cksum_ptype_rss,\t1, 0, 0, 1, 1, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n+R(sec_ts,\t\t\t1, 0, 1, 0, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F)\t\t\t\t\t\t \\\n+R(sec_ts_rss,\t\t\t1, 0, 1, 0, 0, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | RSS_F)\t\t\t\t\t \\\n+R(sec_ts_ptype,\t\t\t1, 0, 1, 0, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F | PTYPE_F)\t\t\t\t \\\n+R(sec_ts_ptype_rss,\t\t1, 0, 1, 0, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(sec_ts_cksum,\t\t\t1, 0, 1, 0, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F | CKSUM_F)\t\t\t\t \\\n+R(sec_ts_cksum_rss,\t\t1, 0, 1, 0, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | CKSUM_F | RSS_F)\t\t\t \\\n+R(sec_ts_cksum_ptype,\t\t1, 0, 1, 0, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F | CKSUM_F | PTYPE_F)\t\t\t \\\n+R(sec_ts_cksum_ptype_rss,\t1, 0, 1, 0, 1, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n+R(sec_ts_mark,\t\t\t1, 0, 1, 1, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F)\t\t\t\t \\\n+R(sec_ts_mark_rss,\t\t1, 0, 1, 1, 0, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F | RSS_F)\t\t\t \\\n+R(sec_ts_mark_ptype,\t\t1, 0, 1, 1, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F | PTYPE_F)\t\t\t \\\n+R(sec_ts_mark_ptype_rss,\t1, 0, 1, 1, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F | PTYPE_F | RSS_F)\t\t \\\n+R(sec_ts_mark_cksum,\t\t1, 0, 1, 1, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F | CKSUM_F)\t\t\t \\\n+R(sec_ts_mark_cksum_rss,\t1, 0, 1, 1, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F | CKSUM_F | RSS_F)\t\t \\\n+R(sec_ts_mark_cksum_ptype,\t1, 0, 1, 1, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F)\t\t \\\n+R(sec_ts_mark_cksum_ptype_rss,\t1, 0, 1, 1, 1, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n+R(sec_vlan,\t\t\t1, 1, 0, 0, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F)\t\t\t\t\t \\\n+R(sec_vlan_rss,\t\t\t1, 1, 0, 0, 0, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | RSS_F)\t\t\t\t \\\n+R(sec_vlan_ptype,\t\t1, 1, 0, 0, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | PTYPE_F)\t\t\t\t \\\n+R(sec_vlan_ptype_rss,\t\t1, 1, 0, 0, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | PTYPE_F | RSS_F)\t\t\t \\\n+R(sec_vlan_cksum,\t\t1, 1, 0, 0, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | CKSUM_F)\t\t\t\t \\\n+R(sec_vlan_cksum_rss,\t\t1, 1, 0, 0, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | CKSUM_F | RSS_F)\t\t\t \\\n+R(sec_vlan_cksum_ptype,\t\t1, 1, 0, 0, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t\t \\\n+R(sec_vlan_cksum_ptype_rss,\t1, 1, 0, 0, 1, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n+R(sec_vlan_mark,\t\t1, 1, 0, 1, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F)\t\t\t\t \\\n+R(sec_vlan_mark_rss,\t\t1, 1, 0, 1, 0, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F | RSS_F)\t\t\t \\\n+R(sec_vlan_mark_ptype,\t\t1, 1, 0, 1, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F)\t\t\t \\\n+R(sec_vlan_mark_ptype_rss,\t1, 1, 0, 1, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F | RSS_F)\t\t \\\n+R(sec_vlan_mark_cksum,\t\t1, 1, 0, 1, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F)\t\t\t \\\n+R(sec_vlan_mark_cksum_rss,\t1, 1, 0, 1, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | RSS_F)\t\t \\\n+R(sec_vlan_mark_cksum_ptype,\t1, 1, 0, 1, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F)\t \\\n+R(sec_vlan_mark_cksum_ptype_rss, 1, 1, 0, 1, 1, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \\\n+R(sec_vlan_ts,\t\t\t1, 1, 1, 0, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F)\t\t\t\t \\\n+R(sec_vlan_ts_rss,\t\t1, 1, 1, 0, 0, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | RSS_F)\t\t\t \\\n+R(sec_vlan_ts_ptype,\t\t1, 1, 1, 0, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | PTYPE_F)\t\t\t \\\n+R(sec_vlan_ts_ptype_rss,\t1, 1, 1, 0, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | PTYPE_F | RSS_F)\t\t \\\n+R(sec_vlan_ts_cksum,\t\t1, 1, 1, 0, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | CKSUM_F)\t\t\t \\\n+R(sec_vlan_ts_cksum_rss,\t1, 1, 1, 0, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | RSS_F)\t\t \\\n+R(sec_vlan_ts_cksum_ptype,\t1, 1, 1, 0, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F)\t\t \\\n+R(sec_vlan_ts_cksum_ptype_rss,\t1, 1, 1, 0, 1, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n+R(sec_vlan_ts_mark,\t\t1, 1, 1, 1, 0, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F)\t\t\t \\\n+R(sec_vlan_ts_mark_rss,\t\t1, 1, 1, 1, 0, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F | RSS_F)\t\t \\\n+R(sec_vlan_ts_mark_ptype,\t1, 1, 1, 1, 0, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F)\t\t \\\n+R(sec_vlan_ts_mark_ptype_rss,\t1, 1, 1, 1, 0, 1, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F)\t \\\n+R(sec_vlan_ts_mark_cksum,\t1, 1, 1, 1, 1, 0, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F)\t\t \\\n+R(sec_vlan_ts_mark_cksum_rss,\t1, 1, 1, 1, 1, 0, 1,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F)\t \\\n+R(sec_vlan_ts_mark_cksum_ptype,\t1, 1, 1, 1, 1, 1, 0,\t\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \\\n+R(sec_vlan_ts_mark_cksum_ptype_rss,\t1, 1, 1, 1, 1, 1, 1,\t\t \\\n+\t\tR_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n \tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n \t\t\t\t\t\t\t\t\t \\\ndiff --git a/drivers/net/cnxk/cn10k_rx_mseg.c b/drivers/net/cnxk/cn10k_rx_mseg.c\nindex 3340771..e7c2321 100644\n--- a/drivers/net/cnxk/cn10k_rx_mseg.c\n+++ b/drivers/net/cnxk/cn10k_rx_mseg.c\n@@ -5,7 +5,7 @@\n #include \"cn10k_ethdev.h\"\n #include \"cn10k_rx.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n \tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_mseg_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n \t{ \\\ndiff --git a/drivers/net/cnxk/cn10k_rx_vec.c b/drivers/net/cnxk/cn10k_rx_vec.c\nindex 166735a..0ccc4df 100644\n--- a/drivers/net/cnxk/cn10k_rx_vec.c\n+++ b/drivers/net/cnxk/cn10k_rx_vec.c\n@@ -5,14 +5,14 @@\n #include \"cn10k_ethdev.h\"\n #include \"cn10k_rx.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n \tuint16_t __rte_noinline __rte_hot\t\t\t\t \\\n \t\tcn10k_nix_recv_pkts_vec_##name(void *rx_queue, \\\n \t\t\t\t\t struct rte_mbuf **rx_pkts, \\\n \t\t\t\t\t uint16_t pkts) \\\n \t{ \\\n \t\treturn cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n-\t\t\t\t\t\t (flags), NULL, NULL); \\\n+\t\t\t\t\t\t (flags), NULL, NULL, 0); \\\n \t}\n \n NIX_RX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_rx_vec_mseg.c b/drivers/net/cnxk/cn10k_rx_vec_mseg.c\nindex 1f44ddd..38e0ec3 100644\n--- a/drivers/net/cnxk/cn10k_rx_vec_mseg.c\n+++ b/drivers/net/cnxk/cn10k_rx_vec_mseg.c\n@@ -5,13 +5,13 @@\n #include \"cn10k_ethdev.h\"\n #include \"cn10k_rx.h\"\n \n-#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \\\n \tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_vec_mseg_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n \t{ \\\n \t\treturn cn10k_nix_recv_pkts_vector( \\\n \t\t\trx_queue, rx_pkts, pkts, (flags) | NIX_RX_MULTI_SEG_F, \\\n-\t\t\tNULL, NULL); \\\n+\t\t\tNULL, NULL, 0); \\\n \t}\n \n NIX_RX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex 8577a7b..c81a612 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -51,9 +51,6 @@\n \n #define NIX_NB_SEGS_TO_SEGDW(x) ((NIX_SEGDW_MAGIC >> ((x) << 2)) & 0xF)\n \n-#define LMT_OFF(lmt_addr, lmt_num, offset) \\\n-\t(void *)((lmt_addr) + ((lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset))\n-\n /* Function to determine no of tx subdesc required in case ext\n * sub desc is enabled.\n */\n", "prefixes": [ "19/27" ] }