Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/97732/?format=api
{ "id": 97732, "url": "http://patches.dpdk.org/api/patches/97732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-7-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210902021505.17607-7-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210902021505.17607-7-ndabilpuram@marvell.com", "date": "2021-09-02T02:14:44", "name": "[06/27] common/cnxk: add nix inline device init and fini", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0818929a9b7038be71ac9098ebff8bcf4a169eb4", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-7-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 18612, "url": "http://patches.dpdk.org/api/series/18612/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18612", "date": "2021-09-02T02:14:38", "name": "net/cnxk: support for inline ipsec", "version": 1, "mbox": "http://patches.dpdk.org/series/18612/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/97732/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/97732/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CE675A0C4C;\n\tThu, 2 Sep 2021 04:17:26 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 83C324113B;\n\tThu, 2 Sep 2021 04:17:07 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 855CD40140\n for <dev@dpdk.org>; Thu, 2 Sep 2021 04:17:06 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 181HQtfT012898;\n Wed, 1 Sep 2021 19:17:04 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9hr5-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 01 Sep 2021 19:17:04 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 1 Sep 2021 19:17:02 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 1 Sep 2021 19:17:01 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 3A3AD3F704B;\n Wed, 1 Sep 2021 19:16:59 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=6yj2uCJXX29VgE92mUX4uWKoBukHdCP37Gu896/HukQ=;\n b=LUvj+Qqmy9AB1cn77zVCLvg4ub90cGR/xa6UjyEpncEG4PW9Qy9CkgtYUtJBgMQ/lA6W\n pXfRoHOCJUhtsUXnbSbVqMqwSpyVs8DKeqpds7sWHFp1pUKTHIboa+BwostGdNDbklmQ\n 73NLNP+dWdQ79r9uGQfXV5wfHWtqITkr6fvs5Qak8Ze5FBTVh2cUgx/ilPscbOmh2gV+\n ZfH4RPfCM53U1cxkY/WrSROyDQMpPyutcCe01UcoBYeS3qSFjL5M+whZHSLta7WRmI3Y\n jD1Vn5vNMX7VaoJX2voXPAAsgXOVx9JyYuVeu8zbMsqs3Mqw50uRAw25ePUFfa5o5d3P OQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<jerinj@marvell.com>, <schalla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 2 Sep 2021 07:44:44 +0530", "Message-ID": "<20210902021505.17607-7-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "zfWwOwbffjQNOzRux2CmPemDODtKf729", "X-Proofpoint-GUID": "zfWwOwbffjQNOzRux2CmPemDODtKf729", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 06/27] common/cnxk: add nix inline device init\n and fini", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support to init and fini nix inline device with NIX LF,\nSSO LF and SSOW LF for inline inbound IPSec in CN10K.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 2 +\n drivers/common/cnxk/roc_cpt.c | 7 +-\n drivers/common/cnxk/roc_idev.c | 2 +\n drivers/common/cnxk/roc_idev_priv.h | 3 +\n drivers/common/cnxk/roc_nix_debug.c | 35 +++\n drivers/common/cnxk/roc_nix_inl.h | 55 ++++\n drivers/common/cnxk/roc_nix_inl_dev.c | 544 +++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_inl_priv.h | 2 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/version.map | 3 +\n 11 files changed, 653 insertions(+), 3 deletions(-)\n create mode 100644 drivers/common/cnxk/roc_nix_inl_dev.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 207ca00..e8940d7 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -28,6 +28,7 @@ sources = files(\n 'roc_nix_debug.c',\n 'roc_nix_fc.c',\n 'roc_nix_irq.c',\n+ 'roc_nix_inl_dev.c',\n 'roc_nix_inl_dev_irq.c',\n 'roc_nix_mac.c',\n 'roc_nix_mcast.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex c1af95e..53f4e4b 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -53,6 +53,8 @@\n #define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6\n #define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7\n #define PCI_DEVID_CNXK_BPHY\t 0xA089\n+#define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0\n+#define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1\n \n #define PCI_DEVID_CN9K_CGX 0xA059\n #define PCI_DEVID_CN10K_RPM 0xA060\ndiff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex 5e35d1b..3222b3e 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -381,11 +381,12 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,\n \tif (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)\n \t\treturn -EINVAL;\n \n-\tPLT_SET_USED(inl_dev_sso);\n-\n \treq = mbox_alloc_msg_cpt_lf_alloc(mbox);\n \treq->nix_pf_func = 0;\n-\treq->sso_pf_func = idev_sso_pffunc_get();\n+\tif (inl_dev_sso && nix_inl_dev_pffunc_get())\n+\t\treq->sso_pf_func = nix_inl_dev_pffunc_get();\n+\telse\n+\t\treq->sso_pf_func = idev_sso_pffunc_get();\n \treq->eng_grpmsk = eng_grpmsk;\n \treq->blkaddr = blkaddr;\n \ndiff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex 1494187..648f37b 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -38,6 +38,8 @@ idev_set_defaults(struct idev_cfg *idev)\n \tidev->num_lmtlines = 0;\n \tidev->bphy = NULL;\n \tidev->cpt = NULL;\n+\tidev->nix_inl_dev = NULL;\n+\tplt_spinlock_init(&idev->nix_inl_dev_lock);\n \t__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);\n }\n \ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex 84e6f1e..2c8309b 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -9,6 +9,7 @@\n struct npa_lf;\n struct roc_bphy;\n struct roc_cpt;\n+struct nix_inl_dev;\n struct idev_cfg {\n \tuint16_t sso_pf_func;\n \tuint16_t npa_pf_func;\n@@ -20,6 +21,8 @@ struct idev_cfg {\n \tuint64_t lmt_base_addr;\n \tstruct roc_bphy *bphy;\n \tstruct roc_cpt *cpt;\n+\tstruct nix_inl_dev *nix_inl_dev;\n+\tplt_spinlock_t nix_inl_dev_lock;\n };\n \n /* Generic */\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 9539bb9..582f5a3 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -1213,3 +1213,38 @@ roc_nix_dump(struct roc_nix *roc_nix)\n \tnix_dump(\" \\trss_alg_idx = %d\", nix->rss_alg_idx);\n \tnix_dump(\" \\ttx_pause = %d\", nix->tx_pause);\n }\n+\n+void\n+roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)\n+{\n+\tstruct nix_inl_dev *inl_dev =\n+\t\t(struct nix_inl_dev *)&roc_inl_dev->reserved;\n+\tstruct dev *dev = &inl_dev->dev;\n+\n+\tnix_dump(\"nix_inl_dev@%p\", inl_dev);\n+\tnix_dump(\" pf = %d\", dev_get_pf(dev->pf_func));\n+\tnix_dump(\" vf = %d\", dev_get_vf(dev->pf_func));\n+\tnix_dump(\" bar2 = 0x%\" PRIx64, dev->bar2);\n+\tnix_dump(\" bar4 = 0x%\" PRIx64, dev->bar4);\n+\n+\tnix_dump(\" \\tpci_dev = %p\", inl_dev->pci_dev);\n+\tnix_dump(\" \\tnix_base = 0x%\" PRIxPTR \"\", inl_dev->nix_base);\n+\tnix_dump(\" \\tsso_base = 0x%\" PRIxPTR \"\", inl_dev->sso_base);\n+\tnix_dump(\" \\tssow_base = 0x%\" PRIxPTR \"\", inl_dev->ssow_base);\n+\tnix_dump(\" \\tnix_msixoff = %d\", inl_dev->nix_msixoff);\n+\tnix_dump(\" \\tsso_msixoff = %d\", inl_dev->sso_msixoff);\n+\tnix_dump(\" \\tssow_msixoff = %d\", inl_dev->ssow_msixoff);\n+\tnix_dump(\" \\tnix_cints = %d\", inl_dev->cints);\n+\tnix_dump(\" \\tnix_qints = %d\", inl_dev->qints);\n+\tnix_dump(\" \\trq_refs = %d\", inl_dev->rq_refs);\n+\tnix_dump(\" \\tinb_sa_base = 0x%p\", inl_dev->inb_sa_base);\n+\tnix_dump(\" \\tinb_sa_sz = %d\", inl_dev->inb_sa_sz);\n+\tnix_dump(\" \\txaq_buf_size = %u\", inl_dev->xaq_buf_size);\n+\tnix_dump(\" \\txae_waes = %u\", inl_dev->xae_waes);\n+\tnix_dump(\" \\tiue = %u\", inl_dev->iue);\n+\tnix_dump(\" \\txaq_aura = 0x%\" PRIx64, inl_dev->xaq_aura);\n+\tnix_dump(\" \\txaq_mem = 0x%p\", inl_dev->xaq_mem);\n+\n+\tnix_dump(\" \\tinl_dev_rq:\");\n+\troc_nix_rq_dump(&inl_dev->rq);\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 1ec3dda..f1fe4a2 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -4,7 +4,62 @@\n #ifndef _ROC_NIX_INL_H_\n #define _ROC_NIX_INL_H_\n \n+/* ONF INB HW area */\n+#define ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ \\\n+\tPLT_ALIGN(sizeof(struct roc_onf_ipsec_inb_sa), ROC_ALIGN)\n+/* ONF INB SW reserved area */\n+#define ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD 384\n+#define ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ \\\n+\t(ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ + ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD)\n+#define ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2 9\n+\n+/* ONF OUTB HW area */\n+#define ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ \\\n+\tPLT_ALIGN(sizeof(struct roc_onf_ipsec_outb_sa), ROC_ALIGN)\n+/* ONF OUTB SW reserved area */\n+#define ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD 128\n+#define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ \\\n+\t(ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD)\n+#define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2 8\n+\n+/* OT INB HW area */\n+#define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \\\n+\tPLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN)\n+/* OT INB SW reserved area */\n+#define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128\n+#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ \\\n+\t(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD)\n+#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10\n+\n+/* OT OUTB HW area */\n+#define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ \\\n+\tPLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN)\n+/* OT OUTB SW reserved area */\n+#define ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD 128\n+#define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ \\\n+\t(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD)\n+#define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2 9\n+\n+/* Alignment of SA Base */\n+#define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)\n+\n /* Inline device SSO Work callback */\n typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);\n \n+struct roc_nix_inl_dev {\n+\t/* Input parameters */\n+\tstruct plt_pci_device *pci_dev;\n+\tuint16_t ipsec_in_max_spi;\n+\tbool selftest;\n+\t/* End of input parameters */\n+\n+#define ROC_NIX_INL_MEM_SZ (1024)\n+\tuint8_t reserved[ROC_NIX_INL_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+/* NIX Inline Device API */\n+int __roc_api roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev);\n+int __roc_api roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev);\n+void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);\n+\n #endif /* _ROC_NIX_INL_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nnew file mode 100644\nindex 0000000..214f183\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -0,0 +1,544 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+#define XAQ_CACHE_CNT 0x7\n+\n+/* Default Rx Config for Inline NIX LF */\n+#define NIX_INL_LF_RX_CFG \\\n+\t(ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR | \\\n+\t ROC_NIX_LF_RX_CFG_IP6_UDP_OPT | ROC_NIX_LF_RX_CFG_DIS_APAD | \\\n+\t ROC_NIX_LF_RX_CFG_CSUM_IL4 | ROC_NIX_LF_RX_CFG_CSUM_OL4 | \\\n+\t ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 | \\\n+\t ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3)\n+\n+uint16_t\n+nix_inl_dev_pffunc_get(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev != NULL) {\n+\t\tinl_dev = idev->nix_inl_dev;\n+\t\tif (inl_dev)\n+\t\t\treturn inl_dev->dev.pf_func;\n+\t}\n+\treturn 0;\n+}\n+\n+static void\n+nix_inl_selftest_work_cb(uint64_t *gw, void *args)\n+{\n+\tuintptr_t work = gw[1];\n+\n+\t*((uintptr_t *)args + (gw[0] & 0x1)) = work;\n+\n+\tplt_atomic_thread_fence(__ATOMIC_ACQ_REL);\n+}\n+\n+static int\n+nix_inl_selftest(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\troc_nix_inl_sso_work_cb_t save_cb;\n+\tstatic uintptr_t work_arr[2];\n+\tstruct nix_inl_dev *inl_dev;\n+\tvoid *save_cb_args;\n+\tuint64_t add_work0;\n+\tint rc = 0;\n+\n+\tif (idev == NULL)\n+\t\treturn -ENOTSUP;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (inl_dev == NULL)\n+\t\treturn -ENOTSUP;\n+\n+\tplt_info(\"Performing nix inl self test\");\n+\n+\t/* Save and update cb to test cb */\n+\tsave_cb = inl_dev->work_cb;\n+\tsave_cb_args = inl_dev->cb_args;\n+\tinl_dev->work_cb = nix_inl_selftest_work_cb;\n+\tinl_dev->cb_args = work_arr;\n+\n+\tplt_atomic_thread_fence(__ATOMIC_ACQ_REL);\n+\n+#define WORK_MAGIC1 0x335577ff0\n+#define WORK_MAGIC2 0xdeadbeef0\n+\n+\t/* Add work */\n+\tadd_work0 = ((uint64_t)(SSO_TT_ORDERED) << 32) | 0x0;\n+\troc_store_pair(add_work0, WORK_MAGIC1, inl_dev->sso_base);\n+\tadd_work0 = ((uint64_t)(SSO_TT_ORDERED) << 32) | 0x1;\n+\troc_store_pair(add_work0, WORK_MAGIC2, inl_dev->sso_base);\n+\n+\tplt_delay_ms(10000);\n+\n+\t/* Check if we got expected work */\n+\tif (work_arr[0] != WORK_MAGIC1 || work_arr[1] != WORK_MAGIC2) {\n+\t\tplt_err(\"Failed to get expected work, [0]=%p [1]=%p\",\n+\t\t\t(void *)work_arr[0], (void *)work_arr[1]);\n+\t\trc = -EFAULT;\n+\t\tgoto exit;\n+\t}\n+\n+\tplt_info(\"Work, [0]=%p [1]=%p\", (void *)work_arr[0],\n+\t\t (void *)work_arr[1]);\n+\n+exit:\n+\t/* Restore state */\n+\tinl_dev->work_cb = save_cb;\n+\tinl_dev->cb_args = save_cb_args;\n+\treturn rc;\n+}\n+\n+static int\n+nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)\n+{\n+\tstruct nix_inline_ipsec_lf_cfg *lf_cfg;\n+\tstruct mbox *mbox = (&inl_dev->dev)->mbox;\n+\tuint32_t sa_w;\n+\n+\tlf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);\n+\tif (lf_cfg == NULL)\n+\t\treturn -ENOSPC;\n+\n+\tif (ena) {\n+\t\tsa_w = plt_align32pow2(inl_dev->ipsec_in_max_spi + 1);\n+\t\tsa_w = plt_log2_u32(sa_w);\n+\n+\t\tlf_cfg->enable = 1;\n+\t\tlf_cfg->sa_base_addr = (uintptr_t)inl_dev->inb_sa_base;\n+\t\tlf_cfg->ipsec_cfg1.sa_idx_w = sa_w;\n+\t\t/* CN9K SA size is different */\n+\t\tif (roc_model_is_cn9k())\n+\t\t\tlf_cfg->ipsec_cfg0.lenm1_max = NIX_CN9K_MAX_HW_FRS - 1;\n+\t\telse\n+\t\t\tlf_cfg->ipsec_cfg0.lenm1_max = NIX_RPM_MAX_HW_FRS - 1;\n+\t\tlf_cfg->ipsec_cfg1.sa_idx_max = inl_dev->ipsec_in_max_spi;\n+\t\tlf_cfg->ipsec_cfg0.sa_pow2_size =\n+\t\t\tplt_log2_u32(inl_dev->inb_sa_sz);\n+\n+\t\tlf_cfg->ipsec_cfg0.tag_const = 0;\n+\t\tlf_cfg->ipsec_cfg0.tt = SSO_TT_ORDERED;\n+\t} else {\n+\t\tlf_cfg->enable = 0;\n+\t}\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static int\n+nix_inl_sso_setup(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct sso_lf_alloc_rsp *sso_rsp;\n+\tstruct dev *dev = &inl_dev->dev;\n+\tuint32_t xaq_cnt, count, aura;\n+\tuint16_t hwgrp[1] = {0};\n+\tstruct npa_pool_s pool;\n+\tuintptr_t iova;\n+\tint rc;\n+\n+\t/* Alloc SSOW LF */\n+\trc = sso_lf_alloc(dev, SSO_LF_TYPE_HWS, 1, NULL);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to alloc SSO HWS, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Alloc HWGRP LF */\n+\trc = sso_lf_alloc(dev, SSO_LF_TYPE_HWGRP, 1, (void **)&sso_rsp);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to alloc SSO HWGRP, rc=%d\", rc);\n+\t\tgoto free_ssow;\n+\t}\n+\n+\tinl_dev->xaq_buf_size = sso_rsp->xaq_buf_size;\n+\tinl_dev->xae_waes = sso_rsp->xaq_wq_entries;\n+\tinl_dev->iue = sso_rsp->in_unit_entries;\n+\n+\t/* Create XAQ pool */\n+\txaq_cnt = XAQ_CACHE_CNT;\n+\txaq_cnt += inl_dev->iue / inl_dev->xae_waes;\n+\tplt_sso_dbg(\"Configuring %d xaq buffers\", xaq_cnt);\n+\n+\tinl_dev->xaq_mem = plt_zmalloc(inl_dev->xaq_buf_size * xaq_cnt,\n+\t\t\t\t inl_dev->xaq_buf_size);\n+\tif (!inl_dev->xaq_mem) {\n+\t\trc = NIX_ERR_NO_MEM;\n+\t\tplt_err(\"Failed to alloc xaq buf mem\");\n+\t\tgoto free_sso;\n+\t}\n+\n+\tmemset(&pool, 0, sizeof(struct npa_pool_s));\n+\tpool.nat_align = 1;\n+\trc = roc_npa_pool_create(&inl_dev->xaq_aura, inl_dev->xaq_buf_size,\n+\t\t\t\t xaq_cnt, NULL, &pool);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to alloc aura for XAQ, rc=%d\", rc);\n+\t\tgoto free_mem;\n+\t}\n+\n+\t/* Fill the XAQ buffers */\n+\tiova = (uint64_t)inl_dev->xaq_mem;\n+\tfor (count = 0; count < xaq_cnt; count++) {\n+\t\troc_npa_aura_op_free(inl_dev->xaq_aura, 0, iova);\n+\t\tiova += inl_dev->xaq_buf_size;\n+\t}\n+\troc_npa_aura_op_range_set(inl_dev->xaq_aura, (uint64_t)inl_dev->xaq_mem,\n+\t\t\t\t iova);\n+\n+\taura = roc_npa_aura_handle_to_aura(inl_dev->xaq_aura);\n+\n+\t/* Setup xaq for hwgrps */\n+\trc = sso_hwgrp_alloc_xaq(dev, aura, 1);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to setup hwgrp xaq aura, rc=%d\", rc);\n+\t\tgoto destroy_pool;\n+\t}\n+\n+\t/* Register SSO, SSOW error and work irq's */\n+\trc = nix_inl_sso_register_irqs(inl_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to register sso irq's, rc=%d\", rc);\n+\t\tgoto release_xaq;\n+\t}\n+\n+\t/* Setup hwgrp->hws link */\n+\tsso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, true);\n+\n+\t/* Enable HWGRP */\n+\tplt_write64(0x1, inl_dev->sso_base + SSO_LF_GGRP_QCTL);\n+\n+\treturn 0;\n+\n+release_xaq:\n+\tsso_hwgrp_release_xaq(&inl_dev->dev, 1);\n+destroy_pool:\n+\troc_npa_pool_destroy(inl_dev->xaq_aura);\n+\tinl_dev->xaq_aura = 0;\n+free_mem:\n+\tplt_free(inl_dev->xaq_mem);\n+\tinl_dev->xaq_mem = NULL;\n+free_sso:\n+\tsso_lf_free(dev, SSO_LF_TYPE_HWGRP, 1);\n+free_ssow:\n+\tsso_lf_free(dev, SSO_LF_TYPE_HWS, 1);\n+\treturn rc;\n+}\n+\n+static int\n+nix_inl_sso_release(struct nix_inl_dev *inl_dev)\n+{\n+\tuint16_t hwgrp[1] = {0};\n+\n+\t/* Disable HWGRP */\n+\tplt_write64(0, inl_dev->sso_base + SSO_LF_GGRP_QCTL);\n+\n+\t/* Unregister SSO/SSOW IRQ's */\n+\tnix_inl_sso_unregister_irqs(inl_dev);\n+\n+\t/* Unlink hws */\n+\tsso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, false);\n+\n+\t/* Release XAQ aura */\n+\tsso_hwgrp_release_xaq(&inl_dev->dev, 1);\n+\n+\t/* Free SSO, SSOW LF's */\n+\tsso_lf_free(&inl_dev->dev, SSO_LF_TYPE_HWS, 1);\n+\tsso_lf_free(&inl_dev->dev, SSO_LF_TYPE_HWGRP, 1);\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n+{\n+\tuint16_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;\n+\tstruct dev *dev = &inl_dev->dev;\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct nix_lf_alloc_rsp *rsp;\n+\tstruct nix_lf_alloc_req *req;\n+\tsize_t inb_sa_sz;\n+\tint rc = -ENOSPC;\n+\n+\t/* Alloc NIX LF needed for single RQ */\n+\treq = mbox_alloc_msg_nix_lf_alloc(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->rq_cnt = 1;\n+\treq->sq_cnt = 1;\n+\treq->cq_cnt = 1;\n+\t/* XQESZ is W16 */\n+\treq->xqe_sz = NIX_XQESZ_W16;\n+\t/* RSS size does not matter as this RQ is only for UCAST_IPSEC action */\n+\treq->rss_sz = ROC_NIX_RSS_RETA_SZ_64;\n+\treq->rss_grps = ROC_NIX_RSS_GRPS;\n+\treq->npa_func = idev_npa_pffunc_get();\n+\treq->sso_func = dev->pf_func;\n+\treq->rx_cfg = NIX_INL_LF_RX_CFG;\n+\treq->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to alloc lf, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tinl_dev->lf_tx_stats = rsp->lf_tx_stats;\n+\tinl_dev->lf_rx_stats = rsp->lf_rx_stats;\n+\tinl_dev->qints = rsp->qints;\n+\tinl_dev->cints = rsp->cints;\n+\n+\t/* Register nix interrupts */\n+\trc = nix_inl_nix_register_irqs(inl_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to register nix irq's, rc=%d\", rc);\n+\t\tgoto lf_free;\n+\t}\n+\n+\t/* CN9K SA is different */\n+\tif (roc_model_is_cn9k())\n+\t\tinb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ;\n+\telse\n+\t\tinb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;\n+\n+\t/* Alloc contiguous memory for Inbound SA's */\n+\tinl_dev->inb_sa_sz = inb_sa_sz;\n+\tinl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,\n+\t\t\t\t\t ROC_NIX_INL_SA_BASE_ALIGN);\n+\tif (!inl_dev->inb_sa_base) {\n+\t\tplt_err(\"Failed to allocate memory for Inbound SA\");\n+\t\trc = -ENOMEM;\n+\t\tgoto unregister_irqs;\n+\t}\n+\n+\t/* Setup device specific inb SA table */\n+\trc = nix_inl_nix_ipsec_cfg(inl_dev, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to setup NIX Inbound SA conf, rc=%d\", rc);\n+\t\tgoto free_mem;\n+\t}\n+\n+\treturn 0;\n+free_mem:\n+\tplt_free(inl_dev->inb_sa_base);\n+\tinl_dev->inb_sa_base = NULL;\n+unregister_irqs:\n+\tnix_inl_nix_unregister_irqs(inl_dev);\n+lf_free:\n+\tmbox_alloc_msg_nix_lf_free(mbox);\n+\trc |= mbox_process(mbox);\n+\treturn rc;\n+}\n+\n+static int\n+nix_inl_nix_release(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct dev *dev = &inl_dev->dev;\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct nix_lf_free_req *req;\n+\tstruct ndc_sync_op *ndc_req;\n+\tint rc = -ENOSPC;\n+\n+\t/* Disable Inbound processing */\n+\trc = nix_inl_nix_ipsec_cfg(inl_dev, false);\n+\tif (rc)\n+\t\tplt_err(\"Failed to disable Inbound IPSec, rc=%d\", rc);\n+\n+\t/* Sync NDC-NIX for LF */\n+\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n+\tif (ndc_req == NULL)\n+\t\treturn rc;\n+\tndc_req->nix_lf_rx_sync = 1;\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tplt_err(\"Error on NDC-NIX-RX LF sync, rc %d\", rc);\n+\n+\t/* Unregister IRQs */\n+\tnix_inl_nix_unregister_irqs(inl_dev);\n+\n+\t/* By default all associated mcam rules are deleted */\n+\treq = mbox_alloc_msg_nix_lf_free(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static int\n+nix_inl_lf_attach(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct msix_offset_rsp *msix_rsp;\n+\tstruct dev *dev = &inl_dev->dev;\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct rsrc_attach_req *req;\n+\tuint64_t nix_blkaddr;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_attach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->modify = true;\n+\t/* Attach 1 NIXLF, SSO HWS and SSO HWGRP */\n+\treq->nixlf = true;\n+\treq->ssow = 1;\n+\treq->sso = 1;\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Get MSIX vector offsets */\n+\tmbox_alloc_msg_msix_offset(mbox);\n+\trc = mbox_process_msg(dev->mbox, (void **)&msix_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tinl_dev->nix_msixoff = msix_rsp->nix_msixoff;\n+\tinl_dev->ssow_msixoff = msix_rsp->ssow_msixoff[0];\n+\tinl_dev->sso_msixoff = msix_rsp->sso_msixoff[0];\n+\n+\tnix_blkaddr = nix_get_blkaddr(dev);\n+\tinl_dev->is_nix1 = (nix_blkaddr == RVU_BLOCK_ADDR_NIX1);\n+\n+\t/* Update base addresses for LF's */\n+\tinl_dev->nix_base = dev->bar2 + (nix_blkaddr << 20);\n+\tinl_dev->ssow_base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20);\n+\tinl_dev->sso_base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20);\n+\treturn 0;\n+}\n+\n+static int\n+nix_inl_lf_detach(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct dev *dev = &inl_dev->dev;\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct rsrc_detach_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_detach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->partial = true;\n+\treq->nixlf = true;\n+\treq->ssow = true;\n+\treq->sso = true;\n+\n+\treturn mbox_process(dev->mbox);\n+}\n+\n+int\n+roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n+{\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct nix_inl_dev *inl_dev;\n+\tstruct idev_cfg *idev;\n+\tint rc;\n+\n+\tpci_dev = roc_inl_dev->pci_dev;\n+\n+\t/* Skip probe if already done */\n+\tidev = idev_get_cfg();\n+\tif (idev == NULL)\n+\t\treturn -ENOTSUP;\n+\n+\tif (idev->nix_inl_dev) {\n+\t\tplt_info(\"Skipping device %s, inline device already probed\",\n+\t\t\t pci_dev->name);\n+\t\treturn -EEXIST;\n+\t}\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct nix_inl_dev) <= ROC_NIX_INL_MEM_SZ);\n+\n+\tinl_dev = (struct nix_inl_dev *)roc_inl_dev->reserved;\n+\tmemset(inl_dev, 0, sizeof(*inl_dev));\n+\n+\tinl_dev->pci_dev = pci_dev;\n+\tinl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi;\n+\tinl_dev->selftest = roc_inl_dev->selftest;\n+\n+\t/* Initialize base device */\n+\trc = dev_init(&inl_dev->dev, pci_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc device\");\n+\t\tgoto error;\n+\t}\n+\n+\t/* Attach LF resources */\n+\trc = nix_inl_lf_attach(inl_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to attach LF resources, rc=%d\", rc);\n+\t\tgoto dev_cleanup;\n+\t}\n+\n+\t/* Setup NIX LF */\n+\trc = nix_inl_nix_setup(inl_dev);\n+\tif (rc)\n+\t\tgoto lf_detach;\n+\n+\t/* Setup SSO LF */\n+\trc = nix_inl_sso_setup(inl_dev);\n+\tif (rc)\n+\t\tgoto nix_release;\n+\n+\tidev->nix_inl_dev = inl_dev;\n+\n+\t/* Perform selftest if asked for */\n+\tif (inl_dev->selftest) {\n+\t\trc = nix_inl_selftest();\n+\t\tif (rc)\n+\t\t\tgoto nix_release;\n+\t}\n+\n+\treturn 0;\n+nix_release:\n+\trc |= nix_inl_nix_release(inl_dev);\n+lf_detach:\n+\trc |= nix_inl_lf_detach(inl_dev);\n+dev_cleanup:\n+\trc |= dev_fini(&inl_dev->dev, pci_dev);\n+error:\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev)\n+{\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct nix_inl_dev *inl_dev;\n+\tstruct idev_cfg *idev;\n+\tint rc;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\tif (!idev->nix_inl_dev ||\n+\t PLT_PTR_DIFF(roc_inl_dev->reserved, idev->nix_inl_dev))\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\tpci_dev = inl_dev->pci_dev;\n+\n+\t/* Release SSO */\n+\trc = nix_inl_sso_release(inl_dev);\n+\n+\t/* Release NIX */\n+\trc |= nix_inl_nix_release(inl_dev);\n+\n+\t/* Detach LF's */\n+\trc |= nix_inl_lf_detach(inl_dev);\n+\n+\t/* Cleanup mbox */\n+\trc |= dev_fini(&inl_dev->dev, pci_dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tidev->nix_inl_dev = NULL;\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex f424009..ab38062 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -54,4 +54,6 @@ void nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev);\n int nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev);\n void nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev);\n \n+uint16_t nix_inl_dev_pffunc_get(void);\n+\n #endif /* _ROC_NIX_INL_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 177db3d..241655b 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -37,6 +37,7 @@\n #define PLT_MEMZONE_NAMESIZE\t RTE_MEMZONE_NAMESIZE\n #define PLT_STD_C11\t\t RTE_STD_C11\n #define PLT_PTR_ADD\t\t RTE_PTR_ADD\n+#define PLT_PTR_DIFF\t\t RTE_PTR_DIFF\n #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID\n #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET\n #define PLT_MIN\t\t\t RTE_MIN\n@@ -77,6 +78,7 @@\n #define plt_cpu_to_be_64 rte_cpu_to_be_64\n #define plt_be_to_cpu_64 rte_be_to_cpu_64\n \n+#define plt_align32pow2\t rte_align32pow2\n #define plt_align32prevpow2 rte_align32prevpow2\n \n #define plt_bitmap\t\t\trte_bitmap\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 5dbb21c..3a35233 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -100,6 +100,9 @@ INTERNAL {\n \troc_nix_get_pf_func;\n \troc_nix_get_vf;\n \troc_nix_get_vwqe_interval;\n+\troc_nix_inl_dev_dump;\n+\troc_nix_inl_dev_fini;\n+\troc_nix_inl_dev_init;\n \troc_nix_is_lbk;\n \troc_nix_is_pf;\n \troc_nix_is_sdp;\n", "prefixes": [ "06/27" ] }