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GET /api/patches/97525/?format=api
{ "id": 97525, "url": "http://patches.dpdk.org/api/patches/97525/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210830031215.557238-2-robinx.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210830031215.557238-2-robinx.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210830031215.557238-2-robinx.zhang@intel.com", "date": "2021-08-30T03:12:13", "name": "[1/3] net/i40e: remove i40evf", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c6329c5b3420f504140c60ddfbb7ce195247c509", "submitter": { "id": 2004, "url": "http://patches.dpdk.org/api/people/2004/?format=api", "name": "Robin Zhang", "email": "robinx.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210830031215.557238-2-robinx.zhang@intel.com/mbox/", "series": [ { "id": 18515, "url": "http://patches.dpdk.org/api/series/18515/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18515", "date": "2021-08-30T03:12:12", "name": "net/i40e: remove i40evf", "version": 1, "mbox": "http://patches.dpdk.org/series/18515/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/97525/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/97525/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C0CE6A0547;\n\tMon, 30 Aug 2021 05:25:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 14E7B410F3;\n\tMon, 30 Aug 2021 05:25:49 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id EF127410EA\n for <dev@dpdk.org>; Mon, 30 Aug 2021 05:25:46 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Aug 2021 20:25:42 -0700", "from unknown (HELO intel-npg-odc-srv03.cd.intel.com)\n ([10.240.178.145])\n by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Aug 2021 20:25:38 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10091\"; a=\"240436251\"", "E=Sophos;i=\"5.84,362,1620716400\"; d=\"scan'208\";a=\"240436251\"", "E=Sophos;i=\"5.84,362,1620716400\"; d=\"scan'208\";a=\"530045258\"" ], "From": "Robin Zhang <robinx.zhang@intel.com>", "To": "dev@dpdk.org", "Cc": "beilei.xing@intel.com, anatoly.burakov@intel.com, jingjing.wu@intel.com,\n mdr@ashroe.eu, qi.z.zhang@intel.com, junfeng.guo@intel.com,\n stevex.yang@intel.com, Robin Zhang <robinx.zhang@intel.com>", "Date": "Mon, 30 Aug 2021 03:12:13 +0000", "Message-Id": "<20210830031215.557238-2-robinx.zhang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210830031215.557238-1-robinx.zhang@intel.com>", "References": "<20210830031215.557238-1-robinx.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 1/3] net/i40e: remove i40evf", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The default VF driver for Intel 700 Series Ethernet Controller already\nswitch to iavf in DPDK 21.05. And i40evf is no need to maintain now,\nso remove i40evf related code.\n\nSigned-off-by: Robin Zhang <robinx.zhang@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.h | 1 -\n drivers/net/i40e/i40e_ethdev_vf.c | 3015 -----------------------------\n drivers/net/i40e/meson.build | 1 -\n drivers/net/i40e/rte_pmd_i40e.c | 9 +-\n 4 files changed, 3 insertions(+), 3023 deletions(-)\n delete mode 100644 drivers/net/i40e/i40e_ethdev_vf.c", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex cd6deabd60..9df425612e 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -1461,7 +1461,6 @@ int i40e_add_macvlan_filters(struct i40e_vsi *vsi,\n \t\t\t int total);\n bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv);\n bool is_i40e_supported(struct rte_eth_dev *dev);\n-bool is_i40evf_supported(struct rte_eth_dev *dev);\n void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw,\n \t\t\t\t\t uint8_t enable);\n int i40e_validate_input_set(enum i40e_filter_pctype pctype,\ndiff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\ndeleted file mode 100644\nindex 0cfe13b7b2..0000000000\n--- a/drivers/net/i40e/i40e_ethdev_vf.c\n+++ /dev/null\n@@ -1,3015 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2010-2016 Intel Corporation\n- */\n-\n-#include <sys/queue.h>\n-#include <stdio.h>\n-#include <errno.h>\n-#include <stdint.h>\n-#include <string.h>\n-#include <unistd.h>\n-#include <stdarg.h>\n-#include <inttypes.h>\n-#include <rte_byteorder.h>\n-#include <rte_common.h>\n-#include <rte_cycles.h>\n-\n-#include <rte_interrupts.h>\n-#include <rte_log.h>\n-#include <rte_debug.h>\n-#include <rte_pci.h>\n-#include <rte_bus_pci.h>\n-#include <rte_atomic.h>\n-#include <rte_branch_prediction.h>\n-#include <rte_memory.h>\n-#include <rte_eal.h>\n-#include <rte_alarm.h>\n-#include <rte_ether.h>\n-#include <ethdev_driver.h>\n-#include <ethdev_pci.h>\n-#include <rte_malloc.h>\n-#include <rte_dev.h>\n-\n-#include \"i40e_logs.h\"\n-#include \"base/i40e_prototype.h\"\n-#include \"base/i40e_adminq_cmd.h\"\n-#include \"base/i40e_type.h\"\n-\n-#include \"i40e_rxtx.h\"\n-#include \"i40e_ethdev.h\"\n-#include \"i40e_pf.h\"\n-\n-/* busy wait delay in msec */\n-#define I40EVF_BUSY_WAIT_DELAY 10\n-#define I40EVF_BUSY_WAIT_COUNT 50\n-#define MAX_RESET_WAIT_CNT 20\n-\n-#define I40EVF_ALARM_INTERVAL 50000 /* us */\n-\n-struct i40evf_arq_msg_info {\n-\tenum virtchnl_ops ops;\n-\tenum i40e_status_code result;\n-\tuint16_t buf_len;\n-\tuint16_t msg_len;\n-\tuint8_t *msg;\n-};\n-\n-struct vf_cmd_info {\n-\tenum virtchnl_ops ops;\n-\tuint8_t *in_args;\n-\tuint32_t in_args_size;\n-\tuint8_t *out_buffer;\n-\t/* Input & output type. pass in buffer size and pass out\n-\t * actual return result\n-\t */\n-\tuint32_t out_size;\n-};\n-\n-enum i40evf_aq_result {\n-\tI40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */\n-\tI40EVF_MSG_NON, /* Read nothing from admin queue */\n-\tI40EVF_MSG_SYS, /* Read system msg from admin queue */\n-\tI40EVF_MSG_CMD, /* Read async command result */\n-};\n-\n-static int i40evf_dev_configure(struct rte_eth_dev *dev);\n-static int i40evf_dev_start(struct rte_eth_dev *dev);\n-static int i40evf_dev_stop(struct rte_eth_dev *dev);\n-static int i40evf_dev_info_get(struct rte_eth_dev *dev,\n-\t\t\t struct rte_eth_dev_info *dev_info);\n-static int i40evf_dev_link_update(struct rte_eth_dev *dev,\n-\t\t\t\t int wait_to_complete);\n-static int i40evf_dev_stats_get(struct rte_eth_dev *dev,\n-\t\t\t\tstruct rte_eth_stats *stats);\n-static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_xstat *xstats, unsigned n);\n-static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_xstat_name *xstats_names,\n-\t\t\t\t unsigned limit);\n-static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);\n-static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,\n-\t\t\t\t uint16_t vlan_id, int on);\n-static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);\n-static int i40evf_dev_close(struct rte_eth_dev *dev);\n-static int i40evf_dev_reset(struct rte_eth_dev *dev);\n-static int i40evf_check_vf_reset_done(struct rte_eth_dev *dev);\n-static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);\n-static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);\n-static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);\n-static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);\n-static int i40evf_init_vlan(struct rte_eth_dev *dev);\n-static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,\n-\t\t\t\t uint16_t rx_queue_id);\n-static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,\n-\t\t\t\t uint16_t rx_queue_id);\n-static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,\n-\t\t\t\t uint16_t tx_queue_id);\n-static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,\n-\t\t\t\t uint16_t tx_queue_id);\n-static int i40evf_add_del_eth_addr(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_ether_addr *addr,\n-\t\t\t\t bool add, uint8_t type);\n-static int i40evf_add_mac_addr(struct rte_eth_dev *dev,\n-\t\t\t struct rte_ether_addr *addr,\n-\t\t\t uint32_t index,\n-\t\t\t uint32_t pool);\n-static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);\n-static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\tuint16_t reta_size);\n-static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\tuint16_t reta_size);\n-static int i40evf_config_rss(struct i40e_vf *vf);\n-static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_rss_conf *rss_conf);\n-static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n-\t\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n-static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n-static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,\n-\t\t\t\t\tstruct rte_ether_addr *mac_addr);\n-static int\n-i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);\n-static int\n-i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);\n-static void i40evf_handle_pf_event(struct rte_eth_dev *dev,\n-\t\t\t\t uint8_t *msg,\n-\t\t\t\t uint16_t msglen);\n-\n-static int\n-i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_ether_addr *mc_addr_set,\n-\t\t\tuint32_t nb_mc_addr, bool add);\n-static int\n-i40evf_set_mc_addr_list(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_ether_addr *mc_addr_set,\n-\t\t\tuint32_t nb_mc_addr);\n-static void\n-i40evf_dev_alarm_handler(void *param);\n-\n-/* Default hash key buffer for RSS */\n-static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];\n-\n-struct rte_i40evf_xstats_name_off {\n-\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n-\tunsigned offset;\n-};\n-\n-static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {\n-\t{\"rx_bytes\", offsetof(struct i40e_eth_stats, rx_bytes)},\n-\t{\"rx_unicast_packets\", offsetof(struct i40e_eth_stats, rx_unicast)},\n-\t{\"rx_multicast_packets\", offsetof(struct i40e_eth_stats, rx_multicast)},\n-\t{\"rx_broadcast_packets\", offsetof(struct i40e_eth_stats, rx_broadcast)},\n-\t{\"rx_dropped_packets\", offsetof(struct i40e_eth_stats, rx_discards)},\n-\t{\"rx_unknown_protocol_packets\", offsetof(struct i40e_eth_stats,\n-\t\trx_unknown_protocol)},\n-\t{\"tx_bytes\", offsetof(struct i40e_eth_stats, tx_bytes)},\n-\t{\"tx_unicast_packets\", offsetof(struct i40e_eth_stats, tx_unicast)},\n-\t{\"tx_multicast_packets\", offsetof(struct i40e_eth_stats, tx_multicast)},\n-\t{\"tx_broadcast_packets\", offsetof(struct i40e_eth_stats, tx_broadcast)},\n-\t{\"tx_dropped_packets\", offsetof(struct i40e_eth_stats, tx_discards)},\n-\t{\"tx_error_packets\", offsetof(struct i40e_eth_stats, tx_errors)},\n-};\n-\n-#define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \\\n-\t\tsizeof(rte_i40evf_stats_strings[0]))\n-\n-static const struct eth_dev_ops i40evf_eth_dev_ops = {\n-\t.dev_configure = i40evf_dev_configure,\n-\t.dev_start = i40evf_dev_start,\n-\t.dev_stop = i40evf_dev_stop,\n-\t.promiscuous_enable = i40evf_dev_promiscuous_enable,\n-\t.promiscuous_disable = i40evf_dev_promiscuous_disable,\n-\t.allmulticast_enable = i40evf_dev_allmulticast_enable,\n-\t.allmulticast_disable = i40evf_dev_allmulticast_disable,\n-\t.link_update = i40evf_dev_link_update,\n-\t.stats_get = i40evf_dev_stats_get,\n-\t.stats_reset = i40evf_dev_xstats_reset,\n-\t.xstats_get = i40evf_dev_xstats_get,\n-\t.xstats_get_names = i40evf_dev_xstats_get_names,\n-\t.xstats_reset = i40evf_dev_xstats_reset,\n-\t.dev_close = i40evf_dev_close,\n-\t.dev_reset\t = i40evf_dev_reset,\n-\t.dev_infos_get = i40evf_dev_info_get,\n-\t.dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,\n-\t.vlan_filter_set = i40evf_vlan_filter_set,\n-\t.vlan_offload_set = i40evf_vlan_offload_set,\n-\t.rx_queue_start = i40evf_dev_rx_queue_start,\n-\t.rx_queue_stop = i40evf_dev_rx_queue_stop,\n-\t.tx_queue_start = i40evf_dev_tx_queue_start,\n-\t.tx_queue_stop = i40evf_dev_tx_queue_stop,\n-\t.rx_queue_setup = i40e_dev_rx_queue_setup,\n-\t.rx_queue_release = i40e_dev_rx_queue_release,\n-\t.rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,\n-\t.rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,\n-\t.tx_queue_setup = i40e_dev_tx_queue_setup,\n-\t.tx_queue_release = i40e_dev_tx_queue_release,\n-\t.rxq_info_get = i40e_rxq_info_get,\n-\t.txq_info_get = i40e_txq_info_get,\n-\t.mac_addr_add\t = i40evf_add_mac_addr,\n-\t.mac_addr_remove = i40evf_del_mac_addr,\n-\t.set_mc_addr_list = i40evf_set_mc_addr_list,\n-\t.reta_update = i40evf_dev_rss_reta_update,\n-\t.reta_query = i40evf_dev_rss_reta_query,\n-\t.rss_hash_update = i40evf_dev_rss_hash_update,\n-\t.rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,\n-\t.mtu_set = i40evf_dev_mtu_set,\n-\t.mac_addr_set = i40evf_set_default_mac_addr,\n-\t.tx_done_cleanup = i40e_tx_done_cleanup,\n-\t.get_monitor_addr = i40e_get_monitor_addr\n-};\n-\n-/*\n- * Read data in admin queue to get msg from pf driver\n- */\n-static enum i40evf_aq_result\n-i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_arq_event_info event;\n-\tenum virtchnl_ops opcode;\n-\tenum i40e_status_code retval;\n-\tint ret;\n-\tenum i40evf_aq_result result = I40EVF_MSG_NON;\n-\n-\tevent.buf_len = data->buf_len;\n-\tevent.msg_buf = data->msg;\n-\tret = i40e_clean_arq_element(hw, &event, NULL);\n-\t/* Can't read any msg from adminQ */\n-\tif (ret) {\n-\t\tif (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)\n-\t\t\tresult = I40EVF_MSG_ERR;\n-\t\treturn result;\n-\t}\n-\n-\topcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);\n-\tretval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);\n-\t/* pf sys event */\n-\tif (opcode == VIRTCHNL_OP_EVENT) {\n-\t\tstruct virtchnl_pf_event *vpe =\n-\t\t\t(struct virtchnl_pf_event *)event.msg_buf;\n-\n-\t\tresult = I40EVF_MSG_SYS;\n-\t\tswitch (vpe->event) {\n-\t\tcase VIRTCHNL_EVENT_LINK_CHANGE:\n-\t\t\tvf->link_up =\n-\t\t\t\tvpe->event_data.link_event.link_status;\n-\t\t\tvf->link_speed =\n-\t\t\t\tvpe->event_data.link_event.link_speed;\n-\t\t\tvf->pend_msg |= PFMSG_LINK_CHANGE;\n-\t\t\tPMD_DRV_LOG(INFO, \"Link status update:%s\",\n-\t\t\t\t vf->link_up ? \"up\" : \"down\");\n-\t\t\tbreak;\n-\t\tcase VIRTCHNL_EVENT_RESET_IMPENDING:\n-\t\t\tvf->vf_reset = true;\n-\t\t\tvf->pend_msg |= PFMSG_RESET_IMPENDING;\n-\t\t\tPMD_DRV_LOG(INFO, \"VF is resetting\");\n-\t\t\tbreak;\n-\t\tcase VIRTCHNL_EVENT_PF_DRIVER_CLOSE:\n-\t\t\tvf->dev_closed = true;\n-\t\t\tvf->pend_msg |= PFMSG_DRIVER_CLOSE;\n-\t\t\tPMD_DRV_LOG(INFO, \"PF driver closed\");\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tPMD_DRV_LOG(ERR, \"%s: Unknown event %d from pf\",\n-\t\t\t\t __func__, vpe->event);\n-\t\t}\n-\t} else {\n-\t\t/* async reply msg on command issued by vf previously */\n-\t\tresult = I40EVF_MSG_CMD;\n-\t\t/* Actual data length read from PF */\n-\t\tdata->msg_len = event.msg_len;\n-\t}\n-\n-\tdata->result = retval;\n-\tdata->ops = opcode;\n-\n-\treturn result;\n-}\n-\n-/**\n- * clear current command. Only call in case execute\n- * _atomic_set_cmd successfully.\n- */\n-static inline void\n-_clear_cmd(struct i40e_vf *vf)\n-{\n-\trte_wmb();\n-\tvf->pend_cmd = VIRTCHNL_OP_UNKNOWN;\n-}\n-\n-/*\n- * Check there is pending cmd in execution. If none, set new command.\n- */\n-static inline int\n-_atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)\n-{\n-\tint ret = rte_atomic32_cmpset(&vf->pend_cmd,\n-\t\t\tVIRTCHNL_OP_UNKNOWN, ops);\n-\n-\tif (!ret)\n-\t\tPMD_DRV_LOG(ERR, \"There is incomplete cmd %d\", vf->pend_cmd);\n-\n-\treturn !ret;\n-}\n-\n-#define MAX_TRY_TIMES 200\n-#define ASQ_DELAY_MS 10\n-\n-static int\n-_i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40evf_arq_msg_info info;\n-\tenum i40evf_aq_result ret;\n-\tint err, i = 0;\n-\n-\tif (_atomic_set_cmd(vf, args->ops))\n-\t\treturn -1;\n-\n-\tinfo.msg = args->out_buffer;\n-\tinfo.buf_len = args->out_size;\n-\tinfo.ops = VIRTCHNL_OP_UNKNOWN;\n-\tinfo.result = I40E_SUCCESS;\n-\n-\terr = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,\n-\t\t args->in_args, args->in_args_size, NULL);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"fail to send cmd %d\", args->ops);\n-\t\t_clear_cmd(vf);\n-\t\treturn err;\n-\t}\n-\n-\tswitch (args->ops) {\n-\tcase VIRTCHNL_OP_RESET_VF:\n-\t\t/*no need to process in this function */\n-\t\terr = 0;\n-\t\tbreak;\n-\tcase VIRTCHNL_OP_VERSION:\n-\tcase VIRTCHNL_OP_GET_VF_RESOURCES:\n-\t\t/* for init adminq commands, need to poll the response */\n-\t\terr = -1;\n-\t\tdo {\n-\t\t\tret = i40evf_read_pfmsg(dev, &info);\n-\t\t\tvf->cmd_retval = info.result;\n-\t\t\tif (ret == I40EVF_MSG_CMD) {\n-\t\t\t\terr = 0;\n-\t\t\t\tbreak;\n-\t\t\t} else if (ret == I40EVF_MSG_ERR)\n-\t\t\t\tbreak;\n-\t\t\trte_delay_ms(ASQ_DELAY_MS);\n-\t\t\t/* If don't read msg or read sys event, continue */\n-\t\t} while (i++ < MAX_TRY_TIMES);\n-\t\t_clear_cmd(vf);\n-\t\tbreak;\n-\tcase VIRTCHNL_OP_REQUEST_QUEUES:\n-\t\t/**\n-\t\t * ignore async reply, only wait for system message,\n-\t\t * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,\n-\t\t * if not, means request queues failed.\n-\t\t */\n-\t\terr = -1;\n-\t\tdo {\n-\t\t\tret = i40evf_read_pfmsg(dev, &info);\n-\t\t\tvf->cmd_retval = info.result;\n-\t\t\tif (ret == I40EVF_MSG_SYS && vf->vf_reset) {\n-\t\t\t\terr = 0;\n-\t\t\t\tbreak;\n-\t\t\t} else if (ret == I40EVF_MSG_ERR ||\n-\t\t\t\t\t ret == I40EVF_MSG_CMD) {\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\trte_delay_ms(ASQ_DELAY_MS);\n-\t\t\t/* If don't read msg or read sys event, continue */\n-\t\t} while (i++ < MAX_TRY_TIMES);\n-\t\t_clear_cmd(vf);\n-\t\tbreak;\n-\n-\tdefault:\n-\t\t/* for other adminq in running time, waiting the cmd done flag */\n-\t\terr = -1;\n-\t\tdo {\n-\t\t\tif (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {\n-\t\t\t\terr = 0;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\trte_delay_ms(ASQ_DELAY_MS);\n-\t\t\t/* If don't read msg or read sys event, continue */\n-\t\t} while (i++ < MAX_TRY_TIMES);\n-\t\t/* If there's no response is received, clear command */\n-\t\tif (i >= MAX_TRY_TIMES) {\n-\t\t\tPMD_DRV_LOG(WARNING, \"No response for %d\", args->ops);\n-\t\t\t_clear_cmd(vf);\n-\t\t}\n-\t\tbreak;\n-\t}\n-\n-\treturn err | vf->cmd_retval;\n-}\n-\n-static int\n-i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tint err;\n-\n-\twhile (!rte_spinlock_trylock(&vf->cmd_send_lock))\n-\t\trte_delay_us_sleep(50);\n-\terr = _i40evf_execute_vf_cmd(dev, args);\n-\trte_spinlock_unlock(&vf->cmd_send_lock);\n-\treturn err;\n-}\n-\n-/*\n- * Check API version with sync wait until version read or fail from admin queue\n- */\n-static int\n-i40evf_check_api_version(struct rte_eth_dev *dev)\n-{\n-\tstruct virtchnl_version_info version, *pver;\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\tversion.major = VIRTCHNL_VERSION_MAJOR;\n-\tversion.minor = VIRTCHNL_VERSION_MINOR;\n-\n-\targs.ops = VIRTCHNL_OP_VERSION;\n-\targs.in_args = (uint8_t *)&version;\n-\targs.in_args_size = sizeof(version);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err) {\n-\t\tPMD_INIT_LOG(ERR, \"fail to execute command OP_VERSION\");\n-\t\treturn err;\n-\t}\n-\n-\tpver = (struct virtchnl_version_info *)args.out_buffer;\n-\tvf->version_major = pver->major;\n-\tvf->version_minor = pver->minor;\n-\tif ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&\n-\t\t(vf->version_minor <= VIRTCHNL_VERSION_MINOR))\n-\t\tPMD_DRV_LOG(INFO, \"Peer is Linux PF host\");\n-\telse {\n-\t\tPMD_INIT_LOG(ERR, \"PF/VF API version mismatch:(%u.%u)-(%u.%u)\",\n-\t\t\t\t\tvf->version_major, vf->version_minor,\n-\t\t\t\t\t\tVIRTCHNL_VERSION_MAJOR,\n-\t\t\t\t\t\tVIRTCHNL_VERSION_MINOR);\n-\t\treturn -1;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_get_vf_resource(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\tuint32_t caps, len;\n-\n-\targs.ops = VIRTCHNL_OP_GET_VF_RESOURCES;\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\tif (PF_IS_V11(vf)) {\n-\t\tcaps = VIRTCHNL_VF_OFFLOAD_L2 |\n-\t\t VIRTCHNL_VF_OFFLOAD_RSS_AQ |\n-\t\t VIRTCHNL_VF_OFFLOAD_RSS_REG |\n-\t\t VIRTCHNL_VF_OFFLOAD_VLAN |\n-\t\t VIRTCHNL_VF_OFFLOAD_RX_POLLING |\n-\t\t VIRTCHNL_VF_CAP_ADV_LINK_SPEED;\n-\t\targs.in_args = (uint8_t *)∩︀\n-\t\targs.in_args_size = sizeof(caps);\n-\t} else {\n-\t\targs.in_args = NULL;\n-\t\targs.in_args_size = 0;\n-\t}\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_GET_VF_RESOURCE\");\n-\t\treturn err;\n-\t}\n-\n-\tlen = sizeof(struct virtchnl_vf_resource) +\n-\t\tI40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);\n-\n-\trte_memcpy(vf->vf_res, args.out_buffer,\n-\t\t\tRTE_MIN(args.out_size, len));\n-\ti40e_vf_parse_hw_config(hw, vf->vf_res);\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_config_promisc(struct rte_eth_dev *dev,\n-\t\t bool enable_unicast,\n-\t\t bool enable_multicast)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\tstruct virtchnl_promisc_info promisc;\n-\n-\tpromisc.flags = 0;\n-\tpromisc.vsi_id = vf->vsi_res->vsi_id;\n-\n-\tif (enable_unicast)\n-\t\tpromisc.flags |= FLAG_VF_UNICAST_PROMISC;\n-\n-\tif (enable_multicast)\n-\t\tpromisc.flags |= FLAG_VF_MULTICAST_PROMISC;\n-\n-\targs.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;\n-\targs.in_args = (uint8_t *)&promisc;\n-\targs.in_args_size = sizeof(promisc);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command \"\n-\t\t\t \"CONFIG_PROMISCUOUS_MODE\");\n-\n-\t\tif (err == I40E_NOT_SUPPORTED)\n-\t\t\treturn -ENOTSUP;\n-\n-\t\treturn -EAGAIN;\n-\t}\n-\n-\tvf->promisc_unicast_enabled = enable_unicast;\n-\tvf->promisc_multicast_enabled = enable_multicast;\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_enable_vlan_strip(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct vf_cmd_info args;\n-\tint ret;\n-\n-\tmemset(&args, 0, sizeof(args));\n-\targs.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;\n-\targs.in_args = NULL;\n-\targs.in_args_size = 0;\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\tret = i40evf_execute_vf_cmd(dev, &args);\n-\tif (ret)\n-\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of \"\n-\t\t\t \"VIRTCHNL_OP_ENABLE_VLAN_STRIPPING\");\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_disable_vlan_strip(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct vf_cmd_info args;\n-\tint ret;\n-\n-\tmemset(&args, 0, sizeof(args));\n-\targs.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;\n-\targs.in_args = NULL;\n-\targs.in_args_size = 0;\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\tret = i40evf_execute_vf_cmd(dev, &args);\n-\tif (ret)\n-\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of \"\n-\t\t\t \"VIRTCHNL_OP_DISABLE_VLAN_STRIPPING\");\n-\n-\treturn ret;\n-}\n-\n-static void\n-i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,\n-\t\t\t\t uint16_t vsi_id,\n-\t\t\t\t uint16_t queue_id,\n-\t\t\t\t uint16_t nb_txq,\n-\t\t\t\t struct i40e_tx_queue *txq)\n-{\n-\ttxq_info->vsi_id = vsi_id;\n-\ttxq_info->queue_id = queue_id;\n-\tif (queue_id < nb_txq && txq) {\n-\t\ttxq_info->ring_len = txq->nb_tx_desc;\n-\t\ttxq_info->dma_ring_addr = txq->tx_ring_phys_addr;\n-\t}\n-}\n-\n-static void\n-i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,\n-\t\t\t\t uint16_t vsi_id,\n-\t\t\t\t uint16_t queue_id,\n-\t\t\t\t uint16_t nb_rxq,\n-\t\t\t\t uint32_t max_pkt_size,\n-\t\t\t\t struct i40e_rx_queue *rxq)\n-{\n-\trxq_info->vsi_id = vsi_id;\n-\trxq_info->queue_id = queue_id;\n-\trxq_info->max_pkt_size = max_pkt_size;\n-\tif (queue_id < nb_rxq && rxq) {\n-\t\trxq_info->ring_len = rxq->nb_rx_desc;\n-\t\trxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;\n-\t\trxq_info->databuffer_size =\n-\t\t\t(rte_pktmbuf_data_room_size(rxq->mp) -\n-\t\t\t\tRTE_PKTMBUF_HEADROOM);\n-\t}\n-}\n-\n-static int\n-i40evf_configure_vsi_queues(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_rx_queue **rxq =\n-\t\t(struct i40e_rx_queue **)dev->data->rx_queues;\n-\tstruct i40e_tx_queue **txq =\n-\t\t(struct i40e_tx_queue **)dev->data->tx_queues;\n-\tstruct virtchnl_vsi_queue_config_info *vc_vqci;\n-\tstruct virtchnl_queue_pair_info *vc_qpi;\n-\tstruct vf_cmd_info args;\n-\tuint16_t i, nb_qp = vf->num_queue_pairs;\n-\tconst uint32_t size =\n-\t\tI40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);\n-\tuint8_t buff[size];\n-\tint ret;\n-\n-\tmemset(buff, 0, sizeof(buff));\n-\tvc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;\n-\tvc_vqci->vsi_id = vf->vsi_res->vsi_id;\n-\tvc_vqci->num_queue_pairs = nb_qp;\n-\n-\tfor (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {\n-\t\ti40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,\n-\t\t\tvc_vqci->vsi_id, i, dev->data->nb_tx_queues,\n-\t\t\ttxq ? txq[i] : NULL);\n-\t\ti40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,\n-\t\t\tvc_vqci->vsi_id, i, dev->data->nb_rx_queues,\n-\t\t\tvf->max_pkt_len, rxq ? rxq[i] : NULL);\n-\t}\n-\tmemset(&args, 0, sizeof(args));\n-\targs.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;\n-\targs.in_args = (uint8_t *)vc_vqci;\n-\targs.in_args_size = size;\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\tret = i40evf_execute_vf_cmd(dev, &args);\n-\tif (ret)\n-\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of \"\n-\t\t\t\"VIRTCHNL_OP_CONFIG_VSI_QUEUES\");\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_config_irq_map(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct vf_cmd_info args;\n-\tuint8_t *cmd_buffer = NULL;\n-\tstruct virtchnl_irq_map_info *map_info;\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\tuint32_t vec, cmd_buffer_size, max_vectors, nb_msix, msix_base, i;\n-\tuint16_t rxq_map[vf->vf_res->max_vectors];\n-\tint err;\n-\n-\tmemset(rxq_map, 0, sizeof(rxq_map));\n-\tif (dev->data->dev_conf.intr_conf.rxq != 0 &&\n-\t\trte_intr_allow_others(intr_handle)) {\n-\t\tmsix_base = I40E_RX_VEC_START;\n-\t\t/* For interrupt mode, available vector id is from 1. */\n-\t\tmax_vectors = vf->vf_res->max_vectors - 1;\n-\t\tnb_msix = RTE_MIN(max_vectors, intr_handle->nb_efd);\n-\n-\t\tvec = msix_base;\n-\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\t\trxq_map[vec] |= 1 << i;\n-\t\t\tintr_handle->intr_vec[i] = vec++;\n-\t\t\tif (vec >= vf->vf_res->max_vectors)\n-\t\t\t\tvec = msix_base;\n-\t\t}\n-\t} else {\n-\t\tmsix_base = I40E_MISC_VEC_ID;\n-\t\tnb_msix = 1;\n-\n-\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\t\trxq_map[msix_base] |= 1 << i;\n-\t\t\tif (rte_intr_dp_is_en(intr_handle))\n-\t\t\t\tintr_handle->intr_vec[i] = msix_base;\n-\t\t}\n-\t}\n-\n-\tcmd_buffer_size = sizeof(struct virtchnl_irq_map_info) +\n-\t\t\tsizeof(struct virtchnl_vector_map) * nb_msix;\n-\tcmd_buffer = rte_zmalloc(\"i40e\", cmd_buffer_size, 0);\n-\tif (!cmd_buffer) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory\");\n-\t\treturn I40E_ERR_NO_MEMORY;\n-\t}\n-\n-\tmap_info = (struct virtchnl_irq_map_info *)cmd_buffer;\n-\tmap_info->num_vectors = nb_msix;\n-\tfor (i = 0; i < nb_msix; i++) {\n-\t\tmap_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;\n-\t\tmap_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;\n-\t\tmap_info->vecmap[i].vector_id = msix_base + i;\n-\t\tmap_info->vecmap[i].txq_map = 0;\n-\t\tmap_info->vecmap[i].rxq_map = rxq_map[msix_base + i];\n-\t}\n-\n-\targs.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;\n-\targs.in_args = (u8 *)cmd_buffer;\n-\targs.in_args_size = cmd_buffer_size;\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_ENABLE_QUEUES\");\n-\n-\trte_free(cmd_buffer);\n-\n-\treturn err;\n-}\n-\n-static int\n-i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,\n-\t\t\t\tbool on)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct virtchnl_queue_select queue_select;\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\tmemset(&queue_select, 0, sizeof(queue_select));\n-\tqueue_select.vsi_id = vf->vsi_res->vsi_id;\n-\n-\tif (isrx)\n-\t\tqueue_select.rx_queues |= 1 << qid;\n-\telse\n-\t\tqueue_select.tx_queues |= 1 << qid;\n-\n-\tif (on)\n-\t\targs.ops = VIRTCHNL_OP_ENABLE_QUEUES;\n-\telse\n-\t\targs.ops = VIRTCHNL_OP_DISABLE_QUEUES;\n-\targs.in_args = (u8 *)&queue_select;\n-\targs.in_args_size = sizeof(queue_select);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"fail to switch %s %u %s\",\n-\t\t\t isrx ? \"RX\" : \"TX\", qid, on ? \"on\" : \"off\");\n-\n-\treturn err;\n-}\n-\n-static int\n-i40evf_start_queues(struct rte_eth_dev *dev)\n-{\n-\tstruct rte_eth_dev_data *dev_data = dev->data;\n-\tint i;\n-\tstruct i40e_rx_queue *rxq;\n-\tstruct i40e_tx_queue *txq;\n-\n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\trxq = dev_data->rx_queues[i];\n-\t\tif (rxq->rx_deferred_start)\n-\t\t\tcontinue;\n-\t\tif (i40evf_dev_rx_queue_start(dev, i) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Fail to start queue %u\", i);\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n-\t\ttxq = dev_data->tx_queues[i];\n-\t\tif (txq->tx_deferred_start)\n-\t\t\tcontinue;\n-\t\tif (i40evf_dev_tx_queue_start(dev, i) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Fail to start queue %u\", i);\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_stop_queues(struct rte_eth_dev *dev)\n-{\n-\tint i;\n-\n-\t/* Stop TX queues first */\n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n-\t\tif (i40evf_dev_tx_queue_stop(dev, i) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Fail to stop queue %u\", i);\n-\t\t}\n-\t}\n-\n-\t/* Then stop RX queues */\n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\tif (i40evf_dev_rx_queue_stop(dev, i) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Fail to stop queue %u\", i);\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_add_del_eth_addr(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_ether_addr *addr,\n-\t\t\tbool add, uint8_t type)\n-{\n-\tstruct virtchnl_ether_addr_list *list;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tuint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \\\n-\t\t\tsizeof(struct virtchnl_ether_addr)];\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\n-\tlist = (struct virtchnl_ether_addr_list *)cmd_buffer;\n-\tlist->vsi_id = vf->vsi_res->vsi_id;\n-\tlist->num_elements = 1;\n-\tlist->list[0].type = type;\n-\trte_memcpy(list->list[0].addr, addr->addr_bytes,\n-\t\t\t\t\tsizeof(addr->addr_bytes));\n-\n-\targs.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;\n-\targs.in_args = cmd_buffer;\n-\targs.in_args_size = sizeof(cmd_buffer);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command %s\",\n-\t\t\t add ? \"OP_ADD_ETH_ADDR\" : \"OP_DEL_ETH_ADDR\");\n-\treturn err;\n-}\n-\n-static int\n-i40evf_add_mac_addr(struct rte_eth_dev *dev,\n-\t\t struct rte_ether_addr *addr,\n-\t\t __rte_unused uint32_t index,\n-\t\t __rte_unused uint32_t pool)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tint err;\n-\n-\tif (rte_is_zero_ether_addr(addr)) {\n-\t\tPMD_DRV_LOG(ERR, \"Invalid mac:%x:%x:%x:%x:%x:%x\",\n-\t\t\t addr->addr_bytes[0], addr->addr_bytes[1],\n-\t\t\t addr->addr_bytes[2], addr->addr_bytes[3],\n-\t\t\t addr->addr_bytes[4], addr->addr_bytes[5]);\n-\t\treturn I40E_ERR_INVALID_MAC_ADDR;\n-\t}\n-\n-\terr = i40evf_add_del_eth_addr(dev, addr, TRUE, VIRTCHNL_ETHER_ADDR_EXTRA);\n-\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"fail to add MAC address\");\n-\telse\n-\t\tvf->vsi.mac_num++;\n-\n-\treturn err;\n-}\n-\n-static void\n-i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct rte_eth_dev_data *data = dev->data;\n-\tstruct rte_ether_addr *addr;\n-\tint err;\n-\n-\taddr = &data->mac_addrs[index];\n-\n-\terr = i40evf_add_del_eth_addr(dev, addr, FALSE, VIRTCHNL_ETHER_ADDR_EXTRA);\n-\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"fail to delete MAC address\");\n-\telse\n-\t\tvf->vsi.mac_num--;\n-\n-\treturn;\n-}\n-\n-static int\n-i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct virtchnl_queue_select q_stats;\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\n-\tmemset(&q_stats, 0, sizeof(q_stats));\n-\tq_stats.vsi_id = vf->vsi_res->vsi_id;\n-\targs.ops = VIRTCHNL_OP_GET_STATS;\n-\targs.in_args = (u8 *)&q_stats;\n-\targs.in_args_size = sizeof(q_stats);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_GET_STATS\");\n-\t\t*pstats = NULL;\n-\t\treturn err;\n-\t}\n-\t*pstats = (struct i40e_eth_stats *)args.out_buffer;\n-\treturn 0;\n-}\n-\n-static void\n-i40evf_stat_update_48(uint64_t *offset,\n-\t\t uint64_t *stat)\n-{\n-\tif (*stat >= *offset)\n-\t\t*stat = *stat - *offset;\n-\telse\n-\t\t*stat = (uint64_t)((*stat +\n-\t\t\t((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);\n-\n-\t*stat &= I40E_48_BIT_MASK;\n-}\n-\n-static void\n-i40evf_stat_update_32(uint64_t *offset,\n-\t\t uint64_t *stat)\n-{\n-\tif (*stat >= *offset)\n-\t\t*stat = (uint64_t)(*stat - *offset);\n-\telse\n-\t\t*stat = (uint64_t)((*stat +\n-\t\t\t((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);\n-}\n-\n-static void\n-i40evf_update_stats(struct i40e_vsi *vsi,\n-\t\t\t\t\tstruct i40e_eth_stats *nes)\n-{\n-\tstruct i40e_eth_stats *oes = &vsi->eth_stats_offset;\n-\n-\ti40evf_stat_update_48(&oes->rx_bytes,\n-\t\t\t &nes->rx_bytes);\n-\ti40evf_stat_update_48(&oes->rx_unicast,\n-\t\t\t &nes->rx_unicast);\n-\ti40evf_stat_update_48(&oes->rx_multicast,\n-\t\t\t &nes->rx_multicast);\n-\ti40evf_stat_update_48(&oes->rx_broadcast,\n-\t\t\t &nes->rx_broadcast);\n-\ti40evf_stat_update_32(&oes->rx_discards,\n-\t\t\t\t&nes->rx_discards);\n-\ti40evf_stat_update_32(&oes->rx_unknown_protocol,\n-\t\t\t &nes->rx_unknown_protocol);\n-\ti40evf_stat_update_48(&oes->tx_bytes,\n-\t\t\t &nes->tx_bytes);\n-\ti40evf_stat_update_48(&oes->tx_unicast,\n-\t\t\t &nes->tx_unicast);\n-\ti40evf_stat_update_48(&oes->tx_multicast,\n-\t\t\t &nes->tx_multicast);\n-\ti40evf_stat_update_48(&oes->tx_broadcast,\n-\t\t\t &nes->tx_broadcast);\n-\ti40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);\n-\ti40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);\n-}\n-\n-static int\n-i40evf_dev_xstats_reset(struct rte_eth_dev *dev)\n-{\n-\tint ret;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_eth_stats *pstats = NULL;\n-\n-\t/* read stat values to clear hardware registers */\n-\tret = i40evf_query_stats(dev, &pstats);\n-\n-\t/* set stats offset base on current values */\n-\tif (ret == 0)\n-\t\tvf->vsi.eth_stats_offset = *pstats;\n-\n-\treturn ret;\n-}\n-\n-static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_xstat_name *xstats_names,\n-\t\t\t\t __rte_unused unsigned limit)\n-{\n-\tunsigned i;\n-\n-\tif (xstats_names != NULL)\n-\t\tfor (i = 0; i < I40EVF_NB_XSTATS; i++) {\n-\t\t\tsnprintf(xstats_names[i].name,\n-\t\t\t\tsizeof(xstats_names[i].name),\n-\t\t\t\t\"%s\", rte_i40evf_stats_strings[i].name);\n-\t\t}\n-\treturn I40EVF_NB_XSTATS;\n-}\n-\n-static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_xstat *xstats, unsigned n)\n-{\n-\tint ret;\n-\tunsigned i;\n-\tstruct i40e_eth_stats *pstats = NULL;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_vsi *vsi = &vf->vsi;\n-\n-\tif (n < I40EVF_NB_XSTATS)\n-\t\treturn I40EVF_NB_XSTATS;\n-\n-\tret = i40evf_query_stats(dev, &pstats);\n-\tif (ret != 0)\n-\t\treturn 0;\n-\n-\tif (!xstats)\n-\t\treturn 0;\n-\n-\ti40evf_update_stats(vsi, pstats);\n-\n-\t/* loop over xstats array and values from pstats */\n-\tfor (i = 0; i < I40EVF_NB_XSTATS; i++) {\n-\t\txstats[i].id = i;\n-\t\txstats[i].value = *(uint64_t *)(((char *)pstats) +\n-\t\t\trte_i40evf_stats_strings[i].offset);\n-\t}\n-\n-\treturn I40EVF_NB_XSTATS;\n-}\n-\n-static int\n-i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct virtchnl_vlan_filter_list *vlan_list;\n-\tuint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +\n-\t\t\t\t\t\t\tsizeof(uint16_t)];\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\n-\tvlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;\n-\tvlan_list->vsi_id = vf->vsi_res->vsi_id;\n-\tvlan_list->num_elements = 1;\n-\tvlan_list->vlan_id[0] = vlanid;\n-\n-\targs.ops = VIRTCHNL_OP_ADD_VLAN;\n-\targs.in_args = (u8 *)&cmd_buffer;\n-\targs.in_args_size = sizeof(cmd_buffer);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_ADD_VLAN\");\n-\t\treturn err;\n-\t}\n-\t/**\n-\t * In linux kernel driver on receiving ADD_VLAN it enables\n-\t * VLAN_STRIP by default. So reconfigure the vlan_offload\n-\t * as it was done by the app earlier.\n-\t */\n-\terr = i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"fail to set vlan_strip\");\n-\n-\treturn err;\n-}\n-\n-static int\n-i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct virtchnl_vf_res_request vfres;\n-\tstruct vf_cmd_info args;\n-\tint err;\n-\n-\tvfres.num_queue_pairs = num;\n-\n-\targs.ops = VIRTCHNL_OP_REQUEST_QUEUES;\n-\targs.in_args = (u8 *)&vfres;\n-\targs.in_args_size = sizeof(vfres);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\n-\trte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);\n-\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\n-\trte_eal_alarm_set(I40EVF_ALARM_INTERVAL, i40evf_dev_alarm_handler, dev);\n-\n-\tif (err != I40E_SUCCESS) {\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_REQUEST_QUEUES\");\n-\t\treturn err;\n-\t}\n-\n-\t/* The PF will issue a reset to the VF when change the number of\n-\t * queues. The PF will set I40E_VFGEN_RSTAT to COMPLETE first, then\n-\t * wait 10ms and set it to ACTIVE. In this duration, vf may not catch\n-\t * the moment that COMPLETE is set. So, for vf, we'll try to wait a\n-\t * long time.\n-\t */\n-\trte_delay_ms(100);\n-\n-\terr = i40evf_check_vf_reset_done(dev);\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"VF is still resetting\");\n-\n-\treturn err;\n-}\n-\n-static int\n-i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct virtchnl_vlan_filter_list *vlan_list;\n-\tuint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +\n-\t\t\t\t\t\t\tsizeof(uint16_t)];\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\n-\tvlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;\n-\tvlan_list->vsi_id = vf->vsi_res->vsi_id;\n-\tvlan_list->num_elements = 1;\n-\tvlan_list->vlan_id[0] = vlanid;\n-\n-\targs.ops = VIRTCHNL_OP_DEL_VLAN;\n-\targs.in_args = (u8 *)&cmd_buffer;\n-\targs.in_args_size = sizeof(cmd_buffer);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err)\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_DEL_VLAN\");\n-\n-\treturn err;\n-}\n-\n-static const struct rte_pci_id pci_id_i40evf_map[] = {\n-\t{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },\n-\t{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },\n-\t{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },\n-\t{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },\n-\t{ .vendor_id = 0, /* sentinel */ },\n-};\n-\n-/* Disable IRQ0 */\n-static inline void\n-i40evf_disable_irq0(struct i40e_hw *hw)\n-{\n-\t/* Disable all interrupt types */\n-\tI40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);\n-\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,\n-\t\t I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);\n-\tI40EVF_WRITE_FLUSH(hw);\n-}\n-\n-/* Enable IRQ0 */\n-static inline void\n-i40evf_enable_irq0(struct i40e_hw *hw)\n-{\n-\t/* Enable admin queue interrupt trigger */\n-\tuint32_t val;\n-\n-\ti40evf_disable_irq0(hw);\n-\tval = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);\n-\tval |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |\n-\t\tI40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;\n-\tI40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);\n-\n-\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,\n-\t\tI40E_VFINT_DYN_CTL01_INTENA_MASK |\n-\t\tI40E_VFINT_DYN_CTL01_CLEARPBA_MASK |\n-\t\tI40E_VFINT_DYN_CTL01_ITR_INDX_MASK);\n-\n-\tI40EVF_WRITE_FLUSH(hw);\n-}\n-\n-static int\n-i40evf_check_vf_reset_done(struct rte_eth_dev *dev)\n-{\n-\tint i, reset;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\tfor (i = 0; i < MAX_RESET_WAIT_CNT; i++) {\n-\t\treset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &\n-\t\t\tI40E_VFGEN_RSTAT_VFR_STATE_MASK;\n-\t\treset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;\n-\t\tif (reset == VIRTCHNL_VFR_VFACTIVE ||\n-\t\t reset == VIRTCHNL_VFR_COMPLETED)\n-\t\t\tbreak;\n-\t\trte_delay_ms(50);\n-\t}\n-\n-\tif (i >= MAX_RESET_WAIT_CNT)\n-\t\treturn -1;\n-\n-\tvf->pend_msg &= ~PFMSG_RESET_IMPENDING;\n-\n-\treturn 0;\n-}\n-static int\n-i40evf_reset_vf(struct rte_eth_dev *dev)\n-{\n-\tint ret;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\n-\tif (i40e_vf_reset(hw) != I40E_SUCCESS) {\n-\t\tPMD_INIT_LOG(ERR, \"Reset VF NIC failed\");\n-\t\treturn -1;\n-\t}\n-\t/**\n-\t * After issuing vf reset command to pf, pf won't necessarily\n-\t * reset vf, it depends on what state it exactly is. If it's not\n-\t * initialized yet, it won't have vf reset since it's in a certain\n-\t * state. If not, it will try to reset. Even vf is reset, pf will\n-\t * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set\n-\t * it to ACTIVE. In this duration, vf may not catch the moment that\n-\t * COMPLETE is set. So, for vf, we'll try to wait a long time.\n-\t */\n-\trte_delay_ms(500);\n-\n-\tret = i40evf_check_vf_reset_done(dev);\n-\tif (ret) {\n-\t\tPMD_INIT_LOG(ERR, \"VF is still resetting\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_init_vf(struct rte_eth_dev *dev)\n-{\n-\tint i, err, bufsz;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tuint16_t interval =\n-\t\ti40e_calc_itr_interval(0, 0);\n-\n-\tvf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n-\tvf->dev_data = dev->data;\n-\trte_spinlock_init(&vf->cmd_send_lock);\n-\terr = i40e_set_mac_type(hw);\n-\tif (err) {\n-\t\tPMD_INIT_LOG(ERR, \"set_mac_type failed: %d\", err);\n-\t\tgoto err;\n-\t}\n-\n-\terr = i40evf_check_vf_reset_done(dev);\n-\tif (err)\n-\t\tgoto err;\n-\n-\ti40e_init_adminq_parameter(hw);\n-\terr = i40e_init_adminq(hw);\n-\tif (err) {\n-\t\tPMD_INIT_LOG(ERR, \"init_adminq failed: %d\", err);\n-\t\tgoto err;\n-\t}\n-\n-\t/* Reset VF and wait until it's complete */\n-\tif (i40evf_reset_vf(dev)) {\n-\t\tPMD_INIT_LOG(ERR, \"reset NIC failed\");\n-\t\tgoto err_aq;\n-\t}\n-\n-\t/* VF reset, shutdown admin queue and initialize again */\n-\tif (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {\n-\t\tPMD_INIT_LOG(ERR, \"i40e_shutdown_adminq failed\");\n-\t\tgoto err;\n-\t}\n-\n-\ti40e_init_adminq_parameter(hw);\n-\tif (i40e_init_adminq(hw) != I40E_SUCCESS) {\n-\t\tPMD_INIT_LOG(ERR, \"init_adminq failed\");\n-\t\tgoto err;\n-\t}\n-\n-\tvf->aq_resp = rte_zmalloc(\"vf_aq_resp\", I40E_AQ_BUF_SZ, 0);\n-\tif (!vf->aq_resp) {\n-\t\tPMD_INIT_LOG(ERR, \"unable to allocate vf_aq_resp memory\");\n-\t\tgoto err_aq;\n-\t}\n-\tif (i40evf_check_api_version(dev) != 0) {\n-\t\tPMD_INIT_LOG(ERR, \"check_api version failed\");\n-\t\tgoto err_api;\n-\t}\n-\tbufsz = sizeof(struct virtchnl_vf_resource) +\n-\t\t(I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));\n-\tvf->vf_res = rte_zmalloc(\"vf_res\", bufsz, 0);\n-\tif (!vf->vf_res) {\n-\t\tPMD_INIT_LOG(ERR, \"unable to allocate vf_res memory\");\n-\t\tgoto err_api;\n-\t}\n-\n-\tif (i40evf_get_vf_resource(dev) != 0) {\n-\t\tPMD_INIT_LOG(ERR, \"i40evf_get_vf_config failed\");\n-\t\tgoto err_alloc;\n-\t}\n-\n-\t/* got VF config message back from PF, now we can parse it */\n-\tfor (i = 0; i < vf->vf_res->num_vsis; i++) {\n-\t\tif (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)\n-\t\t\tvf->vsi_res = &vf->vf_res->vsi_res[i];\n-\t}\n-\n-\tif (!vf->vsi_res) {\n-\t\tPMD_INIT_LOG(ERR, \"no LAN VSI found\");\n-\t\tgoto err_alloc;\n-\t}\n-\n-\tif (hw->mac.type == I40E_MAC_X722_VF)\n-\t\tvf->flags = I40E_FLAG_RSS_AQ_CAPABLE;\n-\tvf->vsi.vsi_id = vf->vsi_res->vsi_id;\n-\n-\tswitch (vf->vsi_res->vsi_type) {\n-\tcase VIRTCHNL_VSI_SRIOV:\n-\t\tvf->vsi.type = I40E_VSI_SRIOV;\n-\t\tbreak;\n-\tdefault:\n-\t\tvf->vsi.type = I40E_VSI_TYPE_UNKNOWN;\n-\t\tbreak;\n-\t}\n-\tvf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;\n-\tvf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n-\n-\t/* Store the MAC address configured by host, or generate random one */\n-\tif (!rte_is_valid_assigned_ether_addr(\n-\t\t\t(struct rte_ether_addr *)hw->mac.addr))\n-\t\trte_eth_random_addr(hw->mac.addr); /* Generate a random one */\n-\n-\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,\n-\t\t (I40E_ITR_INDEX_DEFAULT <<\n-\t\t\tI40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |\n-\t\t (interval <<\n-\t\t\tI40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));\n-\tI40EVF_WRITE_FLUSH(hw);\n-\n-\treturn 0;\n-\n-err_alloc:\n-\trte_free(vf->vf_res);\n-\tvf->vsi_res = NULL;\n-err_api:\n-\trte_free(vf->aq_resp);\n-err_aq:\n-\ti40e_shutdown_adminq(hw); /* ignore error */\n-err:\n-\treturn -1;\n-}\n-\n-static int\n-i40evf_uninit_vf(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\tif (hw->adapter_closed == 0)\n-\t\ti40evf_dev_close(dev);\n-\n-\treturn 0;\n-}\n-\n-static void\n-i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,\n-\t\t__rte_unused uint16_t msglen)\n-{\n-\tstruct virtchnl_pf_event *pf_msg =\n-\t\t\t(struct virtchnl_pf_event *)msg;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\tswitch (pf_msg->event) {\n-\tcase VIRTCHNL_EVENT_RESET_IMPENDING:\n-\t\tPMD_DRV_LOG(DEBUG, \"VIRTCHNL_EVENT_RESET_IMPENDING event\");\n-\t\tvf->vf_reset = true;\n-\t\trte_eth_dev_callback_process(dev,\n-\t\t\t\tRTE_ETH_EVENT_INTR_RESET, NULL);\n-\t\tbreak;\n-\tcase VIRTCHNL_EVENT_LINK_CHANGE:\n-\t\tPMD_DRV_LOG(DEBUG, \"VIRTCHNL_EVENT_LINK_CHANGE event\");\n-\n-\t\tif (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_CAP_ADV_LINK_SPEED) {\n-\t\t\tvf->link_up =\n-\t\t\t\tpf_msg->event_data.link_event_adv.link_status;\n-\n-\t\t\tswitch (pf_msg->event_data.link_event_adv.link_speed) {\n-\t\t\tcase ETH_SPEED_NUM_100M:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_100MB;\n-\t\t\t\tbreak;\n-\t\t\tcase ETH_SPEED_NUM_1G:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_1GB;\n-\t\t\t\tbreak;\n-\t\t\tcase ETH_SPEED_NUM_2_5G:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_2_5GB;\n-\t\t\t\tbreak;\n-\t\t\tcase ETH_SPEED_NUM_5G:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_5GB;\n-\t\t\t\tbreak;\n-\t\t\tcase ETH_SPEED_NUM_10G:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_10GB;\n-\t\t\t\tbreak;\n-\t\t\tcase ETH_SPEED_NUM_20G:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_20GB;\n-\t\t\t\tbreak;\n-\t\t\tcase ETH_SPEED_NUM_25G:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_25GB;\n-\t\t\t\tbreak;\n-\t\t\tcase ETH_SPEED_NUM_40G:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_40GB;\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\tvf->link_speed = VIRTCHNL_LINK_SPEED_UNKNOWN;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tvf->link_up =\n-\t\t\t\tpf_msg->event_data.link_event.link_status;\n-\t\t\tvf->link_speed =\n-\t\t\t\tpf_msg->event_data.link_event.link_speed;\n-\t\t}\n-\n-\t\ti40evf_dev_link_update(dev, 0);\n-\t\trte_eth_dev_callback_process(dev,\n-\t\t\t\tRTE_ETH_EVENT_INTR_LSC, NULL);\n-\t\tbreak;\n-\tcase VIRTCHNL_EVENT_PF_DRIVER_CLOSE:\n-\t\tPMD_DRV_LOG(DEBUG, \"VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\");\n-\t\tbreak;\n-\tdefault:\n-\t\tPMD_DRV_LOG(ERR, \" unknown event received %u\", pf_msg->event);\n-\t\tbreak;\n-\t}\n-}\n-\n-static void\n-i40evf_handle_aq_msg(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_arq_event_info info;\n-\tuint16_t pending, aq_opc;\n-\tenum virtchnl_ops msg_opc;\n-\tenum i40e_status_code msg_ret;\n-\tint ret;\n-\n-\tinfo.buf_len = I40E_AQ_BUF_SZ;\n-\tif (!vf->aq_resp) {\n-\t\tPMD_DRV_LOG(ERR, \"Buffer for adminq resp should not be NULL\");\n-\t\treturn;\n-\t}\n-\tinfo.msg_buf = vf->aq_resp;\n-\n-\tpending = 1;\n-\twhile (pending) {\n-\t\tret = i40e_clean_arq_element(hw, &info, &pending);\n-\n-\t\tif (ret != I40E_SUCCESS) {\n-\t\t\tPMD_DRV_LOG(INFO, \"Failed to read msg from AdminQ,\"\n-\t\t\t\t \"ret: %d\", ret);\n-\t\t\tbreak;\n-\t\t}\n-\t\taq_opc = rte_le_to_cpu_16(info.desc.opcode);\n-\t\t/* For the message sent from pf to vf, opcode is stored in\n-\t\t * cookie_high of struct i40e_aq_desc, while return error code\n-\t\t * are stored in cookie_low, Which is done by\n-\t\t * i40e_aq_send_msg_to_vf in PF driver.*/\n-\t\tmsg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(\n-\t\t\t\t\t\t info.desc.cookie_high);\n-\t\tmsg_ret = (enum i40e_status_code)rte_le_to_cpu_32(\n-\t\t\t\t\t\t info.desc.cookie_low);\n-\t\tswitch (aq_opc) {\n-\t\tcase i40e_aqc_opc_send_msg_to_vf:\n-\t\t\tif (msg_opc == VIRTCHNL_OP_EVENT)\n-\t\t\t\t/* process event*/\n-\t\t\t\ti40evf_handle_pf_event(dev, info.msg_buf,\n-\t\t\t\t\t\t info.msg_len);\n-\t\t\telse {\n-\t\t\t\t/* read message and it's expected one */\n-\t\t\t\tif ((volatile uint32_t)msg_opc ==\n-\t\t\t\t vf->pend_cmd) {\n-\t\t\t\t\tvf->cmd_retval = msg_ret;\n-\t\t\t\t\t/* prevent compiler reordering */\n-\t\t\t\t\trte_compiler_barrier();\n-\t\t\t\t\t_clear_cmd(vf);\n-\t\t\t\t} else\n-\t\t\t\t\tPMD_DRV_LOG(ERR, \"command mismatch,\"\n-\t\t\t\t\t\t\"expect %u, get %u\",\n-\t\t\t\t\t\tvf->pend_cmd, msg_opc);\n-\t\t\t\tPMD_DRV_LOG(DEBUG, \"adminq response is received,\"\n-\t\t\t\t\t \" opcode = %d\", msg_opc);\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tPMD_DRV_LOG(DEBUG, \"Request %u is not supported yet\",\n-\t\t\t\t aq_opc);\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-}\n-\n-/**\n- * Interrupt handler triggered by NIC for handling\n- * specific interrupt. Only adminq interrupt is processed in VF.\n- *\n- * @param handle\n- * Pointer to interrupt handle.\n- * @param param\n- * The address of parameter (struct rte_eth_dev *) regsitered before.\n- *\n- * @return\n- * void\n- */\n-static void\n-i40evf_dev_alarm_handler(void *param)\n-{\n-\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tuint32_t icr0;\n-\n-\ti40evf_disable_irq0(hw);\n-\n-\t/* read out interrupt causes */\n-\ticr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);\n-\n-\t/* No interrupt event indicated */\n-\tif (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))\n-\t\tgoto done;\n-\n-\tif (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {\n-\t\tPMD_DRV_LOG(DEBUG, \"ICR01_ADMINQ is reported\");\n-\t\ti40evf_handle_aq_msg(dev);\n-\t}\n-\n-\t/* Link Status Change interrupt */\n-\tif (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)\n-\t\tPMD_DRV_LOG(DEBUG, \"LINK_STAT_CHANGE is reported,\"\n-\t\t\t\t \" do nothing\");\n-\n-done:\n-\ti40evf_enable_irq0(hw);\n-\trte_eal_alarm_set(I40EVF_ALARM_INTERVAL,\n-\t\t\t i40evf_dev_alarm_handler, dev);\n-}\n-\n-static int\n-i40evf_dev_init(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct i40e_hw *hw\n-\t\t= I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\t/* assign ops func pointer */\n-\teth_dev->dev_ops = &i40evf_eth_dev_ops;\n-\teth_dev->rx_queue_count = i40e_dev_rx_queue_count;\n-\teth_dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;\n-\teth_dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;\n-\teth_dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;\n-\teth_dev->rx_pkt_burst = &i40e_recv_pkts;\n-\teth_dev->tx_pkt_burst = &i40e_xmit_pkts;\n-\n-\t/*\n-\t * For secondary processes, we don't initialise any further as primary\n-\t * has already done this work.\n-\t */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n-\t\ti40e_set_rx_function(eth_dev);\n-\t\ti40e_set_tx_function(eth_dev);\n-\t\treturn 0;\n-\t}\n-\ti40e_set_default_ptype_table(eth_dev);\n-\trte_eth_copy_pci_info(eth_dev, pci_dev);\n-\teth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;\n-\n-\thw->vendor_id = pci_dev->id.vendor_id;\n-\thw->device_id = pci_dev->id.device_id;\n-\thw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;\n-\thw->subsystem_device_id = pci_dev->id.subsystem_device_id;\n-\thw->bus.device = pci_dev->addr.devid;\n-\thw->bus.func = pci_dev->addr.function;\n-\thw->hw_addr = (void *)pci_dev->mem_resource[0].addr;\n-\thw->adapter_stopped = 1;\n-\thw->adapter_closed = 0;\n-\n-\tif(i40evf_init_vf(eth_dev) != 0) {\n-\t\tPMD_INIT_LOG(ERR, \"Init vf failed\");\n-\t\treturn -1;\n-\t}\n-\n-\ti40e_set_default_pctype_table(eth_dev);\n-\trte_eal_alarm_set(I40EVF_ALARM_INTERVAL,\n-\t\t\t i40evf_dev_alarm_handler, eth_dev);\n-\n-\t/* configure and enable device interrupt */\n-\ti40evf_enable_irq0(hw);\n-\n-\t/* copy mac addr */\n-\teth_dev->data->mac_addrs = rte_zmalloc(\"i40evf_mac\",\n-\t\t\t\tRTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,\n-\t\t\t\t0);\n-\tif (eth_dev->data->mac_addrs == NULL) {\n-\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d bytes needed to\"\n-\t\t\t\t\" store MAC addresses\",\n-\t\t\t\tRTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);\n-\t\treturn -ENOMEM;\n-\t}\n-\trte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,\n-\t\t\tð_dev->data->mac_addrs[0]);\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_uninit(struct rte_eth_dev *eth_dev)\n-{\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn -EPERM;\n-\n-\tif (i40evf_uninit_vf(eth_dev) != 0) {\n-\t\tPMD_INIT_LOG(ERR, \"i40evf_uninit_vf failed\");\n-\t\treturn -1;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_check_driver_handler(__rte_unused const char *key,\n-\t\t\t const char *value, __rte_unused void *opaque)\n-{\n-\tif (strcmp(value, \"i40evf\"))\n-\t\treturn -1;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_driver_selected(struct rte_devargs *devargs)\n-{\n-\tstruct rte_kvargs *kvlist;\n-\tint ret = 0;\n-\n-\tif (devargs == NULL)\n-\t\treturn 0;\n-\n-\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n-\tif (kvlist == NULL)\n-\t\treturn 0;\n-\n-\tif (!rte_kvargs_count(kvlist, RTE_DEVARGS_KEY_DRIVER))\n-\t\tgoto exit;\n-\n-\t/* i40evf driver selected when there's a key-value pair:\n-\t * driver=i40evf\n-\t */\n-\tif (rte_kvargs_process(kvlist, RTE_DEVARGS_KEY_DRIVER,\n-\t\t\t i40evf_check_driver_handler, NULL) < 0)\n-\t\tgoto exit;\n-\n-\tret = 1;\n-\n-exit:\n-\trte_kvargs_free(kvlist);\n-\treturn ret;\n-}\n-\n-static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n-\tstruct rte_pci_device *pci_dev)\n-{\n-\tif (!i40evf_driver_selected(pci_dev->device.devargs))\n-\t\treturn 1;\n-\n-\treturn rte_eth_dev_pci_generic_probe(pci_dev,\n-\t\tsizeof(struct i40e_adapter), i40evf_dev_init);\n-}\n-\n-static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)\n-{\n-\treturn rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);\n-}\n-\n-/*\n- * virtual function driver struct\n- */\n-static struct rte_pci_driver rte_i40evf_pmd = {\n-\t.id_table = pci_id_i40evf_map,\n-\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,\n-\t.probe = eth_i40evf_pci_probe,\n-\t.remove = eth_i40evf_pci_remove,\n-};\n-\n-RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);\n-RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);\n-RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, \"* igb_uio | vfio-pci\");\n-RTE_PMD_REGISTER_PARAM_STRING(net_i40e_vf, \"driver=i40evf\");\n-\n-static int\n-i40evf_dev_configure(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_adapter *ad =\n-\t\tI40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n-\tuint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,\n-\t\t\t\tdev->data->nb_tx_queues);\n-\n-\t/* Initialize to TRUE. If any of Rx queues doesn't meet the bulk\n-\t * allocation or vector Rx preconditions we will reset it.\n-\t */\n-\tad->rx_bulk_alloc_allowed = true;\n-\tad->rx_vec_allowed = true;\n-\tad->tx_simple_allowed = true;\n-\tad->tx_vec_allowed = true;\n-\n-\tdev->data->dev_conf.intr_conf.lsc =\n-\t\t!!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC);\n-\n-\tif (num_queue_pairs > vf->vsi_res->num_queue_pairs) {\n-\t\tstruct i40e_hw *hw;\n-\t\tint ret;\n-\n-\t\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n-\t\t\tPMD_DRV_LOG(ERR,\n-\t\t\t\t \"For secondary processes, change queue pairs is not supported!\");\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\n-\t\thw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\t\tif (!hw->adapter_stopped) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Device must be stopped first!\");\n-\t\t\treturn -EBUSY;\n-\t\t}\n-\n-\t\tPMD_DRV_LOG(INFO, \"change queue pairs from %u to %u\",\n-\t\t\t vf->vsi_res->num_queue_pairs, num_queue_pairs);\n-\t\tret = i40evf_request_queues(dev, num_queue_pairs);\n-\t\tif (ret != 0)\n-\t\t\treturn ret;\n-\n-\t\tret = i40evf_dev_reset(dev);\n-\t\tif (ret != 0)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn i40evf_init_vlan(dev);\n-}\n-\n-static int\n-i40evf_init_vlan(struct rte_eth_dev *dev)\n-{\n-\t/* Apply vlan offload setting */\n-\ti40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n-{\n-\tstruct rte_eth_conf *dev_conf = &dev->data->dev_conf;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\tif (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))\n-\t\treturn -ENOTSUP;\n-\n-\t/* Vlan stripping setting */\n-\tif (mask & ETH_VLAN_STRIP_MASK) {\n-\t\t/* Enable or disable VLAN stripping */\n-\t\tif (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)\n-\t\t\ti40evf_enable_vlan_strip(dev);\n-\t\telse\n-\t\t\ti40evf_disable_vlan_strip(dev);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n-{\n-\tstruct i40e_rx_queue *rxq;\n-\tint err;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\trxq = dev->data->rx_queues[rx_queue_id];\n-\n-\terr = i40e_alloc_rx_queue_mbufs(rxq);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX queue mbuf\");\n-\t\treturn err;\n-\t}\n-\n-\trte_wmb();\n-\n-\t/* Init the RX tail register. */\n-\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n-\tI40EVF_WRITE_FLUSH(hw);\n-\n-\t/* Ready to switch the queue on */\n-\terr = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u on\",\n-\t\t\t rx_queue_id);\n-\t\treturn err;\n-\t}\n-\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n-{\n-\tstruct i40e_rx_queue *rxq;\n-\tint err;\n-\n-\trxq = dev->data->rx_queues[rx_queue_id];\n-\n-\terr = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u off\",\n-\t\t\t rx_queue_id);\n-\t\treturn err;\n-\t}\n-\n-\ti40e_rx_queue_release_mbufs(rxq);\n-\ti40e_reset_rx_queue(rxq);\n-\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n-{\n-\tint err;\n-\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\t/* Ready to switch the queue on */\n-\terr = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u on\",\n-\t\t\t tx_queue_id);\n-\t\treturn err;\n-\t}\n-\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n-{\n-\tstruct i40e_tx_queue *txq;\n-\tint err;\n-\n-\ttxq = dev->data->tx_queues[tx_queue_id];\n-\n-\terr = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u off\",\n-\t\t\t tx_queue_id);\n-\t\treturn err;\n-\t}\n-\n-\ti40e_tx_queue_release_mbufs(txq);\n-\ti40e_reset_tx_queue(txq);\n-\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n-{\n-\tint ret;\n-\n-\tif (on)\n-\t\tret = i40evf_add_vlan(dev, vlan_id);\n-\telse\n-\t\tret = i40evf_del_vlan(dev,vlan_id);\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct rte_eth_dev_data *dev_data = dev->data;\n-\tstruct rte_pktmbuf_pool_private *mbp_priv;\n-\tuint16_t buf_size, len;\n-\n-\trxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);\n-\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n-\tI40EVF_WRITE_FLUSH(hw);\n-\n-\t/* Calculate the maximum packet length allowed */\n-\tmbp_priv = rte_mempool_get_priv(rxq->mp);\n-\tbuf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -\n-\t\t\t\t\tRTE_PKTMBUF_HEADROOM);\n-\trxq->hs_mode = i40e_header_split_none;\n-\trxq->rx_hdr_len = 0;\n-\trxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));\n-\tlen = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;\n-\trxq->max_pkt_len = RTE_MIN(len,\n-\t\tdev_data->dev_conf.rxmode.max_rx_pkt_len);\n-\n-\t/**\n-\t * Check if the jumbo frame and maximum packet length are set correctly\n-\t */\n-\tif (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {\n-\t\tif (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||\n-\t\t rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {\n-\t\t\tPMD_DRV_LOG(ERR, \"maximum packet length must be \"\n-\t\t\t\t\"larger than %u and smaller than %u, as jumbo \"\n-\t\t\t\t\"frame is enabled\", (uint32_t)I40E_ETH_MAX_LEN,\n-\t\t\t\t\t(uint32_t)I40E_FRAME_SIZE_MAX);\n-\t\t\treturn I40E_ERR_CONFIG;\n-\t\t}\n-\t} else {\n-\t\tif (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||\n-\t\t rxq->max_pkt_len > I40E_ETH_MAX_LEN) {\n-\t\t\tPMD_DRV_LOG(ERR, \"maximum packet length must be \"\n-\t\t\t\t\"larger than %u and smaller than %u, as jumbo \"\n-\t\t\t\t\"frame is disabled\",\n-\t\t\t\t(uint32_t)RTE_ETHER_MIN_LEN,\n-\t\t\t\t(uint32_t)I40E_ETH_MAX_LEN);\n-\t\t\treturn I40E_ERR_CONFIG;\n-\t\t}\n-\t}\n-\n-\tif ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||\n-\t rxq->max_pkt_len > buf_size)\n-\t\tdev_data->scattered_rx = 1;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_rx_init(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tuint16_t i;\n-\tint ret = I40E_SUCCESS;\n-\tstruct i40e_rx_queue **rxq =\n-\t\t(struct i40e_rx_queue **)dev->data->rx_queues;\n-\n-\ti40evf_config_rss(vf);\n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\tif (!rxq[i] || !rxq[i]->q_set)\n-\t\t\tcontinue;\n-\t\tret = i40evf_rxq_init(dev, rxq[i]);\n-\t\tif (ret != I40E_SUCCESS)\n-\t\t\tbreak;\n-\t}\n-\tif (ret == I40E_SUCCESS)\n-\t\ti40e_set_rx_function(dev);\n-\n-\treturn ret;\n-}\n-\n-static void\n-i40evf_tx_init(struct rte_eth_dev *dev)\n-{\n-\tuint16_t i;\n-\tstruct i40e_tx_queue **txq =\n-\t\t(struct i40e_tx_queue **)dev->data->tx_queues;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n-\t\ttxq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);\n-\n-\ti40e_set_tx_function(dev);\n-}\n-\n-static inline void\n-i40evf_enable_queues_intr(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\n-\tif (!rte_intr_allow_others(intr_handle)) {\n-\t\tI40E_WRITE_REG(hw,\n-\t\t\t I40E_VFINT_DYN_CTL01,\n-\t\t\t I40E_VFINT_DYN_CTL01_INTENA_MASK |\n-\t\t\t I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |\n-\t\t\t I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);\n-\t\tI40EVF_WRITE_FLUSH(hw);\n-\t\treturn;\n-\t}\n-\n-\tI40EVF_WRITE_FLUSH(hw);\n-}\n-\n-static inline void\n-i40evf_disable_queues_intr(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\n-\tif (!rte_intr_allow_others(intr_handle)) {\n-\t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,\n-\t\t\t I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);\n-\t\tI40EVF_WRITE_FLUSH(hw);\n-\t\treturn;\n-\t}\n-\n-\tI40EVF_WRITE_FLUSH(hw);\n-}\n-\n-static int\n-i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tuint16_t interval =\n-\t\ti40e_calc_itr_interval(0, 0);\n-\tuint16_t msix_intr;\n-\n-\tmsix_intr = intr_handle->intr_vec[queue_id];\n-\tif (msix_intr == I40E_MISC_VEC_ID)\n-\t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,\n-\t\t\t I40E_VFINT_DYN_CTL01_INTENA_MASK |\n-\t\t\t I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |\n-\t\t\t (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |\n-\t\t\t (interval <<\n-\t\t\t\tI40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));\n-\telse\n-\t\tI40E_WRITE_REG(hw,\n-\t\t\t I40E_VFINT_DYN_CTLN1(msix_intr -\n-\t\t\t\t\t\t I40E_RX_VEC_START),\n-\t\t\t I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n-\t\t\t (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n-\t\t\t (interval <<\n-\t\t\t\tI40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));\n-\n-\tI40EVF_WRITE_FLUSH(hw);\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tuint16_t msix_intr;\n-\n-\tmsix_intr = intr_handle->intr_vec[queue_id];\n-\tif (msix_intr == I40E_MISC_VEC_ID)\n-\t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);\n-\telse\n-\t\tI40E_WRITE_REG(hw,\n-\t\t\t I40E_VFINT_DYN_CTLN1(msix_intr -\n-\t\t\t\t\t\t I40E_RX_VEC_START),\n-\t\t\t 0);\n-\n-\tI40EVF_WRITE_FLUSH(hw);\n-\n-\treturn 0;\n-}\n-\n-static void\n-i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)\n-{\n-\tstruct virtchnl_ether_addr_list *list;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tint err, i, j;\n-\tint next_begin = 0;\n-\tint begin = 0;\n-\tuint32_t len;\n-\tstruct rte_ether_addr *addr;\n-\tstruct vf_cmd_info args;\n-\n-\tdo {\n-\t\tj = 0;\n-\t\tlen = sizeof(struct virtchnl_ether_addr_list);\n-\t\tfor (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {\n-\t\t\tif (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))\n-\t\t\t\tcontinue;\n-\t\t\tlen += sizeof(struct virtchnl_ether_addr);\n-\t\t\tif (len >= I40E_AQ_BUF_SZ) {\n-\t\t\t\tnext_begin = i + 1;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t\tlist = rte_zmalloc(\"i40evf_del_mac_buffer\", len, 0);\n-\t\tif (!list) {\n-\t\t\tPMD_DRV_LOG(ERR, \"fail to allocate memory\");\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tfor (i = begin; i < next_begin; i++) {\n-\t\t\taddr = &dev->data->mac_addrs[i];\n-\t\t\tif (rte_is_zero_ether_addr(addr))\n-\t\t\t\tcontinue;\n-\t\t\trte_memcpy(list->list[j].addr, addr->addr_bytes,\n-\t\t\t\t\t sizeof(addr->addr_bytes));\n-\t\t\tlist->list[j].type = (j == 0 ?\n-\t\t\t\t\t VIRTCHNL_ETHER_ADDR_PRIMARY :\n-\t\t\t\t\t VIRTCHNL_ETHER_ADDR_EXTRA);\n-\t\t\tPMD_DRV_LOG(DEBUG, \"add/rm mac:%x:%x:%x:%x:%x:%x\",\n-\t\t\t\t addr->addr_bytes[0], addr->addr_bytes[1],\n-\t\t\t\t addr->addr_bytes[2], addr->addr_bytes[3],\n-\t\t\t\t addr->addr_bytes[4], addr->addr_bytes[5]);\n-\t\t\tj++;\n-\t\t}\n-\t\tlist->vsi_id = vf->vsi_res->vsi_id;\n-\t\tlist->num_elements = j;\n-\t\targs.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :\n-\t\t\t VIRTCHNL_OP_DEL_ETH_ADDR;\n-\t\targs.in_args = (uint8_t *)list;\n-\t\targs.in_args_size = len;\n-\t\targs.out_buffer = vf->aq_resp;\n-\t\targs.out_size = I40E_AQ_BUF_SZ;\n-\t\terr = i40evf_execute_vf_cmd(dev, &args);\n-\t\tif (err) {\n-\t\t\tPMD_DRV_LOG(ERR, \"fail to execute command %s\",\n-\t\t\t\t add ? \"OP_ADD_ETHER_ADDRESS\" :\n-\t\t\t\t \"OP_DEL_ETHER_ADDRESS\");\n-\t\t} else {\n-\t\t\tif (add)\n-\t\t\t\tvf->vsi.mac_num++;\n-\t\t\telse\n-\t\t\t\tvf->vsi.mac_num--;\n-\t\t}\n-\t\trte_free(list);\n-\t\tbegin = next_begin;\n-\t} while (begin < I40E_NUM_MACADDR_MAX);\n-}\n-\n-static int\n-i40evf_dev_start(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\tuint32_t intr_vector = 0;\n-\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\thw->adapter_stopped = 0;\n-\n-\tvf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;\n-\tvf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,\n-\t\t\t\t\tdev->data->nb_tx_queues);\n-\n-\t/* check and configure queue intr-vector mapping */\n-\tif (rte_intr_cap_multiple(intr_handle) &&\n-\t dev->data->dev_conf.intr_conf.rxq) {\n-\t\tintr_vector = dev->data->nb_rx_queues;\n-\t\tif (rte_intr_efd_enable(intr_handle, intr_vector))\n-\t\t\treturn -1;\n-\t}\n-\n-\tif (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {\n-\t\tintr_handle->intr_vec =\n-\t\t\trte_zmalloc(\"intr_vec\",\n-\t\t\t\t dev->data->nb_rx_queues * sizeof(int), 0);\n-\t\tif (!intr_handle->intr_vec) {\n-\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d rx_queues\"\n-\t\t\t\t \" intr_vec\", dev->data->nb_rx_queues);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\n-\tif (i40evf_rx_init(dev) != 0){\n-\t\tPMD_DRV_LOG(ERR, \"failed to do RX init\");\n-\t\treturn -1;\n-\t}\n-\n-\ti40evf_tx_init(dev);\n-\n-\tif (i40evf_configure_vsi_queues(dev) != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"configure queues failed\");\n-\t\tgoto err_queue;\n-\t}\n-\tif (i40evf_config_irq_map(dev)) {\n-\t\tPMD_DRV_LOG(ERR, \"config_irq_map failed\");\n-\t\tgoto err_queue;\n-\t}\n-\n-\t/* Set all mac addrs */\n-\ti40evf_add_del_all_mac_addr(dev, TRUE);\n-\t/* Set all multicast addresses */\n-\ti40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,\n-\t\t\t\tTRUE);\n-\n-\tif (i40evf_start_queues(dev) != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"enable queues failed\");\n-\t\tgoto err_mac;\n-\t}\n-\n-\t/* only enable interrupt in rx interrupt mode */\n-\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n-\t\trte_intr_enable(intr_handle);\n-\n-\ti40evf_enable_queues_intr(dev);\n-\n-\treturn 0;\n-\n-err_mac:\n-\ti40evf_add_del_all_mac_addr(dev, FALSE);\n-\ti40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,\n-\t\t\t\tFALSE);\n-err_queue:\n-\treturn -1;\n-}\n-\n-static int\n-i40evf_dev_stop(struct rte_eth_dev *dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n-\t\trte_intr_disable(intr_handle);\n-\n-\tif (hw->adapter_stopped == 1)\n-\t\treturn 0;\n-\ti40evf_stop_queues(dev);\n-\ti40evf_disable_queues_intr(dev);\n-\ti40e_dev_clear_queues(dev);\n-\n-\t/* Clean datapath event and queue/vec mapping */\n-\trte_intr_efd_disable(intr_handle);\n-\tif (intr_handle->intr_vec) {\n-\t\trte_free(intr_handle->intr_vec);\n-\t\tintr_handle->intr_vec = NULL;\n-\t}\n-\t/* remove all mac addrs */\n-\ti40evf_add_del_all_mac_addr(dev, FALSE);\n-\t/* remove all multicast addresses */\n-\ti40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,\n-\t\t\t\tFALSE);\n-\thw->adapter_stopped = 1;\n-\tdev->data->dev_started = 0;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_link_update(struct rte_eth_dev *dev,\n-\t\t __rte_unused int wait_to_complete)\n-{\n-\tstruct rte_eth_link new_link;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\t/*\n-\t * DPDK pf host provide interfacet to acquire link status\n-\t * while Linux driver does not\n-\t */\n-\n-\tmemset(&new_link, 0, sizeof(new_link));\n-\t/* Linux driver PF host */\n-\tswitch (vf->link_speed) {\n-\tcase I40E_LINK_SPEED_100MB:\n-\t\tnew_link.link_speed = ETH_SPEED_NUM_100M;\n-\t\tbreak;\n-\tcase I40E_LINK_SPEED_1GB:\n-\t\tnew_link.link_speed = ETH_SPEED_NUM_1G;\n-\t\tbreak;\n-\tcase I40E_LINK_SPEED_10GB:\n-\t\tnew_link.link_speed = ETH_SPEED_NUM_10G;\n-\t\tbreak;\n-\tcase I40E_LINK_SPEED_20GB:\n-\t\tnew_link.link_speed = ETH_SPEED_NUM_20G;\n-\t\tbreak;\n-\tcase I40E_LINK_SPEED_25GB:\n-\t\tnew_link.link_speed = ETH_SPEED_NUM_25G;\n-\t\tbreak;\n-\tcase I40E_LINK_SPEED_40GB:\n-\t\tnew_link.link_speed = ETH_SPEED_NUM_40G;\n-\t\tbreak;\n-\tdefault:\n-\t\tif (vf->link_up)\n-\t\t\tnew_link.link_speed = ETH_SPEED_NUM_UNKNOWN;\n-\t\telse\n-\t\t\tnew_link.link_speed = ETH_SPEED_NUM_NONE;\n-\t\tbreak;\n-\t}\n-\t/* full duplex only */\n-\tnew_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n-\tnew_link.link_status = vf->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;\n-\tnew_link.link_autoneg =\n-\t\t!(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);\n-\n-\treturn rte_eth_linkstatus_set(dev, &new_link);\n-}\n-\n-static int\n-i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\treturn i40evf_config_promisc(dev, true, vf->promisc_multicast_enabled);\n-}\n-\n-static int\n-i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\treturn i40evf_config_promisc(dev, false, vf->promisc_multicast_enabled);\n-}\n-\n-static int\n-i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\treturn i40evf_config_promisc(dev, vf->promisc_unicast_enabled, true);\n-}\n-\n-static int\n-i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\treturn i40evf_config_promisc(dev, vf->promisc_unicast_enabled, false);\n-}\n-\n-static int\n-i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\n-\tdev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;\n-\tdev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;\n-\tdev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;\n-\tdev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;\n-\tdev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;\n-\tdev_info->min_mtu = RTE_ETHER_MIN_MTU;\n-\tdev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);\n-\tdev_info->reta_size = ETH_RSS_RETA_SIZE_64;\n-\tdev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;\n-\tdev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;\n-\tdev_info->rx_queue_offload_capa = 0;\n-\tdev_info->rx_offload_capa =\n-\t\tDEV_RX_OFFLOAD_VLAN_STRIP |\n-\t\tDEV_RX_OFFLOAD_QINQ_STRIP |\n-\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n-\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n-\t\tDEV_RX_OFFLOAD_TCP_CKSUM |\n-\t\tDEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |\n-\t\tDEV_RX_OFFLOAD_SCATTER |\n-\t\tDEV_RX_OFFLOAD_JUMBO_FRAME |\n-\t\tDEV_RX_OFFLOAD_VLAN_FILTER;\n-\n-\tdev_info->tx_queue_offload_capa = 0;\n-\tdev_info->tx_offload_capa =\n-\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n-\t\tDEV_TX_OFFLOAD_QINQ_INSERT |\n-\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n-\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n-\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n-\t\tDEV_TX_OFFLOAD_SCTP_CKSUM |\n-\t\tDEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |\n-\t\tDEV_TX_OFFLOAD_TCP_TSO |\n-\t\tDEV_TX_OFFLOAD_VXLAN_TNL_TSO |\n-\t\tDEV_TX_OFFLOAD_GRE_TNL_TSO |\n-\t\tDEV_TX_OFFLOAD_IPIP_TNL_TSO |\n-\t\tDEV_TX_OFFLOAD_GENEVE_TNL_TSO |\n-\t\tDEV_TX_OFFLOAD_MULTI_SEGS;\n-\n-\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n-\t\t.rx_thresh = {\n-\t\t\t.pthresh = I40E_DEFAULT_RX_PTHRESH,\n-\t\t\t.hthresh = I40E_DEFAULT_RX_HTHRESH,\n-\t\t\t.wthresh = I40E_DEFAULT_RX_WTHRESH,\n-\t\t},\n-\t\t.rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,\n-\t\t.rx_drop_en = 0,\n-\t\t.offloads = 0,\n-\t};\n-\n-\tdev_info->default_txconf = (struct rte_eth_txconf) {\n-\t\t.tx_thresh = {\n-\t\t\t.pthresh = I40E_DEFAULT_TX_PTHRESH,\n-\t\t\t.hthresh = I40E_DEFAULT_TX_HTHRESH,\n-\t\t\t.wthresh = I40E_DEFAULT_TX_WTHRESH,\n-\t\t},\n-\t\t.tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,\n-\t\t.tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,\n-\t\t.offloads = 0,\n-\t};\n-\n-\tdev_info->rx_desc_lim = (struct rte_eth_desc_lim) {\n-\t\t.nb_max = I40E_MAX_RING_DESC,\n-\t\t.nb_min = I40E_MIN_RING_DESC,\n-\t\t.nb_align = I40E_ALIGN_RING_DESC,\n-\t};\n-\n-\tdev_info->tx_desc_lim = (struct rte_eth_desc_lim) {\n-\t\t.nb_max = I40E_MAX_RING_DESC,\n-\t\t.nb_min = I40E_MIN_RING_DESC,\n-\t\t.nb_align = I40E_ALIGN_RING_DESC,\n-\t};\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n-{\n-\tint ret;\n-\tstruct i40e_eth_stats *pstats = NULL;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_vsi *vsi = &vf->vsi;\n-\n-\tret = i40evf_query_stats(dev, &pstats);\n-\tif (ret == 0) {\n-\t\ti40evf_update_stats(vsi, pstats);\n-\n-\t\tstats->ipackets = pstats->rx_unicast + pstats->rx_multicast +\n-\t\t\t\t\t\tpstats->rx_broadcast;\n-\t\tstats->opackets = pstats->tx_broadcast + pstats->tx_multicast +\n-\t\t\t\t\t\tpstats->tx_unicast;\n-\t\tstats->imissed = pstats->rx_discards;\n-\t\tstats->oerrors = pstats->tx_errors + pstats->tx_discards;\n-\t\tstats->ibytes = pstats->rx_bytes;\n-\t\tstats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;\n-\t\tstats->obytes = pstats->tx_bytes;\n-\t} else {\n-\t\tPMD_DRV_LOG(ERR, \"Get statistics failed\");\n-\t}\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_dev_close(struct rte_eth_dev *dev)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n-\tint ret;\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\tret = i40evf_dev_stop(dev);\n-\n-\ti40e_dev_free_queues(dev);\n-\t/*\n-\t * disable promiscuous mode before reset vf\n-\t * it is a workaround solution when work with kernel driver\n-\t * and it is not the normal way\n-\t */\n-\tif (vf->promisc_unicast_enabled || vf->promisc_multicast_enabled)\n-\t\ti40evf_config_promisc(dev, false, false);\n-\n-\trte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);\n-\n-\ti40evf_reset_vf(dev);\n-\ti40e_shutdown_adminq(hw);\n-\ti40evf_disable_irq0(hw);\n-\n-\t/*\n-\t * If the VF is reset via VFLR, the device will be knocked out of bus\n-\t * master mode, and the driver will fail to recover from the reset. Fix\n-\t * this by enabling bus mastering after every reset. In a non-VFLR case,\n-\t * the bus master bit will not be disabled, and this call will have no\n-\t * effect.\n-\t */\n-\tif (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))\n-\t\tvf->vf_reset = false;\n-\n-\trte_free(vf->vf_res);\n-\tvf->vf_res = NULL;\n-\trte_free(vf->aq_resp);\n-\tvf->aq_resp = NULL;\n-\n-\thw->adapter_closed = 1;\n-\treturn ret;\n-}\n-\n-/*\n- * Reset VF device only to re-initialize resources in PMD layer\n- */\n-static int\n-i40evf_dev_reset(struct rte_eth_dev *dev)\n-{\n-\tint ret;\n-\n-\tret = i40evf_dev_uninit(dev);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = i40evf_dev_init(dev);\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)\n-{\n-\tstruct i40e_vf *vf = I40E_VSI_TO_VF(vsi);\n-\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n-\tint ret;\n-\n-\tif (!lut)\n-\t\treturn -EINVAL;\n-\n-\tif (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {\n-\t\tret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,\n-\t\t\t\t\t lut, lut_size);\n-\t\tif (ret) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Failed to get RSS lookup table\");\n-\t\t\treturn ret;\n-\t\t}\n-\t} else {\n-\t\tuint32_t *lut_dw = (uint32_t *)lut;\n-\t\tuint16_t i, lut_size_dw = lut_size / 4;\n-\n-\t\tfor (i = 0; i < lut_size_dw; i++)\n-\t\t\tlut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)\n-{\n-\tstruct i40e_vf *vf;\n-\tstruct i40e_hw *hw;\n-\tint ret;\n-\n-\tif (!vsi || !lut)\n-\t\treturn -EINVAL;\n-\n-\tvf = I40E_VSI_TO_VF(vsi);\n-\thw = I40E_VSI_TO_HW(vsi);\n-\n-\tif (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {\n-\t\tret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,\n-\t\t\t\t\t lut, lut_size);\n-\t\tif (ret) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Failed to set RSS lookup table\");\n-\t\t\treturn ret;\n-\t\t}\n-\t} else {\n-\t\tuint32_t *lut_dw = (uint32_t *)lut;\n-\t\tuint16_t i, lut_size_dw = lut_size / 4;\n-\n-\t\tfor (i = 0; i < lut_size_dw; i++)\n-\t\t\tI40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);\n-\t\tI40EVF_WRITE_FLUSH(hw);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\t uint16_t reta_size)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tuint8_t *lut;\n-\tuint16_t i, idx, shift;\n-\tint ret;\n-\n-\tif (reta_size != ETH_RSS_RETA_SIZE_64) {\n-\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n-\t\t\t\"(%d) doesn't match the number of hardware can \"\n-\t\t\t\"support (%d)\", reta_size, ETH_RSS_RETA_SIZE_64);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tlut = rte_zmalloc(\"i40e_rss_lut\", reta_size, 0);\n-\tif (!lut) {\n-\t\tPMD_DRV_LOG(ERR, \"No memory can be allocated\");\n-\t\treturn -ENOMEM;\n-\t}\n-\tret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);\n-\tif (ret)\n-\t\tgoto out;\n-\tfor (i = 0; i < reta_size; i++) {\n-\t\tidx = i / RTE_RETA_GROUP_SIZE;\n-\t\tshift = i % RTE_RETA_GROUP_SIZE;\n-\t\tif (reta_conf[idx].mask & (1ULL << shift))\n-\t\t\tlut[i] = reta_conf[idx].reta[shift];\n-\t}\n-\tret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);\n-\n-out:\n-\trte_free(lut);\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\t uint16_t reta_size)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tuint16_t i, idx, shift;\n-\tuint8_t *lut;\n-\tint ret;\n-\n-\tif (reta_size != ETH_RSS_RETA_SIZE_64) {\n-\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n-\t\t\t\"(%d) doesn't match the number of hardware can \"\n-\t\t\t\"support (%d)\", reta_size, ETH_RSS_RETA_SIZE_64);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tlut = rte_zmalloc(\"i40e_rss_lut\", reta_size, 0);\n-\tif (!lut) {\n-\t\tPMD_DRV_LOG(ERR, \"No memory can be allocated\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);\n-\tif (ret)\n-\t\tgoto out;\n-\tfor (i = 0; i < reta_size; i++) {\n-\t\tidx = i / RTE_RETA_GROUP_SIZE;\n-\t\tshift = i % RTE_RETA_GROUP_SIZE;\n-\t\tif (reta_conf[idx].mask & (1ULL << shift))\n-\t\t\treta_conf[idx].reta[shift] = lut[i];\n-\t}\n-\n-out:\n-\trte_free(lut);\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)\n-{\n-\tstruct i40e_vf *vf = I40E_VSI_TO_VF(vsi);\n-\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n-\tint ret = 0;\n-\n-\tif (!key || key_len == 0) {\n-\t\tPMD_DRV_LOG(DEBUG, \"No key to be configured\");\n-\t\treturn 0;\n-\t} else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *\n-\t\tsizeof(uint32_t)) {\n-\t\tPMD_DRV_LOG(ERR, \"Invalid key length %u\", key_len);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {\n-\t\tstruct i40e_aqc_get_set_rss_key_data *key_dw =\n-\t\t\t(struct i40e_aqc_get_set_rss_key_data *)key;\n-\n-\t\tret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);\n-\t\tif (ret)\n-\t\t\tPMD_INIT_LOG(ERR, \"Failed to configure RSS key \"\n-\t\t\t\t \"via AQ\");\n-\t} else {\n-\t\tuint32_t *hash_key = (uint32_t *)key;\n-\t\tuint16_t i;\n-\n-\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n-\t\t\ti40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);\n-\t\tI40EVF_WRITE_FLUSH(hw);\n-\t}\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)\n-{\n-\tstruct i40e_vf *vf = I40E_VSI_TO_VF(vsi);\n-\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n-\tint ret;\n-\n-\tif (!key || !key_len)\n-\t\treturn -EINVAL;\n-\n-\tif (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {\n-\t\tret = i40e_aq_get_rss_key(hw, vsi->vsi_id,\n-\t\t\t(struct i40e_aqc_get_set_rss_key_data *)key);\n-\t\tif (ret) {\n-\t\t\tPMD_INIT_LOG(ERR, \"Failed to get RSS key via AQ\");\n-\t\t\treturn ret;\n-\t\t}\n-\t} else {\n-\t\tuint32_t *key_dw = (uint32_t *)key;\n-\t\tuint16_t i;\n-\n-\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n-\t\t\tkey_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));\n-\t}\n-\t*key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)\n-{\n-\tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n-\tuint64_t hena;\n-\tint ret;\n-\n-\tret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,\n-\t\t\t\t rss_conf->rss_key_len);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\thena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);\n-\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n-\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n-\tI40EVF_WRITE_FLUSH(hw);\n-\n-\treturn 0;\n-}\n-\n-static void\n-i40evf_disable_rss(struct i40e_vf *vf)\n-{\n-\tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n-\n-\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);\n-\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);\n-\tI40EVF_WRITE_FLUSH(hw);\n-}\n-\n-static int\n-i40evf_config_rss(struct i40e_vf *vf)\n-{\n-\tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n-\tstruct rte_eth_rss_conf rss_conf;\n-\tuint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;\n-\tuint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;\n-\tuint16_t num;\n-\tuint8_t *lut_info;\n-\tint ret;\n-\n-\tif (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {\n-\t\ti40evf_disable_rss(vf);\n-\t\tPMD_DRV_LOG(DEBUG, \"RSS not configured\");\n-\t\treturn 0;\n-\t}\n-\n-\tnum = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);\n-\t/* Fill out the look up table */\n-\tif (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {\n-\t\tfor (i = 0, j = 0; i < nb_q; i++, j++) {\n-\t\t\tif (j >= num)\n-\t\t\t\tj = 0;\n-\t\t\tlut = (lut << 8) | j;\n-\t\t\tif ((i & 3) == 3)\n-\t\t\t\tI40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);\n-\t\t}\n-\t} else {\n-\t\tlut_info = rte_zmalloc(\"i40e_rss_lut\", rss_lut_size, 0);\n-\t\tif (!lut_info) {\n-\t\t\tPMD_DRV_LOG(ERR, \"No memory can be allocated\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\n-\t\tfor (i = 0; i < rss_lut_size; i++)\n-\t\t\tlut_info[i] = i % num;\n-\n-\t\tret = i40evf_set_rss_lut(&vf->vsi, lut_info,\n-\t\t\t\t\t rss_lut_size);\n-\t\trte_free(lut_info);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\trss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;\n-\tif ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {\n-\t\ti40evf_disable_rss(vf);\n-\t\tPMD_DRV_LOG(DEBUG, \"No hash flag is set\");\n-\t\treturn 0;\n-\t}\n-\n-\tif (rss_conf.rss_key == NULL || rss_conf.rss_key_len <\n-\t\t(I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {\n-\t\t/* Calculate the default hash key */\n-\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n-\t\t\trss_key_default[i] = (uint32_t)rte_rand();\n-\t\trss_conf.rss_key = (uint8_t *)rss_key_default;\n-\t\trss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *\n-\t\t\tsizeof(uint32_t);\n-\t}\n-\n-\treturn i40evf_hw_rss_hash_set(vf, &rss_conf);\n-}\n-\n-static int\n-i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n-\t\t\t struct rte_eth_rss_conf *rss_conf)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tuint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;\n-\tuint64_t hena;\n-\n-\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));\n-\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;\n-\n-\tif (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */\n-\t\tif (rss_hf != 0) /* Enable RSS */\n-\t\t\treturn -EINVAL;\n-\t\treturn 0;\n-\t}\n-\n-\t/* RSS enabled */\n-\tif (rss_hf == 0) /* Disable RSS */\n-\t\treturn -EINVAL;\n-\n-\treturn i40evf_hw_rss_hash_set(vf, rss_conf);\n-}\n-\n-static int\n-i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n-\t\t\t struct rte_eth_rss_conf *rss_conf)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tuint64_t hena;\n-\n-\ti40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,\n-\t\t\t &rss_conf->rss_key_len);\n-\n-\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));\n-\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;\n-\trss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tstruct rte_eth_dev_data *dev_data = vf->dev_data;\n-\tuint32_t frame_size = mtu + I40E_ETH_OVERHEAD;\n-\tint ret = 0;\n-\n-\t/* check if mtu is within the allowed range */\n-\tif (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)\n-\t\treturn -EINVAL;\n-\n-\t/* mtu setting is forbidden if port is start */\n-\tif (dev_data->dev_started) {\n-\t\tPMD_DRV_LOG(ERR, \"port %d must be stopped before configuration\",\n-\t\t\t dev_data->port_id);\n-\t\treturn -EBUSY;\n-\t}\n-\n-\tif (frame_size > I40E_ETH_MAX_LEN)\n-\t\tdev_data->dev_conf.rxmode.offloads |=\n-\t\t\tDEV_RX_OFFLOAD_JUMBO_FRAME;\n-\telse\n-\t\tdev_data->dev_conf.rxmode.offloads &=\n-\t\t\t~DEV_RX_OFFLOAD_JUMBO_FRAME;\n-\tdev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;\n-\n-\treturn ret;\n-}\n-\n-static int\n-i40evf_set_default_mac_addr(struct rte_eth_dev *dev,\n-\t\t\t struct rte_ether_addr *mac_addr)\n-{\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct rte_ether_addr *old_addr;\n-\tint ret;\n-\n-\told_addr = (struct rte_ether_addr *)hw->mac.addr;\n-\n-\tif (!rte_is_valid_assigned_ether_addr(mac_addr)) {\n-\t\tPMD_DRV_LOG(ERR, \"Tried to set invalid MAC address.\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (rte_is_same_ether_addr(old_addr, mac_addr))\n-\t\treturn 0;\n-\n-\ti40evf_add_del_eth_addr(dev, old_addr, FALSE, VIRTCHNL_ETHER_ADDR_PRIMARY);\n-\n-\tret = i40evf_add_del_eth_addr(dev, mac_addr, TRUE, VIRTCHNL_ETHER_ADDR_PRIMARY);\n-\tif (ret)\n-\t\treturn -EIO;\n-\n-\trte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_ether_addr *mc_addrs,\n-\t\t\tuint32_t mc_addrs_num, bool add)\n-{\n-\tstruct virtchnl_ether_addr_list *list;\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tuint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +\n-\t\t(I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];\n-\tuint32_t i;\n-\tint err;\n-\tstruct vf_cmd_info args;\n-\n-\tif (mc_addrs == NULL || mc_addrs_num == 0)\n-\t\treturn 0;\n-\n-\tif (mc_addrs_num > I40E_NUM_MACADDR_MAX)\n-\t\treturn -EINVAL;\n-\n-\tlist = (struct virtchnl_ether_addr_list *)cmd_buffer;\n-\tlist->vsi_id = vf->vsi_res->vsi_id;\n-\tlist->num_elements = mc_addrs_num;\n-\n-\tfor (i = 0; i < mc_addrs_num; i++) {\n-\t\tif (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid mac:%x:%x:%x:%x:%x:%x\",\n-\t\t\t\t mc_addrs[i].addr_bytes[0],\n-\t\t\t\t mc_addrs[i].addr_bytes[1],\n-\t\t\t\t mc_addrs[i].addr_bytes[2],\n-\t\t\t\t mc_addrs[i].addr_bytes[3],\n-\t\t\t\t mc_addrs[i].addr_bytes[4],\n-\t\t\t\t mc_addrs[i].addr_bytes[5]);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tmemcpy(list->list[i].addr, mc_addrs[i].addr_bytes,\n-\t\t\tsizeof(list->list[i].addr));\n-\t\tlist->list[i].type = VIRTCHNL_ETHER_ADDR_EXTRA;\n-\t}\n-\n-\targs.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;\n-\targs.in_args = cmd_buffer;\n-\targs.in_args_size = sizeof(struct virtchnl_ether_addr_list) +\n-\t\ti * sizeof(struct virtchnl_ether_addr);\n-\targs.out_buffer = vf->aq_resp;\n-\targs.out_size = I40E_AQ_BUF_SZ;\n-\terr = i40evf_execute_vf_cmd(dev, &args);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"fail to execute command %s\",\n-\t\t\tadd ? \"OP_ADD_ETH_ADDR\" : \"OP_DEL_ETH_ADDR\");\n-\t\treturn err;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40evf_set_mc_addr_list(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_ether_addr *mc_addrs,\n-\t\t\tuint32_t mc_addrs_num)\n-{\n-\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n-\tint err;\n-\n-\t/* flush previous addresses */\n-\terr = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,\n-\t\t\t\tFALSE);\n-\tif (err)\n-\t\treturn err;\n-\n-\tvf->mc_addrs_num = 0;\n-\n-\t/* add new ones */\n-\terr = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,\n-\t\t\t\t\tTRUE);\n-\tif (err)\n-\t\treturn err;\n-\n-\tvf->mc_addrs_num = mc_addrs_num;\n-\tmemcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));\n-\n-\treturn 0;\n-}\n-\n-bool\n-is_i40evf_supported(struct rte_eth_dev *dev)\n-{\n-\treturn is_device_supported(dev, &rte_i40evf_pmd);\n-}\ndiff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build\nindex 3c931afeea..efc5f93e35 100644\n--- a/drivers/net/i40e/meson.build\n+++ b/drivers/net/i40e/meson.build\n@@ -12,7 +12,6 @@ objs = [base_objs]\n sources = files(\n 'i40e_ethdev.c',\n 'i40e_rxtx.c',\n- 'i40e_ethdev_vf.c',\n 'i40e_pf.c',\n 'i40e_fdir.c',\n 'i40e_flow.c',\ndiff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c\nindex 2e34140c5b..c15e423656 100644\n--- a/drivers/net/i40e/rte_pmd_i40e.c\n+++ b/drivers/net/i40e/rte_pmd_i40e.c\n@@ -2410,8 +2410,7 @@ int rte_pmd_i40e_flow_type_mapping_reset(uint16_t port)\n \n \tdev = &rte_eth_devices[port];\n \n-\tif (!is_i40e_supported(dev) &&\n-\t !is_i40evf_supported(dev))\n+\tif (!is_i40e_supported(dev))\n \t\treturn -ENOTSUP;\n \n \ti40e_set_default_pctype_table(dev);\n@@ -2431,8 +2430,7 @@ int rte_pmd_i40e_flow_type_mapping_get(\n \n \tdev = &rte_eth_devices[port];\n \n-\tif (!is_i40e_supported(dev) &&\n-\t !is_i40evf_supported(dev))\n+\tif (!is_i40e_supported(dev))\n \t\treturn -ENOTSUP;\n \n \tad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n@@ -2460,8 +2458,7 @@ rte_pmd_i40e_flow_type_mapping_update(\n \n \tdev = &rte_eth_devices[port];\n \n-\tif (!is_i40e_supported(dev) &&\n-\t !is_i40evf_supported(dev))\n+\tif (!is_i40e_supported(dev))\n \t\treturn -ENOTSUP;\n \n \tif (count > I40E_FLOW_TYPE_MAX)\n", "prefixes": [ "1/3" ] }