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GET /api/patches/96840/?format=api
{ "id": 96840, "url": "http://patches.dpdk.org/api/patches/96840/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210812102333.156686-1-radhac@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210812102333.156686-1-radhac@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210812102333.156686-1-radhac@marvell.com", "date": "2021-08-12T10:23:33", "name": "[2/2] drivers/raw: remove octeontx2-ep driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0aef5748c2e1da1226007aec2f55d03c50ef81fc", "submitter": { "id": 2007, "url": "http://patches.dpdk.org/api/people/2007/?format=api", "name": "Radha Chintakuntla", "email": "radhac@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210812102333.156686-1-radhac@marvell.com/mbox/", "series": [ { "id": 18260, "url": "http://patches.dpdk.org/api/series/18260/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18260", "date": "2021-08-12T10:23:09", "name": "[1/2] drivers/raw: remove octeontx2-dma driver", "version": 1, "mbox": "http://patches.dpdk.org/series/18260/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/96840/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/96840/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1AE2EA0C56;\n\tThu, 12 Aug 2021 12:23:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F31054069E;\n\tThu, 12 Aug 2021 12:23:40 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A1EEF40042\n for <dev@dpdk.org>; Thu, 12 Aug 2021 12:23:38 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 17CABTMe023550; Thu, 12 Aug 2021 03:23:37 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3acrnp1kf3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 12 Aug 2021 03:23:37 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 12 Aug 2021 03:23:35 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 12 Aug 2021 03:23:35 -0700", "from rchin-dellt430.marvell.com (rchin-dellt430.marvell.com\n [10.85.176.141])\n by maili.marvell.com (Postfix) with ESMTP id 8122E3F703F;\n Thu, 12 Aug 2021 03:23:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=h1u+a2ppV+xadn4bDjIqGZCCU3ymEDsLqE/DS81J+e4=;\n b=YnNrjH4nLJCNMLmQ/eQSo2HqWOhUDKRy9p8+b7oXwpDNymCmEYsyIT9uommMtXKn5ibF\n fixo8ohquwa+RBescbNLPwgtLuxJOAnmeJxNTd9Bll7JtE9zZ+LKnpmDYIQ+vU4z03U8\n MSXkyYpavpm/tvEm3K2Shqztqh6onKGu41hWC7YaMAPAoKGaPYvr1WJ4FdU6cRfM77gH\n +kngyItNP3wYfD2MchMf3AMHhps9DwMky9I2a5Bs6JfdYe319T/3YGyXrWr7zdyfmvxi\n obOoiwjPat8PRbmMzrkYe8MoY1GgsYdIvEiSx4EbG5Ms89PIXjMli2knW6USzIUJI2QT qw==", "From": "Radha Mohan Chintakuntla <radhac@marvell.com>", "To": "<vburru@marvell.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <sburla@marvell.com>, <jerinj@marvell.com>, \"Radha Mohan\n Chintakuntla\" <radhac@marvell.com>", "Date": "Thu, 12 Aug 2021 03:23:33 -0700", "Message-ID": "<20210812102333.156686-1-radhac@marvell.com>", "X-Mailer": "git-send-email 2.24.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "8zEq2PDvFIlmwxBB0CecOC-7znkBwu6S", "X-Proofpoint-ORIG-GUID": "8zEq2PDvFIlmwxBB0CecOC-7znkBwu6S", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-08-12_03:2021-08-11,\n 2021-08-12 signatures=0", "Subject": "[dpdk-dev] [PATCH 2/2] drivers/raw: remove octeontx2-ep driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Removing the rawdev based octeontx2-ep driver as the dependent\ncommon/octeontx2 will soon be going away. Moreover this driver is no\nlonger required as the net/octeontx_ep driver is sufficient.\n\nSigned-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>\n---\n MAINTAINERS | 6 -\n doc/guides/rawdevs/octeontx2_ep.rst | 82 ---\n drivers/raw/meson.build | 1 -\n drivers/raw/octeontx2_ep/meson.build | 11 -\n drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------\n drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h | 52 --\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------\n drivers/raw/octeontx2_ep/otx2_ep_test.c | 172 -----\n drivers/raw/octeontx2_ep/otx2_ep_vf.c | 475 ------------\n drivers/raw/octeontx2_ep/otx2_ep_vf.h | 10 -\n drivers/raw/octeontx2_ep/version.map | 3 -\n 12 files changed, 2519 deletions(-)\n delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst\n delete mode 100644 drivers/raw/octeontx2_ep/meson.build\n delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\n delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h\n delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\n delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\n delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c\n delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c\n delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h\n delete mode 100644 drivers/raw/octeontx2_ep/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 9f9aa37c68..1d6a408f49 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>\n F: doc/guides/rawdevs/cnxk_bphy.rst\n F: drivers/raw/cnxk_bphy/\n \n-Marvell OCTEON TX2 EP\n-M: Radha Mohan Chintakuntla <radhac@marvell.com>\n-M: Veerasenareddy Burru <vburru@marvell.com>\n-F: drivers/raw/octeontx2_ep/\n-F: doc/guides/rawdevs/octeontx2_ep.rst\n-\n NTB\n M: Xiaoyun Li <xiaoyun.li@intel.com>\n M: Jingjing Wu <jingjing.wu@intel.com>\ndiff --git a/doc/guides/rawdevs/octeontx2_ep.rst b/doc/guides/rawdevs/octeontx2_ep.rst\ndeleted file mode 100644\nindex fb9d346ccf..0000000000\n--- a/doc/guides/rawdevs/octeontx2_ep.rst\n+++ /dev/null\n@@ -1,82 +0,0 @@\n-.. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2019 Marvell International Ltd.\n-\n-Marvell OCTEON TX2 End Point Rawdev Driver\n-==========================================\n-\n-OCTEON TX2 has an internal SDP unit which provides End Point mode of operation\n-by exposing its IOQs to Host, IOQs are used for packet I/O between Host and\n-OCTEON TX2. Each OCTEON TX2 SDP PF supports a max of 128 VFs and Each VF is\n-associated with a set of IOQ pairs.\n-\n-Features\n---------\n-\n-This OCTEON TX2 End Point mode PMD supports\n-\n-#. Packet Input - Host to OCTEON TX2 with direct data instruction mode.\n-\n-#. Packet Output - OCTEON TX2 to Host with info pointer mode.\n-\n-\n-Initialization\n---------------\n-\n-The number of SDP VFs enabled, can be controlled by setting sysfs\n-entry `sriov_numvfs` for the corresponding PF driver.\n-\n-.. code-block:: console\n-\n- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-ep/0000\\:04\\:00.0/sriov_numvfs\n-\n-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be\n-bound to vfio-pci driver.\n-\n-Device Setup\n-------------\n-\n-The OCTEON TX2 SDP End Point VF devices will need to be bound to a\n-user-space IO driver for use. The script ``dpdk-devbind.py`` script\n-included with DPDK can be used to view the state of the devices and to bind\n-them to a suitable DPDK-supported kernel driver. When querying the status\n-of the devices, they will appear under the category of \"Misc (rawdev)\n-devices\", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be\n-used to see the state of those devices alone.\n-\n-Device Configuration\n---------------------\n-\n-Configuring SDP EP rawdev device is done using the ``rte_rawdev_configure()``\n-API, which takes the mempool as parameter. PMD uses this pool to send/receive\n-packets to/from the HW.\n-\n-The following code shows how the device is configured\n-\n-.. code-block:: c\n-\n- struct sdp_rawdev_info config = {0};\n- struct rte_rawdev_info rdev_info = {.dev_private = &config};\n- config.enqdeq_mpool = (void *)rte_mempool_create(...);\n-\n- rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info,\n- sizeof(config));\n-\n-Performing Data Transfer\n-------------------------\n-\n-To perform data transfer using SDP VF EP rawdev devices use standard\n-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.\n-\n-Self test\n----------\n-\n-On EAL initialization, SDP VF devices will be probed and populated into the\n-raw devices. The rawdev ID of the device can be obtained using\n-\n-* Invoke ``rte_rawdev_get_dev_id(\"SDPEP:x\")`` from the test application\n- where x is the VF device's bus id specified in \"bus:device.func\"(BDF)\n- format. Use this index for further rawdev function calls.\n-\n-* The driver's selftest rawdev API can be used to verify the SDP EP mode\n- functional tests which can send/receive the raw data packets to/from the\n- EP device.\ndiff --git a/drivers/raw/meson.build b/drivers/raw/meson.build\nindex f25d5f322c..87694a758e 100644\n--- a/drivers/raw/meson.build\n+++ b/drivers/raw/meson.build\n@@ -12,7 +12,6 @@ drivers = [\n 'ifpga',\n 'ioat',\n 'ntb',\n- 'octeontx2_ep',\n 'skeleton',\n ]\n std_deps = ['rawdev']\ndiff --git a/drivers/raw/octeontx2_ep/meson.build b/drivers/raw/octeontx2_ep/meson.build\ndeleted file mode 100644\nindex 8d7c69aa3c..0000000000\n--- a/drivers/raw/octeontx2_ep/meson.build\n+++ /dev/null\n@@ -1,11 +0,0 @@\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(C) 2019 Marvell International Ltd.\n-#\n-\n-deps += ['bus_pci', 'common_octeontx2', 'rawdev']\n-sources = files(\n- 'otx2_ep_enqdeq.c',\n- 'otx2_ep_rawdev.c',\n- 'otx2_ep_test.c',\n- 'otx2_ep_vf.c',\n-)\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\ndeleted file mode 100644\nindex d04e957d82..0000000000\n--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\n+++ /dev/null\n@@ -1,846 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <string.h>\n-#include <unistd.h>\n-#include <dirent.h>\n-#include <fcntl.h>\n-\n-#include <rte_bus.h>\n-#include <rte_bus_pci.h>\n-#include <rte_eal.h>\n-#include <rte_lcore.h>\n-#include <rte_mempool.h>\n-#include <rte_pci.h>\n-\n-#include <rte_common.h>\n-#include <rte_rawdev.h>\n-#include <rte_rawdev_pmd.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_ep_enqdeq.h\"\n-\n-static void\n-sdp_dmazone_free(const struct rte_memzone *mz)\n-{\n-\tconst struct rte_memzone *mz_tmp;\n-\tint ret = 0;\n-\n-\tif (mz == NULL) {\n-\t\totx2_err(\"Memzone %s : NULL\", mz->name);\n-\t\treturn;\n-\t}\n-\n-\tmz_tmp = rte_memzone_lookup(mz->name);\n-\tif (mz_tmp == NULL) {\n-\t\totx2_err(\"Memzone %s Not Found\", mz->name);\n-\t\treturn;\n-\t}\n-\n-\tret = rte_memzone_free(mz);\n-\tif (ret)\n-\t\totx2_err(\"Memzone free failed : ret = %d\", ret);\n-\n-}\n-\n-/* Free IQ resources */\n-int\n-sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no)\n-{\n-\tstruct sdp_instr_queue *iq;\n-\n-\tiq = sdpvf->instr_queue[iq_no];\n-\tif (iq == NULL) {\n-\t\totx2_err(\"Invalid IQ[%d]\\n\", iq_no);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\trte_free(iq->req_list);\n-\tiq->req_list = NULL;\n-\n-\tif (iq->iq_mz) {\n-\t\tsdp_dmazone_free(iq->iq_mz);\n-\t\tiq->iq_mz = NULL;\n-\t}\n-\n-\trte_free(sdpvf->instr_queue[iq_no]);\n-\tsdpvf->instr_queue[iq_no] = NULL;\n-\n-\tsdpvf->num_iqs--;\n-\n-\totx2_info(\"IQ[%d] is deleted\", iq_no);\n-\n-\treturn 0;\n-}\n-\n-/* IQ initialization */\n-static int\n-sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)\n-{\n-\tconst struct sdp_config *conf;\n-\tstruct sdp_instr_queue *iq;\n-\tuint32_t q_size;\n-\n-\tconf = sdpvf->conf;\n-\tiq = sdpvf->instr_queue[iq_no];\n-\tq_size = conf->iq.instr_type * conf->num_iqdef_descs;\n-\n-\t/* IQ memory creation for Instruction submission to OCTEON TX2 */\n-\tiq->iq_mz = rte_memzone_reserve_aligned(\"iqmz\",\n-\t\t\t\t\tq_size,\n-\t\t\t\t\trte_socket_id(),\n-\t\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n-\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n-\tif (iq->iq_mz == NULL) {\n-\t\totx2_err(\"IQ[%d] memzone alloc failed\", iq_no);\n-\t\tgoto iq_init_fail;\n-\t}\n-\n-\tiq->base_addr_dma = iq->iq_mz->iova;\n-\tiq->base_addr = (uint8_t *)iq->iq_mz->addr;\n-\n-\tif (conf->num_iqdef_descs & (conf->num_iqdef_descs - 1)) {\n-\t\totx2_err(\"IQ[%d] descs not in power of 2\", iq_no);\n-\t\tgoto iq_init_fail;\n-\t}\n-\n-\tiq->nb_desc = conf->num_iqdef_descs;\n-\n-\t/* Create a IQ request list to hold requests that have been\n-\t * posted to OCTEON TX2. This list will be used for freeing the IQ\n-\t * data buffer(s) later once the OCTEON TX2 fetched the requests.\n-\t */\n-\tiq->req_list = rte_zmalloc_socket(\"request_list\",\n-\t\t\t(iq->nb_desc * SDP_IQREQ_LIST_SIZE),\n-\t\t\tRTE_CACHE_LINE_SIZE,\n-\t\t\trte_socket_id());\n-\tif (iq->req_list == NULL) {\n-\t\totx2_err(\"IQ[%d] req_list alloc failed\", iq_no);\n-\t\tgoto iq_init_fail;\n-\t}\n-\n-\totx2_info(\"IQ[%d]: base: %p basedma: %lx count: %d\",\n-\t\t iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,\n-\t\t iq->nb_desc);\n-\n-\tiq->sdp_dev = sdpvf;\n-\tiq->q_no = iq_no;\n-\tiq->fill_cnt = 0;\n-\tiq->host_write_index = 0;\n-\tiq->otx_read_index = 0;\n-\tiq->flush_index = 0;\n-\n-\t/* Initialize the spinlock for this instruction queue */\n-\trte_spinlock_init(&iq->lock);\n-\trte_spinlock_init(&iq->post_lock);\n-\n-\trte_atomic64_clear(&iq->iq_flush_running);\n-\n-\tsdpvf->io_qmask.iq |= (1ull << iq_no);\n-\n-\t/* Set 32B/64B mode for each input queue */\n-\tif (conf->iq.instr_type == 64)\n-\t\tsdpvf->io_qmask.iq64B |= (1ull << iq_no);\n-\n-\tiq->iqcmd_64B = (conf->iq.instr_type == 64);\n-\n-\t/* Set up IQ registers */\n-\tsdpvf->fn_list.setup_iq_regs(sdpvf, iq_no);\n-\n-\treturn 0;\n-\n-iq_init_fail:\n-\treturn -ENOMEM;\n-\n-}\n-\n-int\n-sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no)\n-{\n-\tstruct sdp_instr_queue *iq;\n-\n-\tiq = (struct sdp_instr_queue *)rte_zmalloc(\"sdp_IQ\", sizeof(*iq),\n-\t\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n-\tif (iq == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tsdpvf->instr_queue[iq_no] = iq;\n-\n-\tif (sdp_init_instr_queue(sdpvf, iq_no)) {\n-\t\totx2_err(\"IQ init is failed\");\n-\t\tgoto delete_IQ;\n-\t}\n-\totx2_info(\"IQ[%d] is created.\", sdpvf->num_iqs);\n-\n-\tsdpvf->num_iqs++;\n-\n-\n-\treturn 0;\n-\n-delete_IQ:\n-\tsdp_delete_iqs(sdpvf, iq_no);\n-\treturn -ENOMEM;\n-}\n-\n-static void\n-sdp_droq_reset_indices(struct sdp_droq *droq)\n-{\n-\tdroq->read_idx = 0;\n-\tdroq->write_idx = 0;\n-\tdroq->refill_idx = 0;\n-\tdroq->refill_count = 0;\n-\trte_atomic64_set(&droq->pkts_pending, 0);\n-}\n-\n-static void\n-sdp_droq_destroy_ring_buffers(struct sdp_device *sdpvf,\n-\t\t\t\tstruct sdp_droq *droq)\n-{\n-\tuint32_t idx;\n-\n-\tfor (idx = 0; idx < droq->nb_desc; idx++) {\n-\t\tif (droq->recv_buf_list[idx].buffer) {\n-\t\t\trte_mempool_put(sdpvf->enqdeq_mpool,\n-\t\t\t\tdroq->recv_buf_list[idx].buffer);\n-\n-\t\t\tdroq->recv_buf_list[idx].buffer = NULL;\n-\t\t}\n-\t}\n-\n-\tsdp_droq_reset_indices(droq);\n-}\n-\n-/* Free OQs resources */\n-int\n-sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no)\n-{\n-\tstruct sdp_droq *droq;\n-\n-\tdroq = sdpvf->droq[oq_no];\n-\tif (droq == NULL) {\n-\t\totx2_err(\"Invalid droq[%d]\", oq_no);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tsdp_droq_destroy_ring_buffers(sdpvf, droq);\n-\trte_free(droq->recv_buf_list);\n-\tdroq->recv_buf_list = NULL;\n-\n-\tif (droq->info_mz) {\n-\t\tsdp_dmazone_free(droq->info_mz);\n-\t\tdroq->info_mz = NULL;\n-\t}\n-\n-\tif (droq->desc_ring_mz) {\n-\t\tsdp_dmazone_free(droq->desc_ring_mz);\n-\t\tdroq->desc_ring_mz = NULL;\n-\t}\n-\n-\tmemset(droq, 0, SDP_DROQ_SIZE);\n-\n-\trte_free(sdpvf->droq[oq_no]);\n-\tsdpvf->droq[oq_no] = NULL;\n-\n-\tsdpvf->num_oqs--;\n-\n-\totx2_info(\"OQ[%d] is deleted\", oq_no);\n-\treturn 0;\n-}\n-\n-static int\n-sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,\n-\t\tstruct sdp_droq *droq)\n-{\n-\tstruct sdp_droq_desc *desc_ring = droq->desc_ring;\n-\tuint32_t idx;\n-\tvoid *buf;\n-\n-\tfor (idx = 0; idx < droq->nb_desc; idx++) {\n-\t\tif (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||\n-\t\t (buf == NULL)) {\n-\t\t\totx2_err(\"OQ buffer alloc failed\");\n-\t\t\tdroq->stats.rx_alloc_failure++;\n-\t\t\t/* sdp_droq_destroy_ring_buffers(droq);*/\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\n-\t\tdroq->recv_buf_list[idx].buffer = buf;\n-\t\tdroq->info_list[idx].length = 0;\n-\n-\t\t/* Map ring buffers into memory */\n-\t\tdesc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +\n-\t\t\t(idx * SDP_DROQ_INFO_SIZE));\n-\n-\t\tdesc_ring[idx].buffer_ptr = rte_mem_virt2iova(buf);\n-\t}\n-\n-\tsdp_droq_reset_indices(droq);\n-\n-\treturn 0;\n-}\n-\n-static void *\n-sdp_alloc_info_buffer(struct sdp_device *sdpvf __rte_unused,\n-\tstruct sdp_droq *droq)\n-{\n-\tdroq->info_mz = rte_memzone_reserve_aligned(\"OQ_info_list\",\n-\t\t\t\t(droq->nb_desc * SDP_DROQ_INFO_SIZE),\n-\t\t\t\trte_socket_id(),\n-\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n-\t\t\t\tRTE_CACHE_LINE_SIZE);\n-\n-\tif (droq->info_mz == NULL)\n-\t\treturn NULL;\n-\n-\tdroq->info_list_dma = droq->info_mz->iova;\n-\tdroq->info_alloc_size = droq->info_mz->len;\n-\tdroq->info_base_addr = (size_t)droq->info_mz->addr;\n-\n-\treturn droq->info_mz->addr;\n-}\n-\n-/* OQ initialization */\n-static int\n-sdp_init_droq(struct sdp_device *sdpvf, uint32_t q_no)\n-{\n-\tconst struct sdp_config *conf = sdpvf->conf;\n-\tuint32_t c_refill_threshold;\n-\tuint32_t desc_ring_size;\n-\tstruct sdp_droq *droq;\n-\n-\totx2_info(\"OQ[%d] Init start\", q_no);\n-\n-\tdroq = sdpvf->droq[q_no];\n-\tdroq->sdp_dev = sdpvf;\n-\tdroq->q_no = q_no;\n-\n-\tc_refill_threshold = conf->oq.refill_threshold;\n-\tdroq->nb_desc = conf->num_oqdef_descs;\n-\tdroq->buffer_size = conf->oqdef_buf_size;\n-\n-\t/* OQ desc_ring set up */\n-\tdesc_ring_size = droq->nb_desc * SDP_DROQ_DESC_SIZE;\n-\tdroq->desc_ring_mz = rte_memzone_reserve_aligned(\"sdp_oqmz\",\n-\t\t\t\t\t\tdesc_ring_size,\n-\t\t\t\t\t\trte_socket_id(),\n-\t\t\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n-\t\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n-\n-\tif (droq->desc_ring_mz == NULL) {\n-\t\totx2_err(\"OQ:%d desc_ring allocation failed\", q_no);\n-\t\tgoto init_droq_fail;\n-\t}\n-\n-\tdroq->desc_ring_dma = droq->desc_ring_mz->iova;\n-\tdroq->desc_ring = (struct sdp_droq_desc *)droq->desc_ring_mz->addr;\n-\n-\totx2_sdp_dbg(\"OQ[%d]: desc_ring: virt: 0x%p, dma: %lx\",\n-\t\t q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);\n-\totx2_sdp_dbg(\"OQ[%d]: num_desc: %d\", q_no, droq->nb_desc);\n-\n-\n-\t/* OQ info_list set up */\n-\tdroq->info_list = sdp_alloc_info_buffer(sdpvf, droq);\n-\tif (droq->info_list == NULL) {\n-\t\totx2_err(\"memory allocation failed for OQ[%d] info_list\", q_no);\n-\t\tgoto init_droq_fail;\n-\t}\n-\n-\t/* OQ buf_list set up */\n-\tdroq->recv_buf_list = rte_zmalloc_socket(\"recv_buf_list\",\n-\t\t\t\t(droq->nb_desc * SDP_DROQ_RECVBUF_SIZE),\n-\t\t\t\t RTE_CACHE_LINE_SIZE, rte_socket_id());\n-\tif (droq->recv_buf_list == NULL) {\n-\t\totx2_err(\"OQ recv_buf_list alloc failed\");\n-\t\tgoto init_droq_fail;\n-\t}\n-\n-\tif (sdp_droq_setup_ring_buffers(sdpvf, droq))\n-\t\tgoto init_droq_fail;\n-\n-\tdroq->refill_threshold = c_refill_threshold;\n-\trte_spinlock_init(&droq->lock);\n-\n-\n-\t/* Set up OQ registers */\n-\tsdpvf->fn_list.setup_oq_regs(sdpvf, q_no);\n-\n-\tsdpvf->io_qmask.oq |= (1ull << q_no);\n-\n-\treturn 0;\n-\n-init_droq_fail:\n-\treturn -ENOMEM;\n-}\n-\n-/* OQ configuration and setup */\n-int\n-sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no)\n-{\n-\tstruct sdp_droq *droq;\n-\n-\t/* Allocate new droq. */\n-\tdroq = (struct sdp_droq *)rte_zmalloc(\"sdp_OQ\",\n-\t\t\t\tsizeof(*droq), RTE_CACHE_LINE_SIZE);\n-\tif (droq == NULL) {\n-\t\totx2_err(\"Droq[%d] Creation Failed\", oq_no);\n-\t\treturn -ENOMEM;\n-\t}\n-\tsdpvf->droq[oq_no] = droq;\n-\n-\tif (sdp_init_droq(sdpvf, oq_no)) {\n-\t\totx2_err(\"Droq[%d] Initialization failed\", oq_no);\n-\t\tgoto delete_OQ;\n-\t}\n-\totx2_info(\"OQ[%d] is created.\", oq_no);\n-\n-\tsdpvf->num_oqs++;\n-\n-\treturn 0;\n-\n-delete_OQ:\n-\tsdp_delete_oqs(sdpvf, oq_no);\n-\treturn -ENOMEM;\n-}\n-\n-static inline void\n-sdp_iqreq_delete(struct sdp_device *sdpvf,\n-\t\tstruct sdp_instr_queue *iq, uint32_t idx)\n-{\n-\tuint32_t reqtype;\n-\tvoid *buf;\n-\n-\tbuf = iq->req_list[idx].buf;\n-\treqtype = iq->req_list[idx].reqtype;\n-\n-\tswitch (reqtype) {\n-\tcase SDP_REQTYPE_NORESP:\n-\t\trte_mempool_put(sdpvf->enqdeq_mpool, buf);\n-\t\totx2_sdp_dbg(\"IQ buffer freed at idx[%d]\", idx);\n-\t\tbreak;\n-\n-\tcase SDP_REQTYPE_NORESP_GATHER:\n-\tcase SDP_REQTYPE_NONE:\n-\tdefault:\n-\t\totx2_info(\"This iqreq mode is not supported:%d\", reqtype);\n-\n-\t}\n-\n-\t/* Reset the request list at this index */\n-\tiq->req_list[idx].buf = NULL;\n-\tiq->req_list[idx].reqtype = 0;\n-}\n-\n-static inline void\n-sdp_iqreq_add(struct sdp_instr_queue *iq, void *buf,\n-\t\tuint32_t reqtype)\n-{\n-\tiq->req_list[iq->host_write_index].buf = buf;\n-\tiq->req_list[iq->host_write_index].reqtype = reqtype;\n-\n-\totx2_sdp_dbg(\"IQ buffer added at idx[%d]\", iq->host_write_index);\n-\n-}\n-\n-static void\n-sdp_flush_iq(struct sdp_device *sdpvf,\n-\t\tstruct sdp_instr_queue *iq,\n-\t\tuint32_t pending_thresh __rte_unused)\n-{\n-\tuint32_t instr_processed = 0;\n-\n-\trte_spinlock_lock(&iq->lock);\n-\n-\tiq->otx_read_index = sdpvf->fn_list.update_iq_read_idx(iq);\n-\twhile (iq->flush_index != iq->otx_read_index) {\n-\t\t/* Free the IQ data buffer to the pool */\n-\t\tsdp_iqreq_delete(sdpvf, iq, iq->flush_index);\n-\t\tiq->flush_index =\n-\t\t\tsdp_incr_index(iq->flush_index, 1, iq->nb_desc);\n-\n-\t\tinstr_processed++;\n-\t}\n-\n-\tiq->stats.instr_processed = instr_processed;\n-\trte_atomic64_sub(&iq->instr_pending, instr_processed);\n-\n-\trte_spinlock_unlock(&iq->lock);\n-}\n-\n-static inline void\n-sdp_ring_doorbell(struct sdp_device *sdpvf __rte_unused,\n-\t\tstruct sdp_instr_queue *iq)\n-{\n-\totx2_write64(iq->fill_cnt, iq->doorbell_reg);\n-\n-\t/* Make sure doorbell writes observed by HW */\n-\trte_io_wmb();\n-\tiq->fill_cnt = 0;\n-\n-}\n-\n-static inline int\n-post_iqcmd(struct sdp_instr_queue *iq, uint8_t *iqcmd)\n-{\n-\tuint8_t *iqptr, cmdsize;\n-\n-\t/* This ensures that the read index does not wrap around to\n-\t * the same position if queue gets full before OCTEON TX2 could\n-\t * fetch any instr.\n-\t */\n-\tif (rte_atomic64_read(&iq->instr_pending) >=\n-\t\t\t (int32_t)(iq->nb_desc - 1)) {\n-\t\totx2_err(\"IQ is full, pending:%ld\",\n-\t\t\t (long)rte_atomic64_read(&iq->instr_pending));\n-\n-\t\treturn SDP_IQ_SEND_FAILED;\n-\t}\n-\n-\t/* Copy cmd into iq */\n-\tcmdsize = ((iq->iqcmd_64B) ? 64 : 32);\n-\tiqptr = iq->base_addr + (cmdsize * iq->host_write_index);\n-\n-\trte_memcpy(iqptr, iqcmd, cmdsize);\n-\n-\totx2_sdp_dbg(\"IQ cmd posted @ index:%d\", iq->host_write_index);\n-\n-\t/* Increment the host write index */\n-\tiq->host_write_index =\n-\t\tsdp_incr_index(iq->host_write_index, 1, iq->nb_desc);\n-\n-\tiq->fill_cnt++;\n-\n-\t/* Flush the command into memory. We need to be sure the data\n-\t * is in memory before indicating that the instruction is\n-\t * pending.\n-\t */\n-\trte_smp_wmb();\n-\trte_atomic64_inc(&iq->instr_pending);\n-\n-\t/* SDP_IQ_SEND_SUCCESS */\n-\treturn 0;\n-}\n-\n-\n-static int\n-sdp_send_data(struct sdp_device *sdpvf,\n-\t struct sdp_instr_queue *iq, void *cmd)\n-{\n-\tuint32_t ret;\n-\n-\t/* Lock this IQ command queue before posting instruction */\n-\trte_spinlock_lock(&iq->post_lock);\n-\n-\t/* Submit IQ command */\n-\tret = post_iqcmd(iq, cmd);\n-\n-\tif (ret == SDP_IQ_SEND_SUCCESS) {\n-\t\tsdp_ring_doorbell(sdpvf, iq);\n-\n-\t\tiq->stats.instr_posted++;\n-\t\totx2_sdp_dbg(\"Instr submit success posted: %ld\\n\",\n-\t\t\t (long)iq->stats.instr_posted);\n-\n-\t} else {\n-\t\tiq->stats.instr_dropped++;\n-\t\totx2_err(\"Instr submit failed, dropped: %ld\\n\",\n-\t\t\t (long)iq->stats.instr_dropped);\n-\n-\t}\n-\n-\trte_spinlock_unlock(&iq->post_lock);\n-\n-\treturn ret;\n-}\n-\n-\n-/* Enqueue requests/packets to SDP IQ queue.\n- * returns number of requests enqueued successfully\n- */\n-int\n-sdp_rawdev_enqueue(struct rte_rawdev *rawdev,\n-\t\t struct rte_rawdev_buf **buffers __rte_unused,\n-\t\t unsigned int count, rte_rawdev_obj_t context)\n-{\n-\tstruct sdp_instr_64B *iqcmd;\n-\tstruct sdp_instr_queue *iq;\n-\tstruct sdp_soft_instr *si;\n-\tstruct sdp_device *sdpvf;\n-\n-\tstruct sdp_instr_ih ihx;\n-\n-\tsdpvf = (struct sdp_device *)rawdev->dev_private;\n-\tsi = (struct sdp_soft_instr *)context;\n-\n-\tiq = sdpvf->instr_queue[si->q_no];\n-\n-\tif ((count > 1) || (count < 1)) {\n-\t\totx2_err(\"This mode not supported: req[%d]\", count);\n-\t\tgoto enq_fail;\n-\t}\n-\n-\tmemset(&ihx, 0, sizeof(struct sdp_instr_ih));\n-\n-\tiqcmd = &si->command;\n-\tmemset(iqcmd, 0, sizeof(struct sdp_instr_64B));\n-\n-\tiqcmd->dptr = (uint64_t)si->dptr;\n-\n-\t/* Populate SDP IH */\n-\tihx.pkind = sdpvf->pkind;\n-\tihx.fsz = si->ih.fsz + 8; /* 8B for NIX IH */\n-\tihx.gather = si->ih.gather;\n-\n-\t/* Direct data instruction */\n-\tihx.tlen = si->ih.tlen + ihx.fsz;\n-\n-\tswitch (ihx.gather) {\n-\tcase 0: /* Direct data instr */\n-\t\tihx.tlen = si->ih.tlen + ihx.fsz;\n-\t\tbreak;\n-\n-\tdefault: /* Gather */\n-\t\tswitch (si->ih.gsz) {\n-\t\tcase 0: /* Direct gather instr */\n-\t\t\totx2_err(\"Direct Gather instr : not supported\");\n-\t\t\tgoto enq_fail;\n-\n-\t\tdefault: /* Indirect gather instr */\n-\t\t\totx2_err(\"Indirect Gather instr : not supported\");\n-\t\t\tgoto enq_fail;\n-\t\t}\n-\t}\n-\n-\trte_memcpy(&iqcmd->ih, &ihx, sizeof(uint64_t));\n-\tiqcmd->rptr = (uint64_t)si->rptr;\n-\trte_memcpy(&iqcmd->irh, &si->irh, sizeof(uint64_t));\n-\n-\t/* Swap FSZ(front data) here, to avoid swapping on OCTEON TX2 side */\n-\tsdp_swap_8B_data(&iqcmd->rptr, 1);\n-\tsdp_swap_8B_data(&iqcmd->irh, 1);\n-\n-\totx2_sdp_dbg(\"After swapping\");\n-\totx2_sdp_dbg(\"Word0 [dptr]: 0x%016lx\", (unsigned long)iqcmd->dptr);\n-\totx2_sdp_dbg(\"Word1 [ihtx]: 0x%016lx\", (unsigned long)iqcmd->ih);\n-\totx2_sdp_dbg(\"Word2 [rptr]: 0x%016lx\", (unsigned long)iqcmd->rptr);\n-\totx2_sdp_dbg(\"Word3 [irh]: 0x%016lx\", (unsigned long)iqcmd->irh);\n-\totx2_sdp_dbg(\"Word4 [exhdr[0]]: 0x%016lx\",\n-\t\t\t(unsigned long)iqcmd->exhdr[0]);\n-\n-\tsdp_iqreq_add(iq, si->dptr, si->reqtype);\n-\n-\tif (sdp_send_data(sdpvf, iq, iqcmd)) {\n-\t\totx2_err(\"Data send failed :\");\n-\t\tsdp_iqreq_delete(sdpvf, iq, iq->host_write_index);\n-\t\tgoto enq_fail;\n-\t}\n-\n-\tif (rte_atomic64_read(&iq->instr_pending) >= 1)\n-\t\tsdp_flush_iq(sdpvf, iq, 1 /*(iq->nb_desc / 2)*/);\n-\n-\t/* Return no# of instructions posted successfully. */\n-\treturn count;\n-\n-enq_fail:\n-\treturn SDP_IQ_SEND_FAILED;\n-}\n-\n-static uint32_t\n-sdp_droq_refill(struct sdp_device *sdpvf, struct sdp_droq *droq)\n-{\n-\tstruct sdp_droq_desc *desc_ring;\n-\tuint32_t desc_refilled = 0;\n-\tvoid *buf = NULL;\n-\n-\tdesc_ring = droq->desc_ring;\n-\n-\twhile (droq->refill_count && (desc_refilled < droq->nb_desc)) {\n-\t\t/* If a valid buffer exists (happens if there is no dispatch),\n-\t\t * reuse the buffer, else allocate.\n-\t\t */\n-\t\tif (droq->recv_buf_list[droq->refill_idx].buffer != NULL)\n-\t\t\tbreak;\n-\n-\t\tif (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||\n-\t\t (buf == NULL)) {\n-\t\t\t/* If a buffer could not be allocated, no point in\n-\t\t\t * continuing\n-\t\t\t */\n-\t\t\tdroq->stats.rx_alloc_failure++;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tdroq->recv_buf_list[droq->refill_idx].buffer = buf;\n-\t\tdesc_ring[droq->refill_idx].buffer_ptr = rte_mem_virt2iova(buf);\n-\n-\t\t/* Reset any previous values in the length field. */\n-\t\tdroq->info_list[droq->refill_idx].length = 0;\n-\n-\t\tdroq->refill_idx = sdp_incr_index(droq->refill_idx, 1,\n-\t\t\t\tdroq->nb_desc);\n-\n-\t\tdesc_refilled++;\n-\t\tdroq->refill_count--;\n-\n-\t}\n-\n-\treturn desc_refilled;\n-}\n-\n-static int\n-sdp_droq_read_packet(struct sdp_device *sdpvf __rte_unused,\n-\t\t struct sdp_droq *droq,\n-\t\t struct sdp_droq_pkt *droq_pkt)\n-{\n-\tstruct sdp_droq_info *info;\n-\tuint32_t total_len = 0;\n-\tuint32_t pkt_len = 0;\n-\n-\tinfo = &droq->info_list[droq->read_idx];\n-\tsdp_swap_8B_data((uint64_t *)&info->length, 1);\n-\tif (!info->length) {\n-\t\totx2_err(\"OQ info_list->length[%ld]\", (long)info->length);\n-\t\tgoto oq_read_fail;\n-\t}\n-\n-\t/* Deduce the actual data size */\n-\tinfo->length -= SDP_RH_SIZE;\n-\ttotal_len += (uint32_t)info->length;\n-\n-\totx2_sdp_dbg(\"OQ: pkt_len[%ld], buffer_size %d\",\n-\t\t\t(long)info->length, droq->buffer_size);\n-\tif (info->length > droq->buffer_size) {\n-\t\totx2_err(\"This mode is not supported: pkt_len > buffer_size\");\n-\t\tgoto oq_read_fail;\n-\t}\n-\n-\tif (info->length <= droq->buffer_size) {\n-\t\tpkt_len = (uint32_t)info->length;\n-\t\tdroq_pkt->data = droq->recv_buf_list[droq->read_idx].buffer;\n-\t\tdroq_pkt->len = pkt_len;\n-\n-\t\tdroq->recv_buf_list[droq->read_idx].buffer = NULL;\n-\t\tdroq->read_idx = sdp_incr_index(droq->read_idx,\t1,/* count */\n-\t\t\t\t\t\tdroq->nb_desc /* max rd idx */);\n-\t\tdroq->refill_count++;\n-\n-\t}\n-\n-\tinfo->length = 0;\n-\n-\treturn SDP_OQ_RECV_SUCCESS;\n-\n-oq_read_fail:\n-\treturn SDP_OQ_RECV_FAILED;\n-}\n-\n-static inline uint32_t\n-sdp_check_droq_pkts(struct sdp_droq *droq, uint32_t burst_size)\n-{\n-\tuint32_t min_pkts = 0;\n-\tuint32_t new_pkts;\n-\tuint32_t pkt_count;\n-\n-\t/* Latest available OQ packets */\n-\tpkt_count = rte_read32(droq->pkts_sent_reg);\n-\n-\t/* Newly arrived packets */\n-\tnew_pkts = pkt_count - droq->last_pkt_count;\n-\totx2_sdp_dbg(\"Recvd [%d] new OQ pkts\", new_pkts);\n-\n-\tmin_pkts = (new_pkts > burst_size) ? burst_size : new_pkts;\n-\tif (min_pkts) {\n-\t\trte_atomic64_add(&droq->pkts_pending, min_pkts);\n-\t\t/* Back up the aggregated packet count so far */\n-\t\tdroq->last_pkt_count += min_pkts;\n-\t}\n-\n-\treturn min_pkts;\n-}\n-\n-/* Check for response arrival from OCTEON TX2\n- * returns number of requests completed\n- */\n-int\n-sdp_rawdev_dequeue(struct rte_rawdev *rawdev,\n-\t\t struct rte_rawdev_buf **buffers, unsigned int count,\n-\t\t rte_rawdev_obj_t context __rte_unused)\n-{\n-\tstruct sdp_droq_pkt *oq_pkt;\n-\tstruct sdp_device *sdpvf;\n-\tstruct sdp_droq *droq;\n-\n-\tuint32_t q_no = 0, pkts;\n-\tuint32_t new_pkts;\n-\tuint32_t ret;\n-\n-\tsdpvf = (struct sdp_device *)rawdev->dev_private;\n-\n-\tdroq = sdpvf->droq[q_no];\n-\tif (!droq) {\n-\t\totx2_err(\"Invalid droq[%d]\", q_no);\n-\t\tgoto droq_err;\n-\t}\n-\n-\t/* Grab the lock */\n-\trte_spinlock_lock(&droq->lock);\n-\n-\tnew_pkts = sdp_check_droq_pkts(droq, count);\n-\tif (!new_pkts) {\n-\t\totx2_sdp_dbg(\"Zero new_pkts:%d\", new_pkts);\n-\t\tgoto deq_fail; /* No pkts at this moment */\n-\t}\n-\n-\totx2_sdp_dbg(\"Received new_pkts = %d\", new_pkts);\n-\n-\tfor (pkts = 0; pkts < new_pkts; pkts++) {\n-\n-\t\t/* Push the received pkt to application */\n-\t\toq_pkt = (struct sdp_droq_pkt *)buffers[pkts];\n-\n-\t\tret = sdp_droq_read_packet(sdpvf, droq, oq_pkt);\n-\t\tif (ret) {\n-\t\t\totx2_err(\"DROQ read pakt failed.\");\n-\t\t\tgoto deq_fail;\n-\t\t}\n-\n-\t\t/* Stats */\n-\t\tdroq->stats.pkts_received++;\n-\t\tdroq->stats.bytes_received += oq_pkt->len;\n-\t}\n-\n-\t/* Ack the h/w with no# of pkts read by Host */\n-\trte_write32(pkts, droq->pkts_sent_reg);\n-\trte_io_wmb();\n-\n-\tdroq->last_pkt_count -= pkts;\n-\n-\totx2_sdp_dbg(\"DROQ pkts[%d] pushed to application\", pkts);\n-\n-\t/* Refill DROQ buffers */\n-\tif (droq->refill_count >= 2 /* droq->refill_threshold */) {\n-\t\tint desc_refilled = sdp_droq_refill(sdpvf, droq);\n-\n-\t\t/* Flush the droq descriptor data to memory to be sure\n-\t\t * that when we update the credits the data in memory is\n-\t\t * accurate.\n-\t\t */\n-\t\trte_write32(desc_refilled, droq->pkts_credit_reg);\n-\n-\t\t/* Ensure mmio write completes */\n-\t\trte_wmb();\n-\t\totx2_sdp_dbg(\"Refilled count = %d\", desc_refilled);\n-\t}\n-\n-\t/* Release the spin lock */\n-\trte_spinlock_unlock(&droq->lock);\n-\n-\treturn pkts;\n-\n-deq_fail:\n-\trte_spinlock_unlock(&droq->lock);\n-\n-droq_err:\n-\treturn SDP_OQ_RECV_FAILED;\n-}\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h\ndeleted file mode 100644\nindex 172fdc5568..0000000000\n--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h\n+++ /dev/null\n@@ -1,52 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_EP_ENQDEQ_H_\n-#define _OTX2_EP_ENQDEQ_H_\n-\n-#include <rte_byteorder.h>\n-#include \"otx2_ep_rawdev.h\"\n-\n-#define SDP_IQ_SEND_FAILED (-1)\n-#define SDP_IQ_SEND_SUCCESS (0)\n-\n-#define SDP_OQ_RECV_FAILED (-1)\n-#define SDP_OQ_RECV_SUCCESS (0)\n-\n-static inline uint64_t\n-sdp_endian_swap_8B(uint64_t _d)\n-{\n-\treturn ((((((uint64_t)(_d)) >> 0) & (uint64_t)0xff) << 56) |\n-\t\t(((((uint64_t)(_d)) >> 8) & (uint64_t)0xff) << 48) |\n-\t\t(((((uint64_t)(_d)) >> 16) & (uint64_t)0xff) << 40) |\n-\t\t(((((uint64_t)(_d)) >> 24) & (uint64_t)0xff) << 32) |\n-\t\t(((((uint64_t)(_d)) >> 32) & (uint64_t)0xff) << 24) |\n-\t\t(((((uint64_t)(_d)) >> 40) & (uint64_t)0xff) << 16) |\n-\t\t(((((uint64_t)(_d)) >> 48) & (uint64_t)0xff) << 8) |\n-\t\t(((((uint64_t)(_d)) >> 56) & (uint64_t)0xff) << 0));\n-}\n-\n-static inline void\n-sdp_swap_8B_data(uint64_t *data, uint32_t blocks)\n-{\n-\t/* Swap 8B blocks */\n-\twhile (blocks) {\n-\t\t*data = sdp_endian_swap_8B(*data);\n-\t\tblocks--;\n-\t\tdata++;\n-\t}\n-}\n-\n-static inline uint32_t\n-sdp_incr_index(uint32_t index, uint32_t count, uint32_t max)\n-{\n-\tif ((index + count) >= max)\n-\t\tindex = index + count - max;\n-\telse\n-\t\tindex += count;\n-\n-\treturn index;\n-}\n-\n-#endif /* _OTX2_EP_ENQDEQ_H_ */\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\ndeleted file mode 100644\nindex b2ccdda83e..0000000000\n--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\n+++ /dev/null\n@@ -1,362 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-#include <string.h>\n-#include <unistd.h>\n-\n-#include <rte_bus.h>\n-#include <rte_bus_pci.h>\n-#include <rte_eal.h>\n-#include <rte_lcore.h>\n-#include <rte_mempool.h>\n-#include <rte_pci.h>\n-\n-#include <rte_common.h>\n-#include <rte_rawdev.h>\n-#include <rte_rawdev_pmd.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_ep_rawdev.h\"\n-#include \"otx2_ep_vf.h\"\n-\n-static const struct rte_pci_id pci_sdp_vf_map[] = {\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t PCI_DEVID_OCTEONTX2_EP_RAW_VF)\n-\t},\n-\t{\n-\t\t.vendor_id = 0,\n-\t},\n-};\n-\n-/* SDP_VF default configuration */\n-const struct sdp_config default_sdp_conf = {\n-\t/* IQ attributes */\n-\t.iq = {\n-\t\t.max_iqs = SDP_VF_CFG_IO_QUEUES,\n-\t\t.instr_type = SDP_VF_64BYTE_INSTR,\n-\t\t.pending_list_size = (SDP_VF_MAX_IQ_DESCRIPTORS *\n-\t\t\t\t SDP_VF_CFG_IO_QUEUES),\n-\t},\n-\n-\t/* OQ attributes */\n-\t.oq = {\n-\t\t.max_oqs = SDP_VF_CFG_IO_QUEUES,\n-\t\t.info_ptr = SDP_VF_OQ_INFOPTR_MODE,\n-\t\t.refill_threshold = SDP_VF_OQ_REFIL_THRESHOLD,\n-\t},\n-\n-\t.num_iqdef_descs = SDP_VF_MAX_IQ_DESCRIPTORS,\n-\t.num_oqdef_descs = SDP_VF_MAX_OQ_DESCRIPTORS,\n-\t.oqdef_buf_size = SDP_VF_OQ_BUF_SIZE,\n-\n-};\n-\n-const struct sdp_config*\n-sdp_get_defconf(struct sdp_device *sdp_dev __rte_unused)\n-{\n-\tconst struct sdp_config *default_conf = NULL;\n-\n-\tdefault_conf = &default_sdp_conf;\n-\n-\treturn default_conf;\n-}\n-\n-static int\n-sdp_vfdev_exit(struct rte_rawdev *rawdev)\n-{\n-\tstruct sdp_device *sdpvf;\n-\tuint32_t rawdev_queues, q;\n-\n-\totx2_info(\"%s:\", __func__);\n-\n-\tsdpvf = (struct sdp_device *)rawdev->dev_private;\n-\n-\tsdpvf->fn_list.disable_io_queues(sdpvf);\n-\n-\trawdev_queues = sdpvf->num_oqs;\n-\tfor (q = 0; q < rawdev_queues; q++) {\n-\t\tif (sdp_delete_oqs(sdpvf, q)) {\n-\t\t\totx2_err(\"Failed to delete OQ:%d\", q);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\totx2_info(\"Num OQs:%d freed\", sdpvf->num_oqs);\n-\n-\t/* Free the oqbuf_pool */\n-\trte_mempool_free(sdpvf->enqdeq_mpool);\n-\tsdpvf->enqdeq_mpool = NULL;\n-\n-\totx2_info(\"Enqdeq_mpool free done\");\n-\n-\trawdev_queues = sdpvf->num_iqs;\n-\tfor (q = 0; q < rawdev_queues; q++) {\n-\t\tif (sdp_delete_iqs(sdpvf, q)) {\n-\t\t\totx2_err(\"Failed to delete IQ:%d\", q);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\totx2_sdp_dbg(\"Num IQs:%d freed\", sdpvf->num_iqs);\n-\n-\treturn 0;\n-}\n-\n-static int\n-sdp_chip_specific_setup(struct sdp_device *sdpvf)\n-{\n-\tstruct rte_pci_device *pdev = sdpvf->pci_dev;\n-\tuint32_t dev_id = pdev->id.device_id;\n-\tint ret;\n-\n-\tswitch (dev_id) {\n-\tcase PCI_DEVID_OCTEONTX2_EP_RAW_VF:\n-\t\tsdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_RAW_VF;\n-\t\tret = sdp_vf_setup_device(sdpvf);\n-\n-\t\tbreak;\n-\tdefault:\n-\t\totx2_err(\"Unsupported device\");\n-\t\tret = -EINVAL;\n-\t}\n-\n-\tif (!ret)\n-\t\totx2_info(\"SDP dev_id[%d]\", dev_id);\n-\n-\treturn ret;\n-}\n-\n-/* SDP VF device initialization */\n-static int\n-sdp_vfdev_init(struct sdp_device *sdpvf)\n-{\n-\tuint32_t rawdev_queues, q;\n-\n-\tif (sdp_chip_specific_setup(sdpvf)) {\n-\t\totx2_err(\"Chip specific setup failed\");\n-\t\tgoto setup_fail;\n-\t}\n-\n-\tif (sdpvf->fn_list.setup_device_regs(sdpvf)) {\n-\t\totx2_err(\"Failed to configure device registers\");\n-\t\tgoto setup_fail;\n-\t}\n-\n-\trawdev_queues = (uint32_t)(sdpvf->sriov_info.rings_per_vf);\n-\n-\t/* Rawdev queues setup for enqueue/dequeue */\n-\tfor (q = 0; q < rawdev_queues; q++) {\n-\t\tif (sdp_setup_iqs(sdpvf, q)) {\n-\t\t\totx2_err(\"Failed to setup IQs\");\n-\t\t\tgoto iq_fail;\n-\t\t}\n-\t}\n-\totx2_info(\"Total[%d] IQs setup\", sdpvf->num_iqs);\n-\n-\tfor (q = 0; q < rawdev_queues; q++) {\n-\t\tif (sdp_setup_oqs(sdpvf, q)) {\n-\t\t\totx2_err(\"Failed to setup OQs\");\n-\t\t\tgoto oq_fail;\n-\t\t}\n-\t}\n-\totx2_info(\"Total [%d] OQs setup\", sdpvf->num_oqs);\n-\n-\t/* Enable IQ/OQ for this device */\n-\tsdpvf->fn_list.enable_io_queues(sdpvf);\n-\n-\t/* Send OQ desc credits for OQs, credits are always\n-\t * sent after the OQs are enabled.\n-\t */\n-\tfor (q = 0; q < rawdev_queues; q++) {\n-\t\trte_write32(sdpvf->droq[q]->nb_desc,\n-\t\t\t sdpvf->droq[q]->pkts_credit_reg);\n-\n-\t\trte_io_mb();\n-\t\totx2_info(\"OQ[%d] dbells [%d]\", q,\n-\t\trte_read32(sdpvf->droq[q]->pkts_credit_reg));\n-\t}\n-\n-\trte_wmb();\n-\n-\totx2_info(\"SDP Device is Ready\");\n-\n-\treturn 0;\n-\n-/* Error handling */\n-oq_fail:\n-\t/* Free the allocated OQs */\n-\tfor (q = 0; q < sdpvf->num_oqs; q++)\n-\t\tsdp_delete_oqs(sdpvf, q);\n-\n-iq_fail:\n-\t/* Free the allocated IQs */\n-\tfor (q = 0; q < sdpvf->num_iqs; q++)\n-\t\tsdp_delete_iqs(sdpvf, q);\n-\n-setup_fail:\n-\treturn -ENOMEM;\n-}\n-\n-static int\n-sdp_rawdev_start(struct rte_rawdev *dev)\n-{\n-\tdev->started = 1;\n-\n-\treturn 0;\n-}\n-\n-static void\n-sdp_rawdev_stop(struct rte_rawdev *dev)\n-{\n-\tdev->started = 0;\n-}\n-\n-static int\n-sdp_rawdev_close(struct rte_rawdev *dev)\n-{\n-\tint ret;\n-\tret = sdp_vfdev_exit(dev);\n-\tif (ret) {\n-\t\totx2_err(\" SDP_EP rawdev exit error\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-sdp_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,\n-\t\tsize_t config_size)\n-{\n-\tstruct sdp_rawdev_info *app_info = (struct sdp_rawdev_info *)config;\n-\tstruct sdp_device *sdpvf;\n-\n-\tif (app_info == NULL || config_size != sizeof(*app_info)) {\n-\t\totx2_err(\"Application config info [NULL] or incorrect size\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tsdpvf = (struct sdp_device *)dev->dev_private;\n-\n-\tsdpvf->conf = app_info->app_conf;\n-\tsdpvf->enqdeq_mpool = app_info->enqdeq_mpool;\n-\n-\tsdp_vfdev_init(sdpvf);\n-\n-\treturn 0;\n-\n-}\n-\n-/* SDP VF endpoint rawdev ops */\n-static const struct rte_rawdev_ops sdp_rawdev_ops = {\n-\t.dev_configure = sdp_rawdev_configure,\n-\t.dev_start = sdp_rawdev_start,\n-\t.dev_stop = sdp_rawdev_stop,\n-\t.dev_close = sdp_rawdev_close,\n-\t.enqueue_bufs = sdp_rawdev_enqueue,\n-\t.dequeue_bufs = sdp_rawdev_dequeue,\n-\t.dev_selftest = sdp_rawdev_selftest,\n-};\n-\n-static int\n-otx2_sdp_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,\n-\t\t struct rte_pci_device *pci_dev)\n-{\n-\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n-\tstruct sdp_device *sdpvf = NULL;\n-\tstruct rte_rawdev *sdp_rawdev;\n-\tuint16_t vf_id;\n-\n-\t/* Single process support */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\tif (pci_dev->mem_resource[0].addr)\n-\t\totx2_info(\"SDP_EP BAR0 is mapped:\");\n-\telse {\n-\t\totx2_err(\"SDP_EP: Failed to map device BARs\");\n-\t\totx2_err(\"BAR0 %p\\n BAR2 %p\",\n-\t\t\tpci_dev->mem_resource[0].addr,\n-\t\t\tpci_dev->mem_resource[2].addr);\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tmemset(name, 0, sizeof(name));\n-\tsnprintf(name, RTE_RAWDEV_NAME_MAX_LEN, \"SDPEP:%x:%02x.%x\",\n-\t\t pci_dev->addr.bus, pci_dev->addr.devid,\n-\t\t pci_dev->addr.function);\n-\n-\t/* Allocate rawdev pmd */\n-\tsdp_rawdev = rte_rawdev_pmd_allocate(name,\n-\t\t\t\t\t sizeof(struct sdp_device),\n-\t\t\t\t\t rte_socket_id());\n-\n-\tif (sdp_rawdev == NULL) {\n-\t\totx2_err(\"SDP_EP VF rawdev allocation failed\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tsdp_rawdev->dev_ops = &sdp_rawdev_ops;\n-\tsdp_rawdev->device = &pci_dev->device;\n-\tsdp_rawdev->driver_name = pci_dev->driver->driver.name;\n-\n-\tsdpvf = (struct sdp_device *)sdp_rawdev->dev_private;\n-\tsdpvf->hw_addr = pci_dev->mem_resource[0].addr;\n-\tsdpvf->pci_dev = pci_dev;\n-\n-\t/* Discover the VF number being probed */\n-\tvf_id = ((pci_dev->addr.devid & 0x1F) << 3) |\n-\t\t (pci_dev->addr.function & 0x7);\n-\n-\tvf_id -= 1;\n-\tsdpvf->vf_num = vf_id;\n-\n-\totx2_info(\"SDP_EP VF[%d] probe done\", vf_id);\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_sdp_rawdev_remove(struct rte_pci_device *pci_dev)\n-{\n-\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n-\tstruct rte_rawdev *rawdev;\n-\tstruct sdp_device *sdpvf;\n-\n-\t/* Single process support */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\tif (pci_dev == NULL) {\n-\t\totx2_err(\"SDP_EP:invalid pci_dev!\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\n-\tmemset(name, 0, sizeof(name));\n-\tsnprintf(name, RTE_RAWDEV_NAME_MAX_LEN, \"SDPEP:%x:%02x.%x\",\n-\t\t pci_dev->addr.bus, pci_dev->addr.devid,\n-\t\t pci_dev->addr.function);\n-\n-\trawdev = rte_rawdev_pmd_get_named_dev(name);\n-\tif (rawdev == NULL) {\n-\t\totx2_err(\"SDP_EP: invalid device name (%s)\", name);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tsdpvf = (struct sdp_device *)rawdev->dev_private;\n-\totx2_info(\"Removing SDP_EP VF[%d] \", sdpvf->vf_num);\n-\n-\t/* rte_rawdev_close is called by pmd_release */\n-\treturn rte_rawdev_pmd_release(rawdev);\n-}\n-\n-static struct rte_pci_driver rte_sdp_rawdev_pmd = {\n-\t.id_table = pci_sdp_vf_map,\n-\t.drv_flags = (RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA),\n-\t.probe = otx2_sdp_rawdev_probe,\n-\t.remove = otx2_sdp_rawdev_remove,\n-};\n-\n-RTE_PMD_REGISTER_PCI(sdp_rawdev_pci_driver, rte_sdp_rawdev_pmd);\n-RTE_PMD_REGISTER_PCI_TABLE(sdp_rawdev_pci_driver, pci_sdp_vf_map);\n-RTE_PMD_REGISTER_KMOD_DEP(sdp_rawdev_pci_driver, \"vfio-pci\");\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\ndeleted file mode 100644\nindex dab2fb7541..0000000000\n--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\n+++ /dev/null\n@@ -1,499 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_EP_RAWDEV_H_\n-#define _OTX2_EP_RAWDEV_H_\n-\n-#include <rte_byteorder.h>\n-#include <rte_spinlock.h>\n-\n-/* IQ instruction req types */\n-#define SDP_REQTYPE_NONE (0)\n-#define SDP_REQTYPE_NORESP (1)\n-#define SDP_REQTYPE_NORESP_GATHER (2)\n-\n-/* Input Request Header format */\n-struct sdp_instr_irh {\n-\t/* Request ID */\n-\tuint64_t rid:16;\n-\n-\t/* PCIe port to use for response */\n-\tuint64_t pcie_port:3;\n-\n-\t/* Scatter indicator 1=scatter */\n-\tuint64_t scatter:1;\n-\n-\t/* Size of Expected result OR no. of entries in scatter list */\n-\tuint64_t rlenssz:14;\n-\n-\t/* Desired destination port for result */\n-\tuint64_t dport:6;\n-\n-\t/* Opcode Specific parameters */\n-\tuint64_t param:8;\n-\n-\t/* Opcode for the return packet */\n-\tuint64_t opcode:16;\n-};\n-\n-/* SDP 32B instruction format */\n-struct sdp_instr_32B {\n-\t/* Pointer where the input data is available. */\n-\tuint64_t dptr;\n-\n-\t/* SDP Instruction Header. */\n-\tuint64_t ih;\n-\n-\t/** Pointer where the response for a RAW mode packet\n-\t * will be written by OCTEON TX2.\n-\t */\n-\tuint64_t rptr;\n-\n-\t/* Input Request Header. Additional info about the input. */\n-\tuint64_t irh;\n-};\n-#define SDP_32B_INSTR_SIZE\t(sizeof(sdp_instr_32B))\n-\n-/* SDP 64B instruction format */\n-struct sdp_instr_64B {\n-\t/* Pointer where the input data is available. */\n-\tuint64_t dptr;\n-\n-\t/* SDP Instruction Header. */\n-\tuint64_t ih;\n-\n-\t/** Pointer where the response for a RAW mode packet\n-\t * will be written by OCTEON TX2.\n-\t */\n-\tuint64_t rptr;\n-\n-\t/* Input Request Header. */\n-\tuint64_t irh;\n-\n-\t/* Additional headers available in a 64-byte instruction. */\n-\tuint64_t exhdr[4];\n-};\n-#define SDP_64B_INSTR_SIZE\t(sizeof(sdp_instr_64B))\n-\n-struct sdp_soft_instr {\n-\t/** Input data pointer. It is either pointing directly to input data\n-\t * or to a gather list.\n-\t */\n-\tvoid *dptr;\n-\n-\t/** Response from OCTEON TX2 comes at this address. It is either\n-\t * directlty pointing to output data buffer or to a scatter list.\n-\t */\n-\tvoid *rptr;\n-\n-\t/* The instruction header. All input commands have this field. */\n-\tstruct sdp_instr_ih ih;\n-\n-\t/* Input request header. */\n-\tstruct sdp_instr_irh irh;\n-\n-\t/** The PCI instruction to be sent to OCTEON TX2. This is stored in the\n-\t * instr to retrieve the physical address of buffers when instr is\n-\t * freed.\n-\t */\n-\tstruct sdp_instr_64B command;\n-\n-\t/** If a gather list was allocated, this ptr points to the buffer used\n-\t * for the gather list. The gather list has to be 8B aligned, so this\n-\t * value may be different from dptr.\n-\t */\n-\tvoid *gather_ptr;\n-\n-\t/* Total data bytes transferred in the gather mode request. */\n-\tuint64_t gather_bytes;\n-\n-\t/** If a scatter list was allocated, this ptr points to the buffer used\n-\t * for the scatter list. The scatter list has to be 8B aligned, so\n-\t * this value may be different from rptr.\n-\t */\n-\tvoid *scatter_ptr;\n-\n-\t/* Total data bytes to be received in the scatter mode request. */\n-\tuint64_t scatter_bytes;\n-\n-\t/* IQ number to which this instruction has to be submitted. */\n-\tuint32_t q_no;\n-\n-\t/* IQ instruction request type. */\n-\tuint32_t reqtype;\n-};\n-#define SDP_SOFT_INSTR_SIZE\t(sizeof(sdp_soft_instr))\n-\n-/* SDP IQ request list */\n-struct sdp_instr_list {\n-\tvoid *buf;\n-\tuint32_t reqtype;\n-};\n-#define SDP_IQREQ_LIST_SIZE\t(sizeof(struct sdp_instr_list))\n-\n-/* Input Queue statistics. Each input queue has four stats fields. */\n-struct sdp_iq_stats {\n-\tuint64_t instr_posted; /* Instructions posted to this queue. */\n-\tuint64_t instr_processed; /* Instructions processed in this queue. */\n-\tuint64_t instr_dropped; /* Instructions that could not be processed */\n-};\n-\n-/* Structure to define the configuration attributes for each Input queue. */\n-struct sdp_iq_config {\n-\t/* Max number of IQs available */\n-\tuint16_t max_iqs;\n-\n-\t/* Command size - 32 or 64 bytes */\n-\tuint16_t instr_type;\n-\n-\t/* Pending list size, usually set to the sum of the size of all IQs */\n-\tuint32_t pending_list_size;\n-};\n-\n-/** The instruction (input) queue.\n- * The input queue is used to post raw (instruction) mode data or packet data\n- * to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one\n- * such structure to represent it.\n- */\n-struct sdp_instr_queue {\n-\t/* A spinlock to protect access to the input ring. */\n-\trte_spinlock_t lock;\n-\trte_spinlock_t post_lock;\n-\n-\tstruct sdp_device *sdp_dev;\n-\trte_atomic64_t iq_flush_running;\n-\n-\tuint32_t q_no;\n-\tuint32_t pkt_in_done;\n-\n-\t/* Flag for 64 byte commands. */\n-\tuint32_t iqcmd_64B:1;\n-\tuint32_t rsvd:17;\n-\tuint32_t status:8;\n-\n-\t/* Number of descriptors in this ring. */\n-\tuint32_t nb_desc;\n-\n-\t/* Input ring index, where the driver should write the next packet */\n-\tuint32_t host_write_index;\n-\n-\t/* Input ring index, where the OCTEON TX2 should read the next packet */\n-\tuint32_t otx_read_index;\n-\n-\t/** This index aids in finding the window in the queue where OCTEON TX2\n-\t * has read the commands.\n-\t */\n-\tuint32_t flush_index;\n-\n-\t/* This keeps track of the instructions pending in this queue. */\n-\trte_atomic64_t instr_pending;\n-\n-\tuint32_t reset_instr_cnt;\n-\n-\t/* Pointer to the Virtual Base addr of the input ring. */\n-\tuint8_t *base_addr;\n-\n-\t/* This IQ request list */\n-\tstruct sdp_instr_list *req_list;\n-\n-\t/* SDP doorbell register for the ring. */\n-\tvoid *doorbell_reg;\n-\n-\t/* SDP instruction count register for this ring. */\n-\tvoid *inst_cnt_reg;\n-\n-\t/* Number of instructions pending to be posted to OCTEON TX2. */\n-\tuint32_t fill_cnt;\n-\n-\t/* Statistics for this input queue. */\n-\tstruct sdp_iq_stats stats;\n-\n-\t/* DMA mapped base address of the input descriptor ring. */\n-\tuint64_t base_addr_dma;\n-\n-\t/* Memory zone */\n-\tconst struct rte_memzone *iq_mz;\n-};\n-\n-/* DROQ packet format for application i/f. */\n-struct sdp_droq_pkt {\n-\t/* DROQ packet data buffer pointer. */\n-\tuint8_t\t *data;\n-\n-\t/* DROQ packet data length */\n-\tuint32_t len;\n-\n-\tuint32_t misc;\n-};\n-\n-/** Descriptor format.\n- * The descriptor ring is made of descriptors which have 2 64-bit values:\n- * -# Physical (bus) address of the data buffer.\n- * -# Physical (bus) address of a sdp_droq_info structure.\n- * The device DMA's incoming packets and its information at the address\n- * given by these descriptor fields.\n- */\n-struct sdp_droq_desc {\n-\t/* The buffer pointer */\n-\tuint64_t buffer_ptr;\n-\n-\t/* The Info pointer */\n-\tuint64_t info_ptr;\n-};\n-#define SDP_DROQ_DESC_SIZE\t(sizeof(struct sdp_droq_desc))\n-\n-/* Receive Header */\n-union sdp_rh {\n-\tuint64_t rh64;\n-};\n-#define SDP_RH_SIZE (sizeof(union sdp_rh))\n-\n-/** Information about packet DMA'ed by OCTEON TX2.\n- * The format of the information available at Info Pointer after OCTEON TX2\n- * has posted a packet. Not all descriptors have valid information. Only\n- * the Info field of the first descriptor for a packet has information\n- * about the packet.\n- */\n-struct sdp_droq_info {\n-\t/* The Output Receive Header. */\n-\tunion sdp_rh rh;\n-\n-\t/* The Length of the packet. */\n-\tuint64_t length;\n-};\n-#define SDP_DROQ_INFO_SIZE\t(sizeof(struct sdp_droq_info))\n-\n-/** Pointer to data buffer.\n- * Driver keeps a pointer to the data buffer that it made available to\n- * the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)\n- * addresses, this field is required for the driver to keep track of\n- * the virtual address pointers.\n- */\n-struct sdp_recv_buffer {\n-\t/* Packet buffer, including meta data. */\n-\tvoid *buffer;\n-\n-\t/* Data in the packet buffer. */\n-\t/* uint8_t *data; */\n-};\n-#define SDP_DROQ_RECVBUF_SIZE\t(sizeof(struct sdp_recv_buffer))\n-\n-/* DROQ statistics. Each output queue has four stats fields. */\n-struct sdp_droq_stats {\n-\t/* Number of packets received in this queue. */\n-\tuint64_t pkts_received;\n-\n-\t/* Bytes received by this queue. */\n-\tuint64_t bytes_received;\n-\n-\t/* Num of failures of rte_pktmbuf_alloc() */\n-\tuint64_t rx_alloc_failure;\n-};\n-\n-/* Structure to define the configuration attributes for each Output queue. */\n-struct sdp_oq_config {\n-\t/* Max number of OQs available */\n-\tuint16_t max_oqs;\n-\n-\t/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */\n-\tuint16_t info_ptr;\n-\n-\t/** The number of buffers that were consumed during packet processing by\n-\t * the driver on this Output queue before the driver attempts to\n-\t * replenish the descriptor ring with new buffers.\n-\t */\n-\tuint32_t refill_threshold;\n-};\n-\n-/* The Descriptor Ring Output Queue(DROQ) structure. */\n-struct sdp_droq {\n-\t/* A spinlock to protect access to this ring. */\n-\trte_spinlock_t lock;\n-\n-\tstruct sdp_device *sdp_dev;\n-\t/* The 8B aligned descriptor ring starts at this address. */\n-\tstruct sdp_droq_desc *desc_ring;\n-\n-\tuint32_t q_no;\n-\tuint32_t last_pkt_count;\n-\n-\t/* Driver should read the next packet at this index */\n-\tuint32_t read_idx;\n-\n-\t/* OCTEON TX2 will write the next packet at this index */\n-\tuint32_t write_idx;\n-\n-\t/* At this index, the driver will refill the descriptor's buffer */\n-\tuint32_t refill_idx;\n-\n-\t/* Packets pending to be processed */\n-\trte_atomic64_t pkts_pending;\n-\n-\t/* Number of descriptors in this ring. */\n-\tuint32_t nb_desc;\n-\n-\t/* The number of descriptors pending to refill. */\n-\tuint32_t refill_count;\n-\n-\tuint32_t refill_threshold;\n-\n-\t/* The 8B aligned info ptrs begin from this address. */\n-\tstruct sdp_droq_info *info_list;\n-\n-\t/* receive buffer list contains virtual addresses of the buffers. */\n-\tstruct sdp_recv_buffer *recv_buf_list;\n-\n-\t/* The size of each buffer pointed by the buffer pointer. */\n-\tuint32_t buffer_size;\n-\n-\t/** Pointer to the mapped packet credit register.\n-\t * Host writes number of info/buffer ptrs available to this register\n-\t */\n-\tvoid *pkts_credit_reg;\n-\n-\t/** Pointer to the mapped packet sent register. OCTEON TX2 writes the\n-\t * number of packets DMA'ed to host memory in this register.\n-\t */\n-\tvoid *pkts_sent_reg;\n-\n-\t/* Statistics for this DROQ. */\n-\tstruct sdp_droq_stats stats;\n-\n-\t/* DMA mapped address of the DROQ descriptor ring. */\n-\tsize_t desc_ring_dma;\n-\n-\t/* Info_ptr list is allocated at this virtual address. */\n-\tsize_t info_base_addr;\n-\n-\t/* DMA mapped address of the info list */\n-\tsize_t info_list_dma;\n-\n-\t/* Allocated size of info list. */\n-\tuint32_t info_alloc_size;\n-\n-\t/* Memory zone **/\n-\tconst struct rte_memzone *desc_ring_mz;\n-\tconst struct rte_memzone *info_mz;\n-};\n-#define SDP_DROQ_SIZE\t\t(sizeof(struct sdp_droq))\n-\n-/* IQ/OQ mask */\n-struct sdp_io_enable {\n-\tuint64_t iq;\n-\tuint64_t oq;\n-\tuint64_t iq64B;\n-};\n-\n-/* Structure to define the configuration. */\n-struct sdp_config {\n-\t/* Input Queue attributes. */\n-\tstruct sdp_iq_config iq;\n-\n-\t/* Output Queue attributes. */\n-\tstruct sdp_oq_config oq;\n-\n-\t/* Num of desc for IQ rings */\n-\tuint32_t num_iqdef_descs;\n-\n-\t/* Num of desc for OQ rings */\n-\tuint32_t num_oqdef_descs;\n-\n-\t/* OQ buffer size */\n-\tuint32_t oqdef_buf_size;\n-};\n-\n-/* Required functions for each VF device */\n-struct sdp_fn_list {\n-\tvoid (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);\n-\tvoid (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);\n-\n-\tint (*setup_device_regs)(struct sdp_device *sdpvf);\n-\tuint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);\n-\n-\tvoid (*enable_io_queues)(struct sdp_device *sdpvf);\n-\tvoid (*disable_io_queues)(struct sdp_device *sdpvf);\n-\n-\tvoid (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);\n-\tvoid (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);\n-\n-\tvoid (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);\n-\tvoid (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);\n-};\n-\n-/* SRIOV information */\n-struct sdp_sriov_info {\n-\t/* Number of rings assigned to VF */\n-\tuint32_t rings_per_vf;\n-\n-\t/* Number of VF devices enabled */\n-\tuint32_t num_vfs;\n-};\n-\n-\n-/* Information to be passed from application */\n-struct sdp_rawdev_info {\n-\tstruct rte_mempool *enqdeq_mpool;\n-\tconst struct sdp_config *app_conf;\n-};\n-\n-/* SDP EP VF device */\n-struct sdp_device {\n-\t/* PCI device pointer */\n-\tstruct rte_pci_device *pci_dev;\n-\tuint16_t chip_id;\n-\tuint16_t pf_num;\n-\tuint16_t vf_num;\n-\n-\t/* This device's PCIe port used for traffic. */\n-\tuint16_t pcie_port;\n-\tuint32_t pkind;\n-\n-\t/* The state of this device */\n-\trte_atomic64_t status;\n-\n-\t/* Memory mapped h/w address */\n-\tuint8_t *hw_addr;\n-\n-\tstruct sdp_fn_list fn_list;\n-\n-\t/* Num IQs */\n-\tuint32_t num_iqs;\n-\n-\t/* The input instruction queues */\n-\tstruct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];\n-\n-\t/* Num OQs */\n-\tuint32_t num_oqs;\n-\n-\t/* The DROQ output queues */\n-\tstruct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];\n-\n-\t/* IOQ data buffer pool */\n-\tstruct rte_mempool *enqdeq_mpool;\n-\n-\t/* IOQ mask */\n-\tstruct sdp_io_enable io_qmask;\n-\n-\t/* SR-IOV info */\n-\tstruct sdp_sriov_info sriov_info;\n-\n-\t/* Device configuration */\n-\tconst struct sdp_config *conf;\n-};\n-\n-const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);\n-int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);\n-int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);\n-\n-int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);\n-int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);\n-\n-int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,\n-\t\t unsigned int count, rte_rawdev_obj_t context);\n-int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,\n-\t\t unsigned int count, rte_rawdev_obj_t context);\n-\n-int sdp_rawdev_selftest(uint16_t dev_id);\n-\n-#endif /* _OTX2_EP_RAWDEV_H_ */\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_test.c b/drivers/raw/octeontx2_ep/otx2_ep_test.c\ndeleted file mode 100644\nindex b876275f7a..0000000000\n--- a/drivers/raw/octeontx2_ep/otx2_ep_test.c\n+++ /dev/null\n@@ -1,172 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <stdio.h>\n-#include <stdlib.h>\n-#include <string.h>\n-#include <unistd.h>\n-\n-#include <rte_common.h>\n-#include <rte_eal.h>\n-#include <rte_lcore.h>\n-#include <rte_mempool.h>\n-\n-#include <rte_rawdev.h>\n-#include <rte_rawdev_pmd.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_ep_rawdev.h\"\n-\n-#define SDP_IOQ_NUM_BUFS (4 * 1024)\n-#define SDP_IOQ_BUF_SIZE (2 * 1024)\n-\n-#define SDP_TEST_PKT_FSZ (0)\n-#define SDP_TEST_PKT_SIZE (1024)\n-\n-static int\n-sdp_validate_data(struct sdp_droq_pkt *oq_pkt, uint8_t *iq_pkt,\n-\t\t uint32_t pkt_len)\n-{\n-\tif (!oq_pkt)\n-\t\treturn -EINVAL;\n-\n-\tif (pkt_len != oq_pkt->len) {\n-\t\totx2_err(\"Invalid packet length\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (memcmp(oq_pkt->data, iq_pkt, pkt_len) != 0) {\n-\t\totx2_err(\"Data validation failed\");\n-\t\treturn -EINVAL;\n-\t}\n-\totx2_sdp_dbg(\"Data validation successful\");\n-\n-\treturn 0;\n-}\n-\n-static void\n-sdp_ioq_buffer_fill(uint8_t *addr, uint32_t len)\n-{\n-\tuint32_t idx;\n-\n-\tmemset(addr, 0, len);\n-\n-\tfor (idx = 0; idx < len; idx++)\n-\t\taddr[idx] = idx;\n-}\n-\n-static struct rte_mempool*\n-sdp_ioq_mempool_create(void)\n-{\n-\tstruct rte_mempool *mpool;\n-\n-\tmpool = rte_mempool_create(\"ioqbuf_pool\",\n-\t\t\t\t SDP_IOQ_NUM_BUFS /*num elt*/,\n-\t\t\t\t SDP_IOQ_BUF_SIZE /*elt size*/,\n-\t\t\t\t 0 /*cache_size*/,\n-\t\t\t\t 0 /*private_data_size*/,\n-\t\t\t\t NULL /*mp_init*/,\n-\t\t\t\t NULL /*mp_init arg*/,\n-\t\t\t\t NULL /*obj_init*/,\n-\t\t\t\t NULL /*obj_init arg*/,\n-\t\t\t\t rte_socket_id() /*socket id*/,\n-\t\t\t\t (MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET));\n-\n-\treturn mpool;\n-}\n-\n-\n-int\n-sdp_rawdev_selftest(uint16_t dev_id)\n-{\n-\tstruct sdp_rawdev_info app_info = {0};\n-\tstruct rte_rawdev_info dev_info = {0};\n-\n-\tstruct rte_rawdev_buf *d_buf[1];\n-\tstruct sdp_droq_pkt oq_pkt;\n-\tstruct sdp_soft_instr si;\n-\tstruct sdp_device sdpvf;\n-\n-\tuint32_t buf_size;\n-\tint ret = 0;\n-\tvoid *buf;\n-\n-\totx2_info(\"SDP RAWDEV Self Test: Started\");\n-\n-\tmemset(&oq_pkt, 0x00, sizeof(oq_pkt));\n-\td_buf[0] = (struct rte_rawdev_buf *)&oq_pkt;\n-\n-\tstruct rte_mempool *ioq_mpool = sdp_ioq_mempool_create();\n-\tif (!ioq_mpool) {\n-\t\totx2_err(\"IOQ mpool creation failed\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tapp_info.enqdeq_mpool = ioq_mpool;\n-\tapp_info.app_conf = NULL; /* Use default conf */\n-\n-\tdev_info.dev_private = &app_info;\n-\n-\tret = rte_rawdev_configure(dev_id, &dev_info, sizeof(app_info));\n-\tif (ret) {\n-\t\totx2_err(\"Unable to configure SDP_VF %d\", dev_id);\n-\t\trte_mempool_free(ioq_mpool);\n-\t\treturn -ENOMEM;\n-\t}\n-\totx2_info(\"SDP VF rawdev[%d] configured successfully\", dev_id);\n-\n-\tmemset(&si, 0x00, sizeof(si));\n-\tmemset(&sdpvf, 0x00, sizeof(sdpvf));\n-\n-\tbuf_size = SDP_TEST_PKT_SIZE;\n-\n-\tsi.q_no = 0;\n-\tsi.reqtype = SDP_REQTYPE_NORESP;\n-\tsi.rptr = NULL;\n-\n-\tsi.ih.fsz = SDP_TEST_PKT_FSZ;\n-\tsi.ih.tlen = buf_size;\n-\tsi.ih.gather = 0;\n-\n-\t/* Enqueue raw pkt data */\n-\trte_mempool_get(ioq_mpool, &buf);\n-\tif (!buf) {\n-\t\totx2_err(\"Buffer allocation failed\");\n-\t\trte_mempool_free(ioq_mpool);\n-\t\trte_rawdev_close(dev_id);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tsdp_ioq_buffer_fill(buf, buf_size);\n-\tsi.dptr = (uint8_t *)buf;\n-\n-\trte_rawdev_enqueue_buffers(dev_id, NULL, 1, &si);\n-\tusleep(10000);\n-\n-\t/* Dequeue raw pkt data */\n-\tret = 0;\n-\twhile (ret < 1) {\n-\t\tret = rte_rawdev_dequeue_buffers(dev_id, &d_buf[0], 1, &si);\n-\t\trte_pause();\n-\t}\n-\n-\t/* Validate the dequeued raw pkt data */\n-\tif (sdp_validate_data((struct sdp_droq_pkt *)d_buf[0],\n-\t\t\t buf, buf_size) != 0) {\n-\t\totx2_err(\"Data invalid\");\n-\t\trte_mempool_put(ioq_mpool,\n-\t\t\t\t((struct sdp_droq_pkt *)d_buf[0])->data);\n-\t\trte_mempool_free(ioq_mpool);\n-\t\trte_rawdev_close(dev_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\trte_mempool_put(ioq_mpool, ((struct sdp_droq_pkt *)d_buf[0])->data);\n-\trte_mempool_free(ioq_mpool);\n-\trte_rawdev_close(dev_id);\n-\n-\totx2_info(\"SDP RAWDEV Self Test: Successful\");\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.c b/drivers/raw/octeontx2_ep/otx2_ep_vf.c\ndeleted file mode 100644\nindex bf2a19e369..0000000000\n--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.c\n+++ /dev/null\n@@ -1,475 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_common.h>\n-#include <rte_rawdev.h>\n-#include <rte_rawdev_pmd.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_ep_rawdev.h\"\n-#include \"otx2_ep_vf.h\"\n-\n-static int\n-sdp_vf_reset_iq(struct sdp_device *sdpvf, int q_no)\n-{\n-\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n-\tvolatile uint64_t d64 = 0ull;\n-\n-\t/* There is no RST for a ring.\n-\t * Clear all registers one by one after disabling the ring\n-\t */\n-\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));\n-\n-\td64 = 0xFFFFFFFF; /* ~0ull */\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n-\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n-\n-\twhile ((d64 != 0) && loop--) {\n-\t\totx2_write64(d64, sdpvf->hw_addr +\n-\t\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n-\n-\t\trte_delay_ms(1);\n-\n-\t\td64 = otx2_read64(sdpvf->hw_addr +\n-\t\t\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n-\t}\n-\n-\tloop = SDP_VF_BUSY_LOOP_COUNT;\n-\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n-\twhile ((d64 != 0) && loop--) {\n-\t\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n-\n-\t\trte_delay_ms(1);\n-\n-\t\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n-\t}\n-\n-\td64 = 0ull;\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));\n-\n-\treturn 0;\n-}\n-\n-static int\n-sdp_vf_reset_oq(struct sdp_device *sdpvf, int q_no)\n-{\n-\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n-\tvolatile uint64_t d64 = 0ull;\n-\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n-\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));\n-\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));\n-\n-\td64 = 0xFFFFFFFF;\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n-\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n-\n-\twhile ((d64 != 0) && loop--) {\n-\t\totx2_write64(d64, sdpvf->hw_addr +\n-\t\t\t SDP_VF_R_OUT_SLIST_DBELL(q_no));\n-\n-\t\trte_delay_ms(1);\n-\n-\t\td64 = otx2_read64(sdpvf->hw_addr +\n-\t\t\t\t SDP_VF_R_OUT_SLIST_DBELL(q_no));\n-\t}\n-\n-\tloop = SDP_VF_BUSY_LOOP_COUNT;\n-\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n-\twhile ((d64 != 0) && (loop--)) {\n-\t\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n-\n-\t\trte_delay_ms(1);\n-\n-\t\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n-\t}\n-\n-\td64 = 0ull;\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));\n-\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));\n-\n-\treturn 0;\n-}\n-\n-static void\n-sdp_vf_setup_global_iq_reg(struct sdp_device *sdpvf, int q_no)\n-{\n-\tvolatile uint64_t reg_val = 0ull;\n-\n-\t/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for IQs\n-\t * IS_64B is by default enabled.\n-\t */\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));\n-\n-\treg_val |= SDP_VF_R_IN_CTL_RDSIZE;\n-\treg_val |= SDP_VF_R_IN_CTL_IS_64B;\n-\treg_val |= SDP_VF_R_IN_CTL_ESR;\n-\n-\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));\n-\n-}\n-\n-static void\n-sdp_vf_setup_global_oq_reg(struct sdp_device *sdpvf, int q_no)\n-{\n-\tvolatile uint64_t reg_val = 0ull;\n-\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n-\n-\treg_val |= (SDP_VF_R_OUT_CTL_IMODE);\n-\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);\n-\treg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);\n-\n-\t/* INFO/DATA ptr swap is required */\n-\treg_val |= (SDP_VF_R_OUT_CTL_ES_P);\n-\n-\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n-\n-}\n-\n-static int\n-sdp_vf_reset_input_queues(struct sdp_device *sdpvf)\n-{\n-\tuint32_t q_no = 0;\n-\n-\totx2_sdp_dbg(\"%s :\", __func__);\n-\n-\tfor (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)\n-\t\tsdp_vf_reset_iq(sdpvf, q_no);\n-\n-\treturn 0;\n-}\n-\n-static int\n-sdp_vf_reset_output_queues(struct sdp_device *sdpvf)\n-{\n-\tuint64_t q_no = 0ull;\n-\n-\totx2_sdp_dbg(\" %s :\", __func__);\n-\n-\tfor (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)\n-\t\tsdp_vf_reset_oq(sdpvf, q_no);\n-\n-\treturn 0;\n-}\n-\n-static void\n-sdp_vf_setup_global_input_regs(struct sdp_device *sdpvf)\n-{\n-\tuint64_t q_no = 0ull;\n-\n-\tsdp_vf_reset_input_queues(sdpvf);\n-\n-\tfor (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)\n-\t\tsdp_vf_setup_global_iq_reg(sdpvf, q_no);\n-}\n-\n-static void\n-sdp_vf_setup_global_output_regs(struct sdp_device *sdpvf)\n-{\n-\tuint32_t q_no;\n-\n-\tsdp_vf_reset_output_queues(sdpvf);\n-\n-\tfor (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)\n-\t\tsdp_vf_setup_global_oq_reg(sdpvf, q_no);\n-\n-}\n-\n-static int\n-sdp_vf_setup_device_regs(struct sdp_device *sdpvf)\n-{\n-\tsdp_vf_setup_global_input_regs(sdpvf);\n-\tsdp_vf_setup_global_output_regs(sdpvf);\n-\n-\treturn 0;\n-}\n-\n-static void\n-sdp_vf_setup_iq_regs(struct sdp_device *sdpvf, uint32_t iq_no)\n-{\n-\tstruct sdp_instr_queue *iq = sdpvf->instr_queue[iq_no];\n-\tvolatile uint64_t reg_val = 0ull;\n-\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));\n-\n-\t/* Wait till IDLE to set to 1, not supposed to configure BADDR\n-\t * as long as IDLE is 0\n-\t */\n-\tif (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {\n-\t\tdo {\n-\t\t\treg_val = otx2_read64(sdpvf->hw_addr +\n-\t\t\t\t\t SDP_VF_R_IN_CONTROL(iq_no));\n-\t\t} while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));\n-\t}\n-\n-\t/* Write the start of the input queue's ring and its size */\n-\totx2_write64(iq->base_addr_dma, sdpvf->hw_addr +\n-\t\t SDP_VF_R_IN_INSTR_BADDR(iq_no));\n-\totx2_write64(iq->nb_desc, sdpvf->hw_addr +\n-\t\t SDP_VF_R_IN_INSTR_RSIZE(iq_no));\n-\n-\t/* Remember the doorbell & instruction count register addr\n-\t * for this queue\n-\t */\n-\tiq->doorbell_reg = (uint8_t *) sdpvf->hw_addr +\n-\t\t\t SDP_VF_R_IN_INSTR_DBELL(iq_no);\n-\tiq->inst_cnt_reg = (uint8_t *) sdpvf->hw_addr +\n-\t\t\t SDP_VF_R_IN_CNTS(iq_no);\n-\n-\totx2_sdp_dbg(\"InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\",\n-\t\t iq_no, iq->doorbell_reg, iq->inst_cnt_reg);\n-\n-\t/* Store the current instrn counter(used in flush_iq calculation) */\n-\tiq->reset_instr_cnt = rte_read32(iq->inst_cnt_reg);\n-\n-\t/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR\n-\t * to raise\n-\t */\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));\n-\treg_val = 0xffffffff;\n-\n-\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));\n-\n-}\n-\n-static void\n-sdp_vf_setup_oq_regs(struct sdp_device *sdpvf, uint32_t oq_no)\n-{\n-\tvolatile uint64_t reg_val = 0ull;\n-\tuint64_t oq_ctl = 0ull;\n-\n-\tstruct sdp_droq *droq = sdpvf->droq[oq_no];\n-\n-\t/* Wait on IDLE to set to 1, supposed to configure BADDR\n-\t * as log as IDLE is 0\n-\t */\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n-\n-\twhile (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {\n-\t\treg_val = otx2_read64(sdpvf->hw_addr +\n-\t\t\t\t SDP_VF_R_OUT_CONTROL(oq_no));\n-\t}\n-\n-\totx2_write64(droq->desc_ring_dma, sdpvf->hw_addr +\n-\t\t SDP_VF_R_OUT_SLIST_BADDR(oq_no));\n-\totx2_write64(droq->nb_desc, sdpvf->hw_addr +\n-\t\t SDP_VF_R_OUT_SLIST_RSIZE(oq_no));\n-\n-\toq_ctl = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n-\n-\t/* Clear the ISIZE and BSIZE (22-0) */\n-\toq_ctl &= ~(0x7fffffull);\n-\n-\t/* Populate the BSIZE (15-0) */\n-\toq_ctl |= (droq->buffer_size & 0xffff);\n-\n-\t/* Populate ISIZE(22-16) */\n-\toq_ctl |= ((SDP_RH_SIZE << 16) & 0x7fffff);\n-\totx2_write64(oq_ctl, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n-\n-\t/* Mapped address of the pkt_sent and pkts_credit regs */\n-\tdroq->pkts_sent_reg = (uint8_t *) sdpvf->hw_addr +\n-\t\t\t SDP_VF_R_OUT_CNTS(oq_no);\n-\tdroq->pkts_credit_reg = (uint8_t *) sdpvf->hw_addr +\n-\t\t\t\tSDP_VF_R_OUT_SLIST_DBELL(oq_no);\n-\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));\n-\n-\t/* Clear PKT_CNT register */\n-\trte_write64(0xFFFFFFFFF, (uint8_t *)sdpvf->hw_addr +\n-\t\t SDP_VF_R_OUT_PKT_CNT(oq_no));\n-\n-\t/* Clear the OQ doorbell */\n-\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n-\twhile ((rte_read32(droq->pkts_credit_reg) != 0ull)) {\n-\t\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n-\t\trte_delay_ms(1);\n-\t}\n-\totx2_sdp_dbg(\"SDP_R[%d]_credit:%x\", oq_no,\n-\t\t rte_read32(droq->pkts_credit_reg));\n-\n-\t/* Clear the OQ_OUT_CNTS doorbell */\n-\treg_val = rte_read32(droq->pkts_sent_reg);\n-\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n-\n-\totx2_sdp_dbg(\"SDP_R[%d]_sent: %x\", oq_no,\n-\t\t rte_read32(droq->pkts_sent_reg));\n-\n-\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {\n-\t\treg_val = rte_read32(droq->pkts_sent_reg);\n-\t\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n-\t\trte_delay_ms(1);\n-\t}\n-\n-}\n-\n-static void\n-sdp_vf_enable_iq(struct sdp_device *sdpvf, uint32_t q_no)\n-{\n-\tvolatile uint64_t reg_val = 0ull;\n-\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n-\n-\t/* Resetting doorbells during IQ enabling also to handle abrupt\n-\t * guest reboot. IQ reset does not clear the doorbells.\n-\t */\n-\totx2_write64(0xFFFFFFFF, sdpvf->hw_addr +\n-\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n-\n-\twhile (((otx2_read64(sdpvf->hw_addr +\n-\t\t SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {\n-\n-\t\trte_delay_ms(1);\n-\t}\n-\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n-\treg_val |= 0x1ull;\n-\n-\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n-\n-\totx2_info(\"IQ[%d] enable done\", q_no);\n-\n-}\n-\n-static void\n-sdp_vf_enable_oq(struct sdp_device *sdpvf, uint32_t q_no)\n-{\n-\tvolatile uint64_t reg_val = 0ull;\n-\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n-\treg_val |= 0x1ull;\n-\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n-\n-\totx2_info(\"OQ[%d] enable done\", q_no);\n-}\n-\n-static void\n-sdp_vf_enable_io_queues(struct sdp_device *sdpvf)\n-{\n-\tuint32_t q_no = 0;\n-\n-\tfor (q_no = 0; q_no < sdpvf->num_iqs; q_no++)\n-\t\tsdp_vf_enable_iq(sdpvf, q_no);\n-\n-\tfor (q_no = 0; q_no < sdpvf->num_oqs; q_no++)\n-\t\tsdp_vf_enable_oq(sdpvf, q_no);\n-}\n-\n-static void\n-sdp_vf_disable_iq(struct sdp_device *sdpvf, uint32_t q_no)\n-{\n-\tvolatile uint64_t reg_val = 0ull;\n-\n-\t/* Reset the doorbell register for this Input Queue. */\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n-\treg_val &= ~0x1ull;\n-\n-\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n-}\n-\n-static void\n-sdp_vf_disable_oq(struct sdp_device *sdpvf, uint32_t q_no)\n-{\n-\tvolatile uint64_t reg_val = 0ull;\n-\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n-\treg_val &= ~0x1ull;\n-\n-\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n-\n-}\n-\n-static void\n-sdp_vf_disable_io_queues(struct sdp_device *sdpvf)\n-{\n-\tuint32_t q_no = 0;\n-\n-\t/* Disable Input Queues. */\n-\tfor (q_no = 0; q_no < sdpvf->num_iqs; q_no++)\n-\t\tsdp_vf_disable_iq(sdpvf, q_no);\n-\n-\t/* Disable Output Queues. */\n-\tfor (q_no = 0; q_no < sdpvf->num_oqs; q_no++)\n-\t\tsdp_vf_disable_oq(sdpvf, q_no);\n-}\n-\n-static uint32_t\n-sdp_vf_update_read_index(struct sdp_instr_queue *iq)\n-{\n-\tuint32_t new_idx = rte_read32(iq->inst_cnt_reg);\n-\n-\t/* The new instr cnt reg is a 32-bit counter that can roll over.\n-\t * We have noted the counter's initial value at init time into\n-\t * reset_instr_cnt\n-\t */\n-\tif (iq->reset_instr_cnt < new_idx)\n-\t\tnew_idx -= iq->reset_instr_cnt;\n-\telse\n-\t\tnew_idx += (0xffffffff - iq->reset_instr_cnt) + 1;\n-\n-\t/* Modulo of the new index with the IQ size will give us\n-\t * the new index.\n-\t */\n-\tnew_idx %= iq->nb_desc;\n-\n-\treturn new_idx;\n-}\n-\n-int\n-sdp_vf_setup_device(struct sdp_device *sdpvf)\n-{\n-\tuint64_t reg_val = 0ull;\n-\n-\t/* If application doesn't provide its conf, use driver default conf */\n-\tif (sdpvf->conf == NULL) {\n-\t\tsdpvf->conf = sdp_get_defconf(sdpvf);\n-\t\tif (sdpvf->conf == NULL) {\n-\t\t\totx2_err(\"SDP VF default config not found\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\totx2_info(\"Default config is used\");\n-\t}\n-\n-\t/* Get IOQs (RPVF] count */\n-\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(0));\n-\n-\tsdpvf->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)\n-\t\t\t\t\t & SDP_VF_R_IN_CTL_RPVF_MASK);\n-\n-\totx2_info(\"SDP RPVF: %d\", sdpvf->sriov_info.rings_per_vf);\n-\n-\tsdpvf->fn_list.setup_iq_regs = sdp_vf_setup_iq_regs;\n-\tsdpvf->fn_list.setup_oq_regs = sdp_vf_setup_oq_regs;\n-\n-\tsdpvf->fn_list.setup_device_regs = sdp_vf_setup_device_regs;\n-\tsdpvf->fn_list.update_iq_read_idx = sdp_vf_update_read_index;\n-\n-\tsdpvf->fn_list.enable_io_queues = sdp_vf_enable_io_queues;\n-\tsdpvf->fn_list.disable_io_queues = sdp_vf_disable_io_queues;\n-\n-\tsdpvf->fn_list.enable_iq = sdp_vf_enable_iq;\n-\tsdpvf->fn_list.disable_iq = sdp_vf_disable_iq;\n-\n-\tsdpvf->fn_list.enable_oq = sdp_vf_enable_oq;\n-\tsdpvf->fn_list.disable_oq = sdp_vf_disable_oq;\n-\n-\n-\treturn 0;\n-\n-}\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.h b/drivers/raw/octeontx2_ep/otx2_ep_vf.h\ndeleted file mode 100644\nindex 996f2e51eb..0000000000\n--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.h\n+++ /dev/null\n@@ -1,10 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-#ifndef _OTX2_EP_VF_H_\n-#define _OTX2_EP_VF_H_\n-\n-int\n-sdp_vf_setup_device(struct sdp_device *sdpvf);\n-\n-#endif /*_OTX2_EP_VF_H_ */\ndiff --git a/drivers/raw/octeontx2_ep/version.map b/drivers/raw/octeontx2_ep/version.map\ndeleted file mode 100644\nindex 4a76d1d52d..0000000000\n--- a/drivers/raw/octeontx2_ep/version.map\n+++ /dev/null\n@@ -1,3 +0,0 @@\n-DPDK_21 {\n-\tlocal: *;\n-};\n", "prefixes": [ "2/2" ] }