Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/96750/?format=api
{ "id": 96750, "url": "http://patches.dpdk.org/api/patches/96750/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210810025140.1698163-12-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210810025140.1698163-12-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210810025140.1698163-12-qi.z.zhang@intel.com", "date": "2021-08-10T02:51:23", "name": "[11/28] net/ice/base: add support for starting PHY in bypass mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b773d934e2c447216b5144d7c0e6e22d894b313d", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210810025140.1698163-12-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18242, "url": "http://patches.dpdk.org/api/series/18242/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18242", "date": "2021-08-10T02:51:12", "name": "ice: base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/18242/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/96750/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/96750/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5BAE4A0C54;\n\tTue, 10 Aug 2021 04:49:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 51AD741170;\n\tTue, 10 Aug 2021 04:49:02 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 19D96411BA\n for <dev@dpdk.org>; Tue, 10 Aug 2021 04:48:59 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2021 19:48:59 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:48:57 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10070\"; a=\"214808457\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"214808457\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"483823647\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Tue, 10 Aug 2021 10:51:23 +0800", "Message-Id": "<20210810025140.1698163-12-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "References": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY\n in bypass mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "After starting the timestamping block, hardware begins calculating\nprecise offsets through a process of vernier calibration. This process\nmeasures the effective phase offset of the various internal clocks used\nin the PHY.\n\nOnce hardware completes these measurements, the P_REG_TX_OV_STATUS and\nP_REG_RX_OV_STATUS registers are updated to indicate that the hardware\noffset measurements are done.\n\nThis process does not happen immediately, but requires that at least one\npacket be sent or received in order for the offset in that direction to\nbe calculated.\n\nThis poses a problem in some setups, because software expects the first\npacket sent to be timestamped. This most often occurs if the clock time\nis set by an application during startup. This set time command triggers\na PHY restart. Because of this, the timestamping block is reset, and\ntimestamps are not enabled until vernier calibration is complete. Since\nthis process won't complete until at least one packet is sent through\nthe PHY, timestamps of the very first packet sent will not be obtained.\n\nThis can result in the application failing due to missing timestamps.\n\nTo avoid this, allow starting the PHY in bypass mode. This mode enables\ntimestamps immediately, and skips adding the precise offset measurement.\nThis reduces the accuracy of the timestamp slightly, but ensures that we\nget a reasonable value for the first packet.\n\nThe driver can continue monitoring the P_REG_TX_OV_STATUS and\nP_REG_RX_OV_STATUS registers and exit bypass mode once the total\ncalibration is completed. In this way, once calibration is complete, the\ntimestamps will have the precise offset, but we do not break\napplications which expect to be able to timestamp immediately.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 84 +++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_ptp_hw.h | 1 +\n 2 files changed, 85 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex bf6889029a..8ea75538fa 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -2572,6 +2572,90 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to configure\n+ *\n+ * After hardware finishes vernier calculations for the Tx and Rx offset, this\n+ * function can be used to exit bypass mode by updating the total Tx and Rx\n+ * offsets, and then disabling bypass. This will enable hardware to include\n+ * the more precise offset calibrations, increasing precision of the generated\n+ * timestamps.\n+ *\n+ * This cannot be done until hardware has measured the offsets, which requires\n+ * waiting until at least one packet has been sent and received by the device.\n+ */\n+enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)\n+{\n+\tenum ice_status status;\n+\tu32 val;\n+\n+\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TX_OV_STATUS for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tif (!(val & P_REG_TX_OV_STATUS_OV_M)) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Tx offset is not yet valid for port %u\\n\",\n+\t\t\t port);\n+\t\treturn ICE_ERR_NOT_READY;\n+\t}\n+\n+\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read RX_OV_STATUS for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tif (!(val & P_REG_TX_OV_STATUS_OV_M)) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Rx offset is not yet valid for port %u\\n\",\n+\t\t\t port);\n+\t\treturn ICE_ERR_NOT_READY;\n+\t}\n+\n+\tstatus = ice_phy_cfg_tx_offset_e822(hw, port);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to program total Tx offset for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_phy_cfg_rx_offset_e822(hw, port);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to program total Rx offset for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\t/* Exit bypass mode now that the offset has been updated */\n+\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read P_REG_PS for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tif (!(val & P_REG_PS_BYPASS_MODE_M))\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Port %u not in bypass mode\\n\",\n+\t\t\t port);\n+\n+\tval &= ~P_REG_PS_BYPASS_MODE_M;\n+\tstatus = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to disable bypass for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tice_info(hw, \"Exiting bypass mode on PHY port %u\\n\", port);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n /* E810 functions\n *\n * The following functions operate on the E810 series devices which use\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex f2d87ca1e6..c804085095 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -218,6 +218,7 @@ enum ice_status\n ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);\n enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);\n enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);\n+enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);\n \n /* E810 family functions */\n enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);\n", "prefixes": [ "11/28" ] }