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GET /api/patches/96745/?format=api
{ "id": 96745, "url": "http://patches.dpdk.org/api/patches/96745/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210810025140.1698163-7-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210810025140.1698163-7-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210810025140.1698163-7-qi.z.zhang@intel.com", "date": "2021-08-10T02:51:18", "name": "[06/28] net/ice/base: add clock initialization function", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "696416b6d3cdb665f3dff18e0d301978e7fd244e", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210810025140.1698163-7-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18242, "url": "http://patches.dpdk.org/api/series/18242/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18242", "date": "2021-08-10T02:51:12", "name": "ice: base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/18242/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/96745/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/96745/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9066BA0C54;\n\tTue, 10 Aug 2021 04:49:15 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 614D14118B;\n\tTue, 10 Aug 2021 04:48:50 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 2DA024117F\n for <dev@dpdk.org>; Tue, 10 Aug 2021 04:48:48 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2021 19:48:47 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:48:45 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10070\"; a=\"214808421\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"214808421\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"483823570\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Tue, 10 Aug 2021 10:51:18 +0800", "Message-Id": "<20210810025140.1698163-7-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "References": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 06/28] net/ice/base: add clock initialization\n function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Before the device PTP hardware clock can be initialized, some steps must\nbe taken by the driver. This includes writing some registers and\ninitializing the PHY.\n\nSome of these steps are distinct depending on the device type (E810 or\nE822). Additionally, a future change will introduce more steps for E822\ndevices to program the Clock Generation Unit.\n\nIntroduce ice_ptp_init_phc as well as device-specific sub-functions for\ne810 and e822 devices.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_cgu_regs.h | 117 +++++++++\n drivers/net/ice/base/ice_ptp_consts.h | 74 ++++++\n drivers/net/ice/base/ice_ptp_hw.c | 348 +++++++++++++++++++++++++-\n drivers/net/ice/base/ice_ptp_hw.h | 24 ++\n 4 files changed, 562 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/ice/base/ice_cgu_regs.h", "diff": "diff --git a/drivers/net/ice/base/ice_cgu_regs.h b/drivers/net/ice/base/ice_cgu_regs.h\nnew file mode 100644\nindex 0000000000..6751481e83\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_cgu_regs.h\n@@ -0,0 +1,117 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2021 Intel Corporation\n+ */\n+\n+#ifndef _ICE_CGU_REGS_H_\n+#define _ICE_CGU_REGS_H_\n+\n+#define NAC_CGU_DWORD9 0x24\n+union nac_cgu_dword9 {\n+\tstruct {\n+\t\tu32 time_ref_freq_sel : 3;\n+\t\tu32 clk_eref1_en : 1;\n+\t\tu32 clk_eref0_en : 1;\n+\t\tu32 time_ref_en : 1;\n+\t\tu32 time_sync_en : 1;\n+\t\tu32 one_pps_out_en : 1;\n+\t\tu32 clk_ref_synce_en : 1;\n+\t\tu32 clk_synce1_en : 1;\n+\t\tu32 clk_synce0_en : 1;\n+\t\tu32 net_clk_ref1_en : 1;\n+\t\tu32 net_clk_ref0_en : 1;\n+\t\tu32 clk_synce1_amp : 2;\n+\t\tu32 misc6 : 1;\n+\t\tu32 clk_synce0_amp : 2;\n+\t\tu32 one_pps_out_amp : 2;\n+\t\tu32 misc24 : 12;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define NAC_CGU_DWORD19 0x4c\n+union nac_cgu_dword19 {\n+\tstruct {\n+\t\tu32 tspll_fbdiv_intgr : 8;\n+\t\tu32 fdpll_ulck_thr : 5;\n+\t\tu32 misc15 : 3;\n+\t\tu32 tspll_ndivratio : 4;\n+\t\tu32 tspll_iref_ndivratio : 3;\n+\t\tu32 misc19 : 1;\n+\t\tu32 japll_ndivratio : 4;\n+\t\tu32 japll_iref_ndivratio : 3;\n+\t\tu32 misc27 : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define NAC_CGU_DWORD22 0x58\n+union nac_cgu_dword22 {\n+\tstruct {\n+\t\tu32 fdpll_frac_div_out_nc : 2;\n+\t\tu32 fdpll_lock_int_for : 1;\n+\t\tu32 synce_hdov_int_for : 1;\n+\t\tu32 synce_lock_int_for : 1;\n+\t\tu32 fdpll_phlead_slip_nc : 1;\n+\t\tu32 fdpll_acc1_ovfl_nc : 1;\n+\t\tu32 fdpll_acc2_ovfl_nc : 1;\n+\t\tu32 synce_status_nc : 6;\n+\t\tu32 fdpll_acc1f_ovfl : 1;\n+\t\tu32 misc18 : 1;\n+\t\tu32 fdpllclk_div : 4;\n+\t\tu32 time1588clk_div : 4;\n+\t\tu32 synceclk_div : 4;\n+\t\tu32 synceclk_sel_div2 : 1;\n+\t\tu32 fdpllclk_sel_div2 : 1;\n+\t\tu32 time1588clk_sel_div2 : 1;\n+\t\tu32 misc3 : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define NAC_CGU_DWORD24 0x60\n+union nac_cgu_dword24 {\n+\tstruct {\n+\t\tu32 tspll_fbdiv_frac : 22;\n+\t\tu32 misc20 : 2;\n+\t\tu32 ts_pll_enable : 1;\n+\t\tu32 time_sync_tspll_align_sel : 1;\n+\t\tu32 ext_synce_sel : 1;\n+\t\tu32 ref1588_ck_div : 4;\n+\t\tu32 time_ref_sel : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define TSPLL_CNTR_BIST_SETTINGS 0x344\n+union tspll_cntr_bist_settings {\n+\tstruct {\n+\t\tu32 i_irefgen_settling_time_cntr_7_0 : 8;\n+\t\tu32 i_irefgen_settling_time_ro_standby_1_0 : 2;\n+\t\tu32 reserved195 : 5;\n+\t\tu32 i_plllock_sel_0 : 1;\n+\t\tu32 i_plllock_sel_1 : 1;\n+\t\tu32 i_plllock_cnt_6_0 : 7;\n+\t\tu32 i_plllock_cnt_10_7 : 4;\n+\t\tu32 reserved200 : 4;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define TSPLL_RO_BWM_LF 0x370\n+union tspll_ro_bwm_lf {\n+\tstruct {\n+\t\tu32 bw_freqov_high_cri_7_0 : 8;\n+\t\tu32 bw_freqov_high_cri_9_8 : 2;\n+\t\tu32 biascaldone_cri : 1;\n+\t\tu32 plllock_gain_tran_cri : 1;\n+\t\tu32 plllock_true_lock_cri : 1;\n+\t\tu32 pllunlock_flag_cri : 1;\n+\t\tu32 afcerr_cri : 1;\n+\t\tu32 afcdone_cri : 1;\n+\t\tu32 feedfwrdgain_cal_cri_7_0 : 8;\n+\t\tu32 m2fbdivmod_cri_7_0 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#endif /* _ICE_CGU_REGS_H_ */\ndiff --git a/drivers/net/ice/base/ice_ptp_consts.h b/drivers/net/ice/base/ice_ptp_consts.h\nindex 2bd338c88c..4583dd42ff 100644\n--- a/drivers/net/ice/base/ice_ptp_consts.h\n+++ b/drivers/net/ice/base/ice_ptp_consts.h\n@@ -83,4 +83,78 @@ const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {\n \t},\n };\n \n+const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {\n+\t/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */\n+\t{\n+\t\t/* refclk_pre_div */\n+\t\t1,\n+\t\t/* feedback_div */\n+\t\t197,\n+\t\t/* frac_n_div */\n+\t\t2621440,\n+\t\t/* post_pll_div */\n+\t\t6,\n+\t},\n+\n+\t/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */\n+\t{\n+\t\t/* refclk_pre_div */\n+\t\t5,\n+\t\t/* feedback_div */\n+\t\t223,\n+\t\t/* frac_n_div */\n+\t\t524288,\n+\t\t/* post_pll_div */\n+\t\t7,\n+\t},\n+\n+\t/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */\n+\t{\n+\t\t/* refclk_pre_div */\n+\t\t5,\n+\t\t/* feedback_div */\n+\t\t223,\n+\t\t/* frac_n_div */\n+\t\t524288,\n+\t\t/* post_pll_div */\n+\t\t7,\n+\t},\n+\n+\t/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */\n+\t{\n+\t\t/* refclk_pre_div */\n+\t\t5,\n+\t\t/* feedback_div */\n+\t\t159,\n+\t\t/* frac_n_div */\n+\t\t1572864,\n+\t\t/* post_pll_div */\n+\t\t6,\n+\t},\n+\n+\t/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */\n+\t{\n+\t\t/* refclk_pre_div */\n+\t\t5,\n+\t\t/* feedback_div */\n+\t\t159,\n+\t\t/* frac_n_div */\n+\t\t1572864,\n+\t\t/* post_pll_div */\n+\t\t6,\n+\t},\n+\n+\t/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */\n+\t{\n+\t\t/* refclk_pre_div */\n+\t\t10,\n+\t\t/* feedback_div */\n+\t\t223,\n+\t\t/* frac_n_div */\n+\t\t524288,\n+\t\t/* post_pll_div */\n+\t\t7,\n+\t},\n+};\n+\n #endif /* _ICE_PTP_CONSTS_H_ */\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 8aefcf93fd..cb32a4fb48 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -6,7 +6,7 @@\n #include \"ice_common.h\"\n #include \"ice_ptp_hw.h\"\n #include \"ice_ptp_consts.h\"\n-\n+#include \"ice_cgu_regs.h\"\n \n /* Low level functions for interacting with and managing the device clock used\n * for the Precision Time Protocol.\n@@ -699,6 +699,315 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_read_cgu_reg_e822 - Read a CGU register\n+ * @hw: pointer to the HW struct\n+ * @addr: Register address to read\n+ * @val: storage for register value read\n+ *\n+ * Read the contents of a register of the Clock Generation Unit. Only\n+ * applicable to E822 devices.\n+ */\n+static enum ice_status\n+ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)\n+{\n+\tstruct ice_sbq_msg_input cgu_msg;\n+\tenum ice_status status;\n+\n+\tcgu_msg.opcode = ice_sbq_msg_rd;\n+\tcgu_msg.dest_dev = cgu;\n+\tcgu_msg.msg_addr_low = addr;\n+\tcgu_msg.msg_addr_high = 0x0;\n+\n+\tstatus = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read CGU register 0x%04x, status %d\\n\",\n+\t\t\t addr, status);\n+\t\treturn status;\n+\t}\n+\n+\t*val = cgu_msg.data;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_write_cgu_reg_e822 - Write a CGU register\n+ * @hw: pointer to the HW struct\n+ * @addr: Register address to write\n+ * @val: value to write into the register\n+ *\n+ * Write the specified value to a register of the Clock Generation Unit. Only\n+ * applicable to E822 devices.\n+ */\n+static enum ice_status\n+ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val)\n+{\n+\tstruct ice_sbq_msg_input cgu_msg;\n+\tenum ice_status status;\n+\n+\tcgu_msg.opcode = ice_sbq_msg_wr;\n+\tcgu_msg.dest_dev = cgu;\n+\tcgu_msg.msg_addr_low = addr;\n+\tcgu_msg.msg_addr_high = 0x0;\n+\tcgu_msg.data = val;\n+\n+\tstatus = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write CGU register 0x%04x, status %d\\n\",\n+\t\t\t addr, status);\n+\t\treturn status;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_clk_freq_str - Convert time_ref_freq to string\n+ * @clk_freq: Clock frequency\n+ *\n+ * Convert the specified TIME_REF clock frequency to a string.\n+ */\n+static const char *ice_clk_freq_str(u8 clk_freq)\n+{\n+\tswitch ((enum ice_time_ref_freq)clk_freq) {\n+\tcase ICE_TIME_REF_FREQ_25_000:\n+\t\treturn \"25 MHz\";\n+\tcase ICE_TIME_REF_FREQ_122_880:\n+\t\treturn \"122.88 MHz\";\n+\tcase ICE_TIME_REF_FREQ_125_000:\n+\t\treturn \"125 MHz\";\n+\tcase ICE_TIME_REF_FREQ_153_600:\n+\t\treturn \"153.6 MHz\";\n+\tcase ICE_TIME_REF_FREQ_156_250:\n+\t\treturn \"156.25 MHz\";\n+\tcase ICE_TIME_REF_FREQ_245_760:\n+\t\treturn \"245.76 MHz\";\n+\tdefault:\n+\t\treturn \"Unknown\";\n+\t}\n+}\n+\n+/**\n+ * ice_clk_src_str - Convert time_ref_src to string\n+ * @clk_src: Clock source\n+ *\n+ * Convert the specified clock source to its string name.\n+ */\n+static const char *ice_clk_src_str(u8 clk_src)\n+{\n+\tswitch ((enum ice_clk_src)clk_src) {\n+\tcase ICE_CLK_SRC_TCX0:\n+\t\treturn \"TCX0\";\n+\tcase ICE_CLK_SRC_TIME_REF:\n+\t\treturn \"TIME_REF\";\n+\tdefault:\n+\t\treturn \"Unknown\";\n+\t}\n+}\n+\n+/**\n+ * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit\n+ * @hw: pointer to the HW struct\n+ * @clk_freq: Clock frequency to program\n+ * @clk_src: Clock source to select (TIME_REF, or TCX0)\n+ *\n+ * Configure the Clock Generation Unit with the desired clock frequency and\n+ * time reference, enabling the PLL which drives the PTP hardware clock.\n+ */\n+enum ice_status\n+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n+\t\t enum ice_clk_src clk_src)\n+{\n+\tunion tspll_ro_bwm_lf bwm_lf;\n+\tunion nac_cgu_dword19 dw19;\n+\tunion nac_cgu_dword22 dw22;\n+\tunion nac_cgu_dword24 dw24;\n+\tunion nac_cgu_dword9 dw9;\n+\tenum ice_status status;\n+\n+\tif (clk_freq >= NUM_ICE_TIME_REF_FREQ) {\n+\t\tice_warn(hw, \"Invalid TIME_REF frequency %u\\n\", clk_freq);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (clk_src >= NUM_ICE_CLK_SRC) {\n+\t\tice_warn(hw, \"Invalid clock source %u\\n\", clk_src);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (clk_src == ICE_CLK_SRC_TCX0 &&\n+\t clk_freq != ICE_TIME_REF_FREQ_25_000) {\n+\t\tice_warn(hw, \"TCX0 only supports 25 MHz frequency\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Log the current clock configuration */\n+\tice_debug(hw, ICE_DBG_PTP, \"Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\\n\",\n+\t\t dw24.field.ts_pll_enable ? \"enabled\" : \"disabled\",\n+\t\t ice_clk_src_str(dw24.field.time_ref_sel),\n+\t\t ice_clk_freq_str(dw9.field.time_ref_freq_sel),\n+\t\t bwm_lf.field.plllock_true_lock_cri ? \"locked\" : \"unlocked\");\n+\n+\t/* Disable the PLL before changing the clock source or frequency */\n+\tif (dw24.field.ts_pll_enable) {\n+\t\tdw24.field.ts_pll_enable = 0;\n+\n+\t\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\t/* Set the frequency */\n+\tdw9.field.time_ref_freq_sel = clk_freq;\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the TS PLL feedback divisor */\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tdw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;\n+\tdw19.field.tspll_ndivratio = 1;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the TS PLL post divisor */\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tdw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;\n+\tdw22.field.time1588clk_sel_div2 = 0;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the TS PLL pre divisor and clock source */\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tdw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;\n+\tdw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;\n+\tdw24.field.time_ref_sel = clk_src;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Finally, enable the PLL */\n+\tdw24.field.ts_pll_enable = 1;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Wait to verify if the PLL locks */\n+\tice_msec_delay(1, true);\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tif (!bwm_lf.field.plllock_true_lock_cri) {\n+\t\tice_warn(hw, \"CGU PLL failed to lock\\n\");\n+\t\treturn ICE_ERR_NOT_READY;\n+\t}\n+\n+\t/* Log the current clock configuration */\n+\tice_debug(hw, ICE_DBG_PTP, \"New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\\n\",\n+\t\t dw24.field.ts_pll_enable ? \"enabled\" : \"disabled\",\n+\t\t ice_clk_src_str(dw24.field.time_ref_sel),\n+\t\t ice_clk_freq_str(dw9.field.time_ref_freq_sel),\n+\t\t bwm_lf.field.plllock_true_lock_cri ? \"locked\" : \"unlocked\");\n+\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_init_cgu_e822 - Initialize CGU with settings from firmware\n+ * @hw: pointer to the HW structure\n+ *\n+ * Initialize the Clock Generation Unit of the E822 device.\n+ */\n+static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)\n+{\n+\tstruct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;\n+\tunion tspll_cntr_bist_settings cntr_bist;\n+\tenum ice_status status;\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,\n+\t\t\t\t &cntr_bist.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Disable sticky lock detection so lock status reported is accurate */\n+\tcntr_bist.field.i_plllock_sel_0 = 0;\n+\tcntr_bist.field.i_plllock_sel_1 = 0;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,\n+\t\t\t\t\tcntr_bist.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the CGU PLL using the parameters from the function\n+\t * capabilities.\n+\t */\n+\tstatus = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,\n+\t\t\t\t (enum ice_clk_src)ts_info->clk_src);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization\n+ * @hw: pointer to HW struct\n+ *\n+ * Perform PHC initialization steps specific to E822 devices.\n+ */\n+static enum ice_status ice_ptp_init_phc_e822(struct ice_hw *hw)\n+{\n+\tenum ice_status status;\n+\tu32 regval;\n+\n+\t/* Enable reading switch and PHY registers over the sideband queue */\n+#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)\n+#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)\n+\tregval = rd32(hw, PF_SB_REM_DEV_CTL);\n+\tregval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |\n+\t\t PF_SB_REM_DEV_CTL_PHY0);\n+\twr32(hw, PF_SB_REM_DEV_CTL, regval);\n+\n+\t/* Initialize the Clock Generation Unit */\n+\tstatus = ice_init_cgu_e822(hw);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Set window length for all the ports */\n+\treturn ice_ptp_set_vernier_wl(hw);\n+}\n+\n /**\n * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time\n * @hw: pointer to the HW struct\n@@ -1445,6 +1754,21 @@ enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw)\n \treturn status;\n }\n \n+/**\n+ * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization\n+ * @hw: pointer to HW struct\n+ *\n+ * Perform E810-specific PTP hardware clock initialization steps.\n+ */\n+static enum ice_status ice_ptp_init_phc_e810(struct ice_hw *hw)\n+{\n+\t/* Ensure synchronization delay is zero */\n+\twr32(hw, GLTSYN_SYNC_DLAY, 0);\n+\n+\t/* Initialize the PHY */\n+\treturn ice_ptp_init_phy_e810(hw);\n+}\n+\n /**\n * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time\n * @hw: Board private structure\n@@ -2021,3 +2345,25 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)\n \telse\n \t\treturn ice_clear_phy_tstamp_e822(hw, block, idx);\n }\n+\n+/**\n+ * ice_ptp_init_phc - Initialize PTP hardware clock\n+ * @hw: pointer to the HW struct\n+ *\n+ * Perform the steps required to initialize the PTP hardware clock.\n+ */\n+enum ice_status ice_ptp_init_phc(struct ice_hw *hw)\n+{\n+\tu8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;\n+\n+\t/* Enable source clocks */\n+\twr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);\n+\n+\t/* Clear event status indications for auxiliary pins */\n+\t(void)rd32(hw, GLTSYN_STAT(src_idx));\n+\n+\tif (ice_is_e810(hw))\n+\t\treturn ice_ptp_init_phc_e810(hw);\n+\telse\n+\t\treturn ice_ptp_init_phc_e822(hw);\n+}\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex 8cbe81792d..eb0e410ed8 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -55,6 +55,26 @@ struct ice_time_ref_info_e822 {\n \tu8 pps_delay;\n };\n \n+/**\n+ * struct ice_cgu_pll_params_e822\n+ * @refclk_pre_div: Reference clock pre-divisor\n+ * @feedback_div: Feedback divisor\n+ * @frac_n_div: Fractional divisor\n+ * @post_pll_div: Post PLL divisor\n+ *\n+ * Clock Generation Unit parameters used to program the PLL based on the\n+ * selected TIME_REF frequency.\n+ */\n+struct ice_cgu_pll_params_e822 {\n+\tu32 refclk_pre_div;\n+\tu32 feedback_div;\n+\tu32 frac_n_div;\n+\tu32 post_pll_div;\n+};\n+\n+extern const struct\n+ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];\n+\n /* Table of constants related to possible TIME_REF sources */\n extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];\n \n@@ -79,6 +99,7 @@ enum ice_status\n ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);\n enum ice_status\n ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);\n+enum ice_status ice_ptp_init_phc(struct ice_hw *hw);\n \n /* E822 family functions */\n enum ice_status\n@@ -99,6 +120,9 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts);\n enum ice_status\n ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,\n \t\t bool lock_sbq);\n+enum ice_status\n+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n+\t\t enum ice_clk_src clk_src);\n \n static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)\n {\n", "prefixes": [ "06/28" ] }