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GET /api/patches/96740/?format=api
{ "id": 96740, "url": "http://patches.dpdk.org/api/patches/96740/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210810025140.1698163-2-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210810025140.1698163-2-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210810025140.1698163-2-qi.z.zhang@intel.com", "date": "2021-08-10T02:51:13", "name": "[01/28] net/ice/base: add 1588 capability probe", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6bc30493bbfff9626d680f4370592c430620a76a", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210810025140.1698163-2-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18242, "url": "http://patches.dpdk.org/api/series/18242/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18242", "date": "2021-08-10T02:51:12", "name": "ice: base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/18242/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/96740/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/96740/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B9544A0C54;\n\tTue, 10 Aug 2021 04:48:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9CAD54113F;\n\tTue, 10 Aug 2021 04:48:37 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 2737F4003E\n for <dev@dpdk.org>; Tue, 10 Aug 2021 04:48:34 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2021 19:48:34 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:48:32 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10070\"; a=\"214808399\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"214808399\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"483823506\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Tue, 10 Aug 2021 10:51:13 +0800", "Message-Id": "<20210810025140.1698163-2-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "References": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Parse 1588 timesync capability during device capability probing.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 1 +\n drivers/net/ice/base/ice_common.c | 111 ++++++++++++++++++++++++++\n drivers/net/ice/base/ice_type.h | 72 +++++++++++++++++\n 3 files changed, 184 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 861f5a39b6..8fc0340c0d 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -108,6 +108,7 @@ struct ice_aqc_list_caps_elem {\n #define ICE_AQC_CAPS_TXQS\t\t\t\t0x0042\n #define ICE_AQC_CAPS_MSIX\t\t\t\t0x0043\n #define ICE_AQC_CAPS_FD\t\t\t\t\t0x0045\n+#define ICE_AQC_CAPS_1588\t\t\t\t0x0046\n #define ICE_AQC_CAPS_MAX_MTU\t\t\t\t0x0047\n #define ICE_AQC_CAPS_IWARP\t\t\t\t0x0051\n #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE\t\t0x0076\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 51fca7b166..185b900290 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2086,6 +2086,60 @@ ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,\n \t\t func_p->guar_num_vsi);\n }\n \n+/**\n+ * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @cap: pointer to the capability element to parse\n+ *\n+ * Extract function capabilities for ICE_AQC_CAPS_1588.\n+ */\n+static void\n+ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,\n+\t\t\t struct ice_aqc_list_caps_elem *cap)\n+{\n+\tstruct ice_ts_func_info *info = &func_p->ts_func_info;\n+\tu32 number = LE32_TO_CPU(cap->number);\n+\n+\tinfo->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);\n+\tfunc_p->common_cap.ieee_1588 = info->ena;\n+\n+\tinfo->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);\n+\tinfo->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);\n+\tinfo->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);\n+\tinfo->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);\n+\n+\tinfo->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;\n+\tinfo->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);\n+\n+\tif (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {\n+\t\tinfo->time_ref = (enum ice_time_ref_freq)info->clk_freq;\n+\t} else {\n+\t\t/* Unknown clock frequency, so assume a (probably incorrect)\n+\t\t * default to avoid out-of-bounds look ups of frequency\n+\t\t * related information.\n+\t\t */\n+\t\tice_debug(hw, ICE_DBG_INIT, \"1588 func caps: unknown clock frequency %u\\n\",\n+\t\t\t info->clk_freq);\n+\t\tinfo->time_ref = ICE_TIME_REF_FREQ_25_000;\n+\t}\n+\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: ieee_1588 = %u\\n\",\n+\t\t func_p->common_cap.ieee_1588);\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: src_tmr_owned = %u\\n\",\n+\t\t info->src_tmr_owned);\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: tmr_ena = %u\\n\",\n+\t\t info->tmr_ena);\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: tmr_index_owned = %u\\n\",\n+\t\t info->tmr_index_owned);\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: tmr_index_assoc = %u\\n\",\n+\t\t info->tmr_index_assoc);\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: clk_freq = %u\\n\",\n+\t\t info->clk_freq);\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: clk_src = %u\\n\",\n+\t\t info->clk_src);\n+}\n+\n /**\n * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps\n * @hw: pointer to the HW struct\n@@ -2151,6 +2205,9 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,\n \t\tcase ICE_AQC_CAPS_VSI:\n \t\t\tice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);\n \t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_1588:\n+\t\t\tice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);\n+\t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_FD:\n \t\t\tice_parse_fdir_func_caps(hw, func_p);\n \t\t\tbreak;\n@@ -2204,6 +2261,57 @@ ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n \t\t dev_p->num_vsi_allocd_to_host);\n }\n \n+/**\n+ * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse ICE_AQC_CAPS_1588 for device capabilities.\n+ */\n+static void\n+ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n+\t\t\tstruct ice_aqc_list_caps_elem *cap)\n+{\n+\tstruct ice_ts_dev_info *info = &dev_p->ts_dev_info;\n+\tu32 logical_id = LE32_TO_CPU(cap->logical_id);\n+\tu32 phys_id = LE32_TO_CPU(cap->phys_id);\n+\tu32 number = LE32_TO_CPU(cap->number);\n+\n+\tinfo->ena = ((number & ICE_TS_DEV_ENA_M) != 0);\n+\tdev_p->common_cap.ieee_1588 = info->ena;\n+\n+\tinfo->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;\n+\tinfo->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);\n+\tinfo->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);\n+\n+\tinfo->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;\n+\tinfo->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);\n+\tinfo->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);\n+\n+\tinfo->ena_ports = logical_id;\n+\tinfo->tmr_own_map = phys_id;\n+\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: ieee_1588 = %u\\n\",\n+\t\t dev_p->common_cap.ieee_1588);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr0_owner = %u\\n\",\n+\t\t info->tmr0_owner);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr0_owned = %u\\n\",\n+\t\t info->tmr0_owned);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr0_ena = %u\\n\",\n+\t\t info->tmr0_ena);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr1_owner = %u\\n\",\n+\t\t info->tmr1_owner);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr1_owned = %u\\n\",\n+\t\t info->tmr1_owned);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr1_ena = %u\\n\",\n+\t\t info->tmr1_ena);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: ieee_1588 ena_ports = %u\\n\",\n+\t\t info->ena_ports);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr_own_map = %u\\n\",\n+\t\t info->tmr_own_map);\n+}\n+\n /**\n * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps\n * @hw: pointer to the HW struct\n@@ -2262,6 +2370,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n \t\tcase ICE_AQC_CAPS_VSI:\n \t\t\tice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);\n \t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_1588:\n+\t\t\tice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);\n+\t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_FD:\n \t\t\tice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);\n \t\t\tbreak;\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 2644d5db73..daf1ac6ef6 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -439,6 +439,7 @@ struct ice_hw_common_caps {\n \n \tu8 dcb;\n \tu8 iscsi;\n+\tu8 ieee_1588;\n \tu8 mgmt_cem;\n \n \t/* WoL and APM support */\n@@ -469,12 +470,82 @@ struct ice_hw_common_caps {\n #define ICE_EXT_TOPO_DEV_IMG_PROG_EN\tBIT(1)\n };\n \n+/* IEEE 1588 TIME_SYNC specific info */\n+/* Function specific definitions */\n+#define ICE_TS_FUNC_ENA_M\t\tBIT(0)\n+#define ICE_TS_SRC_TMR_OWND_M\t\tBIT(1)\n+#define ICE_TS_TMR_ENA_M\t\tBIT(2)\n+#define ICE_TS_TMR_IDX_OWND_S\t\t4\n+#define ICE_TS_TMR_IDX_OWND_M\t\tBIT(4)\n+#define ICE_TS_CLK_FREQ_S\t\t16\n+#define ICE_TS_CLK_FREQ_M\t\tMAKEMASK(0x7, ICE_TS_CLK_FREQ_S)\n+#define ICE_TS_CLK_SRC_S\t\t20\n+#define ICE_TS_CLK_SRC_M\t\tBIT(20)\n+#define ICE_TS_TMR_IDX_ASSOC_S\t\t24\n+#define ICE_TS_TMR_IDX_ASSOC_M\t\tBIT(24)\n+\n+/* TIME_REF clock rate specification */\n+enum ice_time_ref_freq {\n+\tICE_TIME_REF_FREQ_25_000\t= 0,\n+\tICE_TIME_REF_FREQ_122_880\t= 1,\n+\tICE_TIME_REF_FREQ_125_000\t= 2,\n+\tICE_TIME_REF_FREQ_153_600\t= 3,\n+\tICE_TIME_REF_FREQ_156_250\t= 4,\n+\tICE_TIME_REF_FREQ_245_760\t= 5,\n+\n+\tNUM_ICE_TIME_REF_FREQ\n+};\n+\n+/* Clock source specification */\n+enum ice_clk_src {\n+\tICE_CLK_SRC_TCX0\t= 0, /* Temperature compensated oscillator */\n+\tICE_CLK_SRC_TIME_REF\t= 1, /* Use TIME_REF reference clock */\n+\n+\tNUM_ICE_CLK_SRC\n+};\n+\n+struct ice_ts_func_info {\n+\t/* Function specific info */\n+\tenum ice_time_ref_freq time_ref;\n+\tu8 clk_freq;\n+\tu8 clk_src;\n+\tu8 tmr_index_assoc;\n+\tu8 ena;\n+\tu8 tmr_index_owned;\n+\tu8 src_tmr_owned;\n+\tu8 tmr_ena;\n+};\n+\n+/* Device specific definitions */\n+#define ICE_TS_TMR0_OWNR_M\t\t0x7\n+#define ICE_TS_TMR0_OWND_M\t\tBIT(3)\n+#define ICE_TS_TMR1_OWNR_S\t\t4\n+#define ICE_TS_TMR1_OWNR_M\t\tMAKEMASK(0x7, ICE_TS_TMR1_OWNR_S)\n+#define ICE_TS_TMR1_OWND_M\t\tBIT(7)\n+#define ICE_TS_DEV_ENA_M\t\tBIT(24)\n+#define ICE_TS_TMR0_ENA_M\t\tBIT(25)\n+#define ICE_TS_TMR1_ENA_M\t\tBIT(26)\n+\n+struct ice_ts_dev_info {\n+\t/* Device specific info */\n+\tu32 ena_ports;\n+\tu32 tmr_own_map;\n+\tu32 tmr0_owner;\n+\tu32 tmr1_owner;\n+\tu8 tmr0_owned;\n+\tu8 tmr1_owned;\n+\tu8 ena;\n+\tu8 tmr0_ena;\n+\tu8 tmr1_ena;\n+};\n+\n /* Function specific capabilities */\n struct ice_hw_func_caps {\n \tstruct ice_hw_common_caps common_cap;\n \tu32 guar_num_vsi;\n \tu32 fd_fltr_guar;\t\t/* Number of filters guaranteed */\n \tu32 fd_fltr_best_effort;\t/* Number of best effort filters */\n+\tstruct ice_ts_func_info ts_func_info;\n };\n \n /* Device wide capabilities */\n@@ -482,6 +553,7 @@ struct ice_hw_dev_caps {\n \tstruct ice_hw_common_caps common_cap;\n \tu32 num_vsi_allocd_to_host;\t/* Excluding EMP VSI */\n \tu32 num_flow_director_fltr;\t/* Number of FD filters available */\n+\tstruct ice_ts_dev_info ts_dev_info;\n \tu32 num_funcs;\n };\n \n", "prefixes": [ "01/28" ] }