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GET /api/patches/96100/?format=api
{ "id": 96100, "url": "http://patches.dpdk.org/api/patches/96100/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210720130944.5407-7-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210720130944.5407-7-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210720130944.5407-7-suanmingm@nvidia.com", "date": "2021-07-20T13:09:35", "name": "[v9,06/15] crypto/mlx5: add memory region management", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "64b833f4de574f78e3a77352e40a56643c61d019", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210720130944.5407-7-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17912, "url": "http://patches.dpdk.org/api/series/17912/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17912", "date": "2021-07-20T13:09:29", "name": "drivers: introduce mlx5 crypto PMD", "version": 9, "mbox": "http://patches.dpdk.org/series/17912/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/96100/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/96100/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7E441A0C48;\n\tTue, 20 Jul 2021 15:10:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A6B9B4068F;\n\tTue, 20 Jul 2021 15:10:20 +0200 (CEST)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam07on2045.outbound.protection.outlook.com [40.107.95.45])\n by mails.dpdk.org (Postfix) with ESMTP id 958104068F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<shirik@nvidia.com>, <gakhil@marvell.com>", "CC": "<matan@nvidia.com>, <david.marchand@redhat.com>, <dev@dpdk.org>, \"Michael\n Baum\" <michaelba@nvidia.com>", "Date": "Tue, 20 Jul 2021 16:09:35 +0300", "Message-ID": "<20210720130944.5407-7-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210720130944.5407-1-suanmingm@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210720130944.5407-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "8416f1ea-6103-4ea9-7689-08d94b7fb780", "X-MS-TrafficTypeDiagnostic": "DM4PR12MB5277:", "X-Microsoft-Antispam-PRVS": "\n <DM4PR12MB5277059B8647EC866F10F893C1E29@DM4PR12MB5277.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:785;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n w8eHm7trde6HOGtGTTe8cAz0bMptraixMcS7NpscvgvfZOOZF5N8LPsB89ArEPIM2A18oI33q6GrOJ8FRpNfwUdS/gBRG3bjgneIgelh8xJT7I9ROXc43ReBwpaozCfe1rALLgqXAZ5jMnW4EMRCG5bepcOg/OZSVfSqNadbvoSO64v9H0o9sha/HrYX2yI4YrPHVNV1K1ZJd4yHpECG/ii4FJNuIpAU5q0mjznbKVItiCFOcIA7xA0yHEKJbh3YvgORLGYkrif6DoegvFV65N9ZGdjn9RjjIXFCAacSdDMZ2Z48D8q7wLa/dVoS2Puw73tFpXnkSDExO+j/Re2O+oehcDkmg9wPVtUqp2+nNTWXc44gS8tdhQLJbk6IQn616O4SWv9QDVCQHdmV1H+rRbGhRMrbkk1UzHAki6JKelVIKGP4jhYzydYHLDH2DPOp36E+eF/bqzk9UH7scBBRa+qKGmH1FqvGSLlw2amd1ks9sib425U5Uqoyeq1GKQAQUn2QGT5nAUndUk66xrFWaySG94xZ1mxE1VRCgQqvugfuIsDOTM4Zzq7K3CvwMnn/K4vFLFXx/9joeXdg5Quze2/NIrJf0IMr6RG7zYLvZFhePhSsxmg9pW3nfwhbWUA4gs+mzL3hFbQeVAOoxITcOd7qm0XlcJflgkZv5BkAc7ItjefYFLBXutpYQOWNItCqXFV2CPoqujW2NB3vU6MKkQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(39860400002)(136003)(346002)(396003)(36840700001)(46966006)(70586007)(110136005)(6666004)(70206006)(107886003)(7636003)(478600001)(336012)(7696005)(26005)(356005)(1076003)(5660300002)(186003)(4326008)(316002)(86362001)(36906005)(16526019)(8936002)(55016002)(2616005)(82310400003)(36756003)(6286002)(36860700001)(82740400003)(83380400001)(426003)(8676002)(47076005)(2906002)(54906003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jul 2021 13:10:16.0065 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8416f1ea-6103-4ea9-7689-08d94b7fb780", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5277", "Subject": "[dpdk-dev] [PATCH v9 06/15] crypto/mlx5: add memory region\n management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nMellanox user space drivers don't deal with physical addresses as part\nof a memory protection mechanism.\nThe device translates the given virtual address to a physical address\nusing the given memory key as an address space identifier.\nThat's why any mbuf virtual address is moved directly to the HW\ndescriptor(WQE).\n\nThe mapping between the virtual address to the physical address is saved\nin MR configured by the kernel to the HW.\n\nEach MR has a key that should also be moved to the WQE by the SW.\n\nWhen the SW sees an unmapped address, it extends the address range and\ncreates a MR using a system call.\n\nAdd memory region cache management:\n\t- 2 level cache per queue-pair - no locks.\n\t- 1 shared cache between all the queues using a lock.\n\nUsing this way, the MR key search per data-path address is optimized.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/cryptodevs/mlx5.rst | 6 +++\n drivers/crypto/mlx5/mlx5_crypto.c | 63 +++++++++++++++++++++++++++++++\n drivers/crypto/mlx5/mlx5_crypto.h | 3 ++\n 3 files changed, 72 insertions(+)", "diff": "diff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nindex ecab385c0d..c41db95d40 100644\n--- a/doc/guides/cryptodevs/mlx5.rst\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -26,6 +26,12 @@ the MKEY is configured to perform crypto operations.\n \n The encryption does not require text to be aligned to the AES block size (128b).\n \n+For security reasons and to increase robustness, this driver only deals with virtual\n+memory addresses. The way resources allocations are handled by the kernel,\n+combined with hardware specifications that allow handling virtual memory\n+addresses directly, ensure that DPDK applications cannot access random\n+physical memory (or memory that does not belong to the current process).\n+\n The PMD uses libibverbs and libmlx5 to access the device firmware or to\n access the hardware components directly.\n There are different levels of objects and bypassing abilities.\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 2fe2e8b871..9416590aba 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -259,6 +259,7 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n \t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));\n \tif (qp->umem_buf != NULL)\n \t\trte_free(qp->umem_buf);\n+\tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n \tmlx5_devx_cq_destroy(&qp->cq_obj);\n \trte_free(qp);\n \tdev->data->queue_pairs[qp_id] = NULL;\n@@ -340,6 +341,14 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Failed to register QP umem.\");\n \t\tgoto error;\n \t}\n+\tif (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,\n+\t\t\t priv->dev_config.socket_id) != 0) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate MR Btree for qp %u.\",\n+\t\t\t(uint32_t)qp_id);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tqp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;\n \tattr.pd = priv->pdn;\n \tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n \tattr.cqn = qp->cq_obj.cq->id;\n@@ -446,6 +455,40 @@ mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)\n \treturn 0;\n }\n \n+/**\n+ * Callback for memory event.\n+ *\n+ * @param event_type\n+ * Memory event type.\n+ * @param addr\n+ * Address of memory.\n+ * @param len\n+ * Size of memory.\n+ */\n+static void\n+mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n+\t\t\t size_t len, void *arg __rte_unused)\n+{\n+\tstruct mlx5_crypto_priv *priv;\n+\n+\t/* Must be called from the primary process. */\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tswitch (event_type) {\n+\tcase RTE_MEM_EVENT_FREE:\n+\t\tpthread_mutex_lock(&priv_list_lock);\n+\t\t/* Iterate all the existing mlx5 devices. */\n+\t\tTAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)\n+\t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n+\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t addr, len);\n+\t\tpthread_mutex_unlock(&priv_list_lock);\n+\t\tbreak;\n+\tcase RTE_MEM_EVENT_ALLOC:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n /**\n * DPDK callback to register a PCI device.\n *\n@@ -528,6 +571,22 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\treturn -1;\n \t}\n+\tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n+\t\t\t MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n+\t\tmlx5_crypto_hw_global_release(priv);\n+\t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n+\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n+\tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n+\t/* Register callback function for global shared MR cache management. */\n+\tif (TAILQ_EMPTY(&mlx5_crypto_priv_list))\n+\t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\tmlx5_crypto_mr_mem_event_cb,\n+\t\t\t\t\t\tNULL);\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n@@ -547,6 +606,10 @@ mlx5_crypto_pci_remove(struct rte_pci_device *pdev)\n \t\tTAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n \tif (priv) {\n+\t\tif (TAILQ_EMPTY(&mlx5_crypto_priv_list))\n+\t\t\trte_mem_event_callback_unregister(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\t\t NULL);\n+\t\tmlx5_mr_release_cache(&priv->mr_scache);\n \t\tmlx5_crypto_hw_global_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 949092cd37..af292ed19f 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -12,6 +12,7 @@\n \n #include <mlx5_common_utils.h>\n #include <mlx5_common_devx.h>\n+#include <mlx5_common_mr.h>\n \n #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n #define MLX5_CRYPTO_KEY_LENGTH 80\n@@ -27,6 +28,7 @@ struct mlx5_crypto_priv {\n \tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tstruct rte_cryptodev_config dev_config;\n+\tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n };\n \n struct mlx5_crypto_qp {\n@@ -36,6 +38,7 @@ struct mlx5_crypto_qp {\n \tvoid *umem_buf;\n \tvolatile uint32_t *db_rec;\n \tstruct rte_crypto_op **ops;\n+\tstruct mlx5_mr_ctrl mr_ctrl;\n };\n \n struct mlx5_crypto_dek {\n", "prefixes": [ "v9", "06/15" ] }