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GET /api/patches/9591/?format=api
{ "id": 9591, "url": "http://patches.dpdk.org/api/patches/9591/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1450354363-102022-1-git-send-email-wojciechx.andralojc@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1450354363-102022-1-git-send-email-wojciechx.andralojc@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1450354363-102022-1-git-send-email-wojciechx.andralojc@intel.com", "date": "2015-12-17T12:12:43", "name": "[dpdk-dev] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR), rte_msr_read and rte_msr_write functions.", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d12a45046e3c0f22a1bce7e9d93951f84412d317", "submitter": { "id": 402, "url": "http://patches.dpdk.org/api/people/402/?format=api", "name": "Wojciech Andralojc", "email": "wojciechx.andralojc@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1450354363-102022-1-git-send-email-wojciechx.andralojc@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/9591/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/9591/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id DF0D08D3A;\n\tThu, 17 Dec 2015 13:13:03 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 1F6117E23\n\tfor <dev@dpdk.org>; Thu, 17 Dec 2015 13:13:01 +0100 (CET)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga102.fm.intel.com with ESMTP; 17 Dec 2015 04:13:00 -0800", "from sie-lab-213-067.ir.intel.com (HELO\n\tsilpixa00385445.ir.intel.com) ([10.237.213.67])\n\tby orsmga003.jf.intel.com with ESMTP; 17 Dec 2015 04:12:59 -0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,440,1444719600\"; d=\"scan'208\";a=\"709605511\"", "From": "Wojciech Andralojc <wojciechx.andralojc@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 17 Dec 2015 12:12:43 +0000", "Message-Id": "<1450354363-102022-1-git-send-email-wojciechx.andralojc@intel.com>", "X-Mailer": "git-send-email 1.9.3", "Subject": "[dpdk-dev] [PATCH] Patch introducing API to read/write Intel\n\tArchitecture Model Specific Registers (MSR),\n\trte_msr_read and rte_msr_write functions.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "There is work in progress to implement Intel Cache Allocation Technology (CAT) support in DPDK, this technology is programmed through MSRs.\nIn the future it will be possible to program CAT through Linux cgroups and DPDK CAT implementation will take advantage of it.\n\nMSR R/W's are privileged ring 0 operations and they must be done in kernel space. For this reason implementation utilizes Linux MSR driver.\n\nSigned-off-by: Wojciech Andralojc <wojciechx.andralojc@intel.com>\n---\n lib/librte_eal/common/Makefile | 1 +\n lib/librte_eal/common/include/arch/arm/rte_msr.h | 65 ++++++++++\n .../common/include/arch/ppc_64/rte_msr.h | 65 ++++++++++\n lib/librte_eal/common/include/arch/tile/rte_msr.h | 65 ++++++++++\n lib/librte_eal/common/include/arch/x86/rte_msr.h | 143 +++++++++++++++++++++\n lib/librte_eal/common/include/generic/rte_msr.h | 78 +++++++++++\n lib/librte_eal/common/include/rte_lcore.h | 18 +++\n 7 files changed, 435 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_msr.h\n create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_msr.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_msr.h\n create mode 100644 lib/librte_eal/common/include/arch/x86/rte_msr.h\n create mode 100644 lib/librte_eal/common/include/generic/rte_msr.h", "diff": "diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex f5ea0ee..567c206 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -48,6 +48,7 @@ endif\n \n GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\n GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h\n+GENERIC_INC += rte_msr.h\n # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk\n ARCH_DIR ?= $(RTE_ARCH)\n ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_msr.h b/lib/librte_eal/common/include/arch/arm/rte_msr.h\nnew file mode 100644\nindex 0000000..85c009c\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_msr.h\n@@ -0,0 +1,65 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_MSR_ARM_H_\n+#define _RTE_MSR_ARM_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_msr.h\"\n+\n+/* Function to read CPU's MSR */\n+static inline int\n+rte_msr_read(__attribute__((unused)) const unsigned lcore,\n+\t\t__attribute__((unused)) const uint32_t reg,\n+\t\t__attribute__((unused)) uint64_t *value)\n+{\n+\treturn -1;\n+}\n+\n+/* Function to write CPU's MSR */\n+static inline int\n+rte_msr_write(__attribute__((unused)) const unsigned lcore,\n+\t\t__attribute__((unused)) const uint32_t reg,\n+\t\t__attribute__((unused)) const uint64_t value)\n+{\n+\treturn -1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_MSR_ARM_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_msr.h b/lib/librte_eal/common/include/arch/ppc_64/rte_msr.h\nnew file mode 100644\nindex 0000000..44f3de2\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_msr.h\n@@ -0,0 +1,65 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_MSR_PPC_64_H_\n+#define _RTE_MSR_PPC_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_msr.h\"\n+\n+/* Function to read CPU's MSR */\n+static inline int\n+rte_msr_read(__attribute__((unused)) const unsigned lcore,\n+\t\t__attribute__((unused)) const uint32_t reg,\n+\t\t__attribute__((unused)) uint64_t *value)\n+{\n+\treturn -1;\n+}\n+\n+/* Function to write CPU's MSR */\n+static inline int\n+rte_msr_write(__attribute__((unused)) const unsigned lcore,\n+\t\t__attribute__((unused)) const uint32_t reg,\n+\t\t__attribute__((unused)) const uint64_t value)\n+{\n+\treturn -1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_MSR_PPC_64_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_msr.h b/lib/librte_eal/common/include/arch/tile/rte_msr.h\nnew file mode 100644\nindex 0000000..8a446f7\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_msr.h\n@@ -0,0 +1,65 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_MSR_TILE_H_\n+#define _RTE_MSR_TILE_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_msr.h\"\n+\n+/* Function to read CPU's MSR */\n+static inline int\n+rte_msr_read(__attribute__((unused)) const unsigned lcore,\n+\t\t__attribute__((unused)) const uint32_t reg,\n+\t\t__attribute__((unused)) uint64_t *value)\n+{\n+\treturn -1;\n+}\n+\n+/* Function to write CPU's MSR */\n+static inline int\n+rte_msr_write(__attribute__((unused)) const unsigned lcore,\n+\t\t__attribute__((unused)) const uint32_t reg,\n+\t\t__attribute__((unused)) const uint64_t value)\n+{\n+\treturn -1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_MSR_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/x86/rte_msr.h b/lib/librte_eal/common/include/arch/x86/rte_msr.h\nnew file mode 100644\nindex 0000000..7632208\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/x86/rte_msr.h\n@@ -0,0 +1,143 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_MSR_X86_64_H_\n+#define _RTE_MSR_X86_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <fcntl.h> /* O_RDONLY */\n+#include <unistd.h> /* pread */\n+\n+#include <rte_debug.h>\n+#include <rte_lcore.h>\n+#include <rte_log.h>\n+\n+#include \"generic/rte_msr.h\"\n+\n+#define CPU_MSR_PATH \"/dev/cpu/%u/msr\"\n+#define CPU_MSR_PATH_MAX_LEN 32\n+\n+/**\n+ * This function should not be called directly.\n+ * Function to open CPU's MSR file\n+ */\n+static int\n+__msr_open_file(const unsigned lcore, int flags)\n+{\n+\tRTE_VERIFY(rte_lcore_is_detected(lcore) == 1);\n+\tif (rte_lcore_is_detected(lcore) != 1)\n+\t\treturn -1;\n+\n+\tint fd = -1;\n+\n+\tchar fname[CPU_MSR_PATH_MAX_LEN];\n+\n+\tmemset(fname, 0, sizeof(fname));\n+\tsnprintf(fname, sizeof(fname)-1, CPU_MSR_PATH, lcore);\n+\n+\tfd = open(fname, flags);\n+\n+\tif (fd < 0)\n+\t\tRTE_LOG(ERR, PQOS, \"Error opening file '%s'!\\n\", fname);\n+\n+\treturn fd;\n+}\n+\n+/* Function to read CPU's MSR */\n+static inline int\n+rte_msr_read(const unsigned lcore, const uint32_t reg, uint64_t *value)\n+{\n+\tRTE_VERIFY(value != NULL);\n+\tRTE_VERIFY(rte_lcore_is_detected(lcore) == 1);\n+\tif (value == NULL || rte_lcore_is_detected(lcore) != 1)\n+\t\treturn -1;\n+\n+\tint ret = -1;\n+\tint fd = -1;\n+\n+\tfd = __msr_open_file(lcore, O_RDONLY);\n+\n+\tif (fd >= 0) {\n+\t\tssize_t read_ret = 0;\n+\n+\t\tread_ret = pread(fd, value, sizeof(value[0]), (off_t)reg);\n+\n+\t\tif (read_ret != sizeof(value[0])) {\n+\t\t\tRTE_LOG(ERR, PQOS, \"RDMSR failed for reg[0x%x] on lcore %u\\n\",\n+\t\t\t\t(unsigned)reg, lcore);\n+\t\t} else\n+\t\t\tret = 0;\n+\n+\t\tclose(fd);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+/* Function to write CPU's MSR */\n+static inline int\n+rte_msr_write(const unsigned lcore, const uint32_t reg, const uint64_t value)\n+{\n+\tRTE_VERIFY(rte_lcore_is_detected(lcore) == 1);\n+\tif (rte_lcore_is_detected(lcore) != 1)\n+\t\treturn -1;\n+\n+\tint ret = -1;\n+\tint fd = -1;\n+\n+\tfd = __msr_open_file(lcore, O_WRONLY);\n+\n+\tif (fd >= 0) {\n+\t\tssize_t write_ret = 0;\n+\n+\t\twrite_ret = pwrite(fd, &value, sizeof(value), (off_t)reg);\n+\t\tif (write_ret != sizeof(value)) {\n+\t\t\tRTE_LOG(ERR, PQOS, \"WRMSR failed for reg[0x%x] <- value[0x%llx] on \"\n+\t\t\t\t\t\"lcore %u\\n\", (unsigned)reg, (unsigned long long)value, lcore);\n+\t\t} else\n+\t\t\tret = 0;\n+\n+\t\tclose(fd);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_MSR_X86_64_H_ */\ndiff --git a/lib/librte_eal/common/include/generic/rte_msr.h b/lib/librte_eal/common/include/generic/rte_msr.h\nnew file mode 100644\nindex 0000000..62f0530\n--- /dev/null\n+++ b/lib/librte_eal/common/include/generic/rte_msr.h\n@@ -0,0 +1,78 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_MSR_H_\n+#define _RTE_MSR_H_\n+\n+/**\n+ * @file\n+ * Architecture specific API to read/write CPU's MSR.\n+ */\n+\n+#include <stdint.h>\n+\n+/**\n+ * Function to read CPU's MSR\n+ *\n+ * @param [in] lcore\n+ * CPU logical core id\n+ *\n+ * @param [in] reg\n+ * MSR reg to read\n+ *\n+ * @param [out] value\n+ * Read value of MSR reg\n+ *\n+ * @return\n+ * Operations status\n+ */\n+static inline int rte_msr_read(const unsigned lcore, const uint32_t reg, uint64_t *value);\n+\n+/**\n+ * Function to write CPU's MSR\n+ *\n+ * @param [in] lcore\n+ * CPU logical core id\n+ *\n+ * @param [in] reg\n+ * MSR reg to write\n+ *\n+ * @param [out] value\n+ * Value to be written to MSR reg\n+ *\n+ * @return\n+ * Operations status\n+ */\n+static inline int rte_msr_write(const unsigned lcore, const uint32_t reg, const uint64_t value);\n+\n+#endif /* _RTE_MSR_H_ */\ndiff --git a/lib/librte_eal/common/include/rte_lcore.h b/lib/librte_eal/common/include/rte_lcore.h\nindex 25460b9..1b72d36 100644\n--- a/lib/librte_eal/common/include/rte_lcore.h\n+++ b/lib/librte_eal/common/include/rte_lcore.h\n@@ -268,6 +268,24 @@ void rte_thread_get_affinity(rte_cpuset_t *cpusetp);\n #endif\n #endif\n \n+/**\n+ * Test if lcore is detected lcore in system.\n+ *\n+ * @param lcore_id\n+ * The identifier of the lcore, which MUST be between 0 and\n+ * RTE_MAX_LCORE-1.\n+ * @return\n+ * True if the given lcore is detected; false otherwise.\n+ */\n+static inline unsigned\n+rte_lcore_is_detected(const unsigned lcore_id)\n+{\n+ if (lcore_id >= RTE_MAX_LCORE)\n+\treturn 0;\n+\n+ return lcore_config[lcore_id].detected;\n+}\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "dpdk-dev" ] }