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GET /api/patches/95685/?format=api
{ "id": 95685, "url": "http://patches.dpdk.org/api/patches/95685/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210712064901.1619583-1-psatheesh@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210712064901.1619583-1-psatheesh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210712064901.1619583-1-psatheesh@marvell.com", "date": "2021-07-12T06:49:00", "name": "[1/2] common/cnxk: add support for rte flow item raw", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d75d3d9ca6f4355813810e999c1c1a73ed3f1f28", "submitter": { "id": 1663, "url": "http://patches.dpdk.org/api/people/1663/?format=api", "name": "Satheesh Paul Antonysamy", "email": "psatheesh@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210712064901.1619583-1-psatheesh@marvell.com/mbox/", "series": [ { "id": 17761, "url": "http://patches.dpdk.org/api/series/17761/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17761", "date": "2021-07-12T06:49:00", "name": "[1/2] common/cnxk: add support for rte flow item raw", "version": 1, "mbox": "http://patches.dpdk.org/series/17761/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95685/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/95685/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D07B6A0C4F;\n\tMon, 12 Jul 2021 08:49:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 58C6F40685;\n\tMon, 12 Jul 2021 08:49:11 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5B5B44003C\n for <dev@dpdk.org>; Mon, 12 Jul 2021 08:49:09 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 16C6kubt002991 for <dev@dpdk.org>; Sun, 11 Jul 2021 23:49:08 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39re6vgews-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 11 Jul 2021 23:49:08 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 11 Jul 2021 23:49:06 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 11 Jul 2021 23:49:06 -0700", "from localhost.localdomain (unknown [10.28.34.33])\n by maili.marvell.com (Postfix) with ESMTP id 736F95B6940;\n Sun, 11 Jul 2021 23:49:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=uld+GfrrkXuIOzk/R0y0tM1xTX+CFKVPjm9jauvKgCY=;\n b=cxhZp+pImBaMpAEhROL4bApxags9IK9ZZPIiN8basTL+KfeKUJXf/xlhFz6xV4iJu2AY\n R44yGu67wKRsjH5YNyzwDi1WC4o5p3R38lhtflSlX/QTxh/APvWHKbe+tQJ17hBb3Og/\n CG7bUO4/v7OlB8i9i6WtixSARASpDPvTNtUNFOcHZK/A5F5TT7ADkX2hMShNyMfDTpsH\n dGuSHb3lX062iuhv5Tej7kzpbpl9tB5DsxjPENWw2Pf7QFD4UGwWxshgqbHgYltPzPhA\n vuHAdkGPsP8JAxxRAfMT6bJnF1yLmmXyzHAM7b59+YTO9VK3qkCO3BPmn9Upy3C0bW0A 8A==", "From": "<psatheesh@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Satheesh Paul <psatheesh@marvell.com>", "Date": "Mon, 12 Jul 2021 12:19:00 +0530", "Message-ID": "<20210712064901.1619583-1-psatheesh@marvell.com>", "X-Mailer": "git-send-email 2.25.4", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "LQHj2QblH6-gcEwN-xjxl3YPjOPpn2mU", "X-Proofpoint-ORIG-GUID": "LQHj2QblH6-gcEwN-xjxl3YPjOPpn2mU", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-07-12_04:2021-07-12,\n 2021-07-12 signatures=0", "Subject": "[dpdk-dev] [PATCH 1/2] common/cnxk: add support for rte flow item\n raw", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Satheesh Paul <psatheesh@marvell.com>\n\nAdd roc API for rte_flow_item_raw to parse custom L2 and L3 protocols.\n\nSigned-off-by: Satheesh Paul <psatheesh@marvell.com>\nReviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 24 ++++++--\n drivers/common/cnxk/roc_nix_ops.c | 14 +++++\n drivers/common/cnxk/roc_npc.h | 11 ++++\n drivers/common/cnxk/roc_npc_parse.c | 86 +++++++++++++++++++++++++++--\n drivers/common/cnxk/roc_npc_priv.h | 9 +--\n drivers/common/cnxk/roc_npc_utils.c | 6 +-\n drivers/common/cnxk/roc_utils.c | 2 +-\n 7 files changed, 136 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 9c529d754..b254f005a 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -278,14 +278,28 @@ struct ready_msg_rsp {\n \tuint16_t __io rclk_freq; /* RCLK frequency */\n };\n \n+enum npc_pkind_type {\n+\tNPC_RX_VLAN_EXDSA_PKIND = 56ULL,\n+\tNPC_RX_CHLEN24B_PKIND,\n+\tNPC_RX_CPT_HDR_PKIND,\n+\tNPC_RX_CHLEN90B_PKIND,\n+\tNPC_TX_HIGIG_PKIND,\n+\tNPC_RX_HIGIG_PKIND,\n+\tNPC_RX_EXDSA_PKIND,\n+\tNPC_RX_EDSA_PKIND,\n+\tNPC_TX_DEF_PKIND,\n+};\n+\n /* Struct to set pkind */\n struct npc_set_pkind {\n \tstruct mbox_msghdr hdr;\n-#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)\n-#define ROC_PRIV_FLAGS_EDSA BIT_ULL(1)\n-#define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2)\n-#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)\n-#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)\n+#define ROC_PRIV_FLAGS_DEFAULT\t BIT_ULL(0)\n+#define ROC_PRIV_FLAGS_EDSA\t BIT_ULL(1)\n+#define ROC_PRIV_FLAGS_HIGIG\t BIT_ULL(2)\n+#define ROC_PRIV_FLAGS_LEN_90B\t BIT_ULL(3)\n+#define ROC_PRIV_FLAGS_EXDSA\t BIT_ULL(4)\n+#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)\n+#define ROC_PRIV_FLAGS_CUSTOM\t BIT_ULL(63)\n \tuint64_t __io mode;\n #define PKIND_TX BIT_ULL(0)\n #define PKIND_RX BIT_ULL(1)\ndiff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c\nindex eeb85a54f..0e28302e7 100644\n--- a/drivers/common/cnxk/roc_nix_ops.c\n+++ b/drivers/common/cnxk/roc_nix_ops.c\n@@ -378,6 +378,8 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)\n \t switch_header_type != ROC_PRIV_FLAGS_EDSA &&\n \t switch_header_type != ROC_PRIV_FLAGS_HIGIG &&\n \t switch_header_type != ROC_PRIV_FLAGS_LEN_90B &&\n+\t switch_header_type != ROC_PRIV_FLAGS_EXDSA &&\n+\t switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA &&\n \t switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {\n \t\tplt_err(\"switch header type is not supported\");\n \t\treturn NIX_ERR_PARAM;\n@@ -399,6 +401,18 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)\n \tif (req == NULL)\n \t\treturn rc;\n \treq->mode = switch_header_type;\n+\n+\tif (switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {\n+\t\treq->mode = ROC_PRIV_FLAGS_CUSTOM;\n+\t\treq->pkind = NPC_RX_CHLEN90B_PKIND;\n+\t} else if (switch_header_type == ROC_PRIV_FLAGS_EXDSA) {\n+\t\treq->mode = ROC_PRIV_FLAGS_CUSTOM;\n+\t\treq->pkind = NPC_RX_EXDSA_PKIND;\n+\t} else if (switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {\n+\t\treq->mode = ROC_PRIV_FLAGS_CUSTOM;\n+\t\treq->pkind = NPC_RX_VLAN_EXDSA_PKIND;\n+\t}\n+\n \treq->dir = PKIND_RX;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\ndiff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h\nindex 2c0a536c9..bab25fd72 100644\n--- a/drivers/common/cnxk/roc_npc.h\n+++ b/drivers/common/cnxk/roc_npc.h\n@@ -36,6 +36,7 @@ enum roc_npc_item_type {\n \tROC_NPC_ITEM_TYPE_CPT_HDR,\n \tROC_NPC_ITEM_TYPE_L3_CUSTOM,\n \tROC_NPC_ITEM_TYPE_QINQ,\n+\tROC_NPC_ITEM_TYPE_RAW,\n \tROC_NPC_ITEM_TYPE_END,\n };\n \n@@ -47,6 +48,16 @@ struct roc_npc_item_info {\n \tconst void *last; /* For range */\n };\n \n+struct roc_npc_flow_item_raw {\n+\tuint32_t relative : 1; /**< Look for pattern after the previous item. */\n+\tuint32_t search : 1; /**< Search pattern from offset. */\n+\tuint32_t reserved : 30; /**< Reserved, must be set to zero. */\n+\tint32_t offset;\t\t/**< Absolute or relative offset for pattern. */\n+\tuint16_t limit;\t\t/**< Search area limit for start of pattern. */\n+\tuint16_t length;\t/**< Pattern length. */\n+\tconst uint8_t *pattern; /**< Byte string to look for. */\n+};\n+\n #define ROC_NPC_MAX_ACTION_COUNT 12\n \n enum roc_npc_action_type {\ndiff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c\nindex d07f91db3..8125035dd 100644\n--- a/drivers/common/cnxk/roc_npc_parse.c\n+++ b/drivers/common/cnxk/roc_npc_parse.c\n@@ -136,14 +136,46 @@ npc_parse_la(struct npc_parse_state *pst)\n \treturn npc_update_parse_state(pst, &info, lid, lt, 0);\n }\n \n+static int\n+npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec,\n+\t\t\t const struct roc_npc_flow_item_raw *raw_mask,\n+\t\t\t struct npc_parse_item_info *info, uint8_t *spec_buf,\n+\t\t\t uint8_t *mask_buf)\n+{\n+\tuint32_t custom_hdr_size = 0;\n+\n+\tmemset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN);\n+\tmemset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN);\n+\tcustom_hdr_size = raw_spec->offset + raw_spec->length;\n+\n+\tmemcpy(spec_buf + raw_spec->offset, raw_spec->pattern,\n+\t raw_spec->length);\n+\n+\tif (raw_mask->pattern) {\n+\t\tmemcpy(mask_buf + raw_spec->offset, raw_mask->pattern,\n+\t\t raw_spec->length);\n+\t} else {\n+\t\tmemset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length);\n+\t}\n+\n+\tinfo->len = custom_hdr_size;\n+\tinfo->spec = spec_buf;\n+\tinfo->mask = mask_buf;\n+\n+\treturn 0;\n+}\n+\n int\n npc_parse_lb(struct npc_parse_state *pst)\n {\n \tconst struct roc_npc_item_info *pattern = pst->pattern;\n \tconst struct roc_npc_item_info *last_pattern;\n+\tconst struct roc_npc_flow_item_raw *raw_spec;\n+\tuint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];\n+\tuint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];\n \tchar hw_mask[NPC_MAX_EXTRACT_HW_LEN];\n \tstruct npc_parse_item_info info;\n-\tint lid, lt, lflags;\n+\tint lid, lt, lflags, len = 0;\n \tint nr_vlans = 0;\n \tint rc;\n \n@@ -221,13 +253,35 @@ npc_parse_lb(struct npc_parse_state *pst)\n \t\tinfo.len = pst->pattern->size;\n \t\tlt = NPC_LT_LB_STAG_QINQ;\n \t\tlflags = NPC_F_STAG_CTAG;\n+\t} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) {\n+\t\traw_spec = pst->pattern->spec;\n+\t\tif (raw_spec->relative)\n+\t\t\treturn 0;\n+\t\tlen = raw_spec->length + raw_spec->offset;\n+\t\tif (len > NPC_MAX_RAW_ITEM_LEN)\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (pst->npc->switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {\n+\t\t\tlt = NPC_LT_LB_VLAN_EXDSA;\n+\t\t} else if (pst->npc->switch_header_type ==\n+\t\t\t ROC_PRIV_FLAGS_EXDSA) {\n+\t\t\tlt = NPC_LT_LB_EXDSA;\n+\t\t} else {\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tnpc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)\n+\t\t\t\t\t\t pst->pattern->spec,\n+\t\t\t\t\t (const struct roc_npc_flow_item_raw *)\n+\t\t\t\t\t\t pst->pattern->mask,\n+\t\t\t\t\t &info, raw_spec_buf, raw_mask_buf);\n+\n+\t\tinfo.hw_hdr_len = 0;\n \t} else {\n \t\treturn 0;\n \t}\n \n \tinfo.hw_mask = &hw_mask;\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n \tnpc_get_hw_supp_mask(pst, &info, lid, lt);\n \n \trc = npc_parse_item_basic(pst->pattern, &info);\n@@ -340,9 +394,12 @@ npc_check_lc_ip_tunnel(struct npc_parse_state *pst)\n int\n npc_parse_lc(struct npc_parse_state *pst)\n {\n+\tconst struct roc_npc_flow_item_raw *raw_spec;\n+\tuint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];\n+\tuint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];\n \tuint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN];\n \tstruct npc_parse_item_info info;\n-\tint lid, lt;\n+\tint lid, lt, len = 0;\n \tint rc;\n \n \tif (pst->pattern->type == ROC_NPC_ITEM_TYPE_MPLS)\n@@ -378,6 +435,26 @@ npc_parse_lc(struct npc_parse_state *pst)\n \t\tlt = NPC_LT_LC_CUSTOM0;\n \t\tinfo.len = pst->pattern->size;\n \t\tbreak;\n+\tcase ROC_NPC_ITEM_TYPE_RAW:\n+\t\traw_spec = pst->pattern->spec;\n+\t\tif (!raw_spec->relative)\n+\t\t\treturn 0;\n+\n+\t\tlen = raw_spec->length + raw_spec->offset;\n+\t\tif (len > NPC_MAX_RAW_ITEM_LEN)\n+\t\t\treturn -EINVAL;\n+\n+\t\tnpc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)\n+\t\t\t\t\t\t pst->pattern->spec,\n+\t\t\t\t\t (const struct roc_npc_flow_item_raw *)\n+\t\t\t\t\t\t pst->pattern->mask,\n+\t\t\t\t\t &info, raw_spec_buf, raw_mask_buf);\n+\n+\t\tlid = NPC_LID_LC;\n+\t\tlt = NPC_LT_LC_NGIO;\n+\t\tinfo.hw_mask = &hw_mask;\n+\t\tnpc_get_hw_supp_mask(pst, &info, lid, lt);\n+\t\tbreak;\n \tdefault:\n \t\t/* No match at this layer */\n \t\treturn 0;\n@@ -388,6 +465,7 @@ npc_parse_lc(struct npc_parse_state *pst)\n \n \tnpc_get_hw_supp_mask(pst, &info, lid, lt);\n \trc = npc_parse_item_basic(pst->pattern, &info);\n+\n \tif (rc != 0)\n \t\treturn rc;\n \ndiff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h\nindex 484c3aeb1..5b884e3fd 100644\n--- a/drivers/common/cnxk/roc_npc_priv.h\n+++ b/drivers/common/cnxk/roc_npc_priv.h\n@@ -5,10 +5,11 @@\n #ifndef _ROC_NPC_PRIV_H_\n #define _ROC_NPC_PRIV_H_\n \n-#define NPC_IH_LENGTH\t 8\n-#define NPC_TPID_LENGTH\t 2\n-#define NPC_HIGIG2_LENGTH 16\n-#define NPC_COUNTER_NONE (-1)\n+#define NPC_IH_LENGTH\t 8\n+#define NPC_TPID_LENGTH\t 2\n+#define NPC_HIGIG2_LENGTH 16\n+#define NPC_MAX_RAW_ITEM_LEN 16\n+#define NPC_COUNTER_NONE (-1)\n \n #define NPC_RSS_GRPS 8\n \ndiff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c\nindex 5c97588e6..5fcb56c35 100644\n--- a/drivers/common/cnxk/roc_npc_utils.c\n+++ b/drivers/common/cnxk/roc_npc_utils.c\n@@ -130,7 +130,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,\n \t}\n \n \t/* We have valid spec */\n-\tinfo->spec = item->spec;\n+\tif (item->type != ROC_NPC_ITEM_TYPE_RAW)\n+\t\tinfo->spec = item->spec;\n \n \t/* If mask is not set, use default mask, err if default mask is\n \t * also NULL.\n@@ -140,7 +141,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,\n \t\t\treturn NPC_ERR_PARAM;\n \t\tinfo->mask = info->def_mask;\n \t} else {\n-\t\tinfo->mask = item->mask;\n+\t\tif (item->type != ROC_NPC_ITEM_TYPE_RAW)\n+\t\t\tinfo->mask = item->mask;\n \t}\n \n \t/* mask specified must be subset of hw supported mask\ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex 542252fe4..9cb8708a7 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -113,7 +113,7 @@ roc_error_msg_get(int errorcode)\n \t\terr_msg = \"NPC invalid spec\";\n \t\tbreak;\n \tcase NPC_ERR_INVALID_MASK:\n-\t\terr_msg = \"NPC invalid mask\";\n+\t\terr_msg = \"NPC invalid mask\";\n \t\tbreak;\n \tcase NPC_ERR_INVALID_KEX:\n \t\terr_msg = \"NPC invalid key\";\n", "prefixes": [ "1/2" ] }