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GET /api/patches/95667/?format=api
{ "id": 95667, "url": "http://patches.dpdk.org/api/patches/95667/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-11-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210712014654.32428-11-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210712014654.32428-11-suanmingm@nvidia.com", "date": "2021-07-12T01:46:38", "name": "[v5,10/26] net/mlx5: manage list cache entries release", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "a09f1ffd89cb8452b937598996ce2680b28a685e", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210712014654.32428-11-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17759, "url": "http://patches.dpdk.org/api/series/17759/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17759", "date": "2021-07-12T01:46:29", "name": "net/mlx5: insertion rate optimization", "version": 5, "mbox": "http://patches.dpdk.org/series/17759/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95667/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/95667/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 77451A0C4D;\n\tMon, 12 Jul 2021 03:48:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E009D411A5;\n\tMon, 12 Jul 2021 03:47:47 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2088.outbound.protection.outlook.com [40.107.92.88])\n by mails.dpdk.org (Postfix) with ESMTP id 98D3941194\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Mon, 12 Jul 2021 04:46:38 +0300", "Message-ID": "<20210712014654.32428-11-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210712014654.32428-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210712014654.32428-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "86d05b19-f404-40fb-c87b-08d944d709de", "X-MS-TrafficTypeDiagnostic": "SA0PR12MB4575:", "X-Microsoft-Antispam-PRVS": "\n <SA0PR12MB457538AC9CB168B90016C89BC1159@SA0PR12MB4575.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:326;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jjTBrCCUCqfxokIpclapSKHoKITOKOdnCD/FngWlXkUOE2FLMMi2OAJguUlZXnpYI1c5AWn2HNwy+ULS2GX69fkSLQXKRLfcfn72a33l/1ctyFWF41T7snv5sZvIruGGMIWOzCIewb0cZCchEyozJfPV1MaI3Mmd1bgv66WZQKzyAgWjeJQcmps8d/TETtAouEjrW1CWyBxGBKtWAJlspOuLONu0p5ZEcajbZc2emLhdyvWxUOcsqugUUrIhdLfhh4IzNcp0hoYfk8KvEIldJBOhiBGMZt3obcCW7j9AtZK4Pzs5NokaxFbvFtNGabKQBvqHb1U+UUX2A1/bfERqM+5vzGU1XTG5TKJ2LgBxsDY5dM0VsLcfKDDpB737VaEyhwoLkc7NrmekH/JwmpriobXP05ERDM3dg1DorC/WwJEOygq9C2wU0lxk4ZeUvPUub25FbiEMHwD5lkS6NJuFcobTYG5raDvtk+gn0tbdDOr+Hf7hxNlQ6EIsw8Z+nKfAkcrbNa0YUxl5HQWeAV49bQB27lGt4P54GYKJEZYlADCK500D6F3wSbwbGA96rDBrGLAvqYC3uJULexjm/K2tS2Wp/pLZNHwr+etrmroZXiYg6yygYMWO4L6db4/ANpupEJJqBi6dNt7srwu0kZc96b/Es53g1sAfmtj2TA5KpI2htaqUPfRQvJZSaMwrZ3aHZbRPUW61hQJPvZ+4pfPP8DahY1dL/hPWK4LZL76XDRc=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(346002)(396003)(376002)(136003)(46966006)(36840700001)(110136005)(36756003)(7696005)(54906003)(82310400003)(82740400003)(36860700001)(4326008)(5660300002)(16526019)(316002)(7636003)(2906002)(55016002)(70586007)(478600001)(186003)(70206006)(36906005)(26005)(356005)(83380400001)(47076005)(426003)(8936002)(6666004)(2616005)(6636002)(86362001)(1076003)(336012)(8676002)(6286002)(34020700004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Jul 2021 01:47:42.1909 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 86d05b19-f404-40fb-c87b-08d944d709de", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT013.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4575", "Subject": "[dpdk-dev] [PATCH v5 10/26] net/mlx5: manage list cache entries\n release", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Matan Azrad <matan@nvidia.com>\n\nWhen a cache entry is allocated by lcore A and is released by lcore B,\nthe driver should synchronize the cache list access of lcore A.\n\nThe design decision is to manage a counter per lcore cache that will be\nincreased atomically when the non-original lcore decreases the reference\ncounter of cache entry to 0.\n\nIn list register operation, before the running lcore starts a lookup in\nits cache, it will check the counter in order to free invalid entries in\nits cache.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_utils.c | 79 +++++++++++++++++++++++------------\n drivers/net/mlx5/mlx5_utils.h | 2 +\n 2 files changed, 54 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c\nindex c4c9adb039..13c7dbe1c2 100644\n--- a/drivers/net/mlx5/mlx5_utils.c\n+++ b/drivers/net/mlx5/mlx5_utils.c\n@@ -47,36 +47,25 @@ __list_lookup(struct mlx5_list *list, int lcore_index, void *ctx, bool reuse)\n \tuint32_t ret;\n \n \twhile (entry != NULL) {\n-\t\tstruct mlx5_list_entry *nentry = LIST_NEXT(entry, next);\n-\n-\t\tif (list->cb_match(list, entry, ctx)) {\n-\t\t\tif (lcore_index < RTE_MAX_LCORE) {\n+\t\tif (list->cb_match(list, entry, ctx) == 0) {\n+\t\t\tif (reuse) {\n+\t\t\t\tret = __atomic_add_fetch(&entry->ref_cnt, 1,\n+\t\t\t\t\t\t\t __ATOMIC_ACQUIRE) - 1;\n+\t\t\t\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p ref: %u.\",\n+\t\t\t\t\tlist->name, (void *)entry,\n+\t\t\t\t\tentry->ref_cnt);\n+\t\t\t} else if (lcore_index < RTE_MAX_LCORE) {\n \t\t\t\tret = __atomic_load_n(&entry->ref_cnt,\n \t\t\t\t\t\t __ATOMIC_ACQUIRE);\n-\t\t\t\tif (ret == 0) {\n-\t\t\t\t\tLIST_REMOVE(entry, next);\n-\t\t\t\t\tlist->cb_clone_free(list, entry);\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tentry = nentry;\n-\t\t\tcontinue;\n-\t\t}\n-\t\tif (reuse) {\n-\t\t\tret = __atomic_add_fetch(&entry->ref_cnt, 1,\n-\t\t\t\t\t\t __ATOMIC_ACQUIRE);\n-\t\t\tif (ret == 1u) {\n-\t\t\t\t/* Entry was invalid before, free it. */\n-\t\t\t\tLIST_REMOVE(entry, next);\n-\t\t\t\tlist->cb_clone_free(list, entry);\n-\t\t\t\tentry = nentry;\n-\t\t\t\tcontinue;\n \t\t\t}\n-\t\t\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p ref++: %u.\",\n-\t\t\t\tlist->name, (void *)entry, entry->ref_cnt);\n+\t\t\tif (likely(ret != 0 || lcore_index == RTE_MAX_LCORE))\n+\t\t\t\treturn entry;\n+\t\t\tif (reuse && ret == 0)\n+\t\t\t\tentry->ref_cnt--; /* Invalid entry. */\n \t\t}\n-\t\tbreak;\n+\t\tentry = LIST_NEXT(entry, next);\n \t}\n-\treturn entry;\n+\treturn NULL;\n }\n \n struct mlx5_list_entry *\n@@ -105,10 +94,31 @@ mlx5_list_cache_insert(struct mlx5_list *list, int lcore_index,\n \t\treturn NULL;\n \tlentry->ref_cnt = 1u;\n \tlentry->gentry = gentry;\n+\tlentry->lcore_idx = (uint32_t)lcore_index;\n \tLIST_INSERT_HEAD(&list->cache[lcore_index].h, lentry, next);\n \treturn lentry;\n }\n \n+static void\n+__list_cache_clean(struct mlx5_list *list, int lcore_index)\n+{\n+\tstruct mlx5_list_cache *c = &list->cache[lcore_index];\n+\tstruct mlx5_list_entry *entry = LIST_FIRST(&c->h);\n+\tuint32_t inv_cnt = __atomic_exchange_n(&c->inv_cnt, 0,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n+\n+\twhile (inv_cnt != 0 && entry != NULL) {\n+\t\tstruct mlx5_list_entry *nentry = LIST_NEXT(entry, next);\n+\n+\t\tif (__atomic_load_n(&entry->ref_cnt, __ATOMIC_RELAXED) == 0) {\n+\t\t\tLIST_REMOVE(entry, next);\n+\t\t\tlist->cb_clone_free(list, entry);\n+\t\t\tinv_cnt--;\n+\t\t}\n+\t\tentry = nentry;\n+\t}\n+}\n+\n struct mlx5_list_entry *\n mlx5_list_register(struct mlx5_list *list, void *ctx)\n {\n@@ -122,6 +132,8 @@ mlx5_list_register(struct mlx5_list *list, void *ctx)\n \t\trte_errno = ENOTSUP;\n \t\treturn NULL;\n \t}\n+\t/* 0. Free entries that was invalidated by other lcores. */\n+\t__list_cache_clean(list, lcore_index);\n \t/* 1. Lookup in local cache. */\n \tlocal_entry = __list_lookup(list, lcore_index, ctx, true);\n \tif (local_entry)\n@@ -147,6 +159,7 @@ mlx5_list_register(struct mlx5_list *list, void *ctx)\n \tentry->ref_cnt = 1u;\n \tlocal_entry->ref_cnt = 1u;\n \tlocal_entry->gentry = entry;\n+\tlocal_entry->lcore_idx = (uint32_t)lcore_index;\n \trte_rwlock_write_lock(&list->lock);\n \t/* 4. Make sure the same entry was not created before the write lock. */\n \tif (unlikely(prev_gen_cnt != list->gen_cnt)) {\n@@ -169,8 +182,8 @@ mlx5_list_register(struct mlx5_list *list, void *ctx)\n \trte_rwlock_write_unlock(&list->lock);\n \tLIST_INSERT_HEAD(&list->cache[lcore_index].h, local_entry, next);\n \t__atomic_add_fetch(&list->count, 1, __ATOMIC_ACQUIRE);\n-\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p new: %u.\",\n-\t\tlist->name, (void *)entry, entry->ref_cnt);\n+\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p new: %u.\", list->name,\n+\t\t(void *)entry, entry->ref_cnt);\n \treturn local_entry;\n }\n \n@@ -179,9 +192,21 @@ mlx5_list_unregister(struct mlx5_list *list,\n \t\t struct mlx5_list_entry *entry)\n {\n \tstruct mlx5_list_entry *gentry = entry->gentry;\n+\tint lcore_idx;\n \n \tif (__atomic_sub_fetch(&entry->ref_cnt, 1, __ATOMIC_ACQUIRE) != 0)\n \t\treturn 1;\n+\tlcore_idx = rte_lcore_index(rte_lcore_id());\n+\tMLX5_ASSERT(lcore_idx < RTE_MAX_LCORE);\n+\tif (entry->lcore_idx == (uint32_t)lcore_idx) {\n+\t\tLIST_REMOVE(entry, next);\n+\t\tlist->cb_clone_free(list, entry);\n+\t} else if (likely(lcore_idx != -1)) {\n+\t\t__atomic_add_fetch(&list->cache[entry->lcore_idx].inv_cnt, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n+\t} else {\n+\t\treturn 0;\n+\t}\n \tif (__atomic_sub_fetch(&gentry->ref_cnt, 1, __ATOMIC_ACQUIRE) != 0)\n \t\treturn 1;\n \trte_rwlock_write_lock(&list->lock);\ndiff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h\nindex 6dade8238d..71da5ab4f9 100644\n--- a/drivers/net/mlx5/mlx5_utils.h\n+++ b/drivers/net/mlx5/mlx5_utils.h\n@@ -311,11 +311,13 @@ struct mlx5_list;\n struct mlx5_list_entry {\n \tLIST_ENTRY(mlx5_list_entry) next; /* Entry pointers in the list. */\n \tuint32_t ref_cnt; /* 0 means, entry is invalid. */\n+\tuint32_t lcore_idx;\n \tstruct mlx5_list_entry *gentry;\n };\n \n struct mlx5_list_cache {\n \tLIST_HEAD(mlx5_list_head, mlx5_list_entry) h;\n+\tuint32_t inv_cnt; /* Invalid entries counter. */\n } __rte_cache_aligned;\n \n /**\n", "prefixes": [ "v5", "10/26" ] }