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GET /api/patches/95566/?format=api
{ "id": 95566, "url": "http://patches.dpdk.org/api/patches/95566/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210708152530.25835-2-shirik@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210708152530.25835-2-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210708152530.25835-2-shirik@nvidia.com", "date": "2021-07-08T15:25:16", "name": "[v6,01/15] drivers: introduce mlx5 crypto PMD", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cda72192943c04d775f6f5f6bbaef70fb2859b21", "submitter": { "id": 1894, "url": "http://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210708152530.25835-2-shirik@nvidia.com/mbox/", "series": [ { "id": 17724, "url": "http://patches.dpdk.org/api/series/17724/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17724", "date": "2021-07-08T15:25:15", "name": "drivers: introduce mlx5 crypto PMD", "version": 6, "mbox": "http://patches.dpdk.org/series/17724/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95566/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/95566/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ED4A9A0C48;\n\tThu, 8 Jul 2021 17:26:17 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7E7A341618;\n\tThu, 8 Jul 2021 17:26:12 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2074.outbound.protection.outlook.com [40.107.92.74])\n by mails.dpdk.org (Postfix) with ESMTP id 2F85C4014F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>,\n <david.marchand@redhat.com>", "Date": "Thu, 8 Jul 2021 18:25:16 +0300", "Message-ID": "<20210708152530.25835-2-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210708152530.25835-1-shirik@nvidia.com>", "References": "<20210701132609.53727-1-shirik@nvidia.com>\n <20210708152530.25835-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "4f8a6852-9784-4164-0d69-08d94224b5bb", "X-MS-TrafficTypeDiagnostic": "DM8PR12MB5496:", "X-Microsoft-Antispam-PRVS": "\n <DM8PR12MB54963CFCA5918747F98F8BF6AA199@DM8PR12MB5496.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:121;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n uhzf4TQGRprQIfvwCqMEXWznyoalHdk7v8zMrVwlj7/CI8xNypw/+fbK4IJ3HR20RV3L/wESkU4aMdevsFPdbuuX4U5EWHhRrLW521UpMM/a1XZ3YP5Fx6Mn1lc/HCw0V6ZpSCvohr+sUvmiRx00vADJCuxubq0VYKxBr7iOf/g+bcvuZvFes3+TBjrhedopasDMEZAMDbK5bxzL3gz64rv/55KcaIp94kEb45M6qJevXZu5asgkfn40VnHRgl2HJjcJykfCSUFO7My0NwkusVNW2LBL4sgjRWQnFJUeFkBjyQZJgwx36LhNZaARi4QxnA/8fJ6TLWIXtL5jngAKbYIvyAXDEtxvh6j1MfahXTiFl8eRzS5KJS2oJcWHOkZOqCXa93A4JK9mzJl+TDdajp5C1GiNKR5PsfHHqUTN1qFOBngF5co8uJCD12sh7ZMASx0kS27ugXfXPh7Ka7jhc9SOy85UPN7Bfq6hAq+RCrKmPJBmwdQi8NAJfrhrv9rawmruc+6ItWaSeKqwXPrxrPsXJcqS7wCCFFDIg5yGbcIIFzKyxw20aLXDq5qSgXitrQddGy7B7TgBD8eeRWUBRKg10b86dhRRXIN/bSlKv9pLJxEzbsjgGxKalFHdPEaQcxeAlH9HJ7s5+cTq7r+9Wd9OHdsH0dwudFtoxMS+skO85GitkbUuoAYRKmWKjBFNtzdDcLHHcgBn9lkkwZYEBA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(39860400002)(346002)(136003)(376002)(36840700001)(46966006)(6286002)(54906003)(336012)(8936002)(70206006)(55016002)(82310400003)(86362001)(6916009)(7696005)(5660300002)(8676002)(36860700001)(16526019)(2616005)(6666004)(30864003)(36756003)(2906002)(36906005)(316002)(82740400003)(83380400001)(47076005)(7636003)(426003)(1076003)(186003)(70586007)(356005)(26005)(4326008)(478600001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Jul 2021 15:26:08.3777 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4f8a6852-9784-4164-0d69-08d94224b5bb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT008.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM8PR12MB5496", "Subject": "[dpdk-dev] [PATCH v6 01/15] drivers: introduce mlx5 crypto PMD", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add a new PMD for Mellanox devices- crypto PMD.\n\nThe crypto PMD will be supported starting Nvidia ConnectX6 and\nBlueField2.\n\nThe crypto PMD will add the support of encryption and decryption using\nthe AES-XTS symmetric algorithm.\n\nThe crypto PMD requires rdma-core and uses mlx5 DevX.\n\nThis patch adds the PCI probing, basic functions, build files and\nlog utility.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n MAINTAINERS | 4 +\n doc/guides/cryptodevs/features/mlx5.ini | 27 +++\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/cryptodevs/mlx5.rst | 63 ++++++\n doc/guides/rel_notes/release_21_08.rst | 5 +\n drivers/common/mlx5/mlx5_common.h | 1 +\n drivers/common/mlx5/mlx5_common_pci.c | 14 ++\n drivers/common/mlx5/mlx5_common_pci.h | 21 +-\n drivers/crypto/meson.build | 1 +\n drivers/crypto/mlx5/meson.build | 26 +++\n drivers/crypto/mlx5/mlx5_crypto.c | 275 ++++++++++++++++++++++++\n drivers/crypto/mlx5/mlx5_crypto_utils.h | 19 ++\n drivers/crypto/mlx5/version.map | 3 +\n 13 files changed, 450 insertions(+), 10 deletions(-)\n create mode 100644 doc/guides/cryptodevs/features/mlx5.ini\n create mode 100644 doc/guides/cryptodevs/mlx5.rst\n create mode 100644 drivers/crypto/mlx5/meson.build\n create mode 100644 drivers/crypto/mlx5/mlx5_crypto.c\n create mode 100644 drivers/crypto/mlx5/mlx5_crypto_utils.h\n create mode 100644 drivers/crypto/mlx5/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex f64fce84ab..0cf9e91330 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1088,6 +1088,10 @@ F: drivers/crypto/octeontx2/\n F: doc/guides/cryptodevs/octeontx2.rst\n F: doc/guides/cryptodevs/features/octeontx2.ini\n \n+Mellanox mlx5\n+M: Matan Azrad <matan@nvidia.com>\n+F: drivers/crypto/mlx5/\n+\n Null Crypto\n M: Declan Doherty <declan.doherty@intel.com>\n F: drivers/crypto/null/\ndiff --git a/doc/guides/cryptodevs/features/mlx5.ini b/doc/guides/cryptodevs/features/mlx5.ini\nnew file mode 100644\nindex 0000000000..ceadd967b6\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/mlx5.ini\n@@ -0,0 +1,27 @@\n+;\n+; Features of a mlx5 crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+HW Accelerated = Y\n+\n+;\n+; Supported crypto algorithms of a mlx5 crypto driver.\n+;\n+[Cipher]\n+\n+;\n+; Supported authentication algorithms of a mlx5 crypto driver.\n+;\n+[Auth]\n+\n+;\n+; Supported AEAD algorithms of a mlx5 crypto driver.\n+;\n+[AEAD]\n+\n+;\n+; Supported Asymmetric algorithms of a mlx5 crypto driver.\n+;\n+[Asymmetric]\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex 279f56a002..747409c441 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -22,6 +22,7 @@ Crypto Device Drivers\n octeontx\n octeontx2\n openssl\n+ mlx5\n mvsam\n nitrox\n null\ndiff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nnew file mode 100644\nindex 0000000000..05a0a449e2\n--- /dev/null\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -0,0 +1,63 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+\n+.. include:: <isonum.txt>\n+\n+MLX5 Crypto Driver\n+==================\n+\n+The MLX5 crypto driver library\n+(**librte_crypto_mlx5**) provides support for **Mellanox ConnectX-6**\n+family adapters.\n+\n+Overview\n+--------\n+\n+The device can provide disk encryption services, allowing data encryption\n+and decryption towards a disk. Having all encryption/decryption\n+operations done in a single device can reduce cost and overheads of the related\n+FIPS certification, as ConnectX-6 is FIPS 140-2 level-2 ready.\n+The encryption cipher is AES-XTS of 256/512 bit key size.\n+\n+MKEY is a memory region object in the hardware, that holds address translation information and\n+attributes per memory area. Its ID must be tied to addresses provided to the hardware.\n+The encryption operations are performed with MKEY read/write transactions, when\n+the MKEY is configured to perform crypto operations.\n+\n+The encryption does not require text to be aligned to the AES block size (128b).\n+\n+The PMD uses libibverbs and libmlx5 to access the device firmware or to\n+access the hardware components directly.\n+There are different levels of objects and bypassing abilities.\n+To get the best performances:\n+\n+- Verbs is a complete high-level generic API.\n+- Direct Verbs is a device-specific API.\n+- DevX allows to access firmware objects.\n+\n+Enabling librte_crypto_mlx5 causes DPDK applications to be linked against\n+libibverbs.\n+\n+\n+Driver options\n+--------------\n+\n+- ``class`` parameter [string]\n+\n+ Select the class of the driver that should probe the device.\n+ `crypto` for the mlx5 crypto driver.\n+\n+\n+Supported NICs\n+--------------\n+\n+* Mellanox\\ |reg| ConnectX\\ |reg|-6 200G MCX654106A-HCAT (2x200G)\n+\n+Prerequisites\n+-------------\n+\n+- Mellanox OFED version: **5.3**\n+ see :doc:`../../nics/mlx5` guide for more Mellanox OFED details.\n+\n+- Compilation can be done also with rdma-core v15+.\n+ see :doc:`../../nics/mlx5` guide for more rdma-core details.\ndiff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst\nindex aca34105c2..d6f98811b5 100644\n--- a/doc/guides/rel_notes/release_21_08.rst\n+++ b/doc/guides/rel_notes/release_21_08.rst\n@@ -98,6 +98,11 @@ New Features\n * Added support for Meter hierarchy.\n * Added devargs options ``allow_duplicate_pattern``.\n \n+* **Added support for Nvidia crypto device driver.**\n+\n+ * Added mlx5 crypto driver to support AES-XTS cipher operations.\n+ The first device to support it is ConnectX-6.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex 306f2f1ab7..790b45f8ea 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -214,6 +214,7 @@ enum mlx5_class {\n \tMLX5_CLASS_VDPA = RTE_BIT64(1),\n \tMLX5_CLASS_REGEX = RTE_BIT64(2),\n \tMLX5_CLASS_COMPRESS = RTE_BIT64(3),\n+\tMLX5_CLASS_CRYPTO = RTE_BIT64(4),\n };\n \n #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE\ndiff --git a/drivers/common/mlx5/mlx5_common_pci.c b/drivers/common/mlx5/mlx5_common_pci.c\nindex 34747c4e07..5547e62d6b 100644\n--- a/drivers/common/mlx5/mlx5_common_pci.c\n+++ b/drivers/common/mlx5/mlx5_common_pci.c\n@@ -31,6 +31,7 @@ static const struct {\n \t{ .name = \"net\", .driver_class = MLX5_CLASS_NET },\n \t{ .name = \"regex\", .driver_class = MLX5_CLASS_REGEX },\n \t{ .name = \"compress\", .driver_class = MLX5_CLASS_COMPRESS },\n+\t{ .name = \"crypto\", .driver_class = MLX5_CLASS_CRYPTO },\n };\n \n static const unsigned int mlx5_class_combinations[] = {\n@@ -38,13 +39,26 @@ static const unsigned int mlx5_class_combinations[] = {\n \tMLX5_CLASS_VDPA,\n \tMLX5_CLASS_REGEX,\n \tMLX5_CLASS_COMPRESS,\n+\tMLX5_CLASS_CRYPTO,\n \tMLX5_CLASS_NET | MLX5_CLASS_REGEX,\n \tMLX5_CLASS_VDPA | MLX5_CLASS_REGEX,\n \tMLX5_CLASS_NET | MLX5_CLASS_COMPRESS,\n \tMLX5_CLASS_VDPA | MLX5_CLASS_COMPRESS,\n \tMLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS,\n+\tMLX5_CLASS_NET | MLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_VDPA | MLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_REGEX | MLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_COMPRESS | MLX5_CLASS_CRYPTO,\n \tMLX5_CLASS_NET | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS,\n \tMLX5_CLASS_VDPA | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS,\n+\tMLX5_CLASS_NET | MLX5_CLASS_REGEX | MLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_VDPA | MLX5_CLASS_REGEX | MLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_NET | MLX5_CLASS_COMPRESS | MLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_VDPA | MLX5_CLASS_COMPRESS | MLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_NET | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS |\n+\tMLX5_CLASS_CRYPTO,\n+\tMLX5_CLASS_VDPA | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS |\n+\tMLX5_CLASS_CRYPTO,\n \t/* New class combination should be added here. */\n };\n \ndiff --git a/drivers/common/mlx5/mlx5_common_pci.h b/drivers/common/mlx5/mlx5_common_pci.h\nindex de89bb98bc..cb8d2f5f87 100644\n--- a/drivers/common/mlx5/mlx5_common_pci.h\n+++ b/drivers/common/mlx5/mlx5_common_pci.h\n@@ -9,17 +9,18 @@\n * @file\n *\n * RTE Mellanox PCI Driver Interface\n- * Mellanox ConnectX PCI device supports multiple class: net,vdpa,regex and\n- * compress devices. This layer enables creating such multiple class of devices\n- * on a single PCI device by allowing to bind multiple class specific device\n- * driver to attach to mlx5_pci driver.\n+ * Mellanox ConnectX PCI device supports multiple class: net,vdpa,regex,compress\n+ * and crypto devices. This layer enables creating such multiple class of\n+ * devices on a single PCI device by allowing to bind multiple class specific\n+ * device driver to attach to mlx5_pci driver.\n *\n- * ----------- ------------ ------------- ----------------\n- * | mlx5 | | mlx5 | | mlx5 | | mlx5 |\n- * | net pmd | | vdpa pmd | | regex pmd | | compress pmd |\n- * ----------- ------------ ------------- ----------------\n- * \\ \\ / /\n- * \\ \\ / /\n+ * -------- -------- --------- ------------ ----------\n+ * | mlx5 | | mlx5 | | mlx5 | | mlx5 | | mlx5 |\n+ * | net | | vdpa | | regex | | compress | | crypto |\n+ * | pmd | | pmd | | pmd | | pmd | | pmd |\n+ * -------- -------- --------- ------------ ----------\n+ * \\ \\ | / /\n+ * \\ \\ | / /\n * \\ \\_--------------_/ /\n * \\_______________| mlx5 |_______________/\n * | pci common |\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex b9fdf9392f..6951607def 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -15,6 +15,7 @@ drivers = [\n 'dpaa_sec',\n 'dpaa2_sec',\n 'kasumi',\n+ 'mlx5',\n 'mvsam',\n 'nitrox',\n 'null',\ndiff --git a/drivers/crypto/mlx5/meson.build b/drivers/crypto/mlx5/meson.build\nnew file mode 100644\nindex 0000000000..6fd70bc477\n--- /dev/null\n+++ b/drivers/crypto/mlx5/meson.build\n@@ -0,0 +1,26 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+\n+if not is_linux\n+\tbuild = false\n+\treason = 'only supported on Linux'\n+\tsubdir_done()\n+endif\n+\n+fmt_name = 'mlx5_crypto'\n+deps += ['common_mlx5', 'eal', 'cryptodev']\n+sources = files(\n+\t'mlx5_crypto.c',\n+)\n+cflags_options = [\n+\t'-std=c11',\n+\t'-Wno-strict-prototypes',\n+\t'-D_BSD_SOURCE',\n+\t'-D_DEFAULT_SOURCE',\n+\t'-D_XOPEN_SOURCE=600',\n+]\n+foreach option:cflags_options\n+\tif cc.has_argument(option)\n+\t\tcflags += option\n+\tendif\n+endforeach\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nnew file mode 100644\nindex 0000000000..fbe3c21aae\n--- /dev/null\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -0,0 +1,275 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include <rte_malloc.h>\n+#include <rte_log.h>\n+#include <rte_errno.h>\n+#include <rte_pci.h>\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+\n+#include <mlx5_glue.h>\n+#include <mlx5_common.h>\n+#include <mlx5_common_pci.h>\n+#include <mlx5_devx_cmds.h>\n+#include <mlx5_common_os.h>\n+\n+#include \"mlx5_crypto_utils.h\"\n+\n+#define MLX5_CRYPTO_DRIVER_NAME mlx5_crypto\n+#define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n+\n+#define MLX5_CRYPTO_FEATURE_FLAGS \\\n+\tRTE_CRYPTODEV_FF_HW_ACCELERATED\n+\n+struct mlx5_crypto_priv {\n+\tTAILQ_ENTRY(mlx5_crypto_priv) next;\n+\tstruct ibv_context *ctx; /* Device context. */\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct rte_cryptodev *crypto_dev;\n+\tvoid *uar; /* User Access Region. */\n+\tuint32_t pdn; /* Protection Domain number. */\n+\tstruct ibv_pd *pd;\n+};\n+\n+TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =\n+\t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);\n+static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;\n+\n+int mlx5_crypto_logtype;\n+\n+uint8_t mlx5_crypto_driver_id;\n+\n+static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME);\n+\n+static const struct rte_driver mlx5_drv = {\n+\t.name = mlx5_crypto_drv_name,\n+\t.alias = mlx5_crypto_drv_name\n+};\n+\n+static struct cryptodev_driver mlx5_cryptodev_driver;\n+\n+static struct rte_cryptodev_ops mlx5_crypto_ops = {\n+\t.dev_configure\t\t\t= NULL,\n+\t.dev_start\t\t\t= NULL,\n+\t.dev_stop\t\t\t= NULL,\n+\t.dev_close\t\t\t= NULL,\n+\t.dev_infos_get\t\t\t= NULL,\n+\t.stats_get\t\t\t= NULL,\n+\t.stats_reset\t\t\t= NULL,\n+\t.queue_pair_setup\t\t= NULL,\n+\t.queue_pair_release\t\t= NULL,\n+\t.sym_session_get_size\t\t= NULL,\n+\t.sym_session_configure\t\t= NULL,\n+\t.sym_session_clear\t\t= NULL,\n+\t.sym_get_raw_dp_ctx_size\t= NULL,\n+\t.sym_configure_raw_dp_ctx\t= NULL,\n+};\n+\n+static void\n+mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv)\n+{\n+\tif (priv->pd != NULL) {\n+\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n+\t\tpriv->pd = NULL;\n+\t}\n+\tif (priv->uar != NULL) {\n+\t\tmlx5_glue->devx_free_uar(priv->uar);\n+\t\tpriv->uar = NULL;\n+\t}\n+}\n+\n+static int\n+mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tstruct mlx5dv_obj obj;\n+\tstruct mlx5dv_pd pd_info;\n+\tint ret;\n+\n+\tpriv->pd = mlx5_glue->alloc_pd(priv->ctx);\n+\tif (priv->pd == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n+\t\treturn errno ? -errno : -ENOMEM;\n+\t}\n+\tobj.pd.in = priv->pd;\n+\tobj.pd.out = &pd_info;\n+\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Fail to get PD object info.\");\n+\t\tmlx5_glue->dealloc_pd(priv->pd);\n+\t\tpriv->pd = NULL;\n+\t\treturn -errno;\n+\t}\n+\tpriv->pdn = pd_info.pdn;\n+\treturn 0;\n+#else\n+\t(void)priv;\n+\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n+\treturn -ENOTSUP;\n+#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n+}\n+\n+static int\n+mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)\n+{\n+\tif (mlx5_crypto_pd_create(priv) != 0)\n+\t\treturn -1;\n+\tpriv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);\n+\tif (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==\n+\t NULL) {\n+\t\trte_errno = errno;\n+\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n+\t\tDRV_LOG(ERR, \"Failed to allocate UAR.\");\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * DPDK callback to register a PCI device.\n+ *\n+ * This function spawns crypto device out of a given PCI device.\n+ *\n+ * @param[in] pci_drv\n+ * PCI driver structure (mlx5_crypto_driver).\n+ * @param[in] pci_dev\n+ * PCI device information.\n+ *\n+ * @return\n+ * 0 on success, 1 to skip this driver, a negative errno value otherwise\n+ * and rte_errno is set.\n+ */\n+static int\n+mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n+\t\t\tstruct rte_pci_device *pci_dev)\n+{\n+\tstruct ibv_device *ibv;\n+\tstruct rte_cryptodev *crypto_dev;\n+\tstruct ibv_context *ctx;\n+\tstruct mlx5_crypto_priv *priv;\n+\tstruct mlx5_hca_attr attr = { 0 };\n+\tstruct rte_cryptodev_pmd_init_params init_params = {\n+\t\t.name = \"\",\n+\t\t.private_data_size = sizeof(struct mlx5_crypto_priv),\n+\t\t.socket_id = pci_dev->device.numa_node,\n+\t\t.max_nb_queue_pairs =\n+\t\t\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,\n+\t};\n+\tRTE_SET_USED(pci_drv);\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\tDRV_LOG(ERR, \"Non-primary process type is not supported.\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -rte_errno;\n+\t}\n+\tibv = mlx5_os_get_ibv_device(&pci_dev->addr);\n+\tif (ibv == NULL) {\n+\t\tDRV_LOG(ERR, \"No matching IB device for PCI slot \"\n+\t\t\tPCI_PRI_FMT \".\", pci_dev->addr.domain,\n+\t\t\tpci_dev->addr.bus, pci_dev->addr.devid,\n+\t\t\tpci_dev->addr.function);\n+\t\treturn -rte_errno;\n+\t}\n+\tDRV_LOG(INFO, \"PCI information matches for device \\\"%s\\\".\", ibv->name);\n+\tctx = mlx5_glue->dv_open_device(ibv);\n+\tif (ctx == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to open IB device \\\"%s\\\".\", ibv->name);\n+\t\trte_errno = ENODEV;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 ||\n+\t attr.crypto == 0 || attr.aes_xts == 0) {\n+\t\tDRV_LOG(ERR, \"Not enough capabilities to support crypto \"\n+\t\t\t\"operations, maybe old FW/OFED version?\");\n+\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -ENOTSUP;\n+\t}\n+\tcrypto_dev = rte_cryptodev_pmd_create(ibv->name, &pci_dev->device,\n+\t\t\t\t\t&init_params);\n+\tif (crypto_dev == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibv->name);\n+\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\treturn -ENODEV;\n+\t}\n+\tDRV_LOG(INFO,\n+\t\t\"Crypto device %s was created successfully.\", ibv->name);\n+\tcrypto_dev->dev_ops = &mlx5_crypto_ops;\n+\tcrypto_dev->dequeue_burst = NULL;\n+\tcrypto_dev->enqueue_burst = NULL;\n+\tcrypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n+\tcrypto_dev->driver_id = mlx5_crypto_driver_id;\n+\tpriv = crypto_dev->data->dev_private;\n+\tpriv->ctx = ctx;\n+\tpriv->pci_dev = pci_dev;\n+\tpriv->crypto_dev = crypto_dev;\n+\tif (mlx5_crypto_hw_global_prepare(priv) != 0) {\n+\t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n+\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\treturn -1;\n+\t}\n+\tpthread_mutex_lock(&priv_list_lock);\n+\tTAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);\n+\tpthread_mutex_unlock(&priv_list_lock);\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_pci_remove(struct rte_pci_device *pdev)\n+{\n+\tstruct mlx5_crypto_priv *priv = NULL;\n+\n+\tpthread_mutex_lock(&priv_list_lock);\n+\tTAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)\n+\t\tif (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0)\n+\t\t\tbreak;\n+\tif (priv)\n+\t\tTAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next);\n+\tpthread_mutex_unlock(&priv_list_lock);\n+\tif (priv) {\n+\t\tmlx5_crypto_hw_global_release(priv);\n+\t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n+\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t}\n+\treturn 0;\n+}\n+\n+static const struct rte_pci_id mlx5_crypto_pci_id_map[] = {\n+\t\t{\n+\t\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,\n+\t\t\t\t\tPCI_DEVICE_ID_MELLANOX_CONNECTX6)\n+\t\t},\n+\t\t{\n+\t\t\t.vendor_id = 0\n+\t\t}\n+\t};\n+\n+static struct mlx5_pci_driver mlx5_crypto_driver = {\n+\t.driver_class = MLX5_CLASS_CRYPTO,\n+\t.pci_driver = {\n+\t\t.driver = {\n+\t\t\t.name = RTE_STR(MLX5_CRYPTO_DRIVER_NAME),\n+\t\t},\n+\t\t.id_table = mlx5_crypto_pci_id_map,\n+\t\t.probe = mlx5_crypto_pci_probe,\n+\t\t.remove = mlx5_crypto_pci_remove,\n+\t\t.drv_flags = 0,\n+\t},\n+};\n+\n+RTE_INIT(rte_mlx5_crypto_init)\n+{\n+\tmlx5_common_init();\n+\tif (mlx5_glue != NULL)\n+\t\tmlx5_pci_driver_register(&mlx5_crypto_driver);\n+}\n+\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(mlx5_cryptodev_driver, mlx5_drv,\n+\t\t\t mlx5_crypto_driver_id);\n+\n+RTE_LOG_REGISTER_DEFAULT(mlx5_crypto_logtype, NOTICE)\n+RTE_PMD_EXPORT_NAME(MLX5_CRYPTO_DRIVER_NAME, __COUNTER__);\n+RTE_PMD_REGISTER_PCI_TABLE(MLX5_CRYPTO_DRIVER_NAME, mlx5_crypto_pci_id_map);\n+RTE_PMD_REGISTER_KMOD_DEP(MLX5_CRYPTO_DRIVER_NAME, \"* ib_uverbs & mlx5_core & mlx5_ib\");\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_utils.h b/drivers/crypto/mlx5/mlx5_crypto_utils.h\nnew file mode 100644\nindex 0000000000..b6c60ca782\n--- /dev/null\n+++ b/drivers/crypto/mlx5/mlx5_crypto_utils.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef RTE_PMD_MLX5_CRYPTO_UTILS_H_\n+#define RTE_PMD_MLX5_CRYPTO_UTILS_H_\n+\n+#include <mlx5_common.h>\n+\n+extern int mlx5_crypto_logtype;\n+\n+#define MLX5_CRYPTO_LOG_PREFIX \"mlx5_crypto\"\n+/* Generic printf()-like logging macro with automatic line feed. */\n+#define DRV_LOG(level, ...) \\\n+\tPMD_DRV_LOG_(level, mlx5_crypto_logtype, MLX5_CRYPTO_LOG_PREFIX, \\\n+\t\t__VA_ARGS__ PMD_DRV_LOG_STRIP PMD_DRV_LOG_OPAREN, \\\n+\t\tPMD_DRV_LOG_CPAREN)\n+\n+#endif /* RTE_PMD_MLX5_CRYPTO_UTILS_H_ */\ndiff --git a/drivers/crypto/mlx5/version.map b/drivers/crypto/mlx5/version.map\nnew file mode 100644\nindex 0000000000..4a76d1d52d\n--- /dev/null\n+++ b/drivers/crypto/mlx5/version.map\n@@ -0,0 +1,3 @@\n+DPDK_21 {\n+\tlocal: *;\n+};\n", "prefixes": [ "v6", "01/15" ] }