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GET /api/patches/95210/?format=api
{ "id": 95210, "url": "http://patches.dpdk.org/api/patches/95210/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210702091446.24635-4-shunh@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210702091446.24635-4-shunh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210702091446.24635-4-shunh@nvidia.com", "date": "2021-07-02T09:14:45", "name": "[v1,3/4] net/mlx5: fix meter flow direction check", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "611fb956f52bd40a444a99437904ea4895c5aafe", "submitter": { "id": 2212, "url": "http://patches.dpdk.org/api/people/2212/?format=api", "name": "Shun Hao", "email": "shunh@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210702091446.24635-4-shunh@nvidia.com/mbox/", "series": [ { "id": 17594, "url": "http://patches.dpdk.org/api/series/17594/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17594", "date": "2021-07-02T09:14:42", "name": "ASO meter sharing support", "version": 1, "mbox": "http://patches.dpdk.org/series/17594/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/95210/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/95210/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 93A48A0A0C;\n\tFri, 2 Jul 2021 11:15:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D81D44138E;\n\tFri, 2 Jul 2021 11:15:21 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2064.outbound.protection.outlook.com [40.107.237.64])\n by mails.dpdk.org (Postfix) with ESMTP id 8E8DB41381;\n Fri, 2 Jul 2021 11:15:19 +0200 (CEST)", "from DS7PR05CA0012.namprd05.prod.outlook.com (2603:10b6:5:3b9::17)\n by BN9PR12MB5366.namprd12.prod.outlook.com (2603:10b6:408:103::20) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.23; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Shun Hao <shunh@nvidia.com>", "To": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>,\n <shahafs@nvidia.com>, Li Zhang <lizh@nvidia.com>", "CC": "<dev@dpdk.org>, <thomas@monjalon.net>, <rasland@nvidia.com>,\n <roniba@nvidia.com>, <stable@dpdk.org>", "Date": "Fri, 2 Jul 2021 12:14:45 +0300", "Message-ID": "<20210702091446.24635-4-shunh@nvidia.com>", "X-Mailer": "git-send-email 2.20.0", "In-Reply-To": "<20210702091446.24635-1-shunh@nvidia.com>", "References": "<20210702091446.24635-1-shunh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "5b46c1bc-01b8-4d5f-0001-08d93d39e8ec", "X-MS-TrafficTypeDiagnostic": "BN9PR12MB5366:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN9PR12MB536668640313E79F8B56C67EC01F9@BN9PR12MB5366.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2733;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n w0gyPr0GfbFe3FV1C+9wLF/9z6vMUxKofYSFcMyUCTIjV5eZCEJnmDOEoDUBjaWOqELviVLAodWE84P5earoqiEvDH+FZFTgL+sT2kf+N1Akn9j4ElbGtXX+rZEGgUV9UT5LRNzPI4/6mTNHs1xjGsEb+5ID3j2yHQBbtE5gAVDY9BXcDRJnAYbExQoucA9O4r0q1bkajFuq+XkYnWbgu+wApl7j/O2cy+c3nLQYiDPno15QIbxUwn+wTbC9Qnn98+8wIj/O29TWN291qA39V4aRE2CdjxWvcRxu9e5WcLh6aeHE8w+J/97ixJGRmLRFizyehEqXfhtVfiN8OlrAulXGiABH5gOjvJAVm40PfUyGO/Q5TmvZOwZ7ld6U3Cih8/p09a6T4f7jqyhbFGhny33oyu3klIwkV7sA381Y3YtyeTvWWQ+s9iByWz1pF5Zkps763N/00HLZNWbGcckQwit6v5eG6jN81UTKd4chxQti8/S5gIHtMdPnT3382jmwqFY2jaeW/q4xBNgfVOUTOriSHCo6gIjf+LJfyrloBpYLuUluLto2/FS9zt/GW9yLJsXwY3IYfYHR3vneFZ8pSl+sGrrT9mpQyi0eIP8oC9ZdHvv2T6K5Fy/pOXgk4mRVTR5NM1bGWrgjnHfo85gW1ez6zhMy0drNQOFr1Jwfcxh6OlWjJw9orRQCb5bospHW0Aq8iQ0ICTl/+Q+UziLeDw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(396003)(39860400002)(376002)(46966006)(36840700001)(426003)(6286002)(6636002)(2616005)(1076003)(54906003)(4326008)(55016002)(47076005)(2906002)(82310400003)(336012)(36860700001)(26005)(82740400003)(70586007)(16526019)(186003)(316002)(36906005)(6666004)(7636003)(83380400001)(8676002)(7696005)(5660300002)(8936002)(478600001)(110136005)(86362001)(356005)(70206006)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Jul 2021 09:15:17.8807 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5b46c1bc-01b8-4d5f-0001-08d93d39e8ec", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT048.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN9PR12MB5366", "Subject": "[dpdk-dev] [PATCH v1 3/4] net/mlx5: fix meter flow direction check", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When preparing prefix flow using ASO meter, if it's tx flow, need\nto make meter action the first one.\n\nCurrently the check of flow direction in switch domain is incorrect\nthat it checks the flow dev port only.\n\nThis adds the fix for the check that if there's port_id match item\nin flow, use that port_id as src port to determine flow direction.\n\nFixes: c99b4f8bc2f1 (\"net/mlx5: support ASO meter action\")\nCc: stable@dpdk.org\n\nSigned-off-by: Shun Hao <shunh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 83 ++++++++++++++++++++++--------------\n 1 file changed, 50 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 3b7c94d92f..c27f6197a0 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -4740,12 +4740,12 @@ flow_meter_split_prep(struct rte_eth_dev *dev,\n \tstruct mlx5_rte_flow_item_tag *tag_item_spec;\n \tstruct mlx5_rte_flow_item_tag *tag_item_mask;\n \tuint32_t tag_id = 0;\n-\tbool copy_vlan = false;\n+\tstruct rte_flow_item *vlan_item_dst = NULL;\n+\tconst struct rte_flow_item *vlan_item_src = NULL;\n \tstruct rte_flow_action *hw_mtr_action;\n \tstruct rte_flow_action *action_pre_head = NULL;\n-\tbool mtr_first = priv->sh->meter_aso_en &&\n-\t\t\t(attr->egress ||\n-\t\t\t(attr->transfer && priv->representor_id != UINT16_MAX));\n+\tint32_t flow_src_port = priv->representor_id;\n+\tbool mtr_first;\n \tuint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;\n \tuint8_t mtr_reg_bits = priv->mtr_reg_share ?\n \t\t\t\tMLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS;\n@@ -4754,6 +4754,42 @@ flow_meter_split_prep(struct rte_eth_dev *dev,\n \tuint8_t flow_id_bits = 0;\n \tint shift;\n \n+\t/* Prepare the suffix subflow items. */\n+\ttag_item = sfx_items++;\n+\tfor (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {\n+\t\tstruct mlx5_priv *port_priv;\n+\t\tconst struct rte_flow_item_port_id *pid_v;\n+\t\tint item_type = items->type;\n+\n+\t\tswitch (item_type) {\n+\t\tcase RTE_FLOW_ITEM_TYPE_PORT_ID:\n+\t\t\tpid_v = items->spec;\n+\t\t\tMLX5_ASSERT(pid_v);\n+\t\t\tport_priv = mlx5_port_to_eswitch_info(pid_v->id, false);\n+\t\t\tif (!port_priv)\n+\t\t\t\treturn rte_flow_error_set(error,\n+\t\t\t\t\t\trte_errno,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM_SPEC,\n+\t\t\t\t\t\tpid_v,\n+\t\t\t\t\t\t\"Failed to get port info.\");\n+\t\t\tflow_src_port = port_priv->representor_id;\n+\t\t\tmemcpy(sfx_items, items, sizeof(*sfx_items));\n+\t\t\tsfx_items++;\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n+\t\t\t/* Determine if copy vlan item below. */\n+\t\t\tvlan_item_src = items;\n+\t\t\tvlan_item_dst = sfx_items++;\n+\t\t\tvlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tsfx_items->type = RTE_FLOW_ITEM_TYPE_END;\n+\tsfx_items++;\n+\tmtr_first = priv->sh->meter_aso_en &&\n+\t\t(attr->egress || (attr->transfer && flow_src_port != 0xffff));\n \t/* For ASO meter, meter must be before tag in TX direction. */\n \tif (mtr_first) {\n \t\taction_pre_head = actions_pre++;\n@@ -4790,7 +4826,16 @@ flow_meter_split_prep(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:\n-\t\t\tcopy_vlan = true;\n+\t\t\tif (vlan_item_dst && vlan_item_src) {\n+\t\t\t\tmemcpy(vlan_item_dst, vlan_item_src,\n+\t\t\t\t\tsizeof(*vlan_item_dst));\n+\t\t\t\t/*\n+\t\t\t\t * Convert to internal match item, it is used\n+\t\t\t\t * for vlan push and set vid.\n+\t\t\t\t */\n+\t\t\t\tvlan_item_dst->type = (enum rte_flow_item_type)\n+\t\t\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_VLAN;\n+\t\t\t}\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n@@ -4862,34 +4907,6 @@ flow_meter_split_prep(struct rte_eth_dev *dev,\n \t\tif (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits)\n \t\t\tpriv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits;\n \t}\n-\t/* Prepare the suffix subflow items. */\n-\ttag_item = sfx_items++;\n-\tfor (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {\n-\t\tint item_type = items->type;\n-\n-\t\tswitch (item_type) {\n-\t\tcase RTE_FLOW_ITEM_TYPE_PORT_ID:\n-\t\t\tmemcpy(sfx_items, items, sizeof(*sfx_items));\n-\t\t\tsfx_items++;\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n-\t\t\tif (copy_vlan) {\n-\t\t\t\tmemcpy(sfx_items, items, sizeof(*sfx_items));\n-\t\t\t\t/*\n-\t\t\t\t * Convert to internal match item, it is used\n-\t\t\t\t * for vlan push and set vid.\n-\t\t\t\t */\n-\t\t\t\tsfx_items->type = (enum rte_flow_item_type)\n-\t\t\t\t\t\t MLX5_RTE_FLOW_ITEM_TYPE_VLAN;\n-\t\t\t\tsfx_items++;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\tsfx_items->type = RTE_FLOW_ITEM_TYPE_END;\n-\tsfx_items++;\n \t/* Build tag actions and items for meter_id/meter flow_id. */\n \tset_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre;\n \ttag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items;\n", "prefixes": [ "v1", "3/4" ] }