Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94705/?format=api
{ "id": 94705, "url": "http://patches.dpdk.org/api/patches/94705/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-10-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-10-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-10-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:09", "name": "[v4,09/62] net/cnxk: add build infra and common probe", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "38da364468830fa1e6e39287db084c9684a4115d", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-10-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "http://patches.dpdk.org/api/series/17449/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/17449/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/94705/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/94705/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DEDB4A0C41;\n\tWed, 23 Jun 2021 06:48:25 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 687A3410F5;\n\tWed, 23 Jun 2021 06:47:50 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0A4D741125\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:47:48 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k7nX025542 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:48 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gj6-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:48 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:47:46 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:47:46 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 4FA3B5B693B;\n Tue, 22 Jun 2021 21:47:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=4hUQvTKmgueapFC5b+KraflyECefAL7IdYM3hd9VX2U=;\n b=LwjTgqRq/l3xoKat+edW0vZTYEX6yCRSMbSgyFpwEI2+8oJ39ea9F8ErDrAs/J4tv9J3\n TBfIOf3aWUTJP+sCVmcXQUH8CMd2zx1xttJysXR7VTOG+us1mnEH6trPG9Q6UQTgquuP\n oSynb8YyDBPxk+46SLpGCUOnB6FzGZsglXPo7xo+09+prPYzhLL31Ag8ZOP40a86D5uP\n AoyqtLDjZo3BQhBdbwKuZeAvL2VoIYpG/58wqsDC+qJ10xhU+fcZE9+8sAWh8R45MX6U\n N+q8byPulc20jVaYVoCk9POMOxlwejsbLH5HmOx4j8utpxT5jdvvcyoivf8UsTlz4K8B JQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:09 +0530", "Message-ID": "<20210623044702.4240-10-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "4qCxd-ld-DdVEOSk_ikemwO1cfnyExXL", "X-Proofpoint-GUID": "4qCxd-ld-DdVEOSk_ikemwO1cfnyExXL", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 09/62] net/cnxk: add build infra and common\n probe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add build infrastructure and common probe and remove for cnxk driver\nwhich is used by both CN10K and CN9K SoC.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n MAINTAINERS | 5 +-\n doc/guides/nics/cnxk.rst | 29 +++++\n doc/guides/nics/features/cnxk.ini | 9 ++\n doc/guides/nics/features/cnxk_vec.ini | 9 ++\n doc/guides/nics/features/cnxk_vf.ini | 9 ++\n doc/guides/nics/index.rst | 1 +\n doc/guides/platform/cnxk.rst | 3 +\n doc/guides/rel_notes/release_21_08.rst | 5 +\n drivers/net/cnxk/cnxk_ethdev.c | 218 +++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 57 +++++++++\n drivers/net/cnxk/meson.build | 14 +++\n drivers/net/cnxk/version.map | 3 +\n drivers/net/meson.build | 1 +\n 13 files changed, 362 insertions(+), 1 deletion(-)\n create mode 100644 doc/guides/nics/cnxk.rst\n create mode 100644 doc/guides/nics/features/cnxk.ini\n create mode 100644 doc/guides/nics/features/cnxk_vec.ini\n create mode 100644 doc/guides/nics/features/cnxk_vf.ini\n create mode 100644 drivers/net/cnxk/cnxk_ethdev.c\n create mode 100644 drivers/net/cnxk/cnxk_ethdev.h\n create mode 100644 drivers/net/cnxk/meson.build\n create mode 100644 drivers/net/cnxk/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 5877a16..b39a1c2 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -745,8 +745,11 @@ M: Kiran Kumar K <kirankumark@marvell.com>\n M: Sunil Kumar Kori <skori@marvell.com>\n M: Satha Rao <skoteshwar@marvell.com>\n T: git://dpdk.org/next/dpdk-next-net-mrvl\n-F: drivers/common/cnxk/\n+F: doc/guides/nics/cnxk.rst\n+F: doc/guides/nics/features/cnxk*.ini\n F: doc/guides/platform/cnxk.rst\n+F: drivers/common/cnxk/\n+F: drivers/net/cnxk/\n \n Marvell mvpp2\n M: Liron Himi <lironh@marvell.com>\ndiff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nnew file mode 100644\nindex 0000000..ca21842\n--- /dev/null\n+++ b/doc/guides/nics/cnxk.rst\n@@ -0,0 +1,29 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(C) 2021 Marvell.\n+\n+CNXK Poll Mode driver\n+=====================\n+\n+The CNXK ETHDEV PMD (**librte_net_cnxk**) provides poll mode ethdev driver\n+support for the inbuilt network device found in **Marvell OCTEON CN9K/CN10K**\n+SoC family as well as for their virtual functions (VF) in SR-IOV context.\n+\n+More information can be found at `Marvell Official Website\n+<https://www.marvell.com/embedded-processors/infrastructure-processors>`_.\n+\n+Features\n+--------\n+\n+Features of the CNXK Ethdev PMD are:\n+\n+Prerequisites\n+-------------\n+\n+See :doc:`../platform/cnxk` for setup information.\n+\n+\n+Driver compilation and testing\n+------------------------------\n+\n+Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n+for details.\ndiff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nnew file mode 100644\nindex 0000000..2c23464\n--- /dev/null\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -0,0 +1,9 @@\n+;\n+; Supported features of the 'cnxk' network poll mode driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Linux = Y\n+ARMv8 = Y\n+Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nnew file mode 100644\nindex 0000000..de78516\n--- /dev/null\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -0,0 +1,9 @@\n+;\n+; Supported features of the 'cnxk_vec' network poll mode driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Linux = Y\n+ARMv8 = Y\n+Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nnew file mode 100644\nindex 0000000..9c96351\n--- /dev/null\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -0,0 +1,9 @@\n+;\n+; Supported features of the 'cnxk_vf' network poll mode driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Linux = Y\n+ARMv8 = Y\n+Usage doc = Y\ndiff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst\nindex 799697c..c1a04d9 100644\n--- a/doc/guides/nics/index.rst\n+++ b/doc/guides/nics/index.rst\n@@ -19,6 +19,7 @@ Network Interface Controller Drivers\n axgbe\n bnx2x\n bnxt\n+ cnxk\n cxgbe\n dpaa\n dpaa2\ndiff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst\nindex cebb3d0..b506c11 100644\n--- a/doc/guides/platform/cnxk.rst\n+++ b/doc/guides/platform/cnxk.rst\n@@ -142,6 +142,9 @@ HW Offload Drivers\n \n This section lists dataplane H/W block(s) available in cnxk SoC.\n \n+#. **Ethdev Driver**\n+ See :doc:`../nics/cnxk` for NIX Ethdev driver information.\n+\n #. **Mempool Driver**\n See :doc:`../mempool/cnxk` for NPA mempool driver information.\n \ndiff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst\nindex a6ecfdf..31e49e1 100644\n--- a/doc/guides/rel_notes/release_21_08.rst\n+++ b/doc/guides/rel_notes/release_21_08.rst\n@@ -55,6 +55,11 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added support for Marvell CN10K SoC ethernet device.**\n+\n+ * Added net/cnxk driver which provides the support for the integrated ethernet\n+ device.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nnew file mode 100644\nindex 0000000..589b0da\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -0,0 +1,218 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#include <cnxk_ethdev.h>\n+\n+/* CNXK platform independent eth dev ops */\n+struct eth_dev_ops cnxk_eth_dev_ops;\n+\n+static int\n+cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct roc_nix *nix = &dev->nix;\n+\tstruct rte_pci_device *pci_dev;\n+\tint rc, max_entries;\n+\n+\teth_dev->dev_ops = &cnxk_eth_dev_ops;\n+\n+\t/* For secondary processes, the primary has done all the work */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\trte_eth_copy_pci_info(eth_dev, pci_dev);\n+\n+\t/* Initialize base roc nix */\n+\tnix->pci_dev = pci_dev;\n+\trc = roc_nix_dev_init(nix);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to initialize roc nix rc=%d\", rc);\n+\t\tgoto error;\n+\t}\n+\n+\tdev->eth_dev = eth_dev;\n+\n+\t/* For vfs, returned max_entries will be 0. but to keep default mac\n+\t * address, one entry must be allocated. so setting up to 1.\n+\t */\n+\tif (roc_nix_is_vf_or_sdp(nix))\n+\t\tmax_entries = 1;\n+\telse\n+\t\tmax_entries = roc_nix_mac_max_entries_get(nix);\n+\n+\tif (max_entries <= 0) {\n+\t\tplt_err(\"Failed to get max entries for mac addr\");\n+\t\trc = -ENOTSUP;\n+\t\tgoto dev_fini;\n+\t}\n+\n+\teth_dev->data->mac_addrs =\n+\t\trte_zmalloc(\"mac_addr\", max_entries * RTE_ETHER_ADDR_LEN, 0);\n+\tif (eth_dev->data->mac_addrs == NULL) {\n+\t\tplt_err(\"Failed to allocate memory for mac addr\");\n+\t\trc = -ENOMEM;\n+\t\tgoto dev_fini;\n+\t}\n+\n+\tdev->max_mac_entries = max_entries;\n+\n+\t/* Get mac address */\n+\trc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to get mac addr, rc=%d\", rc);\n+\t\tgoto free_mac_addrs;\n+\t}\n+\n+\t/* Update the mac address */\n+\tmemcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);\n+\n+\tif (!roc_nix_is_vf_or_sdp(nix)) {\n+\t\t/* Sync same MAC address to CGX/RPM table */\n+\t\trc = roc_nix_mac_addr_set(nix, dev->mac_addr);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to set mac addr, rc=%d\", rc);\n+\t\t\tgoto free_mac_addrs;\n+\t\t}\n+\t}\n+\n+\t/* Initialize roc npc */\n+\tplt_nix_dbg(\"Port=%d pf=%d vf=%d ver=%s hwcap=0x%\" PRIx64\n+\t\t \" rxoffload_capa=0x%\" PRIx64 \" txoffload_capa=0x%\" PRIx64,\n+\t\t eth_dev->data->port_id, roc_nix_get_pf(nix),\n+\t\t roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,\n+\t\t dev->rx_offload_capa, dev->tx_offload_capa);\n+\treturn 0;\n+\n+free_mac_addrs:\n+\trte_free(eth_dev->data->mac_addrs);\n+dev_fini:\n+\troc_nix_dev_fini(nix);\n+error:\n+\tplt_err(\"Failed to init nix eth_dev rc=%d\", rc);\n+\treturn rc;\n+}\n+\n+static int\n+cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tconst struct eth_dev_ops *dev_ops = eth_dev->dev_ops;\n+\tstruct roc_nix *nix = &dev->nix;\n+\tint rc, i;\n+\n+\t/* Nothing to be done for secondary processes */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\troc_nix_npc_rx_ena_dis(nix, false);\n+\n+\t/* Free up SQs */\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\tdev_ops->tx_queue_release(eth_dev->data->tx_queues[i]);\n+\t\teth_dev->data->tx_queues[i] = NULL;\n+\t}\n+\teth_dev->data->nb_tx_queues = 0;\n+\n+\t/* Free up RQ's and CQ's */\n+\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n+\t\tdev_ops->rx_queue_release(eth_dev->data->rx_queues[i]);\n+\t\teth_dev->data->rx_queues[i] = NULL;\n+\t}\n+\teth_dev->data->nb_rx_queues = 0;\n+\n+\t/* Free tm resources */\n+\troc_nix_tm_fini(nix);\n+\n+\t/* Unregister queue irqs */\n+\troc_nix_unregister_queue_irqs(nix);\n+\n+\t/* Unregister cq irqs */\n+\tif (eth_dev->data->dev_conf.intr_conf.rxq)\n+\t\troc_nix_unregister_cq_irqs(nix);\n+\n+\t/* Free nix lf resources */\n+\trc = roc_nix_lf_free(nix);\n+\tif (rc)\n+\t\tplt_err(\"Failed to free nix lf, rc=%d\", rc);\n+\n+\trte_free(eth_dev->data->mac_addrs);\n+\teth_dev->data->mac_addrs = NULL;\n+\n+\t/* Check if mbox close is needed */\n+\tif (!mbox_close)\n+\t\treturn 0;\n+\n+\trc = roc_nix_dev_fini(nix);\n+\t/* Can be freed later by PMD if NPA LF is in use */\n+\tif (rc == -EAGAIN) {\n+\t\teth_dev->data->dev_private = NULL;\n+\t\treturn 0;\n+\t} else if (rc) {\n+\t\tplt_err(\"Failed in nix dev fini, rc=%d\", rc);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+cnxk_nix_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_eth_dev *eth_dev;\n+\tstruct roc_nix *nix;\n+\tint rc = -EINVAL;\n+\n+\teth_dev = rte_eth_dev_allocated(pci_dev->device.name);\n+\tif (eth_dev) {\n+\t\t/* Cleanup eth dev */\n+\t\trc = cnxk_eth_dev_uninit(eth_dev, true);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\trte_eth_dev_release_port(eth_dev);\n+\t}\n+\n+\t/* Nothing to be done for secondary processes */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\t/* Check if this device is hosting common resource */\n+\tnix = roc_idev_npa_nix_get();\n+\tif (nix->pci_dev != pci_dev)\n+\t\treturn 0;\n+\n+\t/* Try nix fini now */\n+\trc = roc_nix_dev_fini(nix);\n+\tif (rc == -EAGAIN) {\n+\t\tplt_info(\"%s: common resource in use by other devices\",\n+\t\t\t pci_dev->name);\n+\t\tgoto exit;\n+\t} else if (rc) {\n+\t\tplt_err(\"Failed in nix dev fini, rc=%d\", rc);\n+\t\tgoto exit;\n+\t}\n+\n+\t/* Free device pointer as rte_ethdev does not have it anymore */\n+\trte_free(nix);\n+exit:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\tint rc;\n+\n+\tRTE_SET_USED(pci_drv);\n+\n+\trc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),\n+\t\t\t\t\t cnxk_eth_dev_init);\n+\n+\t/* On error on secondary, recheck if port exists in primary or\n+\t * in mid of detach state.\n+\t */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)\n+\t\tif (!rte_eth_dev_allocated(pci_dev->device.name))\n+\t\t\treturn 0;\n+\treturn rc;\n+}\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nnew file mode 100644\nindex 0000000..0460d1e\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -0,0 +1,57 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef __CNXK_ETHDEV_H__\n+#define __CNXK_ETHDEV_H__\n+\n+#include <math.h>\n+#include <stdint.h>\n+\n+#include <ethdev_driver.h>\n+#include <ethdev_pci.h>\n+\n+#include \"roc_api.h\"\n+\n+#define CNXK_ETH_DEV_PMD_VERSION \"1.0\"\n+\n+struct cnxk_eth_dev {\n+\t/* ROC NIX */\n+\tstruct roc_nix nix;\n+\n+\t/* Max macfilter entries */\n+\tuint8_t max_mac_entries;\n+\n+\tuint16_t flags;\n+\n+\t/* Pointer back to rte */\n+\tstruct rte_eth_dev *eth_dev;\n+\n+\t/* HW capabilities / Limitations */\n+\tunion {\n+\t\tuint64_t hwcap;\n+\t};\n+\n+\t/* Rx and Tx offload capabilities */\n+\tuint64_t rx_offload_capa;\n+\tuint64_t tx_offload_capa;\n+\tuint32_t speed_capa;\n+\n+\t/* Default mac address */\n+\tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n+};\n+\n+static inline struct cnxk_eth_dev *\n+cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)\n+{\n+\treturn eth_dev->data->dev_private;\n+}\n+\n+/* Common ethdev ops */\n+extern struct eth_dev_ops cnxk_eth_dev_ops;\n+\n+/* Ops */\n+int cnxk_nix_probe(struct rte_pci_driver *pci_drv,\n+\t\t struct rte_pci_device *pci_dev);\n+int cnxk_nix_remove(struct rte_pci_device *pci_dev);\n+\n+#endif /* __CNXK_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nnew file mode 100644\nindex 0000000..7dd4bca\n--- /dev/null\n+++ b/drivers/net/cnxk/meson.build\n@@ -0,0 +1,14 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2021 Marvell.\n+#\n+\n+if not dpdk_conf.get('RTE_ARCH_64')\n+\tbuild = false\n+\treason = 'only supported on 64-bit'\n+\tsubdir_done()\n+endif\n+\n+sources = files('cnxk_ethdev.c')\n+\n+deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']\n+deps += ['common_cnxk', 'mempool_cnxk']\ndiff --git a/drivers/net/cnxk/version.map b/drivers/net/cnxk/version.map\nnew file mode 100644\nindex 0000000..4a76d1d\n--- /dev/null\n+++ b/drivers/net/cnxk/version.map\n@@ -0,0 +1,3 @@\n+DPDK_21 {\n+\tlocal: *;\n+};\ndiff --git a/drivers/net/meson.build b/drivers/net/meson.build\nindex c8b5ce2..5b066fd 100644\n--- a/drivers/net/meson.build\n+++ b/drivers/net/meson.build\n@@ -12,6 +12,7 @@ drivers = [\n 'bnx2x',\n 'bnxt',\n 'bonding',\n+\t'cnxk',\n 'cxgbe',\n 'dpaa',\n 'dpaa2',\n", "prefixes": [ "v4", "09/62" ] }